AN97072 Bus-Controlled Autosync Deflection Controller TDA4853/54

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Bus-Controlled Autosync Deflection Controller TDA4853/54
AN97072
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
Abstract
this application note description Bus-Controlled Autosync Deflection Controller TDA4853 TDA4854 given. find summary specification internal specification, function description drawings illustrate text. Also some layout application proposals given.
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Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
AN97072
Bus-Controlled Autosync Deflection Controller TDA4853/54
Author(s): Rombout Moors Philips Semiconductors Systems Laboratory Eindhoven, Netherlands
Keywords Deflection Synchronisation Autosync Geometry
Number pages:
Date: 97-11-13
Bus-Controlled Autosync Deflection Controller TDA4853/54
Summary
Application Note AN97072
this application note Bus-Controlled Autosync Deflection Controller TDA4853 TDA4854 described. TDA4853 intended monitors. TDA4854 intended monitors where also dynamic focus wave forms required. Basically TDA4853 TDA4854 successors successful TDA4858 TDA4855. Besides integration with internal DAC's also some extra functions incorporated like extended geometry control, line parabola, size modulation etc. described pin. each summary specification internal specification given. Furthermore purpose functioning this described some text, there where useful drawing given illustrating text. some pins application proposal given. performance greatly depends good layout, recommendations given where necessary. With this monitor that combines high performance cost build. example promotion monitor CCM420 described application note AN97032.
Bus-Controlled Autosync Deflection Controller TDA4853/54
CONTENTS
Application Note AN97072
INTRODUCTION HFLB Characteristics Internal configuration Description Application. 2/9: XRAY Characteristics Internal configuration Description Application. BSENS BDRV Characteristics Internal configuration Description Application. Lay-out 7/25: PGND/SGND. Description Application Lay-out HDRV. Characteristics Internal configuration Description Application. Characteristics Internal Configuration Description Application. EWDRV. Characteristics Internal configuration Description Application. VOUT2 VOUT1 Characteristics Internal configuration Description Application. Lay-out VSYNC. 10.1 Characteristics Internal configuration 10.2 Description 10.3 Application. HSYNC. 11.1 Characteristics Internal configuration
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
11.2 Description 11.3 Application. CLBL 12.1 Characteristics Internal configuration 12.2 Description 12.3 Application. HUNLOCK 13.1 Characteristics Internal configuration 13.2 Description 13.3 Application. SDA. 14.1 Internal configuration 14.2 Description 14.3 Application. ASCOR 15.1 Characteristics Internal configuration 15.2 Description 15.3 Application. VSMOD. 16.1 Characteristics Internal configuration 16.2 Description 16.3 Application. 16.4 Lay-out VAGC VREF VCAP 17.1 Characteristics Internal configuration 17.2 Description 17.3 Application. HPLL1 HBUF HREF HCAP 18.1 Characteristics Internal configuration 18.2 Description 18.3 Application. PLL2 19.1 Characteristics Internal configuration 19.2 Description 19.3 Application. HSMOD. 20.1 Characteristics Internal configuration 20.2 Description 20.3 Application. 20.4 Lay-out FOCUS (TDA4854 ONLY). 21.1 Characteristics. 21.2 Description
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
21.3 Application. INTERNAL PROTECTION. 22.1 22.2 18-24 26-32. SOFTWARE CONTROL. REFERENCES.
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
Bus-Controlled Autosync Deflection Controller TDA4853/54
INTRODUCTION
Application Note AN97072
bus-controlled autosync monitor deflection controllers TDA4853/54 (bus-ASDC) successor types autosync deflection controllers TDA4855/58 (ASDC). Main differences bus-ASDC, compared ASDC, are: C-bus driven extended geometry adjustments functions, including stand-by mode; horizontal frequency range extended 15-130kHz; vertical frequency range 50-160Hz; combined horizontal/vertical focus section; cancellation; TV/VCR mode.
pinning (32-pin shrink-DIL) both TDA4853 TDA4854 shown Figure Figure 1.2, with positive negative current directions indicated.
HFLB XRAY BSENS
i.c.
HFLB XRAY BSENS
FOCUS
HSMOD HPLL2 HCAP HREF HBUF HPLL1 SGND VCAP VREF VAGC VSMOD ASCOR current direction
HSMOD HPLL2 HCAP HREF HBUF HPLL1 SGND VCAP VREF VAGC VSMOD ASCOR
BDRV PGND HDRV XSEL EWDRV VOUT2 VOUT1 VSYNC HSYNC CLBL current direction
BDRV PGND HDRV XSEL EWDRV VOUT2 VOUT1 VSYNC HSYNC CLBL
TDA4853
TDA4854
HUNLOCK
HUNLOCK
Figure 1.1: Pinning TDA4853
Figure 1.2: Pinning TDA4854
references from data sheet 1997 April
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL VHFLB positive clamping level VHFLB negative clamping level IHFLB positive clamping current IHFLB negative clamping current VHFLB slicing level IHFLB IHFLB -0.75
Application Note AN97072
HFLB Characteristics Internal configuration
CONDITIONS IHFLB MIN. TYP. MAX. UNIT
Figure 2.1: Internal configuration HFLB
Description
horizontal flyback input HFLB used PLL2 phase detector, that compares flyback pulse horizontal oscillator's saw-tooth voltage. PLL2 detector compensates delay external deflection circuit adjusting phase horizontal drive output pulse (HDRV).
Application
HFLB
horizontal flyback pulse
Figure 2.2: Application HFLB
HFLB connected converted horizontal flyback pulse about Vpp. Figure shows application HFLB. conversion about 1100 done fraction C1\C2. Resistor limits current applied high frequency filtering.
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL VXRAY slicing level
tW(XRAY)
Application Note AN97072
2/9: XRAY Characteristics Internal configuration
CONDITIONS MIN. 6.22 TYP. 6.39 MAX. 6.56 UNIT
6.25V
minimum trigger
pulse width
Rin(XRAY)
VXRAY 6.38 VXRAY 6.38
Figure 3.1: Internal configuration XRAY
Description
XRAY protection input consists voltage detector with precise threshold. this threshold exceeded certain time, control SOFTST reset goes into protection mode. this mode, following states defined: HUNLOCK (pin floating; Capacitor HPLL2 (pin discharged; HDRV (pin floating; BDRV (pin floating; VOUT1 VOUT2 (pin floating; CLBL (pin provides continuous blanking.
possibility reset internal XRAY latch depends application open grounded Same function TDA4854 (XRAY reset control SOFTST) with external resistor from (VCC): XRAY reset possible State internal XRAY latch kept XRAY latch reset
HDRV duty cycle Vout1,Vout2 approx. floating VXRAY VHUNLOCK BDRV duty cycle floating
X-ray latch triggered
floating
Figure 3.2: Activation soft-down sequence XRAY
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application
Application Note AN97072
XRAY protection, must limited tube's specification. flyback pulse from rectified XRAY divider, because proportional EHT. This principle shown Figure 3.3. value should dimensioned such that divider voltage crosses XRAY threshold reached specified upper limit. This upper limit usually XRAY input used, should grounded.
150p 100p XRAY
Figure 3.3: XRAY application
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL
Application Note AN97072
BSENS BDRV Characteristics Internal configuration
CONDITIONS MIN. TYP. MAX. UNIT
Transconductance amplifier VBIN IBIN(max) Vref internal noninverting input VBOP comparator inv. input voltage range VBOP(min) VBOP(max) IBOP (internal prot. circuit clamp level) IBOP(max) gOTA first pole (second pole operates integrator) Gopen, (VBOP\VBIN) CBOP(min) Voltage Comparator BSENS VBSENS comparator noninv. input voltage range output VBSENS, stop
IBSENS, discharge
2.37
5.25 2.58
Figure 4.1: Internal configuration BSENS
CBOP resistive load
capacitive load; IBSENS VBSENS fault condition
0.85
1.15
Figure 4.2: Internal configuration
VBSENS, restart CBSENS(min) IBSENS(max)
discharge disabled (leakage current)
Open Collector Output Stage BDRV IBDRV(max) IBDRV, leak VBDRV, toff(min) BDRV VBDRV IBDRV VHDRV VBDRV
Figure 4.3: Internal configuration BDRV
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
5.3V
Figure 4.4: Internal configuration
Description
HPLL2 SOFT-START 2.5V
function block built shown Figure 4.5. inverting input OTA. output connected BOP. internal clamp diode (5.3V) prevents from high voltages. Also, output compared BSENS. output this comparator sets flipflop that drives open collector stage BDRV. flip-flop reset HDRV. flip-flop edgetriggered device. recommended value load resistor BDRV 470.
HDRV
BDRV
DISCHARGE BSENS
Figure 4.5: Internal diagram control block
Application
function block used many different deflection topologies. common applications combined deflection/EHT circuit 14"/15" monitors (Figure 4.6) deflection generator with buckconverter (Figure 4.7). Another application deflection generator with boost-convertor, however this application tested (Figure 4.8). more detailed description other applications, Application Note AN96052: Converter Topologies Horizontal Deflection Generators' (see ref.
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
100E
TDA4853/54
BDRV
470E BC375
150µ 250V 120E
BZX79
250V BC376
BYV99 IRF9630
adj. BSENS
Optional damper
full circuit description ETV/AN96002, Modification Autosync Monitor MK-II Positive Flyback Pulse Concept, p.10
HSMOD/VSMOD Application
HFLB
Deflection
PR02 BAS11 BYD33D 150p AT4043_87A
PR01 220n
HDRV
BSN274
EW-AMP
EWDRV
Figure 4.6: Combined deflection/EHT circuit
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
100E
TDA4853/54
BDRV
470E 1N4148 BC375
150µ 250V 120E
BZX79
250V
BC376
250V
BYV99 IRF9630
adj. BSENS
core
full circuit description AN97032, Circuit description CCM420 monitor, p.22
100V BZX79 C6V8 NFR25 1N4148 HDRV 100E 680E EWDRV 220E BC375b 180n 630V AT4043_87A 470n 1N5822 STOCK07 +HDEFL
HFLB
BY459F
220n
-HDEFL
1N4148
Figure 4.7: Deflection generator with buck-convertor
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
TDA4853/54
BDRV +(++
BSENS
preferred! AN96052, Converter Topologies Horizontal Deflection with TDA4855/58, p.8:Table p.18/19 par.
EWDRV HFLB Horizontal Deflection
HDRV
Figure 4.8: Deflection generator with boost-converter
Lay-out
track that connected should short possible order limit EMI. This means that, resistor connected BIN, this resistor should close possible.
Bus-Controlled Autosync Deflection Controller TDA4853/54
7/25: PGND/SGND Description
Application Note AN97072
Power ground PGND connected substrate signal ground SGND must connected externally PGND.
Application Lay-out
connecting other components ground paths allowed
optimum performance, ground tracks should routed shown Figure 5.1. Only connection other ground tracks allowed.
horizontal section
vertical section
TDA4853/54
section Vout
BDRV
HDRV
Supply
connect only this path ground
Optional capacitors avoid crosstalk PCB-tracks BDRV HDRV must "see" each other.
Figure 5.1: Ground lay-out
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL VHDRV,
Application Note AN97072
HDRV Characteristics Internal configuration
CONDITIONS IHDRV IHDRV MIN. 45.5 TYP. 48.5 MAX. 51.5 UNIT
IHDRV,leak tHDRV,off
VHDRV IHDRV 31.45 IHDRV IHDRV
Figure 6.1: Internal configuration HDRV
Description
horizontal drive pulse (HDRV) open collector output that directly drive driver transistor. Optimised drive conditions achieved over whole frequency range slightly frequency-dependent duty cycle. output duty cycle will decrease supply voltage VHPLL2 drops below passes into floating state VHPLL2 decreases
Application
typical application shown Figure 6.2. more detailed description this horizontal drive application, application note AN96091: `Low Power Cost Horizontal Drive Circuits with Core' (see ref.
Horizontal deflection
HDRV 100E
470n
680E
220E
150n
Figure 6.2: Application HDRV
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL normal mode activation continuous blanking mode Vcc(min) continuous blanking mode disable HDRV, BDRV, VOUT1/2 HUNLOCK, SOFTST enable HDRV, BDRV, VOUT1/2 HUNLOCK IVcc IVcc, stand-by SOFTST reset; VPLL2 increasing from typ. SOFTST decreasing from typ. SOFTST decreasing from decreasing from
Application Note AN97072
Characteristics Internal Configuration
CONDITIONS MIN. TYP. MAX. UNIT
Figure 7.1: Internal configuration
Description
internal voltage stabilizer provides internal references with stabilised voltage. drops below (typically) 8.3V C-data been received after power-up, internal soft-start protection functions disable HDRV, BDRV, VOUT1/VOUT2 HUNLOCK. Also, internal C-bus will generate acknowledge SOFTST reset, forcing into stand-by mode. Figure Figure show this shut-down start-up sequence.
8.6V
typical values
continuous blanking activated (pin16 PLL2 soft-down sequence triggered
8.6V
typical values
continuous blanking PLL2 soft-start/-down enabled
8.1V
I2C-data accepted video clamping pulse disabled
8.3V
I2C-data accepted video clamping pulse enabled STDBY=0
3.5V
continuous blanking disappears
3.5V
continuous blanking activated (pin
Figure 7.2: Shut-down sequence
Figure 7.3: Start-up sequence
Bus-Controlled Autosync Deflection Controller TDA4853/54
during normal operation, drops below (typically) protection mode activated HUNLOCK passes into protection status (floating). This mode protects deflection stages tube during start-up, shut-down fault conditions. table right shows measures normal mode entered after protection occured. soft-start procedure activated C-bus, protection actions will performed well-defined sequence. This same sequence pulling HPLL2 ground, HPLL2 (pin 30). EVENT
supply voltage
Application Note AN97072
ACTION
increase supply voltage; reload registers; soft start C-bus.
Power (Vcc 8.1V)
reload registers; soft start C-bus.
XRAY (pin triggered
reload registers; soft start C-bus.
HPLL2 (pin externally pulled ground
release HPLL2 (pin
protection mode active, several pins forced into defined state: HUNLOCK (pin floating; Capacitor HPLL2 (pin discharged; HDRV (pin floating; BDRV (pin floating; VOUT1 VOUT2 (pin floating; CLBL (pin provides continuous blanking.
Protection mode changed into normal operation setting SOFTST=1.
Application
68uF
+12V
supply connected series resistor must decoupled electrolytic capacitor about 68uF, close possible itself (see Figure 7.4).
Figure 7.4: Input filter
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL VEWDRV,const bottom output Internally stabilised VEWDRV(max) maximum output
Application Note AN97072
EWDRV Characteristics Internal configuration
CONDITIONS register HPIN 0DEC register HCOR 04DEC register HTRAP 08DEC register HSIZE 255DEC Clipping control VOVSCN=1 VPOS extreme. Corner clipping vertical saw-tooth 110% nominal value MIN. 1.05 TYP. MAX. 1.35 UNIT
108E 108E
0.72
VEWDRV parabola
Frequency tracking from control FMULT=1, 31.45 Frequency tracking from control FMULT=1, Frequency tracking disabled control FMULT=0
1.42
1.42
Figure 8.1: Internal configuration EWDRV
VEWDRV parabola values VHPIN VHCOR VHTRAP, VHSIZE below VHPIN
Linearity error with frequency tracking (FMULT=1)
Nominal vertical settings (unless specified otherwise):
VSIZE=127DEC VOVSCN=0, VSMOD=0µA, VPC=1, VSC=1, VLC=1, HPC=1.
Register HPIN=0DEC Register HPIN=63DEC
0.04 1.42 0.08
VHCOR
Register HCOR=0DEC control VSC=0 Register HCOR=31DEC control VSC=0
-0.64
Bus-Controlled Autosync Deflection Controller TDA4853/54
Register HCOR=XDEC control VSC=1 VHTRAP Register HTRAP=0DEC Control VPC=0 Register HTRAP=15DEC Control VPC=0 Register HTRAP=XDEC Control VPC=1 VHSIZE Register HSIZE=0DEC Register HSIZE=255DEC VHSMOD IHSMOD -120 IHSMOD 0.13 0.69 0.02 -0.33 0.33
Application Note AN97072
Description
parabola wave-form EW-drive output controlled I2C-registers horizontal pincushion (HPIN), horizontal size (HSIZE), corner correction (HCOR) trapezium correction (HTRAP), well analogue input horizontal size modulation (HSMOD). HTRAP set/reset control HCOR control VSC. HPIN, HCOR HTRAP track with both vertical horizontal size (VSIZE/HSIZE), vertical position (VPOS) analogue modulation input HSMOD.
modes EWDRV operation chosen control FHMULT: FMULT=1: EWDRV wave-form tracks with horizontal frequency, used driving diode modulator stages which require voltage, proportional line frequency. FMULT=0: EWDRV wave-form does track with horizontal frequency, used modulators that need voltage, independent line frequency (e.g. converter circuits).
Figure Figure show effect register values EWDRV voltage wave-form.
EWDRV
EWDRV HPIN HCOR
vertical period vertical period
Figure 8.2: Corner correction
Figure 8.3: Pincushion
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
EWDRV HTRAP
14.4V
HSMOD effect
hypothetical area
HSMOD
clipping
7.0V HSMOD
vertical period
Figure 8.4: Trapezium correction
HSMOD HSIZ
bottom
1.2V vertical period
Figure 8.5: Size adjustment effect HSMOD
Application
EWDRV used modes: With line frequency tracking: FMULT=1, EWDRV used feed amplifier that controls amplitude horizontal deflection. This horizontal option used combined +165V +12V deflection EHT/deflection applications that circuit diode modulator. application shown Figure 300k 180k 8.6. This also described Application Note `Modification 160k Autosync Monitor MK-II Positive Feedback-Pulse Concept', ETV/AN96002 (see ref. which update Application Note AN95086 (see ref.
Figure 8.6: Application EWDRV with frequency tracking
EWDRV
EWDRV
Without line frequency tracking: FMULT=0, this used separate EHT/deflection systems. this case, application consists resistor (pin Figure 8.7. value resistor typically 56k. other applications, Application Notes: Topologies Horizontal Deflection with TDA4855/58', AN96052, ref. `Circuit Description CCM420 Monitor', AN97032, ref.
Figure 8.7: Application EWDRV without frequency tracking
Bus-Controlled Autosync Deflection Controller TDA4853/54
SYMBOL IVOUT Ivout1 Ivout2
(peak-peak value)
Application Note AN97072
VOUT2 VOUT1 Characteristics Internal configuration
CONDITIONS Nominal vertical settings: MIN. 0.76 TYP. 0.85 MAX. 0.94 UNIT
VSIZE=127DEC VOVSCN=0, VSMOD=0µA, VPC=1, VSC=1, VLC=1, HPC=1.
Ivout1(max), Ivout2(max) VVOUT1, VVOUT2 Voffset Vlinearity vertical size
Control VOVSCN=1 allowed voltage Nominal vertical settings Nominal vertical settings Nominal vertical settings; register VSIZE 0DEC, VOVSC Nominal vertical settings; register VSIZE 127DEC, VOVSC
0.54
0.66 ±2.5 ±1.5
Figure 9.1: Vertical current outputs
vertical size
Nominal vertical settings; register VSIZE 0DEC, VOVSC Nominal vertical settings; register VSIZE 127DEC, VOVSC
115.9
116.8
117.7
vertical size
IVSMOD IVSMOD -120
-11.5
vertical shift, referred vertical size 100%
register VPOS 0DEC,
register VPOS 127DEC, register VPOS XDEC,
11.5
Bus-Controlled Autosync Deflection Controller TDA4853/54
Description
Application Note AN97072
vertical outputs VOUT1 VOUT2 differential current outputs, superimposed common bias current source amplitude adjusted register VSIZE modulation input VSMOD compensation, Figure 9.2. VGA350 mode, register VOVSCN activate increase vertical size.
Vout1 VSIZE VSMOD
Vout1
VPOS
Vout2
Vout2
vertical period
vertical period
Figure 9.2: VOUT1 VOUT2 with size adjustment compensation
Figure 9.3: VOUT1 VOUT2 with position adjustment VPOS
Vertical position adjusted register VPOS, depicted Figure 9.3. vertical size position also affect EWDRV output, focus parabola, vertical linearity vertical linearity balance. this way, re-adjustment these parameters necessary after altering vertical size position.
Vout1 VLINBAL
Vout1 VLIN
Vout2 Vout2
vertical period vertical period
Figure 9.5: VOUT1 VOUT2 with linearity balance adjustment VLINBAL
Figure 9.4: VOUT1 VOUT2 with linearity adjustment VLIN
Vertical linearity adjustable register VLIN (see Figure 9.4) switched control VSC. same holds vertical S-correction unbalance, adjusted register VLINBAL (see Figure 9.5) switched on/off control VLC.
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application
Application Note AN97072
TDA4854 TDA4861 Deflection
differential output currents VOUT1 VOUT2 directly coupled vertical deflection boosters with differential current inputs, such TDA8354 TDA4866. Other boosters which have traditional op-amp configuration (e.g. TDA4861) need interface shown Figure 9.6.
Figure 9.6: Interface VOUT1 VOUT2 with vertical booster
Lay-out
output deflection controller 100E 100p 100E 100p input booster TDA4866
tracks should short possible. loop area, formed tracks from VOUT1, VOUT2, BOOSTER_IN1 BOOSTER_IN2, should small possible. This means that tracks from VOUT1 BOOSTER_IN1 VOUT2 BOOSTER_IN2 should close possible another. tracks longer than approximately used, both outputs TDA4853/54 well inputs booster should filtered prevention.This shown Figure booster with current inputs Figure booster with voltage inputs. should close IC's pins possible.
Figure 9.7: prevention with booster current inputs
100E 100p
output deflection controller
input booster TDA8351/4861
Figure 9.8: prevention with booster voltage inputs
Bus-Controlled Autosync Deflection Controller TDA4853/54
10.1
SYMBOL VVSYNC
Application Note AN97072
VSYNC Characteristics Internal configuration
CONDITIONS input signal slicing level MIN. polarity change 0.45 TYP. MAX. UNIT
IVSYNC tVSYNC(max) tdelay(VPOL)
VSYNC 5.5V
100E 1.4V 7.3V
Figure 10.1: Internal configuration VSYNC
10.2
Description
Vertical synchronisation input (VSYNC) slices signals 1.4V. output vertical sync slicer goes into polarity normaliser. Then OR-ed with vertical sync pulses generated vertical integrator which extracts vertical sync from composite sync applied H/C-sync. output this OR-function vertical oscillator.
10.3
Application
VSYNC input/ VSYNC microcontroller VSYNC
VSYNC connected directly vertical sync input vertical sync output microcontroller series resistor. Tracks should kept short possible. tracks longer than approximately input filter should implemented, shown Figure 10.2.
Figure 10.2: Input filter VSYNC
Bus-Controlled Autosync Deflection Controller TDA4853/54
11.1
SYMBOL tHSYNC(max) Thorizontal tdelay(HPOL) DC-coupled signals VHSYNC input signal slicing level IHSYNC VHSYNC 0.8V VHSYNC 5.5V tW_HSYNC(min) trise_HSYNC tfall_HSYNC AC-coupled video signals VHSYNC input signal slicing level source) Vclamp_HSYNC Icharge_HSYNC tW_HSYNC(min) Rsource(max) rdiff_HSYNC duty cycle during sync sync clamping level VHSYNC Vclamp_HSYNC 1.28 1500 -200
Application Note AN97072
HSYNC Characteristics Internal configuration
CONDITIONS MIN. TYP. MAX. UNIT
1.28V
1.4V
Figure 11.1: Internal configuration HSYNC
11.2
Description
HSYNC
slicing level 1.4V 120mV
Horizontal sync input (HSYNC) handle both DCcoupled signals (horizontal composite sync) AC-coupled negative-going video sync signals. DC-coupled signals sliced have limited input current. AC-coupled syncs clamped 1.28 sliced resulting fixed absolute slicing level 120mV, Figure 11.2. both input signals, separated sync signal integrated polarity normalised. Normalised horizontal sync pulses
clamping level 1.28V
horizontal period
Figure 11.2: HSYNC with AC-coupled input
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
vertical sync integrator, PLL1 phase detector frequency locked loop. Equalisation pulses prohibited correct functioning PLL1 phase detector.
11.3
Application
HSYNC connected directly horizontal sync input, horizontal sync output microcontroller series resistor green colour channel Sync-On-Green (SOG) application. Tracks should kept short possible. tracks longer than approximately input filter should implemented, shown Figure 11.3.
HSYNC input HSYNC microcontroller
HSYNC
Figure 11.3: Input filter HSYNC
Bus-Controlled Autosync Deflection Controller TDA4853/54
12.1
SYMBOL Vclamp tclamp slope clamp pulse tdelay_clamp
Application Note AN97072
CLBL Characteristics Internal configuration
CONDITIONS level VCLBL 20pF trailing edge horizontal sync; control CLAMP VCLBL MIN. 4.32 TYP. 4.75 MAX. 5.23 UNIT ns\V
Figure 12.1: Internal configuration CLBL
tclamp(max)
trailing edge horizontal sync; control CLAMP VCLBL
tclamp(max)
leading edge horizontal sync; control CLAMP VCLBL
0.15
tdelay_clamp
leading edge horizontal sync; control CLAMP VCLBL
VCLBL_blank tCLBL
blank
level control VBLK
(also
HUNLOCK) tCLBL
blank
(also
control VBLK
HUNLOCK) VCLBL_vscan ICLBL_sink ICLBL_source ICLBL 0.59 0.63 0.67 -3.0
12.2
Description
video clamping/vertical blanking signal CLBL sand-castle pulse which especially suitable video controllers, such TDA488x-family, also direct application video output stages. signal consists levels (see Figure 12.2):
Bus-Controlled Autosync Deflection Controller TDA4853/54
4.75V
Application Note AN97072
CLBL
1.9V 0.63V clamp pulse vertical blanking
upper level (4.75 video clamping, triggered trailing leading edge horizontal sync pulse C-selectable control CLAMP). Pulse width determined internal monoflop. lower level (1.9 vertical blanking, derived directly from internal oscillator wave-form.
Figure 12.2: Timing diagram CLBL
Continuous blanking will activated following conditions true: Soft start horizontal drive (HPLL2 (pin pulled down, externally C-bus); Frequency-locked loop search mode (PLL1 unlocked); horizontal flyback pulses HFLB (pin X-ray protection activated; Supply voltage (pin below
Horizontal unlock blanking switched control BLKDIS while vertical blanking protection blanking remain.
12.3
Application
CLBL output used applications: Coupled clamping/blanking inputs video controller TDA488x series resistor 100. These video controllers extract vertical blanking with negligible delay. However, (additional) vertical blanking grid wanted, CLBL less suitable because delay that caused filtering 4.75V clamping pulses. this case recommended HUNLOCK signal (pin 17). Directly output amplifier black level stabilisation.
Bus-Controlled Autosync Deflection Controller TDA4853/54
13.1 HUNLOCK Characteristics Internal configuration
Application Note AN97072
SYMBOL VHUNLOCK level VHUNLOCK,BLANK vertical blanking IHUNLOCK sink/source current IHUNLOCK,LEAK
CONDITIONS internal sink current saturation voltage with locked PLL1 internal sink current
MIN.
TYP.
MAX.
UNIT
VHUNLOCK
VHUNLOCK with PLL1 unlocked and/or protection active
Figure 13.1: Internal configuration HUNLOCK
13.2
Description
HUNLOCK indicates lock situation PLL1. This occur either search/protection mode range situation. detected microcontroller external pull-up resistor applied +5V, because HUNLOCK will floating case lock situation. Additionally, HUNLOCK will generate fast vertical blanking signals Unlock blanking switched control BLKDIS, while vertical blanking remains. This necessary enabling on-screen display case missing/wrong sync. HUNLOCK signals depicted Figure 13.2.
HUNLOCK
200mV 200mV
vertical blanking BLKDIS=1
lock/ protection BLKDIS=0
Figure 13.2: HUNLOCK wave-forms
Bus-Controlled Autosync Deflection Controller TDA4853/54
13.3 Application
Application Note AN97072
HUNLOCK used three purposes: fast vertical blanking grid1 during normal operation. pulse amplified transistor Note: this situation transistor fully conducting. protection blanking HUNLOCK floating pulled output voltage determined ratio R3+R4. this situation transistor blocked consequently will drop quickly -200 Volt, blanking picture completely. Information microprocessor. Note: vertical blanking 1Volt will recognized input microprocessor. Note: microprocessor needs 3.3V input, dashed connection should used.
+11V
MPSA92 BC548 120k
HUNLOCK 3.3V Microcontroller
Full grid1 blanking will also occur when Volt supply lowered. good spot suppression power switch off, recommended connect supply circuit Figure 13.3 supply vertical output stage, because this disappears quicker than supply voltage TDA4853/54.
-200V
Figure 13.3: HUNLOCK application with
Bus-Controlled Autosync Deflection Controller TDA4853/54
14.1 Internal configuration
Application Note AN97072
Figure 14.1: Internal configuration
Figure 14.2: Internal configuration
14.2
Description
characteristics application C-bus clock input (SCL) data input (SDA) described detail Philips data handbook IC12: Peripherals' (see ref.
14.3
Application
inputs connected series resistor SDA/SCL lines master. C-bus controlled software interface-board necessary. This software interface described Laboratory Report ETV8835: `User's Guide C-bus Control Programs' (see ref. register contents changed during vertical scan, this might result visible interference screen. cause this interference abrupt change picture geometry which takes effect random locations within visible picture. avoid this kind interference, least adjustment critical geometry parameters HSIZE, HPOS, VSIZE VPOS should synchronized with vertical flyback. This should done such way, that adjustment change takes effect during vertical blanking time. very slow interfaces, might neccessary delay transmission last byte only last bit) message until start V-sync V-blanking.
V-sync V-blanking parameter change takes effect
Figure 14.3: I2C-control
Bus-Controlled Autosync Deflection Controller TDA4853/54
15.1
SYMBOL VASCOR maximum output VASCOR centre output VASCOR,min minimum output VASCOR maximum output swing IASCOR maximum output current VHPARAL VHPINBAL values below VASCOR,HPARAL vertical saw-tooth Nominal vertical settings (unless specified otherwise): -1.5 +0.05
Application Note AN97072
ASCOR Characteristics Internal configuration
CONDITIONS MIN. TYP. MAX. UNIT
480E
Figure 15.1: Internal configuration ASCOR
VSIZE=127DEC VOVSCN=0, VSMOD=0µA, VPC=1, VSC=1, VLC=1, HPC=1.
Register HPARAL=0DEC control HPC=0 Register HPARAL=15DEC control HPC=0 Register HPARAL=XDEC control HPC=1 0.05 0.825 -0.825
VASCOR,HPINBAL vertical parabola
Register HPINBAL=0DEC Control HBC=0 Register HPINBAL=15DEC Control HBC=0 Register HPINBAL=XDEC Control HBC=1
-1.0
0.05
15.2
Description
Asymmetric EW-correction (ASCOR) voltage output superimposed wave-forms vertical parabola saw-tooth. Amplitude polarity controlled horizontal parallelogram (register HPARAL) horizontal unbalance (register HPINBAL). Figure 15.2 Figure 15.3 show ASCOR with adjustment registers HPARAL parallelogram correction HPINBAL vertical centre-line adjustment.
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
ASCOR
ASCOR
HPARAL
HPINBAL
vertical period
vertical period
Figure 15.2: ASCOR with parallelogram correction
Figure 15.3: ASCOR with unbalance correction
Asymmetric correction achieved internal modulation PLL2 horizontal phase (control ACD=1) external DC-shift horizontal deflection (control ACD=0). tube used that does need asymmetric corrections, ASCOR also serve other purposes.
15.3
Application
Three different applications ASCOR possible: Control ACD=0: asymmetric correction achieved feeding ASCOR DC-amplifier that controls DC-shift horizontal deflection means DC-shift transformer. Control ACD=1: asymmetric correction achieved internal modulation PLL2 horizontal phase. ASCOR left unused, because correction performed internally. this case, control range HPARAL HPINBAL increased application Figure 15.4. Start values are: R=330k C=100nF. Increase smaller adjustment range. soft-start time increased about with values mentioned. Note: bending vertical line occurs maximum HPARAL amplitude, reduce capacitor value until minimum Farad. Control ACD=0: asymmetric correction used. tube does need parallelogram unbalance correction, ASCOR used other applications, e.g. convergence vertical focus.
ASCOR HPLL2
12nF
Figure 15.4: Increase HPARAL/HPINBAL control range
Bus-Controlled Autosync Deflection Controller TDA4853/54
VSMOD
Application Note AN97072
16.1
SYMBOL vertical size
Characteristics Internal configuration
CONDITIONS IVSMOD IVSMOD -120 MIN. TYP. MAX. UNIT
Vref(VSMOD) RVSMOD BVSMOD
250E
Figure 16.1: Internal configuration VSMOD
16.2
Description
Vertical size modulation (VSMOD) analogue modulation input size compensation with changing EHT. case combined EHT/deflection application, used compensate load variations. Modulation this will result vertical size reduction Note: polarity VSMOD (and HSMOD) inverted, compared VAMP (and EWWID) TDA4855. Size reduction achieved correcting differential output currents VOUT1 VOUT2. does affect wave-forms, vertical focus, unbalance parallelogram corrections. Figure 16.2 shows vertical current outputs function modulation VSMOD case full white picture screen.
Vout1
I=0uA VSMOD I=-120uA
Vout2
vertical period
Figure 16.2: Vertical Output Currents function VSMOD
Bus-Controlled Autosync Deflection Controller TDA4853/54
16.3 Application
Application Note AN97072
load unstabilized increases, voltage will decrease thus, vertical size will increase. This increased size compensated sinking current from VSMOD. Variation current VSMOD from -120µA will result vertical size variation actual size differential output currents. Load variations compensated possible applications: parallel capacitor bleeder present transformer. With divider buffer, 1information transferred VSMOD. This best solution, because signal does phase. application VSMOD implemented shown Figure 16.3.
600M 220k 4.5V 100k
EHT(25kV load) +12V BC548 BC558 HSMOD VSMOD
/100V
Figure 16.3: VSMOD application with divider
This divider creates base voltage within range voltage HSMOD. decrease voltage will result voltage over sinking current from HSMOD. time constants divider (C1*R1 C2*R2) should equal. values should recalculated contains other component values should have leakage current µA). full VSMOD control range with voltage drop (2.5kV), value will 3k9.
optimised dimensioning follow next steps: Adjust HSMOD application values; Display white (about width height), flashing on/off about 1Hz, white border line reference (see Figure 16.4); Adjust optimised vertical size correction displacement border line screen) apply this value fixed resistor.
white border white white border white border white white border
Without compensation
With compensation
Figure 16.4: Screen view effect VSMOD
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
footpoint transformer (not grounded) used information resistor. This solution will, however, result VSMOD phase therefor, geometry compensation will optimal. application VSMOD this case depicted Figure 16.5. footpoint equal voltage HSMOD. variation beam current from 700µA will result voltage drop over 700µ*5k6 Now, value calculated, because equal voltage drop over should sink 120µA from HSMOD: 4\120µ 33k. time constant created should between horizontal vertical period ms).
VSMOD
HSMOD
Figure 16.5: Application VSMOD Current Sense
optimised dimensioning follow next steps: Adjust HSMOD application values; Display white (about width height), flashing on/off about white border line reference (see Figure 16.4); Adjust optimised vertical size correction displacement border line screen) apply this value fixed resistor.
slight interaction from VSMOD HSMOD vice versa possible. This VSMOD/HSMOD application concept also used beam current limiting (BCL).
16.4
Lay-out
both applications, tracks should short possible, especially track from resistor VSMOD. This resistor Figure 16.3 Figure 16.5. these tracks longer then approximately input filtering will necessary order eliminate possible problems. This done input filter, shown Figure 16.6, where should close possible input pin.
Application Control Current 100E 100p VSMOD
Figure 16.6: filtering VSMOD
Bus-Controlled Autosync Deflection Controller TDA4853/54
17.1
SYMBOL free-running
Application Note AN97072
VAGC VREF VCAP Characteristics Internal configuration
CONDITIONS RVREF CVCAP MIN. TYP. MAX. 43.3 UNIT
catching range tscan delay between trigger pulse start VCAP ramp tscan delay
RVREF control VBLK
control VBLK
Figure 17.1: Internal configuration VAGC
VVREF CVAGC IVAGC control AGDIS control AGDIS
Figure 17.2: Internal configuration VREF
Figure 17.3: Internal configuration VCAP
17.2
Description
Vertical automatic gain control done VAGC, which disabled resetting control AGCDIS. vertical reference input VREF determines vertical free-running frequency connecting resistor ground, together with capacitor CVCAP VCAP.
Bus-Controlled Autosync Deflection Controller TDA4853/54
17.3 Application
Application Note AN97072
vertical oscillator amplitude
capacitor CVCAP connected vertical capacitor VCAP input determines freerunning vertical frequency, together with resistor RVREF VREF. Figure 17.4 shows determine value CVCAP. Note: stable internal references well optimised noise linearity performance, always apply value VREF.
42Hz -10% 50Hz 160Hz
spread Cvcap: Rvref:
safety margin
application vertical automatic gain control VAGC consists capacitor with value ground. VAGC should loaded externally order avoid non-linearities vertical size. Application VAGC, VREF VCAP shown Figure 17.5.
VAGC VREF VCAP
Cvcap
10.8*Rvref*f
10.8*22k*42 100nF
150. 220nF Cvagc
100nF Rvref Cvcap
Figure 17.4: Vertical (free-running) frequency
Figure 17.5: Application VAGC/VREF/VCAP
Bus-Controlled Autosync Deflection Controller TDA4853/54
18.1
SYMBOL tHPLL1,lock IHPLL1 level locked mode level locked mode VHBUF fH(min) fH(max) VHREF ffree-running testing only fH(max) RHBUF RHREF 2.4k; CHCAP 10nF.
Application Note AN97072
HPLL1 HBUF HREF HCAP Characteristics Internal configuration
CONDITIONS MIN. 2.43 30.53 TYP. 2.55 31.45 MAX. 2.68 32.39 UNIT
4.4V
Figure 18.1: Internal configuration HPLL1
7.7V
2.525V
Figure 18.2: Internal configuration HBUF Figure 18.3: Internal configuration HREF/HCAP
18.2
Description
HPLL1 loop filter input horizontal phase locked loop PLL1, that synchronises horizontal oscillator with HSYNC. oscillator frequency deviates more than HSYNC, PLL1 goes into search mode. After tuning horizontal oscillator, PLL1 goes into soft-lock mode during vertical period then passes into normal operation.
Bus-Controlled Autosync Deflection Controller TDA4853/54
minimum horizontal frequency determined capacitor HCAP resistor HREF. Because capacitor value fixed nF), minimum frequency actually determined resistor RHREF only. Horizontal frequency range determined resistor RHBUF from HBUF HREF. Figure 18.4 shows determine minimum maximum frequency calculating RHREF RHBUF. TV-mode centred around fmin (pin HBUF floating) with control range ±10%. This mode only allowed between 15.625 kHz.
Application Note AN97072
2.5V
HBUF
0.5V calculation spread Cvcap: Rvref: calculation spread Cvcap: Rvref:
Figure 18.4: Determination minimum/maximum frequency
18.3
Application
PLL1 loop filter connected HPLL1 (see Figure 18.5). These values optimised jitter. scan time search mode determined 100nF capacitor. allowed load HPLL1 externally. application HBUF/HREF/HCAP shown Figure 18.6.
HCAP HREF HBUF Rhbuf
HPLL1
100n
Rhref Chcap 10nF
Figure 18.5: Application HPLL1
Figure 18.6: Application HREF/HBUF/HCAP
equations below show calculate RHBUF RHREF.
RHREF
5k28
fmin [kHz] 15.625
RHBUF
1k26
fmax [kHz]
HREF
0.0012 [kHz] 0.0012 [kHz] 0.0012 [kHz]
HREF HBUF HREF
1k51 1k02
2k56
31.45
1k85 1k16
Some common values maximum/minimum frequencies corresponding values RHBUF RHREF shown table right.
Bus-Controlled Autosync Deflection Controller TDA4853/54
19.1
SYMBOL PLL2 advance horizontal drive w.r.t. middle horizontal flyback minimum advance; register HPINBAL=07DEC; register HPARAL=07DEC. IPLL2 sPLL2 (relative sensitivity PLL2, w.r.t. horizontal period) VHPLL2(max) IPLL2,charge Capacity protection/soft start mV/%
Application Note AN97072
PLL2 Characteristics Internal configuration
CONDITIONS maximum advance; register HPINBAL=07DEC; register HPARAL=07DEC. MIN. TYP. MAX. UNIT 7.7V
6.25V
Figure 19.1: Internal configuration HPLL2
19.2
Description
PLL2 phase detector compares HFLB input oscillator's saw-tooth voltage adjusts phase HDRV, compensating delay external horizontal deflection circuit (e.g. storage time variations). HPLL2 used soft-start, protection power-down modes pulling HPLL2 ground, externally DC-current internally resetting register SOFTST. Figure 19.2 Figure 19.3 show soft-start soft-down sequences. soft-start only performed supply voltage least
4.6V
4.6V
HPLL2
typical values duty cycle increase
continuous blanking PLL2 enabled frequency detector enabled HDRV/HFLB protection enabled
HPLL2
continuous blanking activated PLL2 disabled frequency detector disabled HDRV/HFLB protection disabled
3.3V
typical values
BDRV duty cycle nominal value
BDRV duty cycle starts decrease
BDRV duty cycle starts increase HDRV duty cycle nominal value
duty cycle increase
BDRV floating HDRV duty cycle starts decrease
1.7V HDRV duty cycle starts increase Vout1/Vout2 enabled
44.4
1.7V
HDRV floating Vout1/Vout2 disabled
Figure 19.2: Soft-start sequence
Figure 19.3: Soft-down sequence
Bus-Controlled Autosync Deflection Controller TDA4853/54
19.3 Application
Application Note AN97072
application HPLL2 consists capacitor ground, which should changed optimal internal functionality. This filter capacitor determines soft-start timing.
Bus-Controlled Autosync Deflection Controller TDA4853/54
20.1
SYMBOL VEWDRV,const
Application Note AN97072
HSMOD Characteristics Internal configuration
CONDITIONS IHSMOD HSIZE=255DEC IHSMOD -120 HSIZE=255DEC 0.69 MIN. TYP. 0.02 MAX. UNIT
250E
Vref(HSMOD) RHSMOD BHSMOD
Figure 20.1: Internal configuration HSMOD
20.2
Description
14.4
HSMOD effect
hypothetical area
HSMOD
Horizontal size modulation (HSMOD) analogue input horizontal deflection correction. used combined EHT/deflection systems compensate ripple deflection supply, caused load variations. Modulation this input will result linear variation drive output (EWDRV). control range this input tracks with actual value C-controlled register HSIZE. Note: polarity HSMOD (and VSMOD) inverted, compared EWWID (and VAMP) TDA4855. Figure 20.2 shows EWDRV output function HSMOD input, depending DCcomponent EWDRV. Figure 20.3 shows screen view, displaying white bar. corresponding EWDRV wave-form with compensation HSMOD depicted Figure 20.4.
clipping level
7.0V HSMOD
EWDRV
VHSMOD VHSIZE bottom level vert. period
Figure 20.2: EWDRV with modulation HSMOD
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
EWDRV
Figure 20.3: White screen without with compensation HSMOD
HSMOD
VHSMOD VHSMOD
HSMOD 0.69V HSIZE ;FHMULT=0 120µA 14.4 HSMOD 0.69V HSIZE HREF ;FHMULT=1 120µA 14.4 2.36mA
vertical period
Figure 20.4: EWDRV output with white compensation HSMOD
20.3
Application
load increases, voltage will decrease thus, horizontal size will increase. This increased size compensated sinking current from HSMOD. Variation current HSMOD from -120µA will result horizontal size variation 0.02 0.69 EWDRV. Load variations compensated possible applications: parallel capacitor bleeder present transformer. With divider buffer, 1information transferred HSMOD. This best solution, because signal does phase. application HSMOD implemented shown Figure 20.5. This divider creates base voltage within range voltage HSMOD. decrease voltage will result voltage over sinking current from HSMOD. time constants divider (C1*R1 C2*R2) must equal. values should recalculated contains other component values should have leakage current µA). full HSMOD control range with voltage drop (2.5kV), value will 3k9.
600M 220k 4.5V 100k
EHT(25kV load) +12V BC548 BC558 HSMOD VSMOD
/100V
Figure 20.5: HSMOD application with divider
Bus-Controlled Autosync Deflection Controller TDA4853/54
Application Note AN97072
optimised dimensioning follow next steps: Adjust horizontal size, pincushion, corner trapezium correction optimised values; Display white (about width height); Adjust optimised horizontal size correction apply this value fixed resistor.
optimised alignment, base should
HSMOD
VSMOD
Figure 20.6: Application HSMOD Current Sense
footpoint transformer (not grounded) used information resistor. This solution will, however, result HSMOD phase therefor, geometry compensation will optimal. application HSMOD this case depicted Figure 20.6. footpoint equal voltage HSMOD. variation beam current from 700µA will result voltage drop over 700µ*5k6 Now, value calculated, because equal voltage drop over should sink 120µA from HSMOD: 4/120µ 33k. time constant created should between horizontal vertical period ms). optimised dimensioning (and R3), follow next steps:
Display cross hatch pattern; Adjust horizontal size, pincushion, corner trapezium correction optimised values; Display white (about width height); Adjust optimised horizontal size correction apply this value fixed resistor.
slight interaction from HSMOD VSMOD vice versa possible. This HSMOD/VSMOD application concept also used beam current limiting (BCL).
20.4
Lay-out
both applications, tracks should short possible, especially track from resistor HSMOD. This resistor Figure 20.5 Figure 20.6. these tracks longer then approximately input filtering will necessary order eliminate possible problems. This done current input filter, shown Figure 20.7, where should close input possible.
Application Control Current
100E 100p
HSMOD
Figure 20.7: filtering HSMOD
Bus-Controlled Autosync Deflection Controller TDA4853/54
21.1
SYMBOL FOCUS maximum output FOCUS minimum output HFOCUS output swing register HFOCUS=31DEC VFOCUS output swing Nominal vertical settings: 0.02 register HFOCUS=0DEC 0.06 IFOCUS
Application Note AN97072
FOCUS (TDA4854 ONLY) Characteristics
CONDITIONS IFOCUS MIN. TYP. MAX. UNIT
120E 200E
120E
VSIZE=127DEC VOVSCN=0, VSMOD=0µA, VPC=1, VSC=1, VLC=1, HPC=1.
register VFOCUS=0DEC Nominal vertical settings register VFOCUS=07DEC
IFOCUS maximum output current CFOCUS (maximum capacitive load) tprecorr
tdelay
±1.5
Figure 21.1: Internal configuration FOCUS
1.9µs tflyback 5.5µs tflyback 12.5µs
TV-mode
Bus-Controlled Autosync Deflection Controller TDA4853/54
21.2 Description
Application Note AN97072
HFLB
Focus output focus correction
FOCUS voltage output dynamic focus applications. Both vertical (register VFOCUS) horizontal (register HFOCUS) parabolas adjusted. horizontal parabola independent horizontal frequency, changing horizontal size require correction HFOCUS. vertical parabola frequency-independent tracks with vertical adjustments. phase advance horizontal parabola implemented compensate delay external focus amplifier, illustrated Figure 21.2.
Figure 21.2: Phase advance FOCUS
21.3
Application
Focus Amplifier
FOCUS used drive focus amplifier, connected Dynamic Focus input LOT. Figure 21.3 shows possible application FOCUS pin, which optional focus amplifier implemented. inverting amplifier should have gain 100-150, determined This amplification depends tube's focus specification. Capacitor adjusts delay focus amplifier, enabling correct matching pre-delay actual delay. more detailed application focus amplifier, Application Note AN97032: `Circuit Description CCM420 Monitor' Verhees
FOCUS 100-150x Dynamic Focus
Figure 21.3: Application FOCUS
Bus-Controlled Autosync Deflection Controller TDA4853/54
22.1 INTERNAL PROTECTION
Application Note AN97072
Pins have internal protection circuit shown Figure 22.1.
Figure 22.1: Internal protection pins 4,11,12,13,16
22.2
18-24 26-32
Pins 18-24 26-32 have internal protection circuit shown Figure 22.2.
7.3V
7.3V
Figure 22.2: Internal protection 18-24 26-32
Bus-Controlled Autosync Deflection Controller TDA4853/54
SOFTWARE CONTROL
Application Note AN97072
software engineers, flowdiagram given data sheet simplified.
(Re)start
Check fault condition
Goto Standby-mode
STDBY SOFTST=0
H-SYNC PRESENT STABLE?
STDBY SOFTST=0
LOAD OTHER REGISTERS
HUNLOCK=1? WAIT 80ms (note
WAIT 80ms (note (Re)start
STDBY SOFTST=0
STDBY SOFTST=1
Figure 23.1: Flowdiagram software control
Notes:
supply voltage Volt, there will acknowledge. status register; bits STDBY SOFTST changed internally (e.g. protection supply) externally I2C, they read back. Refresh/reload/update allowed registers times, except command register 0DHEX. Loading control bits STDBY SOFTST never allowed. Synchronize data transfer with Vsync. This prevents visible disturbances. also description (pin 18/19). Allow stabilisation internal operation. Allow soft stop drive signals HDRV BDRV.
Bus-Controlled Autosync Deflection Controller TDA4853/54
Ref. Ref. Ref. Ref. Ref. Ref. Ref.
Application Note AN97072
REFERENCES
ETV/AN96002: `Modification Autosync Monitor Mk-II Positive Flyback Concept' Groot-Hulze, issued November 1996 AN95086: `PCALE Autosync Monitor Mk-II Circuit Description` Misdom, issued September 1995 Data Handbook IC12: Peripherals', issued October 1995 ETV8835: `User's Guide Control Programs' Demmers, issued December 1988 AN96091: `Low Power Cost Horizontal Drive Circuits with Core' Vaneerdewegh, issued August 1996 AN96052: Converter Topologies Horizontal Deflection Generators' Verhees, issued September 1996 AN97032: `Circuit Description CCM420 Monitor' Verhees

AN97072 Bus-Controlled Autosync Deflection Controller TDA4853/54

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