AN10216-01 MANUAL Abstract Manual provides broad overview va
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AN10216-01 Manual
AN10216-01
MANUAL
Abstract Manual provides broad overview various serial buses,
should considered, technical detail works, previous limitations/solutions, comparison SMBus, Intelligent Platform Management Interface implementations, review different devices that available patent/royalty information. Manual presented during hour TecForum DesignCon 2003 Jose, January 2003.
Jean-Marc Irazabal Technical Marketing Manager Steve Blozis International Product Manager
Specialty Logic Product Line Logic Product Group
Philips Semiconductors
March 2003
AN10216-01 Manual
TABLE CONTENTS
TABLE CONTENTS OVERVIEW DESCRIPTION SERIAL OVERVIEW.4 UART OVERVIEW.6 OVERVIEW.6 OVERVIEW OVERVIEW.9 1394 OVERVIEW OVERVIEW SERIAL COMPARISON SUMMARY THEORY OPERATION TERMINOLOGY.13 START STOP CONDITIONS HARDWARE CONFIGURATION COMMUNICATION.14 TERMINOLOGY TRANSFER DESIGNER BENEFITS MANUFACTURERS BENEFITS OVERCOMING PREVIOUS LIMITATIONS ADDRESS CONFLICTS CAPACITIVE LOADING (ISOLATION) VOLTAGE LEVEL TRANSLATION INCREASE RELIABILITY (SLAVE DEVICES).21 INCREASING RELIABILITY (MASTER DEVICES).22 CAPACITIVE LOADING (BUFFER).22 LIVE INSERTION INTO LONG LENGTHS PARALLEL CONTROLLER DEVELOPMENT TOOLS EVALUATION BOARD OVERVIEW.26 PURPOSE DEVELOPMENT TOOL EVALUATION BOARD WIN-I2CNT SCREEN EXAMPLES.28 ORDER 2002-1A EVALUATION COMPARISON WITH SMBUS I2C/SMBUS COMPLIANCY DIFFERENCES SMBUS SMBUS INTELLIGENT PLATFORM MANAGEMENT INTERFACE (IPMI) INTEL SERVER MANAGEMENT.33 PICMG VMEBUS DEVICE OVERVIEW RECEPTION.36 RADIO RECEPTION
AN10216-01 Manual
AUDIO PROCESSING DUAL TONE MULTI-FREQUENCY (DTMF).37 DISPLAY DRIVER LIGHT SENSOR REAL TIME CLOCK/CALENDAR GENERAL PURPOSE EXPANDERS DIMMERS BLINKERS SWITCH MULTIPLEXERS SWITCHES.43 VOLTAGE LEVEL TRANSLATORS REPEATERS HUBS SWAP BUFFERS EXTENDERS ELECTRO-OPTICAL ISOLATION RISE TIME ACCELERATORS PARALLEL CONTROLLER DIGITAL POTENTIOMETERS ANALOG DIGITAL CONVERTERS SERIAL RAM/EEPROM HARDWARE MONITORS/TEMP VOLTAGE SENSORS MICROCONTROLLERS PATENT LEGAL INFORMATION ADDITIONAL INFORMATION APPLICATION NOTES.50
AN10216-01 Manual
OVERVIEW
Description
Philips Semiconductors developed over years extensive collection specific general purpose devices. This application note developed from hour long Overview TecForum presentation DesignCon 2003 Jose, January 2003 provides broad overview compares other serial buses, works, ways overcome previous limitations, uses such Intelligent Platform Management Interface, overview various different categories devices patent/royalty information. Full size Slides posted file Philips Logic collateral site DesignCon 2003 TecForum Overview file. Place holder title slides have been removed from this application note some slides with text have been incorporated into application note speaker notes. Serial Overview
three shared signal lines, timing, data, R/W. selection communicating partners made with separate wire each chip. number chips grows, selection wires. next stage multiplexing selection wires call them address bus. there address wires select devices using `one 256' decoder parallel system there could more) data wires. Taken next step, share function wires between addresses data starts take quite hardware worst still have lots wires. take different approach eliminate except data wiring itself. Then need multiplex data, selection (address), direction info read/write. need develop relatively complex rules that, save those wires. This presentation covers buses that only data lines that they still attractive sending data over reasonable distances least meters, perhaps even
Typical Signaling Characteristics
tive
IEEE1394
SERIAL BUSES
UART
DesignCon 2003 TecForum Overview
Slide
General concept Serial communications
Parallel Serial Shift Register
select select select READ WRITE?
enable
Shift Reg# Ser.
enable
Shift Reg# Ser.
enable
Shift Reg# Ser.
DATA
"MASTER"
SLAVE
SLAVE
SLAVE
LVTTL RS422/485 PECL LVPECL LVDS SMBus 1394 GTL+
point point communication does require Select control signal asynchronous communication does have Clock signal Data, Select signals share same line, depending protocol Notice that Slave cannot communicate with Slave (except `master') Only `master' start communicating. Slaves `only speak when spoken
DesignCon 2003 TecForum Overview
GTLP
Slide
DesignCon 2003 TecForum Overview
Buses come forms, serial parallel. data and/or addresses sent over wire, after bit, over wires once. Always there some share common wiring, some rules, some synchronization. Slide shows serial data with
Slide Devices communicate differentially single ended with various signal characteristics shown Slide
AN10216-01 Manual
also because used within software general data path that drivers use.
Transmission Standards
2500 Data Transfer Rate (Mbps)
GTLP
1394.a
=RS-6 /PEC L/LV
General Purpose Logic
RS-422 RS-485
RS-232 RS-423
Cable Length (meters)
1000
Backplane Length (meters) DesignCon 2003 TecForum Overview
Slide various data transmission rates length cable backplane length different transmission standards shown Slide
Terminology USB: older terms such spec version discouraged. There just "USB" (meaning original Mbits/sec Mbits/sec speeds version 1.1) Hi-Speed meaning faster Mbits/sec option included spec version 2.0. Parts conforming capable Mbits/sec certified Hi-Speed will then feature logo with stripe "Hi-Speed" fitted above standard logo. reason avoid spec version generic name that this version includes older versions speeds well Hi-Speed specs. compliance does imply Hi-Speed (480 Mbits/sec). compliant with specifications only capable older `full speed' Mbits/sec.
characteristics compared
Data (bits sec) 400k 400k 3.4M diff erential (low speed, 1.1) full speed, 1.1) (2.0) IEEE-1394 125k 1.5M 1.5/12M 480M 400M+ meter 10km cable specs cables linking nodes cable node node) hops, 4.5M each specs specs 6-bit address propagation delays Length limiting actor iring capacitance propagation delays iring capacitance total capacitance Typ.number Node number limiting actor 400pF limit 100pF load resistance transceiver drive high speed
Speed various connectivity methods (bits/sec)
Wire) (`Industrial', SMBus) (fault tolerant) (high speed) `High Speed mode' (1.1) SCSI (parallel bus) Fast SCSI Ultra SCSI-3 Firewire IEEE1394 Hi-Speed (2.0) (typ) (original speed) 8-80 18-160
DesignCon 2003 TecForum Overview
Slide
DesignCon 2003 TecForum Overview
Slide Increasing fast serial transmission specifications shown Slide Proper treatment version trying beat emerging 1394a spec that looking improved spec beyond scope this presentation. Philips developing leading-edge components support both 1394 buses. Today path forward built "OTG" applications costs complexity this probably beyond limits many customers. designers identified designing large international markets then please contact group additional support, particularly Host solutions. Apologies inclusion parallel SCSI bus. intended comparison purposes
Slide look three important characteristics: Speed, data rate Number devices allowed connected share wires) Total length wiring Numbers supposed realistic estimates based meeting specifications. rules made broken! When buffered, limited wiring propagation delays still possible much longer distances using slower clock rates maybe also compromising rise fall-time specifications buffered because bound conform specifications. figure Slide limiting range propagation delays conservative allows published response delays chips like older memories. Measured chip responses typically that allows long cable delays and/or
AN10216-01 Manual
operation well above with P82B96. theoretical round-trip delay cable only approx maximum allowed delay, assuming zero delays ICs, about kHz. figures quite conservative; they `often quoted values'. round trip delay cable about while kbps implies nominal time, need sample during second half time. That under user's control, needs attention. IEEE-1394 still `emerging standards'. Figures quoted practical; they just based specification restrictions. UART Overview bits rebuilds (parallel) byte puts buffer. Along with converting between serial parallel, UART does some other things byproduct (side effect) primary task. voltage used represent bits also converted (changed). Extra bits (called start stop bits) added each byte before transmitted. Also, while flow rate bytes/s) parallel speed inside computer very high, flow rate UART serial port side much lower. UART fixed rates (speeds) that serial port interface.
UART Applications
Server Server Processor Digital Processor Datacom Datacom controller controller rModem Modem
What UART?
(Universal Asynchronous Receiver Transmitter) Communication standard implemented 60's. Simple, universal, well understood well supported. Slow speed communication standard: Mbits/s Asynchronous means that data clock included data: Sender Receiver must agree timing parameters advance. "Start" "Stop" bits indicates data sent Parity information also sent
Start Stop Parity Information
Public Private application Telephone Internet Network Serial Interface
Analog Digital
application
Parallel Interface Modem Modem
Client Client Processor Processor
Datacom Datacom controller controller Serial Interface
Appliance Terminals Entertainment Home Security
Cash register
Display
Micro Micro Data contr. contr. UART
Address
Robotics Automotive Cellular Medical
Memory Memory
Interface Server
DUART DUART SC28L92 SC28L92
code reader Overview DesignCon 2003 TecForum Printer
Data
DesignCon 2003 TecForum Overview
Slide Overview
Slide UARTs (Universal Asynchronous Receiver Transmitter) serial chips your motherboard internal modem card). UART function also done chip that does other things well. older computers like many 486's, chips were disk controller card. Still older computers have dedicated serial boards. UARTs purpose convert bytes from PC's parallel serial bit-stream. cable going serial port serial only wire each direction flow. serial port sends stream bits, time. Conversely, stream that enters serial port external cable converted parallel bytes that computer understand. UARTs deal with data byte-sized pieces, which conveniently also size ASCII characters. have terminal hooked your When type character, terminal gives that character transmitter (also UART). transmitter sends that byte onto serial line, time, specific rate. end, receiving UART takes
What SPI?
Serial Peripheral Interface (SPI) 4-wire full-duplex synchronous serial data link:
SCLK: Serial Clock MOSI: Master Slave Data from Master Slave MISO: Master Slave Data from Slave Master Slave Select
Originally developed Motorola Used connecting peripherals each other microprocessors Shift register that serially transmits data other devices Actually wire interface with number devices Only master active time Various Speed transfers (function system clock)
DesignCon 2003 TecForum Overview
Slide Serial Peripheral Interface (SPI) circuit synchronous serial data link that standard across many Motorola microprocessors other peripheral chips. provides support high bandwidth mega baud) network connection amongst CPUs other devices supporting SPI.
AN10216-01 Manual
connected devices recognized?
SCLK MOSI MISO MASTER SCLK MOSI MISO SCLK MOSI MISO SCLK MOSI MISO SLAVE
SLAVE
SLAVE
synchronized serial clock (SCLK). data transferred each clock cycle. Four clock modes defined value clock polarity clock phase bits. clock polarity determines level clock idle state clock phase determines which clock edge places data bus. hardware device capable operation more than mode will have some method selecting value these bits. Overview
Simple transfer scheme, bits Allows many devices through addition shift register Full duplex communications Number wires proportional number devices
DesignCon 2003 TecForum Overview
What (Controller Area Network)
Proposed Bosch with automotive applications mind (and promoted Germany industrial applications) Relatively complex coding messages Relatively accurate (usually) fixed timing modules participate every communication Content-oriented (message) addressing scheme
Slide essentially "three-wire plus slave selects" serial eight sixteen data transfer applications. three wires carry information between devices connected bus. Each device acts simultaneously transmitter receiver. three lines transfer data (one line each direction) third serial clock. Some devices only transmitters while others only receivers. Generally, device that transmits usually possesses capability receive data also. display example receive-only device while EEPROM receiver transmit device. devices connected classified Master Slave devices. master device initiates information transfer generates clock control signals. slave device controlled master through slave select (chip enable) line active only when selected. Generally, dedicated select line required each slave device. same device possess functionality master slave point time, only master control multi-master mode configuration. slave device that selected must release (make high impedance) slave output line. employs simple shift register data transfer scheme: Data clocked into active devices first-in, first-out fashion. this manner that devices transmit receive full duplex mode. lines unidirectional: signal clock line (SCLK) generated master primarily used synchronize data transfer. master-out, slave-in (MOSI) line carries data from master slave master-in, slave-out (MISO) line carries data from slave master. Each slave device selected master individual select lines. Information transferred rate near zero bits second Mbits second. Data transfer usually performed eight/sixteen blocks. data transfer
Filter
Frame
Filter
DesignCon 2003 TecForum Overview
Slide objective achieve reliable communications relatively critical control system applications e.g. engine management anti-lock brakes. There several aspects reliability availability when important data needs sent, possibility bits message being corrupted noise etc., electrical/mechanical failure modes wiring. least ceramic resonator possibly quartz crystal needed generate accurate timing needed. clock data combined `high' bits succession interpreted error. clock timings important. connected modules must same timings. modules looking error data point wiring will report that error message re-sent etc.
AN10216-01 Manual
protocol Advantages
Accepted standard Automotive industrial applications
interfacing between various vendors easier implement
Start Frame
Identifier Remote Transmission Request Identifier Extension Data Length Code Data Cyclic Redundancy Check Acknowledge Frame Intermission Frame Space
Freedom select suitable hardware
differential wire
Secure communications, high Level error detection
messages (Cyclic Redundancy Check) Reporting logging Faulty devices disconnect themselves latency time Configuration flexibility
Very intelligent controller requested generate such protocol
DesignCon 2003 TecForum Overview
High degree immunity (when using Si-On-Insulator technology)
DesignCon 2003 TecForum Overview
Slide Like I2C, wires pulled resistors their resting state called `recessive' state. When transceiver drives forces voltage called `dominant' state. identifier indicates meaning data, intended recipient. nodes receive `filter' this identifier decide whether data not. using `multicast' many modules message, modules checking message transmission errors. Arbitration `bit wise' like module forcing beats module trying loser withdraws again later. DLC: data length code CRC: cyclic redundancy check (remainder division calculation). devices that pass will acknowledge will generate error flag after data frame finishes. ACK: acknowledge. Error frame: least) consecutive dominant bits then recessive bits.
Slide products from many manufacturers compatible hardware will selected dedicated each particular system design. Some transceivers will compatible with others, that more likely exception than rule. designs usually individual systems that intended modified. Philips parts greatly enhance feature reliability their ability partbroken wiring disconnect themselves they recording many errors. There several aspects reliability availability when important data needs sent, possibility bits message being corrupted noise etc., consequences electrical/mechanical failure modes wiring. these aspects treated seriously specifications suppliers interface example Philips believes conventional high voltage processes good enough uses Silicon-on-insulator technology increase ruggedness avoid alternative using common-mode chokes protection. give example immunity, transceiver must able cope with jump-start load-dump voltages supply wires. That supply +/40 lines, plus transients -150 V/+100 capacitively coupled from pulse generator test circuit!
message `filter' programmed test 11-bit identifier bytes data general bits) decide whether accept message issue interrupt. could also look 29-bit identifier.
AN10216-01 Manual
Overview
Advantages
pluggable, need open cabinets Automatic configuration devices connected together Push become standard
standard iMac, supported Windows, 99%of
What (Universal Serial Bus)
Originally standard connecting peripherals Defined Intel, Microsoft, Intended replace large number legacy ports Single master Host) system with peripherals Simple plug play; need open Standardized plugs, ports, cables over penetration Adapting requirements flexibility Host function
Hardware/Software allows dynamic exchanging Host/Slave roles longer only system Host. camera printer.
Interfaces (bridges) other communication channels exist
serial port (serial port vanishing from laptops) IrDA Ethernet
Extreme volumes force down hardware prices Protocol evolving fast
DesignCon 2003 TecForum Overview DesignCon 2003 TecForum Overview
Slide Slide most complex buses presented here. While hardware transceivers relatively simple, software complex able efficiently service many different applications with very different data rates requirements. Mbps rate (with Mbps planned) over twisted pair with 4-pin connector wires power supply). also limited short distances most meters (depends configuration). Linux supports bus, although devices that plug into supported. synchronous transmits special packets like network. Just like network, have several devices attached Each device gets time-slice exclusive short time. device also guaranteed fixed intervals. device monopolize other device wants aims mass-market products design-ins less convenient small users. serial port vanishing from laptop gone from iMac. There hardware bridges available from other communication channels there higher power consumption this way. Philips innovating products minimize power offer maximum flexibility system design.
Versions specification
Established, large peripheral markets Well controlled hardware, special 4-pin plugs/sockets 12MBits/sec (normal) 1.5Mbits/sec (low speed) data rate Challenging IEEE1394/Firewire video possibilities clock Hi-Speed means it's real "UHF" transmission Hi-Speed option needs more complex chip hardware software Hi-Speed component prices about compared full speed
Topology (original concept, USB1.1, USB2.0)
Host host system Provides power peripherals Provides ports connecting more peripheral devices. Provides power, terminations External supply Powered Device, Interfaces Endpoints Device collection data interface(s) Interface collection endpoints (data channels) Endpoint associated with FIFO(s) data interfacing
DesignCon 2003 TecForum Overview
"OTG" Supplement hardware smaller 5-pin plugs/sockets Lower power (reduced bus-powering)
DesignCon 2003 TecForum Overview
Monitor Host
Slide hardware well established. shape plug/socket Host different from shape peripheral end. always single point-to-point link over cable. allow connection multiple peripherals introduced. functions multiplex data from `downstream' peripherals into `upstream' data linkage Host. Hi-Speed systems necessary system start communicating normal system then additional hardware (faster transceivers etc) activated allow higher speed. Hi-Speed system much more complex (hardware/software) than normal (1.1).
Device
Slide Slide shows typical configuration.
AN10216-01 Manual
Hi-Speed development `stand-alone' Host such ISP1161 ISP1561 allowed Host function embedded products such Digital Still Cameras printers that more direct transfer data possible without using path Camera Printer under control host. That step transfer involves connecting camera (one cable) also printer (second cable). goal without next step involved shrinking connector hardware, make more compatible with small products like digital cameras, making provision (extra pin) dynamic exchanging Host slave device functions without removing cable reversing master/slave connectors. hardware specification version called (OTG). specification longer requires Host provide power supply peripherals indeed allows arbitration determine whether Host peripheral neither) will provide system power. 1394 Overview specified well over 8-30 volts (approx) leading some unkind references `fire' wire! 1394 software message format consists timeslots within which data sent blocks `channels'. real-time data transfer possible guarantee availability more channels guarantee certain data rate. This important video because it's good sending packet corrected data after blank appeared screen! Microsoft says, "IEEE 1394 defines single interconnection that serves many purposes user scenarios. addition adoption consumer electronics industry, vendors-including Compaq, Dell, IBM, Fujitsu, Toshiba, Sony, NEC, Gateway-are shipping Windows-based with 1394 buses. IEEE 1394 complements Universal Serial (USB) particularly optimized connecting digital media devices high-speed storage devices peer-to-peer bus. Devices have more builtin intelligence than devices, they independently processor, resulting better performance. 100-, 200-, 400-Mbps transfer rates currently specified IEEE 1394a standard proposed enhancements 1394b well suited meeting throughput requirements multiple streaming input/output devices connected single licensing patented IEEE 1394 technology been established $0.25 system. With connectivity storage, scanners, printers, other types consumer devices, IEEE 1394 gives users benefits great legacy-free connector- true Plug Play experience hassle-free connectivity."
What IEEE1394
standard devised handle high data throughput requirements MPEG-2
Video requires constant transfer rates with guaranteed bandwidth Data rates 100, 200, Mbits/sec looking Gb/s
Also known "Firewire" (registered trademark Apple) Automatically re-configures itself each device added
True plug play Hot-plugging devices allowed
devices, cable `hops', with max. hops Bandwidth guaranteed
DesignCon 2003 TecForum Overview
Slide 1394 claim more proven established than both `emerging' specifications that trying out-do each other! Philips strongly supports BOTH. 1394 chosen Philips link set-top boxes, DVD, digital TVs. 1394 version taking Mb/sec more recently version higher speed allow longer cable runs, perhaps meter hops! 1394 sends information over PAIR twisted pairs. data, other clocking strobe. clock simply recovered Ex-Or data strobe line signals. needed. There provision lots remote device powering cable 6-pin plug connection version used. power wires
1394 Topology
Physical layer Analog interface cable Simple repeater Performs arbitration
Link layer
Assembles dis-assembles packets Handles response acknowledgment functions
Host controller
DesignCon 2003 TecForum Overview
Implements higher levels protocol
Slide
AN10216-01 Manual
Overview Each device connected software addressable unique address simple master/slave relationships exist times; masters operate master-transmitters master-receivers. It's true multi-master including collision detection arbitration prevent data corruption more masters simultaneously initiate data transfer. Serial, 8-bit oriented, bi-directional data transfers made kbit/s Standardmode, kbit/s Fast-mode, Mbit/s High-speed mode. On-chip filtering rejects spikes data line preserve data integrity. number that connected same segment limited only maximum capacitive loading
What (Inter-IC)
Originally, defined Philips providing simple talk between IC's using minimum number pins specifications build simple universal guaranteeing compatibility parts (ICs) from different manufacturers:
Simple Hardware standards Simple Software protocol standard
specific wiring connectors most often it's just tracks become recognised standard throughout industry used major manufacturers
DesignCon 2003 TecForum Overview
Slide Originally, designed link small number devices single card, such manage tuning radio maximum allowable capacitance allow proper rise fall times optimum clock data signal integrity with speed kbps. 1992 standard speed increased kbps, keep with ever-increasing performance requirements ICs. 1998 specification, increased speed Mbits/sec. devices designed able communicate together same two-wire system functional architecture limited only imagination designer. while application lengths within confines consumer products such PCs, cellular phones, radios sets grew quickly, only system integrators were using span room building. being increasingly used multiple card systems, such blade servers, where each card needs isolatable allow card insertion removal while rest system operation, systems where many more devices need located onto same card, where total device trace capacitance would have exceeded extension control devices help expand beyond limit about devices allow control more devices, even those with same address. These devices popular with designers they continue expand increase range devices maintenance control applications. Features Only lines required: serial data line (SDA) serial clock line (SCL).
Software
Simple procedures that allow communication start, achieve data transfer, stop
Described Philips protocol (rules) Message serial data format very simple Often generated simple software general purpose micro Dedicated peripheral devices contain complete interface Multi-master capable with arbitration feature
Each identified address code
Address unique
master that initiates communication provides clock signal (SCL)
There maximum clock frequency MINIMUM SPEED
DesignCon 2003 TecForum Overview
Slide Communication Procedure that wants talk another must: Wait until sees activity bus. both high. 'free'. message that says 'its mine' have STARTED bus. other then LISTEN data whether they might will called (addressed). Provide CLOCK (SCL) wire clock signal. will used reference time which each DATA data (SDA) wire will correct (valid) used. data data wire (SDA) must valid time clock wire (SCL) switches from 'low' 'high' voltage. serial form unique binary 'address' (name) that wants communicate with. message (one bit) telling whether wants SEND RECEIVE data from other chip. (The read/write wire gone!)
AN10216-01 Manual
other ACKNOWLEDGE (using bit) that recognized address ready communicate. After other acknowledges data transferred. first sends receives many 8-bit words data wants. After every 8-bit data word sending expects receiving acknowledge transfer going When data finished first chip must free does that special message called 'STOP'. just information transferred special 'wiggling' SDA/SCL wires bus. rules that when data addresses being sent, DATA wire only allowed changed voltage (so, '1', '0') when voltage clock line LOW. 'start' 'stop' special messages BREAK that rule, that they recognized special. several Masters could control Slave, different times. `smart' communications must transferred DATA, perhaps used address info. protocol does allow very complex systems. It's `keep simple' bus. course system designers free innovate provide complex systems based simple bus. Serial Comparison Summary
Pros Cons different buses
UART
Well Known Cost effective Simple
Secure Fast
Fast Plug&Play Simple cost
Fast Universally accepted cost Large Portfolio
Simple Well known Universally accepted Plug&Play Large portfolio Cost effective
Limited functionality Point Point
Complex Automotive oriented Limited portfolio
Powerful master Plug&Play required Plug&Play Specific drivers required "fixed" standard
Limited speed
connected devices recognized?
Master device `polls' used specific unique identification "addresses" that designer included system Devices with Master capability identify themselves other specific Master devices advise their specific address functionality
Allows designers build `plug play' systems speed different each device, only maximum limit
Expensive firmware DesignCon 2003 TecForum Overview
Slide Most Philips devices plug play. That because MOST chips system needs fixed nothing added later. That because added chip EXPECTED take part EVERY data conversation will know clock speed cannot synchronize. That means falsely reports timing error every message crashes system.
Only devices exchange data during `conversation'
DesignCon 2003 TecForum Overview
Slide device with ability initiate messages called `master'. might know exactly what other chips connected, which case simply addresses wants, there might optional chips then checks what's there sending each address seeing whether gets response (acknowledge). example might telephone with micro some models, there could EEPROM guarantee memory data, some models there might display using driver. There software written cover possibilities. micro finds display then drives otherwise program arranged skip that software code. simplest buses this presentation. Only chips involved communication Master that initiates signals Slave that responded when addressed.
Philips special transceivers that allow them listen without taking part conversations. This special feature allows them synchronize their clocks THEN actively join conversations. from Philips, becomes POSSIBLE some minor plug/play system. USB/SPI/MicroWire mostly UARTS just 'one point point' data transfer systems. then uses multiplexing data path forwarding messages service multiple devices. Only SOFTWARE addressing determine participants transfer data between (I2C) more (CAN) chips connected same wires. best speed maintenance control applications where devices have added removed from system.
AN10216-01 Manual
Theory Operation Compatible with number processors with integrated ports (micro 8,16,32 bits) 8048, 80C51 6800 68xxx architectures Easily emulated software microcontroller Available from important number component manufacturers
Introduction
Inter-IC developed Philips 80's Simple bi-directional 2-wire bus:
serial data (SDA) serial clock (SCL)
become worldwide industry standard used major manufacturers Multi-master capable with arbitration feature Master-Slave communication; Two-device only communication Each identified address code slave
receiver-only device transmitter with capability both receive send data
DesignCon 2003 TecForum Overview
Hardware architecture
Pull-up resistors Typical value
Slide very easy understand use. Slides give good explanation specifics different speeds. Many people have asked where rise time measured specification stipulates it's between VDD. This becomes important when buffers `distort' rising edges bus. keeping waveform distortions below VDD, that portion rising edge will counted part formal rise time.
Open Drain structure Open Collector) both
DesignCon 2003 TecForum Overview
Slide Terminology Transmitter device that sends data bus. transmitter either device that puts data accord `mastertransmitter'), response request from data from another devices `slave-transmitter'). Receiver device that receives data from bus. Master component that initializes transfer, generates clock signal, terminates transfer. master either transmitter receiver. Slave device addressed master. slave either receiver transmitter. Multi-master ability more than master co-exist same time without collision data loss. Arbitration prearranged procedure that authorizes only master time take control bus. Synchronization prearranged procedure that synchronizes clock signals provided more masters. data signal line (Serial DAta) clock signal line (Serial CLock)
numbers
Standard-Mode
Rate (kbits/s) Load (pF) Rise time (ns) Spike Filtered (ns) Address Bits
Rise Time
Fast-Mode
High-SpeedMode
1700 3400
1000
0.7xVDD
DesignCon 2003 TecForum Overview
0.3xVDD Sink Current
Slide medium speed serial with impressive list features: Resistant glitches noise Supported large diverse range peripheral devices well-known robust protocol long track record field respectable communication distance which extended longer distances with extenders
AN10216-01 Manual
START/STOP conditions
Data must stable when High
µcontroller
Address, Basics
µcontroller
1010 1010A2A1A0R/W
Exceptions START STOP conditions
Fixed Hardware Selectable Each device addressed individually software
EEPROM
devices functions easily `clipped existing bus!
Unique address device: fully fixed with programmable part through hardware pin(s).
Programmable pins mean that several same devices share same Address allocation coordinated I2C-bus committee different types devices with 7-bit format (others reserved)
DesignCon 2003 TecForum Overview
DesignCon 2003 TecForum Overview
Slide START STOP Conditions Within procedure bus, unique situations arise which defined START STOP conditions. START: HIGH transition line while HIGH STOP: HIGH transition line while HIGH master always generates START STOP conditions. considered busy after START condition. considered free again certain time after STOP condition. stays busy repeated START (Sr) generated instead STOP condition. this respect, START repeated START (Sr) conditions functionally identical. symbol will used generic term represent both START repeated START conditions, unless particularly relevant. Detection START STOP conditions devices connected easy they incorporate necessary interfacing hardware. However, microcontrollers with such interface have sample line least twice clock period sense transition.
Slide HARDWARE CONFIGURATION Slide shows hardware configuration bus. `bus' wires named (serial data) (serial clock). These wires have same configuration. They pulled-up logic `high' level resistors connected single positive supply, usually +3.3 designers moving +2.5 towards near future. connected devices have open-collector (opendrain CMOS both terms mean only lower transistor included) driver stages that transmit data pulling low, high impedance sense amplifiers that monitor voltage receive data. Unless devices communicating turning lower transistor pull low, both lines remain `high'. initiate communication chip pulls line low. then responsibility drive line with clock pulses, until finished, called `master'. COMMUNICATION Communication established 8-bit bytes exchanged, each being acknowledged using data generated receiving party, until data transfer complete. made free other when `master' releases line during time when high. Apart from special exceptions start stop, device allowed change state line unless line low. masters start communication same time, arbitration performed determine "winner" (the master that keeps control continue transmission) "loser" (the master that must abort transmission). masters even generate cycles clock data that `match', eventually will output `low' when other tries `high'. `low' wins,
AN10216-01 Manual
`loser' device withdraws waits until freed again. There minimum clock speed; fact device that problems `keep pace' allowed `complain' holding clock line low. Because device generating clock also monitoring voltage bus, immediately `knows' there problem wait until device releases line. full details capabilities refer Philips Semiconductors Specification document `The specification' `The from theory practice' book Paret Fenger published John Wiley Sons. specification other useful application information found Philips Semiconductors site master releases line accomplish Acknowledge phase. other device connected bus, decoded recognized `address', will acknowledge pulling line low. responding chip called `slave'.
Read Write Operations
Write Slave device
data bytes data dataP slave address data slave address data Master transmitter
Slave receiver
Write
Each byte acknowledged slave device
master "MASTER TRANSMITTER": transmits both Clock Data during communication
Read from Slave device
slave address
data bytes
data
data
receiver
transmitter
Read
Each byte acknowledged master device (except last one, just before STOP condition)
master "MASTER TRANSMITTER then MASTER RECEIVER": transmits Clock time sends slave address data then becomes receiver
DesignCon 2003 TecForum Overview
Slide
Address, 7-bit 10-bit formats
byte after START determines Slave addressed Some exceptions rule: "General Call" address: devices addressed 0000 10-bit slave addressing 1111 addressing
Terminology Transfer (FREE) free; data line clock both high state. (START) (Repeated START) data transfer begins with start condition (not start bit). level data line changes from high low, while clock line remains high. When this occurs, `busy'. (CHANGE) while clock line low, data transferred applied data line transmitter. During this time, change state, along line remains low. (DATA) high information data line valid during high level clock line. This level must maintained stable during entire time that clock remains high avoid misinterpretation Start Stop condition. (STOP) data transfer terminated stop condition, (not stop bit). This occurs when level data line passes from state high state, while clock line remains high. When data transfer been terminated, free once again.
bits
DATA Only device will acknowledge
10-bit addressing
DATA
MSBs remaining bits More than device Only device will acknowledge acknowledge
DesignCon 2003 TecForum Overview
Slide Slide shows address scheme. device attached common they talk with each other, passing information back forth. Each device unique 7-bit 10-bit address. 7-bit devices, typically first four bits fixed, next three bits hardware address pins (A0, that allow user modify address allowing eight same devices operate bus. These pins held high VCC, sometimes through resistor, held GND. last initial byte indicates master going send (write) receive (read) data from slave. Each transmission sequence must begin with start condition with stop condition. clock pulse, `high' data going read from other device, `low' data going sent (write). During clock,
AN10216-01 Manual
Read Write Operations
Combined Write Read
slave address slave address data bytes data dataSr slave address
data bytes
data data
data data
Slide shows multiple masters synchronize their clocks, example during arbitration. When capacitance affects rise fall times master will also adjust timing similar way.
Write
Each byte acknowledged slave device
Combined Read Write
slave address
data bytes
data
Read Each byte acknowledged master device (except last one, just before STOP condition)
data bytes data data
Protocol Arbitration
more masters generate START condition same time Arbitration done while HIGH Slaves involved
data
slave address Adata data slave address
Each byte Write Each byte acknowledged acknowledged master device slave device (except last one, just before Re-START condition) DesignCon 2003 TecForum Overview
Read
Master loses arbitration DATA1
Slide Slide shows combined read write operation.
Start command
DesignCon 2003 TecForum Overview
Acknowledge; Clock Stretching
Acknowledge Done clock pulse mandatory Transmitter releases line Receiver pulls down line (SCL must HIGH) Transfer aborted acknowledge
acknowledge
Acknowledge
Slide there masters same bus, there arbitration procedures applied both take control same time. When chips start communication same time they even generate cycles clock data that `match', eventually will output `low' when other tries `high'. `low' wins, `loser' device withdraws waits until freed again. Once master (e.g., microcontroller) control, other master take control until first master sends stop condition places idle state.
Clock Stretching
Slave device hold CLOCK line when performing other functions Master slow down clock accommodate slow slaves
DesignCon 2003 TecForum Overview
Slide Slide shows Acknowledge phase done slave devices stretch clock signal. Most Philips slave devices control clock line.
What need drive bus?
Slave Slave Slave Slave
Master
Master
Protocol Clock Synchronization
Master
There basic ways drive bus:
With Microcontroller with on-chip Interface oriented interrupted after every transmission (Example: 87LPC76x) Byte oriented interrupted after every byte transmission (Example: 87C552) With microcontroller: 'Bit Banging'
protocol emulated bi-directional open drain port
With microcontroller conjunction with controller like PCF8584 PCA9564 parallel interface
DesignCon 2003 TecForum Overview
Slide
period determined longest clock period HIGH period determined shortest clock HIGH period
DesignCon 2003 TecForum Overview
Slide shows there multiple ways control slaves.
Slide
AN10216-01 Manual
Pull-up Resistor calculation
Approach Static Load Worst Case scenario: maximum current load that output transistor handle This gives minimum pull-up resistor value With (min Rmin Approach Dynamic load maximum value rise time: Standard-mode (100 kHz) Fast-mode (400 kHz) Dynamic load defined device output capacitances (number devices) trace, wiring
DesignCon 2003 TecForum Overview
facto world standard that implemented over 1000 different (Philips 400) licensed more than companies
recovery
Typical case when masters fails when doing read operation slave line then usable anymore because "Slave-Transmitter" mode. Methods recover line are: Reset slave device (assuming device Reset pin) recovery sequence leave "Slave-Transmitter" mode
V(t) (1-e Rising time defined between Trise 0.847.RC
recovery sequence done following: Send clock pulses line master keep High until "Slave-Transmitter" releases line perform operation Keeping High during means that "Master-Receiver" does acknowledge previous byte receive
Slide Slide shows typical resistor values needed proper operation. total capacitance either wire, with pull-up resistor. Designer Benefits Functional blocks block diagram correspond with actual ICs; designs proceed rapidly from block diagram final schematic. need design interfaces because interface already integrated on-chip. Integrated addressing data-transfer protocol allow systems completely software-defined. same types often used many different applications. Design-time reduces designers quickly become familiar with frequently used functional blocks represented compatible ICs. added removed from system without affecting other circuits bus. Fault diagnosis debugging simple; malfunctions immediately traced. Assembling library reusable software modules reduce software development time.
"Slave-Transmitter" then goes idle state master then sends STOP command initializing completely
DesignCon 2003 TecForum Overview
Slide Slide shows hung could recovered. become hung several reasons, e.g. Incorrect power-up and/or reset procedure Power chip interrupted brown-outs Noise wiring causes false clock data signals
Protocol Summary
START STOP DATA HIGH transition while HIGH HIGH transition while HIGH 8-bit word, first (Address, Control, Data) must stable when HIGH change only when number bytes transmitted unrestricted done each clock pulse during HIGH period transmitter releases HIGH receiver pulls DOWN line Generated master(s) Maxim speed specified minimum speed receiver hold when performing another function (transmitter Wait state) master slow down clock slow devices Master start transfer only free Several masters start transfer same time Arbitration done line Master that lost arbitration must stop sending data
ACKNOWLEDGE
CLOCK
ARBITRATION
Manufacturers Benefits simple 2-wire serial minimizes interconnections have fewer pins there many tracks; result smaller less expensive PCBs completely integrated protocol eliminates need address decoders other `glue logic' multi-master capability allows rapid testing/alignment end-user equipment external connections assembly-line Increases system design flexibility allowing simple construction equipment variants easy upgrading keep design up-to-date
DesignCon 2003 TecForum Overview
Slide Slide provides summary protocol.
AN10216-01 Manual
Summary Advantages
Simple Hardware standard Simple protocol standard Easy remove functions devices (hardware software) Easy upgrade applications Simpler PCB: Only traces required communicate between devices Very convenient monitoring applications Fast enough "Human Interfaces" applications Displays, Switches, Keyboards Control, Alarm systems Large number different devices semiconductors business Well known robust
DesignCon 2003 TecForum Overview
example, application where identical EEPROMs used (EE1, EE2, EE4), four channel PCA9546 used. master plugged main upstream while EEPROMs plugged downstream channels (CH1, CH2, CH4). master needs perform operation EE3, will have Connect upstream channel Simply communicate with EE3. EE1, electrically removed from main long selected. Some multiplexers offer Interrupt feature, allowing collection different downstream Interrupts (generated downstream devices). Interrupt output provides information (transition from High Low) master every time more Interrupt generated (transition from High Low) downstream devices.
Slide Slide summarizes advantages bus. Overcoming Previous Limitations Address Conflicts
Multiplexers: Address Deconflict
EEPROM EEPROM
solve address conflicts?
protocol limitation: when device does have address programmable (fixed), only same device plugged same
MASTER
Same devices with same address
multiplexer used this limitation
EEPROM EEPROM
allows split dynamically main several sub-branches order talk device time programmable through additional pins required control More than multiplexer plugged same Products
Channels Standard PCA9540 PCA9546 PCA9548 w/Interrupt Logic PCA9542/43 PCA9544/45
MULTIPLEXER
MASTER
multiplexer allows address device then other
DesignCon 2003 TecForum Overview
DesignCon 2003 TecForum Overview
Slide SCL/SDA upstream channel fans multiple SCx/SDx channels that selected programmable control register. command sent main used select deselect downstream channels. Multiplexers select none only SCx/SDx channels time since they were designed primarily address conflict resolution such when multiple devices with same address need attached same only talk devices time. These devices used video projectors server applications. Other applications include: Address conflict resolution (e.g., EEPROMs DIMMs). sub-branch isolation
Slide 10-bit address that unique each device identifies device. This address Partly fixed, part programmable (allowing have more than same device same bus) Fully fixed allowing have only single same device device. more than same "non programmable" device (fully fixed address) required specific application, then necessary temporarily remove non-addressed device(s) from when talking with targeted device. multiplexers allow dynamically split main into subI2C buses. Each sub-bus (downstream channel) connected main (upstream channel) simple 2-byte command.
AN10216-01 Manual
level shifting (e.g., each individual SCx/SDx channel operated device powered Multiplexers allow dynamic splitting overloaded into several sub-branches with total capacitive load smaller than specified Note that this method does allow master access buses same time. Only part will accessible time. Multiplexers allow splitting have buffering capability. Buffers repeaters allow increasing total capacitive load beyond without splitting several branches. PCA9515 used, loaded with each side device.
Interrupt logic inputs each channel combined output included every multiplexer provide flag master system monitoring. These devices isolate capacitive loading either side device designer must take into account trace device capacitance both sides device active channels. Pull resistors must used channels Capacitive Loading (isolation)
beyond load?
protocol limitation: maximum capacitive load load higher parameters will violated.
Practical case: Multi-card application
following example shows build application where: Four identical control cards used (same devices, same I2Caddress) Devices each card controlled through Each card monitors controls some digital information Digital information Interrupt signals (Alarm monitoring) Reset signals (device initialization, Alarm Reset) Each card generates Interrupt when more) device generates Interrupt (Alarm condition detected) master handle only Interrupt signal application
multiplexer used this limitation
allows split dynamically main several sub-branches order divide capacitive load programmable through additional pins required control More than multiplexer plugged same LIMITATION: sub-branches cannot addressed same time Products: Channels
Standard PCA9540 PCA9546 PCA9548
w/Interrupt Logic PCA9542/43 PCA9544/45
DesignCon 2003 TecForum Overview
DesignCon 2003 TecForum Overview
Slide specification limits maximum capacitive load applications where higher capacitive load required, types devices used: multiplexers switches buffers repeaters
Slide this application, identical cards used. Identical means that same devices used, that devices each card have same address. Each card monitors controls some specific signal those signals controlled/monitored through using PCA9554 type device. this application, each card monitors some alarm system's system controls some LEDs visual status. Each alarm, when triggered, generates Interrupt that sent master processing. PCA9554 collects Interrupt signals sends "Card General Interrupt" master. When master processes alarm, sends Reset signal corresponding alarm clear Master receives only Interrupt signal, which combination Interrupt signals cards. Since cards identical, then necessary deconflict different addresses isolate cards that accessed. PCA9544 this application functions: Deconflict addresses creating busses that isolated Collect Interrupt from each card propagate "General Interrupt" master
Multiplexers: Capacitive load split
MASTER
MASTER
MULTIPLEXER
multiplexer splits downstream busses upstream
DesignCon 2003 TecForum Overview
Slide
AN10216-01 Manual
Multiplexers: Multi-card Application
Cards identical card selected controlled time PCA9544 collects Interrupt
Card Card Card Card Reset Reset Alarm Alarm Reset System
high level voltage value, determined voltage applied pull resistors. applications where several voltage levels required (e.g. accommodate legacy architecture with newer devices working only), switches allow creating with different high level voltage values minimum cost. this example, have existing want some features with devices "non tolerant". used. master controlling existing devices will located upstream channel downstream channels will used with pull resistors other one. Software changes will include drivers devices simple 2byte command allows program switch with downstream channels active time. master then sees with devices does have take care high level voltage required make them work correctly. does have care either about location device needs talk (downstream channel channel since both active same time.
9544 MASTER
INT0 INT1 INT2 INT3
95540
Interrupt signals collected into signal DesignCon 2003 TecForum Overview
Slide When card application triggers alarm condition, PCA9554 collects through inputs generates Interrupt card level). PCA9544 collects Interrupts (from each card) sends "General Interrupt" master. Master then interrogates PCA9544 Interrupt status register order determine which card cause Master then connects corresponding channel order interrogate PCA9554 reading Input register. Once done, Master knows which alarm been triggered process When this done, Master then clear corresponding alarm accessing corresponding card programming PCA9554 (write output register) Voltage Level Translation
Switches: Voltage Level Shifting
device device device device device Devices supplied 3.3V tolerant
Devices supplied MASTER
Products
Channels GTL2002 PCA9540 PCA9542/43 PCA9546 PCA9544/45 GTL2010 PCA9548 GTL2000
device device device
MASTER
SWITCH
device
device
3.3V
accommodate different logic levels same bus?
protocol: open drain structure bus, voltage level fixed voltage connected pull-up resistor. different voltage levels required (e.g., master core legacy devices voltage level translators need used
DesignCon 2003 TecForum Overview
Slide SCL/SDA upstream channel fans multiple SCx/SDx channels that selected programmable control register. Switches select individual SCx/SDx channels time, once combination through commands very primary designed sub-branch isolation level shifting also work fine address conflict resolution. Just make sure select channels same time. Applications same multiplexers since multiple channels selected same time switches really great level shifting (e.g., individual SCx/SDx channels device powered
switch used accommodate those different voltage levels.
allows split dynamically main several sub-branches allow different supply voltages connected pull resistors devices programmable through additional required control which channel active More than channel active same time master does have remember which branch address (broadcast) More than switch plugged same
DesignCon 2003 TecForum Overview
Slide open drain architecture bus, pull resistors specific voltage required. Once this done, devices will have same
AN10216-01 Manual
hardware reset been added switches. provides means resetting should hang without rebooting entire system very useful server applications where impractical reset entire system when hangs switches reset channels selected. Interrupt logic inputs output available PCA9543 PCA9545 provide flag master system monitoring. PCA9546 lower cost version PCA9545 without Interrupt Logic. PCA9548 provides eight channels more convenient then dual channel devices since device address does have shift. These devices isolate capacitive loading either side device designer must take into account trace device capacitance both sides device (active channels only). Pull resistors must used channels. Increase Reliability (Slave Devices)
Isolate hanging segment(s)
Device Device MASTER 9548 Device Device Device
RESET
Device Device Device
DesignCon 2003 TecForum Overview
Slide Let's take example where devices (DEV1 DEV8) used where functional devices need controlled even though more devices failing. Slave devices will located each downstream channel PCA9548 (8-channel switch with Reset) (CH1 CH8). power downstream channels disabled. master (located upstream channel) sends byte command enabling downstream channels. then normal with master slave devices. Let's assume that DEV4 CH4) fails. then hangs cannot normally controlled master anymore. After detection this condition, master must maintenance routine where: resets PCA9548, thus disabling downstream channels. enables downstream channels (CH1 CH8) until hangs again (CH4 active). master then knows that device connected responsible failure resets again PCA9548 take control programs functional channels active (CH1 disables Note that this algorithm also applied more than channel hang same time.
increase reliability bus? (Slave devices)
protocol: device does work properly hangs bus, then device addressed anymore until rogue device separated from reset.
switch used split several branches that isolated hangs
Switches allow main split dynamically several sub-branches that active time deactivated device particular branch hangs When malfunctioning sub-branch been isolated, other branches still available programmable through additional required control More than switch plugged same
DesignCon 2003 TecForum Overview
Slide open drain architecture bus, device fails keeps clock data line high level, stuck this configuration device controlled until failed device isolated from bus. Some architectures require still operational even though more devices failed longer operate normally. switch with Reset capability allows Split dynamically several subbranches (with several devices each) Disconnect devices case hangs Reprogram isolate more branch that working properly.
AN10216-01 Manual
Isolate hanging segments Discrete stand alone solution
SEGMENT
Isolate failing master
MAIN MASTER
Slave
Demux
SEGMENT
MASTER
BACKUP MASTER
Main
Slave
SEGMENT
Main Master control
When fails, backup master asks take control Previous master then isolated multiplexer
buffer isolates branch (capacitive isolation) power supply controlled sensor sensed sensor generates timeout when stays buffer Hi-Z when power supply off.
DesignCon 2003 TecForum Overview
Downstream initialized (all devices waiting START condition) Switch master done Products
Device PCA9541 upstream channels
DesignCon 2003 TecForum Overview
Slide Slide shows discrete solution with option timing, discrete capacitors, isolate segment. Increasing Reliability (Master Devices)
Slide master selector allows switching between master backup (and vice versa main master comes back line). Before switching from upstream channel other one, device makes sure that previous device anymore (fully isolated) switching done after making sure that downstream "clean" configuration. downstream devices have been initialized again (essential when previous master failed middle transaction thus well initialized) idle configuration. This done converting master selector into temporary master (just after isolating failing master) allowing send necessary sequence clock pulses while maintained high then STOP command). While sequence done, downstream well initialized switch master performed automatically PCA9541. Capacitive Loading (Buffer)
increase reliability bus? (Master devices)
protocol: master does work properly reliability systems will decrease since monitoring control critical parameters possible anymore (voltage, temperature, cooling system)
demultiplexer used switch from failing master backup.
allows have independent masters control without fault system corruption failed master completely isolated from initialized demultiplexer before switching from master other programmable through additional required control More than demultiplexer plugged same
DesignCon 2003 TecForum Overview
Slide master fails does work properly, reliability applications will decrease since monitoring control essential parameters cannot controlled anymore (e.g. temperature monitoring, voltage monitoring, cooling control). then often essential have backup master replace functioning main master. master selector then essential device allowing switching between masters. used point point application master backup master control card multi point application master backup master control several cards.
beyond load?
protocol limitation: maximum capacitive load load higher parameters will violated.
repeater used this limitation
allows double capacitive load (repeater) make times higher (hub repeaters) Multi-master capable, voltage level translation channels active same time Limitation: Repeater/hub cannot used series Products:
Device PCA9515 PC9516 repea ENABLE pins
DesignCon 2003 TecForum Overview
Slide
AN10216-01 Manual
repeaters hubs allow increasing maximum capacitive load without degrading performances (rising falling times) data clock signals. They multi-master capable.
repeater (PCA9515) (PCA9516)
9515
Master
Using PCA9516 this application, masters only talk with masters same main master since signal sent through hubs. masters will able arbitrate control located different hubs. That ideal limits designers' ability expand their bus. PCA9515 PCA9516 only used device (either PCA9515 PCA9516) system since levels will transmitted through second device. overcome this limitation, PCA9518 released. Similar PCA9516 with four extra open drain signal pins that allow internal device logic interconnected into unlimited number segments with only repeater delay between segments.
9516
DesignCon 2003 TecForum Overview
PCA9518 Applications
Master Master
DesignCon 2003 TecForum Overview
Slide Repeaters allow doubling capacitive load, each side device Hubs allow multiplying load with each channel
9518 9518
Inter Device
used 9518 9518
Slide possible communication paths shown green. communication possible over paths, communicate with other hub. When communication between hubs master required then multi-drop approach with P82B96 should used.
scale adding segments?
Some applications require architecture enhancements where several isolated hubs need added with capability communication
Slide PCA9518, like PCA9515/16, transparent arbitration contention protocols multimaster environment master talk other master segment. enable pins used isolate four five segments device. Place pull resistor un-isolatable segment leave unused there requirement enable disable segment. Using PCA9518 this application, master talk other master cards main master talk with master with only repeater delay.
expandable used easily upgrade this type application
allows expand numbers hubs without limit Multi-master capable, voltage level translation channels active same time channels expandable individually disabled) Products:
Device PCA9518 repeate ENABLE pins
DesignCon 2003 TecForum Overview
Slide There some applications where more than channels required. Masters Server Blades Application Main Master able isolate blade with hardware enable GPIO
AN10216-01 Manual
accommodate devices same bus?
protocol limitation: application where devices (masters and/or slaves) present same bus, lowest frequency must used guarantee safe behavior.
repeater used isolate from devices when communication required
allows easily upgrade applications where legacy devices share access with newer devices Each side repeater work with different logic voltage levels Products:
main master with ability choosing between depending devices needs talk masters, working only (can part system legacy) another working kHz.
Device PCA9515
repeaters
ENABLE pins
DesignCon 2003 TecForum Overview
Slide different specification available (100 kHz, MHz), devices designed specification suitable work properly kHz, while opposite true. applications where upgrades have been performed using newer devices while keeping legacy devices, become necessary separate devices from devices when transfer performed.
case, master located "400 only" side capability control PCA9515's ENABLE order disable device when communication initiated (the "100 only" side will then communication). During communication, PCA9515 enabled allow communication with other side. case, both masters located each side PCA9515 control basically same above devices. Live Insertion into
live insert?
protocol limitation: application where active, designed insertion devices.
swap buffer used detect idle condition isolate capacitance, prevent glitching when inserting cards into active backplane.
Repeaters work with same logic level each side except PCA9512 which works with logic voltage levels same time Products:
PCA9515 Application Example
slave devices
SCL1 SDA1 ENABLE OPTIONAL SCL0 SDA0
slave devices
Device PCA9511 PCA9512 PCA9513 PCA9514
repeaters
ENABLE pins
DesignCon 2003 TecForum Overview
MASTER
MASTER
Slide never designed used live insertion applications, newer applications telecom cards that require 24/7 operation require ability removed inserted into active system maintenance control applications.
Master works access slaves their maximum speed (100 only devices) Master works only PCA9515 disabled (ENABLE when Master sends commands
DesignCon 2003 TecForum Overview
Slide PCA9515 used this purpose. side device will have devices running while other side will have devices running kHz. Note that each side PCA9515 work different logic voltage levels. example, "older" devices while "newer" devices work There could also more than master bus:
AN10216-01 Manual
Swap Buffer
PLUG SCL0 SCL1
Parallel Controller
micro-controller without develop dual master application with single micro-controller?
Some micro-controllers integrates port, others don't
SDA0 READY
SDA1
controller used interface with micro-controller's parallel port
Card plugged system Buffer Hi-Z state buffer checks activity main When idle, upstream downstream buses connected Ready signal informs that both buses connected together
DesignCon 2003 TecForum Overview
generates commands with instructions from micro controller's parallel port (8-bits) receives data from send them micro-controller converts software device with parallel port device
DesignCon 2003 TecForum Overview
Slide PCA9511/12/13/14 designed these types live insertion applications. Long Lengths
send commands through long cables?
limitation: maximum capacitive load limit, sending commands over wire pF/m) long distances hard achieve
Slide There many applications where there need convert bits parallel data into port. PCF8584 PCA9564 allow building single master system using parallel port 8051 type microcontroller that does have interface. also allows building double master system with using built-in interface parallel port same micro-controller.
extender used
high drive outputs Possible distances range from meters over twisted-pair phone cables. over short distances. Others applications: Multi-point applications: link applications, factory applications opto-electrical isolation Infra-red radio links Products:
Device P82B715 P82B96
DesignCon 2003 TecForum Overview
Parallel Controller
Master without interface
Master
9564
Multi-Master capability isolated with same device
Master
9564
Slide
Products
SDA1 SCL1 SDA2 SCL2
freq Clock source External Internal Parallel interface Slow Fast
P82B715 P82B96 designed long distance transmission bus.
Voltage range PCF8584 5.5V PCA9564 3.6V w/5V tolerance
DesignCon 2003 TecForum Overview
Slide Philips offers devices, PCF8584 PCA9564. PCA9564 similar PCF8584 operates with various enhancements added that were requested engineers. PCA9564 serves interface between most standard parallel-bus microcontrollers/ microprocessors serial allows parallel system communicate bi-directionally with bus. This commonly referred master. Communication with carried byte-wise basis using interrupt polled handshake.
AN10216-01 Manual
controls specific sequences, protocol, arbitration timing. internal oscillator PCA9564 regulated within 10%.
Voltage range freq. Clock source flexible Parallel interface processors PCA9564 2.3-3.6V Internal Fast PCF8584 4.5-5.5V External Slow Comments PCA9564 tolerant Faster Less expensive more Compatible with faster
WIN-I2CNTDLL: 32-bit Win-I2CNT including driver docs Developer 32-bit embedded applications WIN-I2CNT: 32-bit Software/Adapter 95/98/ME/2000, Enhanced control. Free updates from Website WIN-I2C: General Purpose legacy 16-bit Software/Adapter Basic Legacy control with running Windows 3.1x I2CPORT: General Purpose Printer Port Adapter v1.0 Generic adapter (Not compatible with Win-I2C/Win-I2CNT Software)
addition, PCA9564 been made very similar Philips standard 80C51 microcontroller hardware existing code utilized with modifications. Development Tools Evaluation Board Overview Purpose Development Tool Evaluation Board provide cost platform that allows Field Application Engineers, designers educators easily test demonstrate devices platform that allows multiple operations performed setting similar real system environment.
Evaluation Board 2002-1 Overview
-Win95/98/2000/NT/XP Parallel Port 2002-1 Evaluation Cable
Win-I2CNT Win-I2CNT Software Software
I2CPORT Port I2CPORT Adapter Card Port Adapter Card
Cable
Adapter Card
Cable Power Supply 2002-1 Evaluation Board(s)
Cable Power Supply 2002-1 Evaluation Board(s)
Cable
2002-1A Evaluation Board
DesignCon 2003 TecForum Overview
Slide Slide shows 2002-1A connected shows evaluation boards used same time.
I2CPORT Adapter Card
FEATURES Converts Personal Computer parallel port master Simple graphical interface commands Win-I2CNT software compatible with Windows 2000 Order kits www.demoboard.com
DesignCon 2003 TecForum Overview
Win-I2CNT adapter connects standard DB-25 powered evaluation board
2Kbit EEPROM parallel port
Slide 2002-1A evaluation board purchased from http://www.demoboard.com $199. Demo boards include demoboard.com include: I2C-Trace: Tracer Monitor captures displays messages WIN-SMBUS: SMBUS Protocol S/W-H/W Supports SMBus SMBus v1.0 protocol
Evaluation Board signals
Jumper Voltage Selection (Bus voltage) Open Closed DesignCon 2003 TecForum Overview
Slide
AN10216-01 Manual
I2CPORT adapter card plugs into parallel port provides interface between Personal Computer operating kHz.
AN10216-01 Manual
Evaluation Board 2002-1A Overview
SCL/SDA
Main
Device
Expanders
GPIO register value GPIO value
PCA9501
GPIO programming
2002-1A Evaluation Board
GPIO Read Write Options
PCA9550
PCA9551
PCA9554
PCA9543
PCA9555
PCA9561
PCA9515
P82B96
PCA9501
PCF8582
GPIO address EEPROM address
RJ11
LM75A LM75A
Auto Write Feature
SCL1/SDA1
REGULATORS
Selected byte information
SCL2/SDA2
SCL0/SDA0
Write Time Byte 13910
devices evaluation board evaluation boards daisy chained without address conflict Boards cascadable through connectors, RJ11 phone cable cable board regulators
DesignCon 2003 TecForum Overview
EEPROM Read Write Options EEPROM same value DesignCon 2003 TecForum Overview
EEPROM programming
Slide There many devices evaluation board including GPIO, Blinkers, Switches, Switches Buffers. Win-I2CNT Screen Examples
Slide Slide shows GPIO kbit EEPROM selection PCA9501.
Device
Device address Control Register Value Read Write Operation Channel Selection
Multiplexers/Switches
PCA9543
Starting Software
Clicking Win- I2CNT icon will start software will give following window
Working Window Selection
Open device specific screen modes clock. Slow adequate slow ports solve some potential compatibility issue
Open Universal modes screen
Interrupt Status
Indicates clock (SCL) frequency Indicates that communications start problem, message "WIN-I2C hardware detected" displayed Action: check Adapter Card DesignCon 2003 TecForum Overview
Auto Write Feature
DesignCon 2003 TecForum Overview Help Hints Parallel Port
Slide Slide shows selection possibilities PCA9543/45/46/48 switches.
Device Drivers/Blinkers PCA9551
Slide Slide shows start screen from which other screens selected.
drivers states Register values Device address Auto Write Feature Read Write Operation Frequencies duty cycles programming DesignCon 2003 TecForum Overview
Slide
AN10216-01 Manual
Slide shows selections PCA9551 Blinker. PCA9551 PWMs controls each (ON, OFF, BLINK1 BLINK2).
Device Non-Volatile Registers PCA9561
Device Address
Device
Auto Write Feature
Expanders
Output Register Read Write Operation (all registers)
PCA9554
EEPROMs Read Write Operation MUX_IN Read Operation Data (EEPROM, MUX_IN) Multiplexing
Device address Input Register Configuratio Register Polarity Register Register Programming Read Write Operation (specific register)
Note: MUX_IN, MUX_SELECT pins controlled Software
DesignCon 2003 TecForum Overview
Slide Slide shows PCA9561 Switch along with PCA8550 PCA9559/60.
DesignCon 2003 TecForum Overview
Slide Slide shows true output GPIO. Controls allow Program bits inputs outputs Program output state output bits Read logic state each input output Invert bits that have been read
Device
Thermal Management
Read Write Operation (all registers)
LM75A
Auto Write Feature
Temperature monitoring
Device address
Read Write Operation (specific register)
Device
Auto Write Feature
Expanders
Polarity Registers Input Registers
PCA9555
Device modes
Read Write Operation (all registers)
Temperature Monitoring Programming frequency DesignCon 2003 TecForum Overview
Start Monitoring
Device Address Register Programming Configuration Registers Read Write Operation (specific Register) Output Registers
Slide Slide allows control LM75A monitoring temperature graph.
Device
DesignCon 2003 TecForum Overview
EEPROM PCA9515
(2K)
Control window operating scheme same PCA9501's 2KBit EEPROM
Slide Slide shows true output GPIO.
repeater software control Buffered connector available Enable Control accessible
P82B96
buffer software control come from Port Adapter Adapter through cable sent through RJ11 cables others boards power supplies
DesignCon 2003 TecForum Overview
Slide
AN10216-01 Manual
Slide discusses devices 2002-1A evaluation board that controlled bus. They just provide possibility expand/extend internal 3.3V external devices. PCA9515 allows connection using short wiring another having 3.3-5 standard chips. P82B96 allows options demonstrate: Linking second evaluation board using cable provide power data link Linking evaluation boards using very long telephony cable, m/33 even more. Linking evaluation board cable I2CPORT adapter card. allows more convenient separation Just include adapter card. Expanding another fully standard operating desired voltage from AN10146-01 full details.
program Universal Screen?
Length messages variable: instructions different messages programmed First START STOP instructions removed Re-Start Command Write Command Read Command Instruction
"Insert" "Delete"
Remove Instruction Data: keys
DesignCon 2003 TecForum Overview
Slide Slide shows easy program universal programming screen.
Some others interesting Features
clock frequency modified (Options Menu). Acknowledge ignored stand alone experiment (Options Menu). Universal Transmitter/Receiver program saved file. Device specific screens different depending selected device. options usually covered those screens. Good tool learn devices work test features. Possibility build some small applications connecting devices together through headers.
Universal Receiver Transmitter Screen
Commands Programming
sequencing parameters
DesignCon 2003 TecForum Overview
Slide
Sequencer Send Sequence selected programming message DesignCon 2003 TecForum Overview Programmable delay between messages
There many interesting features Win-I2CNT system that help experiment with devices.
Slide Slide shows universal screen where command sequence used program device.
AN10216-01 Manual
Order 2002-1A Evaluation idea look general systems that dynamic address allocation (even including ones that hardware) find software design ideas building these systems.
Obtain Evaluation
2002-1A Evaluation Board consists the: 2002-1A Evaluation Board I2CPort Adapter Card parallel port 4-wire connector cable Adapter Card cable included) power supply CD-ROM with operating instructions Win-I2CNT software that provides easy graphical interface specific devices evaluation board also with general purpose mode other devices.
SMBus Electrical Differences
Purchase 2002-1A Evaluation Board www.demoboard.com
DesignCon 2003 TecForum Overview
Slide Comparison with SMBus
Power version SMBus Specification only SMBus specification found SMBus site www.SMBus.org
Some words SMBus
Protocol derived from Original purpose: define communication link between: intelligent battery charger microcontroller Most recent specification: Version Include power version "normal" power version found www.SMBus.org Some minor differences between SMBus: Electrical Timing Operating modes
DesignCon 2003 TecForum Overview
DesignCon 2003 TecForum Overview
Slide SMBus used today system management most PCs. Developed Intel others 1995, modified some electrical software characteristics better compatibility with quickly decreasing power supply budget portable equipment. SMBus also "High Power" version that includes sink current" version that strictly cannot driven chips.
Slide SMBus uses hardware, hardware addressing, adds second-level software building special systems. particular specifications include "Address Resolution Protocol" that make dynamic address allocations. "Dynamic reconfiguration: hardware software allow devices "hot-plugged" used immediately, without restarting system. devices recognized automatically assigned unique addresses. This advantage results plug-and-play user interface." both those protocols there very useful distinction made between System Host other devices system that have names, functions, masters slaves. also used hardware with some form dynamic address assignment Optical network module specifications find this website:
SMBus Timing operating modes Differences
Timing: Minimum clock frequency Maximum clock frequency Clock timeout Operating modes slaves must acknowledge their address time (mechanism detect removable device's presence)
DesignCon 2003 TecForum Overview
Slide I2C/SMBus compliancy SMBus protocols basically same: SMBus master will able control devices vice-versa protocol level. SMBus clock defined from while
AN10216-01 Manual
kHz, kHz, MHz). This means that running frequency lower than will SMBus compliant since specification does allow Logic levels slightly different also: SMBus: 0.8V high 2.1V, 30%/70% CMOS level I2C. This deal device below then there problem since logic hi/lo levels recognized. Timeout feature: SMBus timeout feature, resetting devices communication takes long (thus explaining clock frequency kHz). "DC" meaning that slave device stretches master clock when performing some routine while master accessing This will notify master: "I'm busy right want loose communication with you, hold little will continue when done" "little bit" eternity, least lower than kHz). SMBus protocol just assumes that something takes long, then means that there problem that everybody must reset order clear this mode. Slave devices then allowed hold clock long. Differences SMBus SMBus Here statement from SMBus document: This specification defines classes electrical characteristics, power high power. first class, originally defined SMBus specifications, designed primarily with Smart Batteries mind, could used with other lowpower devices. This version specification introduces alternative higher power electrical characteristics. This class appropriate when higher drive capability required, example with SMBus devices add-in cards connecting such cards across connector between each other SMBus devices system board. Devices powered another power source, VBus, with, example, Smart Batteries) will inter-operate long they adhere SMBus electrical specifications their class. Philips devices have higher power electrical characteristics than SMBus1.0. Main parameter current sink capability with 0.4V. SMBus power SMBus high power Philips SMBus "high power" devices also electrically compatible with specifications SMBus devices from others always compatible with I2C. Philips devices electrically compatible with power SMBus specifications will normally conform software features like time-out. Example typical slave device, PCA9552. will SMBus compliant Fclock device works 3.3V higher environment Note: PCA9552 will able reset itself communication time higher than timeout value. That pretty much case Philips devices. Often time-out feature added cents discrete hardware. Slide Intelligent Platform Management Interface (IPMI) Intel initiative conjunction with Dell consists three specifications: IPMI software extensions Intelligent Platform Management (IPMB) intra-chassis side box) extensions Inter Chassis Management (ICMB) interchassis (outside box) extensions Needed since complexity systems increase, MTBF decreases. IPMI defines standardized, abstracted, message-based interface intelligent platform management hardware defines standardized records describing platform management devices their characteristics. IPMI provides self monitoring capability increasing reliability systems IPMI Provides self monitoring capability increasing reliability systems Monitor server physical health characteristics: Temperatures Voltages Fans Chassis intrusion General system management: Automatic alerting Automatic system shutdown re-start Remote re-start Power control
AN10216-01 Manual
More information: Standardized protocol extending management control, monitoring, event delivery within chassis: based Multi-master Simple Request/Response Protocol Uses IPMI Command sets Supports non-IPMI devices Physically write only (master capable devices), swap required. Enables Baseboard Management Controller (BMC) accept IPMI request messages from other management controllers system. Allows non-intelligent devices well management controllers bus. serves controller give system software access IPMB Defines standardized interface intelligent platform management Hardware Prediction early monitoring hardware failures Diagnosis hardware problems Automatic recovery restoration measures after failure Permanent availability management Facilitate management recovery Autonomous Management Functions: Monitoring, Event Logging, Platform Inventory, Remote Recovery Implemented using Autonomous Management Hardware: Designed Microcontrollers based implementations Hardware implementation isolated from software implementation sensors events then added without software changes
Overall IPMI Architecture
ICMB
IPMB
DesignCon 2003 TecForum Overview
Slide Where IPMI being used Intel Server Management Servers today mission-critical applications. There literally time downtime. That Intel created Intel® Server Management hardware software technologies built right into most Intel® sever boards that monitors diagnoses server health. Intel Server Management helps give your customers more server uptime, increased peace mind, lower support costs, revenue opportunities. More information: /server_management PICMG PICMG (PCI Industrial Computer Manufacturers Group) consortium over companies collaboratively develop open specifications high performance telecommunications industrial computing applications. PICMG specifications include CompactPCI® Eurocard, rack mount applications PCI/ISA passive backplane, standard format cards. Recently, PICMG announced beginning development series specifications, called AdvancedTCATM, next-generation telecommunications equipment, with form factor based switched fabric architectures. More information found http://www.picmg.org
AN10216-01 Manual
IPMI within PICMG
Known cPCI cPCI
AdvancedTCA
Specification PICMG PICMG PICMG
Based IPMI IPMI
Comments IPMB Single swap IPMB optional Dual redundant swap IPMB mandatory
Slide shows redundant buses that would interface through PCA9511 PCA9512/13/14.
Motorola, Mostek Signetics cooperated define standard Mechanical standard based Eurocard format. Large body mechanical hardware readily available socket connector scheme more resilient mechanical wear than older printed circuit board edge connectors. Hundreds component manufacturers support applications such industrial controls, military, telecommunications, office automation instrumentation systems.
DesignCon 2003 TecForum Overview
PICMG 2.0: CompactPCI Core PICMG 2.9: System Management PICMG 3.0: AdvancedTCA Core Ethernet Star (1000BX XAUI) FC-PH links mixed with 1000BX InfiniBand® Star Mesh StarFabric Express
DesignCon 2003 TecForum Overview
Slide IPMI with additional extension used basis PICMG PICMG 3.x.
www.vita.com
Managed ATCA Board Example
Slide VMEbus VMEbus computer architecture. term 'VME' stands VERSAmodule Eurocard first coined 1980 group manufacturers defined This group composed people from Motorola, Mostek Signetics corporations were cooperating define standard. term 'bus' generic term describing computer data path, hence name VMEbus. Actually, origin term 'VME' never been formally defined. Other widely used definitions VERSAbus-E, VERSAmodule Europe VERSAmodule European. However, term 'Eurocard' tends better, VMEbus originally combination VERSAbus electrical standard, Eurocard mechanical form factor. VERSAbus first defined Motorola Corporation 1979 68000 microprocessor. Initially, competed with other buses such MultibusTM, Bus, S-100 Q-bus. However, rarely used anymore. microcomputer industry began with advent microprocessor, 1980 many buses were showing their age. Most worked well with only types microprocessors, small addressing range were rather slow. VMEbus architects were charged with defining that would microprocessor independent, easily upgraded from 32-bit data paths, implement reliable mechanical standard allow independent vendors build compatible products. proprietary rights were assigned bus, which helped stimulate third party product development. Anyone make VMEbus products without royalty fees licenses. Since much work already done VERSAbus used framework standard.
PCA9511
PCA9511
Dual, redundant -48VDC power distribution each card high current, bladed power connector High frequency differential data connectors Robust keying block alignment pins Robust, redundant system management 280mm card size 1.2" (6HP) pitch Flexible rear connector area
DesignCon 2003 TecForum Overview
Slide Slide shows IPMI used within AdvancedTCA card.
Managed ATCA Shelf: Example
PCA9511 PCA9511 PCA9511 PCA9511
PCA9511 PCA9511
PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511
DesignCon 2003 TecForum Overview
Slide
AN10216-01 Manual
Device Overview addition, mechanical standard based Eurocard format chosen. Eurocard term that loosely describes family products based around 41612 603-2 connector standards, IEEE 1101 board standards 41494 297-3 rack standards. When VMEbus first developed, Eurocard format been well established Europe several years. large body mechanical hardware such card cages, connectors sub-racks were readily available. socket connector scheme more resilient mechanical wear than older printed circuit board edge connectors. marriage VERSAbus electrical specification Eurocard format resulted VMEbus Revision released 1981. VMEbus specification since been refined through revisions C.1, 821, IEEE 1014-1987 ANSI/VITA 1-1994. ANSI, VITA, IEEE standards important because they make VMEbus publicly defined specification. Since proprietary rights assigned vendors users need worry that their products will become obsolete whim single manufacturer. Since introduction, VMEbus generated thousands products attracted hundreds manufacturers boards, mechanical hardware, software interface chips. continues grow support diverse applications such industrial controls, military, telecommunications, office automation instrumentation systems. IPMI Architecture draft standard indirectly calls IPMI over system management protocol since there nothing gained reinventing different form system management VME. only change from PICMG system management specification redefine backplane pins used redefine capacitance that board present bus. change required because backplane connectors different from cPCI. capacitance change required because cPCI have maximum slots have maximum slots. System Management Draft Standard VITA 200x Draft draft provides more information.
Device Categories
Reception Radio Reception Audio Processing Infrared Control DTMF display control Clocks/timers General Purpose display control Extension/Control Converters EEPROM/RAM Hardware Monitors Microcontroller
DesignCon 2003 TecForum Overview
Slide devices broken down into different categories. reception: Provides tuning reception Radio reception: Provides radio tuning reception Audio Processing Infra-Red control DTMF: Dual Tone Multiple Frequency display control: Provides power segments that controlled display control: Provides power segments that controlled Real time clocks event counters: counting passage time, chronometer, periodic alarms safety applications, system energy conservation, time date stamp point sales terminals bank machines. General Purpose Digital Input/Output (I/O): monitoring `YES' `NO' information, such whether switch closed tank overflows; controlling contact, turning LED, turning relay, starting stopping motor, reading digital number presented port (via switch, example). Extension/Control: expends beyond limit, allows different voltage devices same allows devices with same address selectively addressed bus. Analog/digital conversion: measurement size physical quantity (temperature, pressure.), proportional control; transformation physical analog values into numerical values calculation. Digital/analog conversion: creation particular control voltages control motors contrast. RAM: Random Access Memory
AN10216-01 Manual
EEPROM: Electrically Erasable Programmable Read Only Memory, retains digital information even when powered down Hardware Monitors: monitoring temperature voltage systems Microprocessors: Provides brains behind operation. devices designed process that allows best electrical performance manufactured Philips third party fabs through world. Philips taken initiative offer same process multiple internal fabs provide redundancy continuation supply market condition. Reception
Product Characteristics
Package Offerings Typically DIP, SSOP, QSOP, TSSOP HVQFN packages Frequency Range Typically operation Newer devices operating Graphic devices Operating Supply Voltage Range Newer devices with tolerance Operating temperature range Typically Some Hardware address pins Typically three (AO, provided allow eight identical device same sometimes limitations there fewer address pins
DesignCon 2003 TecForum Overview
Reception
SAA56xx family microcontrollers derivative Philips industry-standard 80C51 microcontroller intended central control mechanism television receiver. They provide control functions television system, incorporate integrated Data Capture display function either Teletext Closed Caption. Additional features over SAA55xx family have been included, e.g. 100/120 (2H/2V only) display timing modes, page operation (50/60 mode 16:9, 4:3), higher frequency microcontroller, increased character storage, more 80C51 peripherals larger Display memory. operation, only 50/60 display option available. Byte level dual port
DesignCon 2003 TecForum Overview
Slide frequency range most newer devices moving future devices where typical uses would consumer electronics where master designer wants rapidly send information then move other processing needs. operating range most newer CMOS devices allow operation 2.5, nodes. Some processes restrict voltage range node. Most customers have moved from several moving rapidly even near future. working next generation general purpose devices support operation currently have some display drivers that operate down operating temperature range typically specified industrial temperature range again depending process application, range specified higher lower. automotive, military aviation industries have expressed more interest devices cost simplicity operation future devices temperature ranges expanded meet their needs. devices were typically offered either limited their equipment where space premium. Newer devices typically offered TSSOP near chip scale HVQFN packages.
Slide used means easily move control status information devices. SA56xx given example this type device. Radio Reception
Radio Reception
TEA6845H single with radio tuner intended microcontroller tuning with provides following functions:
double conversion receiver bands) with 10.7 single conversion receiver with integrated image rejection 10.7 capable selecting weather, Europe East Europe Japan bands.
DesignCon 2003 TecForum Overview
Slide Again, used control frequency selection control audio sound control interface with microcontroller. Special software programs, applied connecting during factory testing, automatically perform alignment sections receiver, eliminating need manual mechanical adjustments. alignment information will stored some non-volatile memory
AN10216-01 Manual
chip re-sent receiver chip, where stored R.A.M., each time power applied receiver. Audio Processing chip voltage reference PCD3311C PCD3312C provide constant output amplitudes that independent operating supply voltage ambient temperature. on-chip filtering system assures very total harmonic distortion accordance with CEPT recommendations. addition standard DTMF frequencies devices also provide: Twelve standard frequencies used simplex modem applications data rates from 1200 bits second octaves musical scales steps semitones. Display Driver
Audio Processing
SAA7740H functionspecific digital signal processor. device capable performing processing listening-environments such equalization, hall-effects, reverberation, surround-sound digital volume/balance control. SAA7740H also reconfigured dual quad filter mode) that used digital filter with programmable characteristics. SAA7740H realizes most functions directly hardware. flexibility exists possibility download function parameters, correction coefficients various configurations from host microcontroller. parameters passed real time functions switched simultaneously. SAA7740H accepts digital stereo signals I2S-bus format audio sampling frequency (fast provides digital stereo outputs.
DesignCon 2003 TecForum Overview
Display Driver
Display Control Display size: line characters icons DDRAM CGRAM Sequencer Control logic
driver
Slide used control audio sound balance. Dual Tone Multi-Frequency (DTMF)
Column driver
CGROM Bias voltage Voltage generator multiplier
Supply
DTMF/Modem/Musical Tone Generators
Display driver complex device example "complete" system chip generates voltages, adjusts contrast, temperature compensates, stores messages, CGROM etc.
DesignCon 2003 TecForum Overview
Slide display driver complex driver example "complete" system chip generates voltages, adjusts contrast, temperature compensates, stores messages, CGROM etc.
Modem musical tone generation Telephone tone dialing DTMF Dual Tone Multiple Frequency baud rate modem
DesignCon 2003 TecForum Overview
Segment Driver
Segment Control Display sizes single chip:
Slide
Control logic
PCD3311C PCD3312C single-chip silicon gate CMOS integrated circuits. They intended principally telephone sets provide dualtone multi-frequency (DTMF) combinations required tone dialing systems. various audio output frequencies generated from on-chip 3.58 quartz crystal-controlled oscillator. separate crystal used, separate microcontroller required control devices. Both devices interface compatible microcontrollers serial input. PCD3311C also interface directly standard microcontrollers, accepting binary coded parallel input. With their on37
Supply
Bias voltage generator
Sequencer
Backplane drivers
Segment drivers
Segment driver less complex driver (e.g., just segment driver).
DesignCon 2003 TecForum Overview
Slide segment driver less complex driver (e.g., just segment driver). Philips focus large
AN10216-01 Manual
volume consumer display apps, which right color displays near future will OLED (organic displays). OLED drivers will most probably useable with conventional LEDs. beyond current roadmap that stretches only about VGA. This simply because requirements that mobile telecomm market, main focus. find already that does give enough transmission rate display data serial mainly intended control text overlay signals such displays. Light Sensor recently developed technically most advanced. RTCs have interrupt output track exact year. This must done software customer. They 4-year calendar base count years. PCF8583 added advantage bytes integrated with RTC. This could important such small required then replace chips with one. General Purpose Expanders
General Purpose Expanders
General Purpose Supply I2C-bus interface Interrupt Input/ output stages alternative analog input configurations
address decoder
Light Sensor
TSL2550 sensor converts intensity ambient light into digital signals that, turn, used control backlighting display screens found portable equipment, such laptops, cell phones, PDAs, camcorders, systems. device also used monitor control commercial residential lighting conditions. allowing display brightness adjusted ambient conditions, sensor expected bring about significant reduction power dissipation portables. TSL2550 all-silicon sensor combines photodetectors, with detectors sensitive both visible infrared light other sensitive only light. photodetectors's output converted digital format, which form information used approximate response human ambient light conditions sans element, which cannot perceive.
DesignCon 2003 TecForum Overview
Transfers keyboard, ACPI Power switch, keypad, switch other inputs microcontroller Expand microcontroller where located near source various cards outputs drive LEDs, sensors, fans, enable other input pins, relays timers Quasi outputs used Input Output without configuration register.
DesignCon 2003 TecForum Overview
Slide Let's talk about some newer devices, such these general-purpose input output (GPIO) expansion I2C/SMBus.
Slide Slide shows innovation light detectors that uses transfer information from sensor. Real Time Clock/Calendar
Quasi Output Expanders Registers
program outputs
Address OUTPUT DATA
Latches
Multiple writes possible during same communication Multiple reads possible during same communication
read input values
Address INPUT DATA
Real Time Clock/Calendar
Real-Time Clock Calendar 32kHz Counters: min, day, month, year Oscillator prescaler
Real time clocks event counters count passage time chronometer They used applications such
Important know
power-up, I/O's HIGH; Only current source active additional strong pull-up resistors allows fast rising edges I/O's should HIGH before using them Inputs
DesignCon 2003 TecForum Overview
Alarm-, TimerRegisters (240 Byte 8583)
I2C-bus interface
periodic alarms safety applications system energy conservation time date stamp point sales terminals bank machines
Interrupt
address decoder
Slide PCF8574 PCA8575 well known general purpose expanders. PCA9500 combination PCF8574 with EEPROM. interrupt replaced EEPROM write protect (WP). EEPROM different fixed address then GPIO. PCA9501 combination PCF8574 with EEPROM. device offered 20-pin TSSOP package four extra pins allow
DesignCon 2003 TecForum Overview
Slide Philips offers four RTCs, these PCF8593, PCF8583, PCF8573 PCF8563. PCF8563 most
AN10216-01 Manual
interrupt output included addition extra three pins then used offer total address pins allowing these devices share same bus. devices design telecom maintenance control applications. PCA9558 combination PCA9557 with EEPROM 5-bit Switch.
True Output Expanders Example
Input Reg# Polarity Reg# Read/ Write Config Reg# Read/ Write Output Reg# Read/ Write I/O's
True Output
Address Address
Expanders Registers
CONFIG DATA POLARITY DATA
Read
configure device
need access Configuration Polarity registers once programmed
DesignCon 2003 TecForum Overview
program outputs
Address OUTPUT DATA
Slide
Multiple writes possible during same communication
read input values
Address Address INPUT DATA
Slide shows example PCA9554/54A/57 programmable.
Multiple reads possible during same communication
DesignCon 2003 TecForum Overview
Signal monitoring and/or Control
Advantages
Easy implement (Hardware Software) Extend microcontroller: I/O's located near source various cards Save GPIO's microcontroller Only wires needed, independently numbers signals Signal(s) from masters Fast enough control keyboards Simplify layout Devices exist market massively used
Slide These newer device's true outputs provide active source sink current sources does rely upon pull resistor provide source current. four sets registers within true outputs devices programmable provide for: Configuration (Input Output) control, Input (value), Output (value) Polarity (active high low). PCA9554/54A/55 devices have interrupt output pins configured interrupt inputs. These newly released devices have same address footprint PCF8574/74A/75 require some software modifications different registers. PCA9554 PCA9555 have same address while PCA9554A slightly different fixed address allowing devices (eight eight 54/55 combination) same I2C/SMBus. PCA9556/57 feature Hardware Reset instead interrupt output that allows device reset remotely should become hung PCA9557 improved version PCA9556 that electrical characteristics PCA9554/54A. Information GPIO selection contained within application note AN469.
DesignCon 2003 TecForum Overview
Slide Signal Monitoring and/or Control first approach GPIO's master(s) controlling application. some applications, these GPIO's best approach. Reasons following: Number signals monitor/control important requires amount master's GPIO's. Signals remote location implying more complex layout, with long traces (making design more sensitive noise) Upgrade (more signals monitor/control) requires total re-layout limited number GPIO's still available master.
AN10216-01 Manual
Signal monitoring and/or Control
Proposed devices
(20-25 8574/74A CA9500/58 CA9501 8575/75C
tied sending repeated transmissions blink LEDs currently done when GPIO used. PCA9530/31/32/33 PCA9550/51/52/53 provide same amount electrical sink capability PCA9554/55/57 have built oscillator programmable blink rates. user definable blink rates duty cycles programmed I2C/SMBus. These programmed during initial range between every seconds Dimmers between every seconds Blinkers. Thereafter only single transmission required turn individual LEDs: blink programmable blink rates. duty cycle used `dim' LEDs using Dimmers setting blink rate (faster than blinking) then changing average current through changing duty cycle. internal oscillator regulated accuracy external components required. tolerance recommended human factor engineers. These devices allow program specific blink rates then command blink these rates without sending further commands. normal GPIOs blink LEDs, must send command followed command followed command duration blink. This have many LEDs blink much traffic bus, have microcontroller overhead burn, this many LEDs will your micro controller. Hence need dedicated blinkers stand alone part option. Unused pins used normal input output, since they open-drain, pull resistor will needed logic high outputs. Hardware Reset included, allowing blinker reset independently from rest I2C/SMBus higher level system. Each open drain output sink current with total package sinking capacity limited devices device (100 each byte). Typical LEDs take 10-25 current when operation.
Outputs
Reset
Interrupt
True Output (20-25 sink source) PCA9556/57 PCA9534/54/54A PCA9535/55
Advantages
Number scalable Programmable address allowing more than device Interrupt output monitor changes inputs Software controlling device(s) easy implement
DesignCon 2003 TecForum Overview
Slide GPIO device approach provides elegant solution with minimum hardware software changes: device(s) plugged existing application Minor software change required control device(s) Easily upgradeable adding more GPIO devices) Remote signals easily controlled (requires only longer trace wires only) Changes monitored input signals propagated master through single Interrupt line. master easily interrogate GPIO determine which input(s) generated Interrupt Application Note AN469 more information GPIOs. Dimmers Blinkers
Dimmers Blinkers
Supply address decoder I2C-bus interface alternative analog input configurations Reset Input/ output stages
I2C/SMBus tied sending repeated transmissions turn LEDs then "blink" LEDs. Frees micro's timer Continues blink LEDs even when longer connected master used cycle relays timers Higher frequency rate allows LEDs dimmed varying duty cycle Red/Green/Blue color mixing applications.
DesignCon 2003 TecForum Overview
Slide These devices useful driving blinking. I2C/SMBus micro controller
Oscillator
AN10216-01 Manual
Blinkers Dimmers
Frequency Duty Cycle (00H) (00H)
(FFH) (FFH) 99.6 Blinkers Dimmers
Input Register(s) PWM0 PSC0
Frequency Duty Cycle
PWM0
PSC0 PWM1
PSC0 PWM1
PWM1 PSC1
PSC1
PSC1
LED0Selector
OFF, BR1,
DesignCon 2003 TecForum Overview
GPIO's used control LEDs order visual status, like example blink slowly when normal condition, blink faster alarm mode. main disadvantages this method following: ON/OFF commands need sent time master tied sending ON/OFF commands when LEDs needs controlled least timer master needs dedicated this purpose Blinking lost hangs master fails
Slide Slide shows register configuration Blinkers Dimmers.
Products:
Using visual status
Outputs Reset PCA9550 PCA9553 PCA9551 PCA9552
Blinkers
Blinking between times second once every seconds
Blinkers Dimmers Programming
program blinking rates
Address PSC0 pointer PSC1 PSC0 PWM1 PWM0
Outputs
Reset PCA9530 PCA9533 PCA9531 PCA9532
Dimmers
Blinking between times second once every seconds. used dimming/brightness stepper motor control
PSC0 pointer 8-bit devices PSC0 pointer 16-bit devices
program drivers
Address SEL0 pointer LEDSEL2 LEDSEL0 LEDSEL3 LEDSEL1
DesignCon 2003 TecForum Overview
Slide blinkers provide elegant autonomous solution: They have built-in accurate oscillator requiring external components They programmed access selectable fully programmable blinking rates) Output state (Blinking rate Blinking rate Permanently Permanently OFF) programmed access anytime. Blinking lost, once device programmed, case hangs master fails. Application Note AN264 more information Dimmers/Blinkers.
LEDSEL0 pointer 8-bit devices LEDSEL0 pointer 16-bit devices Only 16-bit devices have selector reg
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