Bank Number VREFB Group VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 V

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Bank Number VREFB Group VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 V

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Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 Name Function VCCIO1 VCCIO1 DATA0 DCLK CLK0 CLK1 nCONFIG CLK2 CLK3 VCCIO1 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 ASDO nCSO LVDS9p LVDS9n LVDS8p LVDS8n LVDS7p LVDS7n LVDS6p LVDS6n VREFB1N0 LVDS5p LVDS5n DATA0 DCLK ASDO nCSO CRC_ERROR CLKUSR DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DQ0L6 DQ0L7 DM0L DQ1L0 DPCLK1/DQS1L DQ1L6 DQ1L7 DQ1L8 DM1L0/BWS#1L0 DQ1L9 DPCLK0/DQS0L DQ1L0 DQ1L1 DQ1L2 DQ1L3 x8/x9 Q208 x16/x18 x8/x9 Q208 F256 x16/x18 F256
DQ0L0 DQ0L1 DQ0L2 DQ0L3 DQ0L4
DQ1L0 DQ1L1 DQ1L2 DQ1L3 DQ1L4
DPCLK0/DQS0L
DPCLK0/DQS0L
DPCLK0/DQS0L DQ0L5
DPCLK0/DQS0L DQ1L5
DATA0 DCLK LVDSCLK0p/input(3) LVDSCLK0n/input(3)
nCONFIG LVDSCLK1p/input(3) LVDSCLK1n/input(3) LVDS4p LVDS4n LVDS3p LVDS3n LVDS2p
DQ1L4 DQ1L5 DQ1L6
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 Name Function VCCIO1 GND_PLL1 VCCD_PLL1 GND_PLL1 VCCA_PLL1 GNDA_PLL1 VCCIO4 VCCIO4 VCCINT Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 LVDS2n VREFB1N1 x8/x9 Q208 x16/x18 x8/x9 Q208 F256 DQ1L1 DQ1L2 DQ1L7 DQ1L8 DM1L/BWS#1L DQ1L3 DQ1L4 DQ1L5 DQ1L6 DQ1L7 DQ1L8 DM1L/BWS#1L x16/x18 F256 DQ1L10 DQ1L11 DQ1L12 DQ1L13 DQ1L14 DQ1L15 DQ1L16 DQ1L17 DM1L1/BWS#1L1
LVDS1p LVDS1n LVDS0p LVDS0n PLL1_OUTp PLL1_OUTn
LVDS58n LVDS58p LVDS57p LVDS57n LVDS56p LVDS56n LVDS55p LVDS55n
DEV_OE
DM1B/BWS#1B DQ1B8 DQ1B7 DQ1B6 DQ1B5 DPCLK2/DQS1B
DM1B/BWS#1B DQ1B8 DQ1B7 DQ1B6 DQ1B5 DPCLK2/DQS1B
DM1B1/BWS#1B1 DQ1B17 DQ1B16 DQ1B15 DQ1B14 DPCLK2/DQS1B
DM1B/BWS#1B DQ1B8 DQ1B7 DQ1B6 DQ1B5 DPCLK2/DQS1B DQ1B4
DM1B1/BWS#1B1 DQ1B17 DQ1B16 DQ1B15 DQ1B14 DPCLK2/DQS1B DQ1B13
DQ1B3 DQ1B12
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 Name Function VCCIO4 VCCIO4 VCCINT VCCIO4 VCCIO4 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 VREFB4N1 LVDS54p LVDS54n LVDS60p LVDS60n LVDS53p LVDS53n LVDS52p LVDS52n LVDS59p LVDS59n LVDS51p LVDS51n DM0B DQ1B8 DQ1B4 x8/x9 Q208 DQ1B4 DQ1B3 x16/x18 x8/x9 Q208 F256 DQ1B13 DQ1B12 DQ1B2 DQ1B1 x16/x18 F256 DQ1B11 DQ1B10
DQ1B3 DQ1B2 DQ1B1 DQ1B0
DQ1B2 DQ1B1 DQ1B0
DQ1B11 DQ1B10 DQ1B9
DQ1B0
DQ1B9 DM1B0/BWS#1B0
LVDS50p LVDS50n LVDS49p LVDS49n LVDS48p LVDS48n VREFB4N0 LVDS47p LVDS47n LVDS46p LVDS46n
DPCLK4/DQS0B DM0B DM1B0/BWS#1B0 DQ1B8 DQ1B7 DQ1B6 DQ1B5 DQ1B4 DPCLK4/DQS0B DQ1B3 DQ0B7 DQ1B7
DQ0B7 DQ0B6 DQ0B5 DQ0B4 DPCLK4/DQS0B DQ0B3
DQ0B6 DQ0B5 DPCLK4/DQS0B DQ0B4
DQ1B6 DQ1B5 DPCLK4/DQS0B DQ1B4
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N0 Name Function VCCIO4 VCCIO3 nSTATUS VCCIO3 CONF_DONE MSEL1 MSEL0 CLK7 CLK6 CLK5 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 LVDS45p LVDS45n LVDS44p LVDS44n LVDS43p LVDS43n LVDS42n LVDS42p LVDS41n LVDS41p LVDS40n LVDS40p LVDS39n LVDS39p LVDS38n LVDS38p VREFB3N1 LVDS37n LVDS37p nSTATUS CONF_DONE MSEL1 MSEL0 LVDS36n LVDS36p LVDSCLK3n/input(3) LVDSCLK3p/input(3) LVDSCLK2n/input(3) DM1R/BWS#1R DQ1R8 x8/x9 Q208 DQ0B2 DQ0B1 DQ0B0 x16/x18 x8/x9 Q208 F256 DQ1B2 DQ1B1 DQ1B0 DQ0B3 DQ0B2 DQ0B1 DQ0B0 x16/x18 F256 DQ1B3 DQ1B2 DQ1B1 DQ1B0
DM1R/BWS#1R
DM1R1/BWS#1R1
INIT_DONE nCEO
DQ1R8 DQ1R7 DQ1R6 DQ1R5 DQ1R4 DQ1R3 DQ1R2
DQ1R17 DQ1R16 DQ1R15 DQ1R14 DQ1R13 DQ1R12 DQ1R11
DM1R/BWS#1R DQ1R8 DQ1R7 DQ1R6 DQ1R5 DQ1R4
DM1R1/BWS#1R1 DQ1R17 DQ1R16 DQ1R15 DQ1R14 DQ1R13
DQ1R3 DQ1R2
DQ1R12 DQ1R11
DQ1R7 DPCLK6/DQS1R
DQ1R1 DPCLK6/DQS1R
DQ1R10 DPCLK6/DQS1R
DQ1R1 DPCLK6/DQS1R
DQ1R10 DPCLK6/DQS1R
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 Name Function CLK4 VCCIO3 VCCIO3 GND_PLL2 VCCD_PLL2 GND_PLL2 VCCA_PLL2 GNDA_PLL2 VCCIO2 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 LVDSCLK2p/input(3) LVDS35n LVDS35p LVDS34n LVDS34p LVDS33n LVDS33p LVDS32n LVDS32p LVDS31n LVDS31p VREFB3N0 LVDS30n LVDS30p DQ1R6 DPCLK7/DQS0R DQ1R5 DQ1R4 DQ1R3 DQ1R2 DQ1R1 x8/x9 Q208 DQ1R0 DPCLK7/DQS0R DM0R x16/x18 x8/x9 Q208 F256 DQ1R9 DQ1R0 DPCLK7/DQS0R DPCLK7/DQS0R DM1R0/BWS#1R0 DM0R DQ1R8 DQ1R7 DQ1R6 DQ1R5 DQ1R4 DQ1R3 DQ1R2 DQ1R1 DQ1R0 x16/x18 F256 DQ1R9 DPCLK7/DQS0R DM1R0/BWS#1R0 DQ1R8 DQ1R7 DQ1R6 DQ1R5 DQ1R4 DQ1R3 DQ1R2 DQ1R1 DQ1R0
DQ0R7 DQ0R6 DQ0R5 DQ0R4 DQ0R3 DQ0R2 DQ0R1 DQ0R0
DQ0R7 DQ0R6 DQ0R5 DQ0R4 DQ0R3 DQ0R2 DQ0R1 DQ0R0
LVDS29n LVDS29p PLL2_OUTp PLL2_OUTn
LVDS28n LVDS28p LVDS27n LVDS27p LVDS26n LVDS26p
DQ1R0
DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4
DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4
DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4
DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 Name Function VCCIO2 VCCINT VCCIO2 VCCIO2 VCCINT VCCIO2 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 DPCLK8/DQS0T x8/x9 Q208 x16/x18 x8/x9 Q208 F256 x16/x18 F256
LVDS25n LVDS25p VREFB2N0 LVDS24n LVDS24p LVDS23n LVDS23p LVDS22n
DPCLK8/DQS0T
DPCLK8/DQS0T
DQ0T5 DPCLK8/DQS0T
DQ1T5 DPCLK8/DQS0T
DQ0T5 DQ0T6 DQ0T7
DQ1T5 DQ1T6 DQ1T7 DQ1T8 DQ0T6 DQ0T7 DQ1T6 DQ1T7 DQ1T8
LVDS22p
LVDS21n LVDS21p LVDS20n LVDS20p
LVDS19n LVDS19p LVDS18n LVDS18p VREFB2N1 LVDS17n LVDS17p
DQ1T0 DQ1T1
DM0T
DM1T0/BWS#1T0
DM0T
DM1T0/BWS#1T0
DQ1T2
DQ1T0
DQ1T9 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4 DQ1T5 DQ1T9 DQ1T10 DQ1T11 DQ1T12 DQ1T13 DQ1T14
DQ1T1 DQ1T2 DQ1T3 DQ1T3 DQ1T4 DQ1T4 DQ1T5
DQ1T10 DQ1T11 DQ1T12 DQ1T13 DQ1T14
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 Name Function VCCIO2 VCCIO2 VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 LVDS16n LVDS16p LVDS15n LVDS15p LVDS14n LVDS14p LVDS13n LVDS13p LVDS12n LVDS12p LVDS11p LVDS11n LVDS10p LVDS10n x8/x9 Q208 x16/x18 x8/x9 Q208 F256 x16/x18 F256
DEV_CLRn
DQ1T5 DPCLK10/DQS1T DQ1T6 DQ1T7 DQ1T8 DM1T/BWS#1T
DPCLK10/DQS1T DQ1T6 DQ1T7 DQ1T8 DM1T/BWS#1T
DPCLK10/DQS1T DQ1T15 DQ1T16 DQ1T17 DM1T1/BWS#1T1
DQ1T6 DPCLK10/DQS1T DQ1T7 DQ1T8 DM1T/BWS#1T
DQ1T15 DPCLK10/DQS1T DQ1T16 DQ1T17 DM1T1/BWS#1T1
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group Name Function VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 x8/x9 Q208 x16/x18 x8/x9 Q208 F256 x16/x18 F256
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version Note (1),
Bank Number VREFB Group Name Function Optional Function(s) Configuration T144 Q208 F256 x8/x9 Function T144 x8/x9 Q208 x16/x18 x8/x9 Q208 F256 x16/x18 F256
Notes: Optional Functions (LVDS, DDR, etc) available some pins certain packages. E.g. EP2C8, LVDS70 pair available Q208 F256 T144. DQS0T, DQS1T, DQS0B DQS1B functions only available F672 F896 packages. dedicated pins used feed global clock networks, they used general-purpose input pins feed core logic. They have support register.
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Tables Page
Information CycloneII EP2C5 Device Version
Name Type (1st, 2nd, Function) Description Supply Reference Pins These internal logic array voltage supply pins. VCCINT also supplies power input buffers used LVPECL, LVDS(regular pins) ,differential HSTL differential SSTL standards. VCCINT pins must connected These supply voltage pins banks through Each bank support different voltage level. VCCIO supplies power output buffers standards. VCCIO also supplies power input buffers used LVTTL, LVCMOS, 3.3-V PCI, 3.3-V PCIX,differential SSTL, differential HSTL, LVDS (regular I/O) standards. Device ground pins. pins should connected board plane. Input reference voltage each bank. bank uses voltage-referenced standard, then these pins used voltage-reference pins bank. voltage reference standards used bank, VREF pins available user pins. Analog power PLLs[1.2]. designer must connect these pins even used. Designer advised keep isolated from other better jitter performance. Digital power PLLs[1.2]. designer must connect these pins even used. Analog ground PLLs[1.2]. designer connect this plane board. Ground PLLs[1.2]. designer connect this plane board. drive signals into these pins. Dedicated Configuration/JTAG Pins Dedicated configuration clock pin. configuration, DCLK used clock configuration data from external source into Cyclone device. mode, DCLK output from Cyclone device that provides timing configuration interface. DCLK should left floating. Designer should drive high low, whichever more convenient board. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. Dedicated configuration data input pin. serial configuration modes, bit-wide configuration data received through this pin. mode, DATA0 internal pull-up resistor that always active. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. Configuration input pins that Cyclone device configuration scheme. These pins must hardwired VCCPD GND. designer should connect MSEL[0.1] Fast JTAG-based Configuration. Dedicated active-low chip enable. When low, device enabled. When high, device disabled. multi-device configuration, first device tied while nCEO drives next device chain. single device configuration, tied low. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry.
VCCINT
Power
VCCIO[1.8]
Power Ground
VREFB[1.4]N[0.1] VCCA_PLL[1.2] VCCD_PLL[1.2] GNDA_PLL[1.2] GND_PLL[1.2]
Power Power Ground Ground Connect
DCLK
Input (PS) Output (AS)
DATA0
Input
MSEL[0.1]
Input
Input
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Definitions Page
Information CycloneII EP2C5 Device Version
Name Type (1st, 2nd, Function) Description Dedicated configuration control input. Pulling this during user-mode will cause FPGA lose configuration data, enter reset state tri-state pins. Returning this logic high level will initiate reconfiguration. configuration scheme uses enhanced configuration device EPC2, nCONFIG tied directly configuration device's nINIT_CONF pin. JTAG configuration used, nCONFIG tied VCC. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. This dedicated configuration status pin. status output, CONF_DONE drives before during configuration. Once configuration data received without error initialization cycle starts, CONF_DONE released. status input, CONF_DONE goes high after data received. Then device initializes enters user mode. available user pin. CONF_DONE should pulled high external 10-k pull-up resistor. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. This dedicated configuration status pin. FPGA drives nSTATUS immediately after power-up releases after time. status output, nSTATUS pulled error occurs during configuration. status input, device enters error state when nSTATUS driven external source during configuration initialization. available user pin. nSTATUS should pulled high external 10-k pull-up resistor. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. Dedicated JTAG input pin. JTAG circuitry disabled connecting GND. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. Dedicated JTAG input pin. JTAG circuitry disabled connecting VCC. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. Dedicated JTAG input pin. JTAG circuitry disabled connecting VCC. input buffer this supports hysteresis using Schmitt (Schmidt) trigger circuitry. Dedicated JTAG output pin. JTAG circuitry disabled leaving unconnected. Clockgand Pins global clock input user input pins. Dedicated global clock input pins that also used negative terminal inputs differential global clock input user input pins. Optional positive terminal external clock outputs from [1.2]. These pins only differential standard being output Optional negative terminal external clock outputs from PLL[1.2]. These pins only differential standard being output Optional/Dual-Purpose Configuration Pins
nCONFIG
Input
CONF_DONE
Bidirectional (open-drain)
nSTATUS CLK[0,2,4,6,8,10,12,14], LVDSCLK[0.7]p CLK[1,3,5,7,9,11,13,15], LVDSCLK[0.7]n PLL[1.2]_OUTp PLL[1.2]_OUTn
Bidirectional (open-drain) Input Input Input Output Clock, Input Clock, Input I/O, Output I/O, Output
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Definitions Page
Information CycloneII EP2C5 Device Version
Name Type (1st, 2nd, Function) Description Output that drives when device configuration complete. During multi-device configuration, this feeds subsequent device's must pulled high Vccio external pull-up resistor. During single device configuration last device multi-device configuration, this used user after configuration.
nCEO
I/O, Output
nCSO
I/O, Output
ASDO
I/O, Output
Output control signal from Cyclone FPGA serial configuration device mode that enables configuration device driving low. mode, nCSO internal weak pull-up resistor, which always active. Output control signal from Cyclone FPGA serial configuration device mode used read configuration data. mode, ASDO internal weak pull-up resistor, which always active.
Active high signal that indicates that error detection circuit detected errors configuration SRAM bits. This optional used when error detection circuit enabled. Optional chip-wide reset that allows override clears device registers. When this driven low, registers cleared; when this driven high, registers behave programmed. DEV_CLRn does affect JTAG boundary-scan programming operations. This enabled turning Enable device-wide reset (DEV_CLRn) option Quartus software. Optional that allows override tri-states device. When this driven low, pins tri-stated; when this driven high, pins behave defined design. This enabled turning Enable device-wide output enable (DEV_OE) option Quartus software. This dual-purpose status used when enabled INIT_DONE. When enabled, transition from high indicates when device entered user mode. INIT_DONE output enabled, INIT_DONE cannot used user after configuration. This enabled turning Enable INIT_DONE output option Quartus software.
CRC_ERROR
I/O, Output
DEV_CLRn
(when option off), Input (when option
DEV_OE
(when option off), Input (when option
INIT_DONE
I/O, Output (open-drain)
CLKUSR
Optional user-supplied clock input. Synchronizes initialization more devices. this enabled user-supplied configuration clock, used user pin. This enabled turning Enable user-supplied start-up clock (CLKUSR) option Quartus software. I/O, Input Dual-Purpose Differential External Memory Interface Pins Dual-purpose differential transmitter/receiver channels These channels used transmitting/receiving LVDS compatible signals. Pins with suffix carry positive signal differential channel. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins.
LVDS[0-59][p,n]
I/O, TX/RX channel
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Definitions Page
Information CycloneII EP2C5 Device Version
Name Type (1st, 2nd, Function) Description Dual-purpose DPCLK/DQS pins connect global clock network high-fanout control signals such clocks, asynchronous clears, presets clock enables. also used optional data strobe signal external memory interfacing. These pins drive dedicated phase shift circuitry, which allows fine tune phase shift input clocks strobes properly align clock edges needed capture data. Optional data signal external memory interfacing modes. Optional data signal external memory interfacing modes. Optional data mask pins x16/x18 modes required when writing SDRAM DDR2 SDRAM devices. signal indicates that write valid. signal high, memory masks signals. Each group signals requires pin. Optional data mask pins x8/x9 modes required when writing SDRAM DDR2 SDRAM devices. signal indicates that write valid. signal high, memory masks signals. Each group signals requires pin. Byte Write Select active pin. When asserted active, will select which byte written into device during write operation. Bytes written remain unchange. Deselecting will cause write data ignored written into device. Byte Write Select active pin. When asserted active, will select which byte written into device during write operation. Bytes written remain unchange. Deselecting will cause write data ignored written into device.
DPCLK[0,1,2,4,6,7,8,10]/ DQ1[B,L,R,T][0.17] DQ[0,1][B,L,R,T][0.8]
I/O, DPCLK/DQS I/O, I/O,
DM1[B,L,R,T][0,1]
I/O,
DM[0.1][B,L,R,T]
I/O,
BWS#1[B,L,R,T][0,1]
I/O,
BWS#[0.1][B,L,R,T]
I/O,
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Definitions Page
Information CycloneII EP2C5 Device,
VREFB2N1 VREFB2N0
PLL2
VREFB1N0
VREFB1N1
VREFB4N1 VREFB4N0 Bank Diagram VREFB3N1
PLL1
Notes: This view silicon die. 2.This pictoral representation only idea placement device. Refer list Quartus software exact locations.
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Page
VREFB3N0
Information CycloneII EP2C5 Device Version
Version Number Date 10/6/2004 1/18/2005 2/24/2005 5/3/2005 Changes Made Initial revision Added F256 package Modified Definitions DATA0 Added CRC_ERROR List Definition Changed name from GNDD_PLL GNDG_PLL GND_PLL Finalize Modified Type column Definitions VREFB[1.8]N[0.1] pins Modified LVDS naming List: LVDS12p/n LVDS22p/n LVDS22p/n LVDS21p/n LVDS21p/n LVDS20p/n LVDS20p/n LVDS19p/n LVDS19p/n LVDS18p/n LVDS18p/n LVDS17p/n LVDS11p/n LVDS16p/n LVDS17p/n LVDS15p/n LVDS10p/n LVDS14p/n LVDS16p/n LVDS13p/n LVDS15p/n LVDS12p/n LVDS14p/n LVDS11p/n LVDS13p/n LVDS10p/n Added footnote pins that support Optional Functions (LVDS, DDR, etc) Added footnote DQS0T, DQS1T, DQS0B DQS1B pins Modified Description pins Modified Description VREFB[1.4]N[0.1] pins Modified Description VCCA_PLL[1.4] VCCD_PLL[1.4] pins Added Description pins Added comment PLL_OUT pins Definitions Added "I/O" type nCEO, nCSO ASDO Modified Description NCONFIG, NCE, DATA0, TMS, TCK, TDI, NSTATUS, CONDONE DCLK pins Modified Description VCCIO VCCINT. Moved nCEO Discription from section "Dedicated Configuration/JTAG Pins" section "Optional/Dual-Purpose Configuration Pins" Modified Description number PLLs available from
6/2/2005 7/28/2005
2/10/2006
3/1/2006 6/16/2006
10/11/2006
PT-EP2C5-1.9 Copyright 2006 Altera Corp. Revision History Page

Bank Number VREFB Group VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 V

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