Bank Number VREF Bank Name/Function VCCA_PLL7 GNDA_PLL7 VCCG_PLL7 GNDG
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Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function VCCA_PLL7 GNDA_PLL7 VCCG_PLL7 GNDG_PLL7 FPLL7CLKp FPLL7CLKn VREF0B2 VREF1B2 Optional Function(s) Configuration Function B956 F1020 F1508 DIFFIO
Speed
VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2
DIFFIO_RX57p DIFFIO_RX57n DIFFIO_TX57p DIFFIO_TX57n DIFFIO_RX56p DIFFIO_RX56n DIFFIO_TX56p DIFFIO_TX56n DIFFIO_RX55p DIFFIO_RX55n DIFFIO_TX55p DIFFIO_TX55n DIFFIO_RX54p DIFFIO_RX54n DIFFIO_TX54p DIFFIO_TX54n DIFFIO_RX53p DIFFIO_RX53n DIFFIO_TX53p DIFFIO_TX53n DIFFIO_RX52p DIFFIO_RX52n DIFFIO_TX52p DIFFIO_TX52n DIFFIO_RX51p DIFFIO_RX51n DIFFIO_TX51p DIFFIO_TX51n DIFFIO_RX50p DIFFIO_RX50n DIFFIO_TX50p DIFFIO_TX50n DIFFIO_RX49p DIFFIO_RX49n DIFFIO_TX49p DIFFIO_TX49n DIFFIO_RX48p DIFFIO_RX48n DIFFIO_TX48p DIFFIO_TX48n DIFFIO_RX47p DIFFIO_RX47n DIFFIO_TX47p DIFFIO_TX47n DIFFIO_RX46p DIFFIO_RX46n DIFFIO_TX46p DIFFIO_TX46n DIFFIO_RX45p DIFFIO_RX45n DIFFIO_TX45p DIFFIO_TX45n DIFFIO_RX44p DIFFIO_RX44n DIFFIO_TX44p DIFFIO_TX44n
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 Name/Function VREF2B2 CLK0n CLK0p CLK1p VCCA_PLL1 GNDA_PLL1 VCCG_PLL1 GNDG_PLL1 VCCA_PLL2 Optional Function(s) DIFFIO_RX43p DIFFIO_RX43n DIFFIO_TX43p DIFFIO_TX43n DIFFIO_RX42p DIFFIO_RX42n DIFFIO_TX42p DIFFIO_TX42n DIFFIO_RX41p DIFFIO_RX41n DIFFIO_TX41p DIFFIO_TX41n DIFFIO_RX40p DIFFIO_RX40n DIFFIO_TX40p DIFFIO_TX40n DIFFIO_RX39p/RUP2 DIFFIO_RX39n/RDN2 DIFFIO_TX39p DIFFIO_TX39n DIFFIO_RX38p DIFFIO_RX38n DIFFIO_TX38p DIFFIO_TX38n DIFFIO_RX37p DIFFIO_RX37n DIFFIO_TX37p DIFFIO_TX37n DIFFIO_RX36p DIFFIO_RX36n DIFFIO_TX36p DIFFIO_TX36n DIFFIO_RX35p DIFFIO_RX35n DIFFIO_TX35p DIFFIO_TX35n DIFFIO_RX34p DIFFIO_RX34n DIFFIO_TX34p DIFFIO_TX34n DIFFIO_RX33p DIFFIO_RX33n DIFFIO_TX33p DIFFIO_TX33n DIFFIO_RX32p DIFFIO_RX32n DIFFIO_TX32p DIFFIO_TX32n DIFFIO_RX31p DIFFIO_RX31n DIFFIO_TX31p DIFFIO_TX31n DIFFIO_RX30p DIFFIO_RX30n DIFFIO_TX30p DIFFIO_TX30n Configuration Function B956 F1020 F1508 AA32 AA30 DIFFIO
Speed
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
CLK1n
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function GNDA_PLL2 VCCG_PLL2 GNDG_PLL2 CLK2p CLK2n CLK3p VREF0B1 VREF1B1 Optional Function(s) Configuration Function B956 F1020 F1508 DIFFIO
Speed
AA31 AA28 AA29 AA35 AA34 AA39 AA38 AA27 AA26 AA37 AA36 AB27 AB26 AB38 AB39 AA33 AE29 AB37 AB36 AB33 AB32 AC39 AC38 AB28 AB29 AC37 AC36 AB31 AB30 AD39 AD38 AC26 AC27 AD37 AD36 AC31 AC30 AE37 AE36 AC28 AC29 AF37 AF36 AD29 AD28 AE38 AF39 AB34 AB35 AF29 AF38 AG38 AC32 AC33 AG37 AG36 AC34 AC35 AH39 AH38 AD34 AD35 AH37
VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1
CLK3n DIFFIO_RX29p DIFFIO_RX29n DIFFIO_TX29p DIFFIO_TX29n DIFFIO_RX28p DIFFIO_RX28n DIFFIO_TX28p DIFFIO_TX28n DIFFIO_RX27p DIFFIO_RX27n DIFFIO_TX27p DIFFIO_TX27n DIFFIO_RX26p DIFFIO_RX26n DIFFIO_TX26p DIFFIO_TX26n DIFFIO_RX25p DIFFIO_RX25n DIFFIO_TX25p DIFFIO_TX25n DIFFIO_RX24p DIFFIO_RX24n DIFFIO_TX24p DIFFIO_TX24n DIFFIO_RX23p DIFFIO_RX23n DIFFIO_TX23p DIFFIO_TX23n DIFFIO_RX22p DIFFIO_RX22n DIFFIO_TX22p DIFFIO_TX22n DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n DIFFIO_RX20p/RUP1 DIFFIO_RX20n/RDN1 DIFFIO_TX20p DIFFIO_TX20n DIFFIO_RX19p DIFFIO_RX19n DIFFIO_TX19p DIFFIO_TX19n DIFFIO_RX18p DIFFIO_RX18n DIFFIO_TX18p DIFFIO_TX18n DIFFIO_RX17p DIFFIO_RX17n DIFFIO_TX17p DIFFIO_TX17n DIFFIO_RX16p DIFFIO_RX16n DIFFIO_TX16p DIFFIO_TX16n DIFFIO_RX15p
AB31 AA31
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
AA30 AB30
AA29
AA28
AB29 AB28
AC31 AD31 AE31 AF31 AC30 AD30 AF30 AE30 AG30
AA31 AA30 AB31 AB30 AA28 AA29 AA22 AB23 AB32 AC31 AA23 AD32 AD31 AC29 AC30 AD30 AD29 AE32
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 VREF3B1 Name/Function VREF2B1 VREF3B1 FPLL8CLKn FPLL8CLKp Optional Function(s) DIFFIO_RX15n DIFFIO_TX15p DIFFIO_TX15n DIFFIO_RX14p DIFFIO_RX14n DIFFIO_TX14p DIFFIO_TX14n DIFFIO_RX13p DIFFIO_RX13n DIFFIO_TX13p DIFFIO_TX13n DIFFIO_RX12p DIFFIO_RX12n DIFFIO_TX12p DIFFIO_TX12n DIFFIO_RX11p DIFFIO_RX11n DIFFIO_TX11p DIFFIO_TX11n DIFFIO_RX10p DIFFIO_RX10n DIFFIO_TX10p DIFFIO_TX10n DIFFIO_RX9p DIFFIO_RX9n DIFFIO_TX9p DIFFIO_TX9n DIFFIO_RX8p DIFFIO_RX8n DIFFIO_TX8p DIFFIO_TX8n DIFFIO_RX7p DIFFIO_RX7n DIFFIO_TX7p DIFFIO_TX7n DIFFIO_RX6p DIFFIO_RX6n DIFFIO_TX6p DIFFIO_TX6n DIFFIO_RX5p DIFFIO_RX5n DIFFIO_TX5p DIFFIO_TX5n DIFFIO_RX4p DIFFIO_RX4n DIFFIO_TX4p DIFFIO_TX4n DIFFIO_RX3p DIFFIO_RX3n DIFFIO_TX3p DIFFIO_TX3n DIFFIO_RX2p DIFFIO_RX2n DIFFIO_TX2p DIFFIO_TX2n DIFFIO_RX1p DIFFIO_RX1n DIFFIO_TX1p DIFFIO_TX1n DIFFIO_RX0p DIFFIO_RX0n DIFFIO_TX0p DIFFIO_TX0n Configuration Function B956 AH30 AC29 AD29 AE29 AF29 AA26 AH29 AG29 AC28 AD28 AE28 AF28 AA27 F1020 AE31 AE30 AE29 AF32 AF31 AF30 AF29 AG31 AG32 AB25 AG30 AG29 AA25 AA24 AH32 AH31 AA27 AA26 AH29 AG28 AB27 AB26 AG25 AG26 AC25 AC26 F1508 AH36 AD33 AD32 AJ39 AJ38 AD31 AD30 AJ37 AJ36 AE35 AE34 AK38 AK39 AE33 AE32 AK37 AK36 AF35 AF34 AG29 AL37 AL36 AF33 AF32 AM39 AM38 AG35 AG34 AN39 AN38 AG33 AG32 AM37 AM36 AH34 AH35 AP38 AP39 AK35 AK34 AN37 AN36 AH33 AH32 AR38 AR39 AJ35 AJ34 AT39 AT38 AJ33 AJ32 AH29 AM35 AM34 AK32 AK33 AP36 AP37 AL33 AL32 AR37 AR36 AH31 AH30 AL38 AL39 DIFFIO
Speed
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
AB27 AC27
AE27 AD27
AG27 AF27
AB26 AC26
AC27 AC28
AD26 AE26
AD28 AD27
AA25 AB25
AD26 AD25
AD25 AC25 AA22
AE28 AE27 AG27
AA24 AB24
AE25 AE26
AD24 AC24
AF27 AF28
AE25 AF25 AG31 AH31
AF26 AF25 AB29 AB28
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF3B1 VREF3B1 Name/Function VCCA_PLL8 GNDA_PLL8 VCCG_PLL8 GNDG_PLL8 VREF0B8 VREF1B8 Optional Function(s) Configuration Function B956 F1020 F1508 AG30 AG31 AJ30 AJ31 AL31 AK31 AR35 AU36 AT35 AN32 AV36 AT34 AN33 AV34 AP33 AU34 AL30 AU33 AR34 AW33 AU35 AW34 AW36 AV33 AJ29 AM31 AV32 AK29 AU32 AN31 AW32 AR33 AP32 AV35 AR32 AL29 AU31 AT33 AV31 AK28 AW31 AP31 AW30 AW35 AU30 AM29 AV30 AK27 AU29 AN30 AV29 AT32 AW29 AT31 AP29 AL28 AP30 AN29 AR28 AL27 AT28 AJ28 AR31 AU28 AR30 AV28 DIFFIO
Speed
AB23 AA23 AD23 AC23 AG28
AJ31 AJ32 AJ30 AH30 AB24
VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8
DQ9B7 DQ9B6 DQ9B5 DQ9B4 DQ9B3 DQS9B
AJ30 AK29 AJ29 AE24 AJ28 AF26 AL28 AH27 AK28 AB22 AH28 AL27 AJ27 AK27 AC22
AC24 AH28 AK30 AG24 AJ28 AC23 AJ29 AE24 AK29 AG23 AK28 AH27 AD24 AL30 AF24 AL29 AM29 AD23
DQ3B15 DQ3B14 DQ3B13 DQ3B12 DQ3B11
DQ1B31 DQ1B30 DQ1B29 DQ1B28 DQ1B27
DQ9B2 DQ9B1 DQ9B0
DQ3B10 DQ3B9 DQ3B8
DQ1B26 DQ1B25 DQ1B24
DQ8B7 DQ8B6 DQ8B5 DQ8B4 DQ8B3 DQS8B DQ8B2 DQ8B1 DQ8B0
AH26 AG26 AD22 AK26 AL26 AH25 AC21 AJ26 AK25 AJ25 AA21 AL25 AE22
AH26 AJ27 AE23 AL28 AF23 AK27 AB22 AJ26 AC22 AL27 AG22 AM27 AM28 AD22 AK26 AF22
DQ3B7 DQ3B6 DQ3B5 DQ3B4 DQ3B3 DQS3B DQ3B2 DQ3B1 DQ3B0
DQ1B23 DQ1B22 DQ1B21 DQ1B20 DQ1B19
DQ1B18 DQ1B17 DQ1B16
DQ7B7 DQ7B6
AG24 AH23 AB21 AA19 AK24 AH24
AH24 AJ24 AH25 AE22 AJ25 AA21 AK25
DQ2B15 DQ2B14
DQ1B15 DQ1B14
DQ7B5 DQ7B4
DQ2B13 DQ2B12
DQ1B13 DQ1B12
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 Name/Function VREF2B8 VREF3B8 CLK5p Optional Function(s) Configuration Function B956 AD21 AJ23 AJ24 AL24 AC20 AK23 AL23 F1020 AB21 AL25 AL26 AC21 AK24 AG21 AM25 AM26 F1508 AK26 AR27 AM28 AT27 AN28 AW28 AP28 AU27 AT30 AV27 AM27 AL26 AT29 AN26 AR29 AR26 AN27 AT26 AK25 AU26 AP27 AV26 AL25 AW26 AP26 AU25 AM26 AT25 AN25 AR25 AM25 AV25 AJ27 AH24 AK24 AJ24 AL24 AF23 AT24 AP25 AU24 AM24 AV24 AN24 AW24 AH23 AW23 AP24 AU23 AR24 AR23 AL23 AV23 AK23 AT23 AM23 AJ23 AR22 AL22 AN23 AN22 AP23 AP22 AJ26 AU22 AT22 AW22 DIFFIO
Speed
DQ2B11 DQ1B11 DQS1B DQ2B10 DQ2B9 DQ2B8 DQ1B10 DQ1B9 DQ1B8
DQ7B3 DQS7B DQ7B2 DQ7B1 DQ7B0
FCLK3 FCLK2 DQ6B7 DQ6B6 DQ6B5 DQ6B4 PGM2 DQ6B3 DQS6B DQ6B2 CRC_ERROR DQ6B1 DQ6B0 RDN8
AF23 AF22 AG22 AH22 AK22 AG21 AF24 AH21 AD20 AJ22 AL22 AE21 AJ21 AK21 AB20 AE23 AC19
AE21 AF21 AJ23 AL24 AH22 AD21 AM24 AA20 AK23 AG20 AJ22 AB20 AL23 AF20 AK22 AL22 AH23 AC20 AD20
DQ2B7 DQ2B6 DQ2B5 DQ2B4 DQ2B3 DQS2B DQ2B2 DQ2B1 DQ2B0
DQ1B7 DQ1B6 DQ1B5 DQ1B4 DQ1B3
DQ1B2 DQ1B1 DQ1B0
RUP8 DQ5B7 DQ5B6 DQ5B5 DQ5B4 RDYnBSY DQ5B3 DQS5B DQ5B2 DQ5B1 DQ5B0
AG25 AG20 AH20 AE20 AK20 AD19 AL20 AG23 AG19 AE19 AJ20 AH19 AF20 AJ19 AK19 AF21
AH19 AM22 AJ21 AE20 AK21 AK18 AL21 AA19 AH20 AB19 AJ20 AJ18 AK20 AC19 AL20 AD19 AM20 AG19
CLK5n CLK4n
AE18 AB19 AH18 AJ18 AK18
AH18 AH21 AJ19 AK19 AL19
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 Name/Function CLK4p PLL_ENA MSEL0 MSEL1 MSEL2 VCC_PLL6_OUTB VCC_PLL6_OUTA VCCA_PLL6 GNDA_PLL6 VCCG_PLL6 GNDG_PLL6 VCCA_PLL12 GNDA_PLL12 VCCG_PLL12 GNDG_PLL12 CLK7p CLK6p nCEO nIO_PULLUP VCCSEL PORSEL VREF0B7 Optional Function(s) Configuration Function PLL_ENA MSEL0 MSEL1 MSEL2 PLL6_OUT3n PLL6_OUT3p PLL6_OUT2n PLL6_OUT2p PLL6_FBn PLL6_FBp PLL6_OUT1n PLL6_OUT1p PLL6_OUT0n PLL6_OUT0p B956 AL18 AF19 AF18 AG18 AG17 AL17 AK17 AJ17 AH17 AJ15 AH15 AL15 AK15 AL16 AK16 AC18 AD17 AB17 AC17 AD15 AD16 AC14 AD14 AC15 AB15 AJ14 AH14 AL14 AK14 AF17 AF16 F1020 AM19 AF19 AG18 AE18 AE19 AM18 AL18 AK17 AJ17 AM17 AL17 AK16 AJ16 AM16 AL16 AB17 AE17 AG17 AH17 AD16 AB16 AG16 AH16 AF16 AE16 AM15 AL15 AK15 AJ15 AF18 AH15 F1508 AV22 AM22 AP21 AG21 AM21 AV20 AW20 AW21 AV21 AU20 AT20 AU21 AT21 AU19 AT19 AH21 AJ21 AK21 AL20 AJ20 AH20 AK19 AL19 AJ19 AH19 AW18 AV18 AW19 AV19 AN20 AP20 AP19 AR19 AG20 AR20 AM19 AN19 AH18 AJ18 AL18 AM18 AK18 AN18 AJ15 AP18 AR16 AR18 AM17 AT18 AU18 AL17 AH17 AU17 AJ17 AR17 AK17 AT17 AM16 AV17 AP16 AV16 AF16 AU16 AH16 AW17 DIFFIO
Speed
VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF1B7 VREF1B7 VREF1B7
CLK7n CLK6n/PLL12_OUT nCEO
PGM0 nIO_PULLUP VCCSEL PORSEL
AE17 AE16 AE15 AG16
AD18 AF15 AJ14 AG15
INIT_DONE
AF15
AE15
AB14 AA16
AH12 AC18
DQ4B7 DQ4B6 RUnLU DQ4B5 DQ4B4 DQ4B3 PGM1 DQS4B DQ4B2
AE14 AK13 AH16 AG13 AJ16 AH13 AA15 AJ13 AK12 AG15 AJ12 AA13 AL12
AB18 AA18 AL13 AE14 AM13 AF14 AH13 AD14 AJ13 AD15 AK13 AG14 AJ12 AB15 AK12
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 Name/Function VREF1B7 VREF2B7 Optional Function(s) Configuration Function B956 F1020 AC15 AL12 AH14 AM11 AC14 F1508 AP15 AT16 AN17 AW16 AP17 AK16 AJ16 AL16 AN16 AT15 AL15 AR15 AM15 AV15 AN15 AJ14 AV14 AP13 AW14 AM14 AU15 AP14 AR14 AR11 AT14 AN13 AU14 AK15 AM13 AP11 AL14 AT13 AN14 AT11 AU13 AM12 AV13 AT10 AV12 AP12 AR13 AP10 AU12 AR10 AR12 AK14 AT12 AL12 AW12 AN11 AN12 AL13 AJ13 AN10 AV11 AK13 AW11 AU10 AW10 AM11 AU11 AV10 DIFFIO
Speed
AG12 AF14 AH12 AG14
DQ4B1 DEV_CLRn DQ4B0 RDN7
RUP7 DQ3B7 DQ3B6 DQ3B5
AD13 AF13 AL10 AJ11 AC13 AK11 AE13 AB13 AG11 AH11 AD12 AJ10 AE12 AG10 AC12 AH10 AK10
DQ3B4 DQ3B3 DQS3B DQ3B2 DQ3B1 DQ3B0
AK14 AF13 AL10 AA15 AK11 AE13 AL11 AG13 AH10 AK10 AD13 AJ11 AL14 AE12 AJ10 AB14 AH11
DQ1B15 DQ1B14 DQ1B13
DQ0B31 DQ0B30 DQ0B29
DQ1B12 DQ1B11 DQS1B DQ1B10 DQ1B9 DQ1B8
DQ0B28 DQ0B27
DQ0B26 DQ0B25 DQ0B24
DQ2B7 FCLK5 FCLK4 DQ2B6 DQ2B5 DQ2B4 DQ2B3 DQS2B DQ2B2 DQ2B1 DQ2B0
AF12 AF11 AE11 AE10 AF10
AM14 AF12 AB13 AA14 AC13 AE11 AD12 AC12
DQ1B7
DQ0B23
DQ1B6 DQ1B5 DQ1B4 DQ1B3
DQ0B22 DQ0B21 DQ0B20 DQ0B19 DQS0B
DQ1B2 DQ1B1 DQ1B0
DQ0B18 DQ0B17 DQ0B16
AD11 AB12 AA11 AD10 AC11 AC10
AG12 AD11 AA13 AF11 AB12 AE10 AD10
DQ1B7 DQ1B6 DQ1B5 DQ1B4 DQ1B3 DQS1B
DQ0B15 DQ0B14 DQ0B13 DQ0B12 DQ0B11 DQS0B
DQ0B15 DQ0B14 DQ0B13 DQ0B12 DQ0B11
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 Name/Function VREF3B7 GNDG_PLL9 VCCG_PLL9 GNDA_PLL9 VCCA_PLL9 FPLL9CLKp FPLL9CLKn VREF0B6 Optional Function(s) DQ1B2 DQ1B1 DQ1B0 Configuration Function B956 F1020 AC11 AF10 F1508 AK12 AL11 AK11 AJ12 AL10 AJ10 AG10 AH10 AH11 DIFFIO
Speed
DQ0B10 DQ0B9 DQ0B8 DQ0B10 DQ0B9 DQ0B8
DQ0B7 DQ0B6 DQ0B5
AB11
DQ0B4 DQ0B3 DQS0B DQ0B2 DQ0B1 DQ0B0
AG11 AB11 AA12 AG10
DQ0B7 DQ0B6 DQ0B5
DQ0B7 DQ0B6 DQ0B5
DQ0B4 DQ0B3
DQ0B4 DQ0B3
DQ0B2 DQ0B1 DQ0B0
DQ0B2 DQ0B1 DQ0B0
VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6
DIFFIO_TX115n DIFFIO_TX115p DIFFIO_RX115n DIFFIO_RX115p DIFFIO_TX114n DIFFIO_TX114p DIFFIO_RX114n DIFFIO_RX114p DIFFIO_TX113n DIFFIO_TX113p DIFFIO_RX113n DIFFIO_RX113p DIFFIO_TX112n DIFFIO_TX112p DIFFIO_RX112n DIFFIO_RX112p DIFFIO_TX111n DIFFIO_TX111p DIFFIO_RX111n DIFFIO_RX111p DIFFIO_TX110n DIFFIO_TX110p
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
AA10
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF0B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF1B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 Name/Function VREF1B6 VREF2B6 Optional Function(s) DIFFIO_RX110n DIFFIO_RX110p DIFFIO_TX109n DIFFIO_TX109p DIFFIO_RX109n DIFFIO_RX109p DIFFIO_TX108n DIFFIO_TX108p DIFFIO_RX108n DIFFIO_RX108p DIFFIO_TX107n DIFFIO_TX107p DIFFIO_RX107n DIFFIO_RX107p DIFFIO_TX106n DIFFIO_TX106p DIFFIO_RX106n DIFFIO_RX106p DIFFIO_TX105n DIFFIO_TX105p DIFFIO_RX105n DIFFIO_RX105p DIFFIO_TX104n DIFFIO_TX104p DIFFIO_RX104n DIFFIO_RX104p DIFFIO_TX103n DIFFIO_TX103p DIFFIO_RX103n DIFFIO_RX103p DIFFIO_TX102n DIFFIO_TX102p DIFFIO_RX102n DIFFIO_RX102p DIFFIO_TX101n DIFFIO_TX101p DIFFIO_RX101n DIFFIO_RX101p DIFFIO_TX100n DIFFIO_TX100p DIFFIO_RX100n DIFFIO_RX100p DIFFIO_TX99n DIFFIO_TX99p DIFFIO_RX99n DIFFIO_RX99p DIFFIO_TX98n DIFFIO_TX98p DIFFIO_RX98n DIFFIO_RX98p DIFFIO_TX97n DIFFIO_TX97p DIFFIO_RX97n DIFFIO_RX97p DIFFIO_TX96n DIFFIO_TX96p DIFFIO_RX96n DIFFIO_RX96p DIFFIO_TX95n DIFFIO_TX95p DIFFIO_RX95n/RDN6 DIFFIO_RX95p/RUP6 DIFFIO_TX94n DIFFIO_TX94p DIFFIO_RX94n Configuration Function B956 F1020 F1508 AG11 AD10 AF11 AD12 AD11 AC11 AC12 DIFFIO
Speed
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
AA10 AC10 AB10 AA11
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF2B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 VREF3B6 Name/Function VREF3B6 CLK8p CLK9n CLK9p GNDG_PLL3 VCCG_PLL3 GNDA_PLL3 VCCA_PLL3 GNDG_PLL4 VCCG_PLL4 GNDA_PLL4 VCCA_PLL4 CLK10p CLK11p CLK11n Optional Function(s) DIFFIO_RX94p DIFFIO_TX93n DIFFIO_TX93p DIFFIO_RX93n DIFFIO_RX93p DIFFIO_TX92n DIFFIO_TX92p DIFFIO_RX92n DIFFIO_RX92p DIFFIO_TX91n DIFFIO_TX91p DIFFIO_RX91n DIFFIO_RX91p DIFFIO_TX90n DIFFIO_TX90p DIFFIO_RX90n DIFFIO_RX90p DIFFIO_TX89n DIFFIO_TX89p DIFFIO_RX89n DIFFIO_RX89p DIFFIO_TX88n DIFFIO_TX88p DIFFIO_RX88n DIFFIO_RX88p DIFFIO_TX87n DIFFIO_TX87p DIFFIO_RX87n DIFFIO_RX87p DIFFIO_TX86n DIFFIO_TX86p DIFFIO_RX86n DIFFIO_RX86p CLK8n Configuration Function B956 F1020 F1508 AC10 AB10 AB11 AB13 AB12 AE11 AA12 AA13 AA11 AA10 DIFFIO
Speed
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5
CLK10n
DIFFIO_TX85n DIFFIO_TX85p DIFFIO_RX85n DIFFIO_RX85p DIFFIO_TX84n DIFFIO_TX84p DIFFIO_RX84n DIFFIO_RX84p DIFFIO_TX83n DIFFIO_TX83p DIFFIO_RX83n DIFFIO_RX83p DIFFIO_TX82n DIFFIO_TX82p DIFFIO_RX82n
HIGH HIGH HIGH HIGH HIGH HIGH HIGH
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF0B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF1B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 Name/Function VREF0B5 VREF1B5 Optional Function(s) DIFFIO_RX82p DIFFIO_TX81n DIFFIO_TX81p DIFFIO_RX81n DIFFIO_RX81p DIFFIO_TX80n DIFFIO_TX80p DIFFIO_RX80n DIFFIO_RX80p DIFFIO_TX79n DIFFIO_TX79p DIFFIO_RX79n DIFFIO_RX79p DIFFIO_TX78n DIFFIO_TX78p DIFFIO_RX78n DIFFIO_RX78p DIFFIO_TX77n DIFFIO_TX77p DIFFIO_RX77n DIFFIO_RX77p DIFFIO_TX76n DIFFIO_TX76p DIFFIO_RX76n/RDN5 DIFFIO_RX76p/RUP5 DIFFIO_TX75n DIFFIO_TX75p DIFFIO_RX75n DIFFIO_RX75p DIFFIO_TX74n DIFFIO_TX74p DIFFIO_RX74n DIFFIO_RX74p DIFFIO_TX73n DIFFIO_TX73p DIFFIO_RX73n DIFFIO_RX73p DIFFIO_TX72n DIFFIO_TX72p DIFFIO_RX72n DIFFIO_RX72p DIFFIO_TX71n DIFFIO_TX71p DIFFIO_RX71n DIFFIO_RX71p DIFFIO_TX70n DIFFIO_TX70p DIFFIO_RX70n DIFFIO_RX70p DIFFIO_TX69n DIFFIO_TX69p DIFFIO_RX69n DIFFIO_RX69p DIFFIO_TX68n DIFFIO_TX68p DIFFIO_RX68n DIFFIO_RX68p DIFFIO_TX67n DIFFIO_TX67p DIFFIO_RX67n DIFFIO_RX67p DIFFIO_TX66n DIFFIO_TX66p DIFFIO_RX66n DIFFIO_RX66p Configuration Function B956 F1020 F1508 DIFFIO
Speed
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 VREF2B5 Name/Function VREF2B5 FPLL10CLKn FPLL10CLKp GNDG_PLL10 VCCG_PLL10 GNDA_PLL10 VCCA_PLL10 VREF0B4 Optional Function(s) DIFFIO_TX65n DIFFIO_TX65p DIFFIO_RX65n DIFFIO_RX65p DIFFIO_TX64n DIFFIO_TX64p DIFFIO_RX64n DIFFIO_RX64p DIFFIO_TX63n DIFFIO_TX63p DIFFIO_RX63n DIFFIO_RX63p DIFFIO_TX62n DIFFIO_TX62p DIFFIO_RX62n DIFFIO_RX62p DIFFIO_TX61n DIFFIO_TX61p DIFFIO_RX61n DIFFIO_RX61p DIFFIO_TX60n DIFFIO_TX60p DIFFIO_RX60n DIFFIO_RX60p DIFFIO_TX59n DIFFIO_TX59p DIFFIO_RX59n DIFFIO_RX59p DIFFIO_TX58n DIFFIO_TX58p DIFFIO_RX58n DIFFIO_RX58p Configuration Function B956 F1020 F1508 DIFFIO
Speed
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4
DQ0T0 DQ0T1 DQ0T2 DQS0T DQ0T3 DQ0T4
DQ0T0 DQ0T1 DQ0T2
DQ0T0 DQ0T1 DQ0T2
DQ0T3 DQ0T4
DQ0T3 DQ0T4
DQ0T5 DQ0T6 DQ0T7
DQ0T5 DQ0T6 DQ0T7
DQ0T5 DQ0T6 DQ0T7
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 Name/Function VREF1B4 VREF2B4 Optional Function(s) Configuration Function B956 F1020 F1508 DIFFIO
Speed
DQ1T0 DQ1T1 DQ1T2 DQS1T DQ1T3 DQ1T4 DQ1T5 DQ1T6 DQ1T7
DQ0T8 DQ0T9 DQ0T10 DQS0T DQ0T11 DQ0T12 DQ0T13 DQ0T14 DQ0T15
DQ0T8 DQ0T9 DQ0T10
DQ0T11 DQ0T12 DQ0T13 DQ0T14 DQ0T15
DQ2T0 DQ2T1 DQ2T2 DQS2T DQ2T3 DQ2T4 DQ2T5 DQ2T6 FCLK6 FCLK7 DQ2T7
DQ1T0 DQ1T1 DQ1T2
DQ0T16 DQ0T17 DQ0T18 DQS0T
DQ1T3 DQ1T4 DQ1T5 DQ1T6
DQ0T19 DQ0T20 DQ0T21 DQ0T22
DQ1T7
DQ0T23
DQ3T0 DQ3T1 DQ3T2 DQS3T DQ3T3 DQ3T4
DQ1T8 DQ1T9 DQ1T10 DQS1T DQ1T11 DQ1T12
DQ0T24 DQ0T25 DQ0T26
DQ0T27 DQ0T28
DQ3T5 DQ3T6 DEV_OE
DQ1T13 DQ1T14
DQ0T29 DQ0T30
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 Name/Function VREF3B4 TRST CLK12p CLK13p VCCA_PLL11 GNDA_PLL11 VCCG_PLL11 GNDG_PLL11 TEMPDIODEp TEMPDIODEn VCCA_PLL5 GNDA_PLL5 VCCG_PLL5 GNDG_PLL5 VCC_PLL5_OUTA VCC_PLL5_OUTB Optional Function(s) DQ3T7 RUP4 Configuration Function B956 F1020 F1508 DIFFIO
Speed
DQ1T15 DQ0T31
RDN4 DQ4T0 DQ4T1 DQ4T2 DQS4T DATA0 DQ4T3 DQ4T4 DQ4T5 DATA1 DQ4T6 DQ4T7
DATA2
TRST DATA3
CLK12n CLK13n/PLL11_OUT
VREF0B3 VREF0B3 VREF0B3
PLL5_OUT0p PLL5_OUT0n PLL5_OUT1p
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF2B3 VREF2B3 Name/Function nSTATUS nCONFIG DCLK CONF_DONE CLK14p CLK15p VREF0B3 VREF1B3 Optional Function(s) PLL5_OUT1n PLL5_FBp PLL5_FBn PLL5_OUT2p PLL5_OUT2n PLL5_OUT3p PLL5_OUT3n nSTATUS nCONFIG DCLK CONF_DONE CLK14n CLK15n Configuration Function B956 F1020 F1508 DIFFIO
Speed
DATA4 DQ5T0 DQ5T1 DATA5 DQ5T2 DQS5T DQ5T3 DATA6 DQ5T4 DQ5T5 DQ5T6 DQ5T7 RUP3
RDN3 DQ6T0 DQ6T1 DATA7 DQ6T2 DQS6T DQ6T3 CLKUSR DQ6T4 DQ6T5 DQ6T6 DQ6T7 FCLK0 FCLK1
DQ2T0 DQ2T1 DQ2T2 DQS2T DQ2T3 DQ2T4 DQ2T5 DQ2T6 DQ2T7
DQ1T0 DQ1T1 DQ1T2
DQ1T3 DQ1T4 DQ1T5 DQ1T6 DQ1T7
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 Name/Function VREF2B3 VREF3B3 Optional Function(s) Configuration Function B956 F1020 F1508 DIFFIO
Speed
DQ7T0 DQ7T1 DQ7T2 DQS7T DQ7T3 DQ7T4 DQ7T5
DQ2T8 DQ2T9 DQ2T10
DQ1T8 DQ1T9 DQ1T10 DQS1T
DQ2T11 DQ2T12 DQ2T13
DQ1T11 DQ1T12 DQ1T13
DQ7T6 DQ7T7
DQ2T14 DQ2T15
DQ1T14 DQ1T15
DQ8T0 DQ8T1 DQ8T2 DQS8T DQ8T3
DQ3T0 DQ3T1 DQ3T2 DQS3T DQ3T3
DQ1T16 DQ1T17 DQ1T18
DQ1T19
DQ8T4 DQ8T5 DQ8T6 DQ8T7
DQ3T4 DQ3T5 DQ3T6 DQ3T7
DQ1T20 DQ1T21 DQ1T22 DQ1T23
DQ9T0 DQ9T1 DQ9T2
DQ3T8 DQ3T9 DQ3T10
DQ1T24 DQ1T25 DQ1T26
DQS9T DQ9T3 DQ9T4 DQ9T5 DQ9T6 DQ9T7
DQ3T11 DQ3T12 DQ3T13 DQ3T14 DQ3T15
DQ1T27 DQ1T28 DQ1T29 DQ1T30 DQ1T31
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Information StratixEP1S60 Device,
Bank Number VREF Bank VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 Name/Function VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Optional Function(s) Configuration Function B956 F1020 F1508 AA25 AE39 AU39 AM33 AW37 AW25 AR21 AE22 AM30 AE19 AM20 AW15 AM10 AB15 DIFFIO
Speed
AA32 AK31 AK32 AC17 AM21 AM30
AJ31
AL29 AL19
AC16 AL13
AC16 AM12
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Optional Function(s) Configuration Function B956 AA20 AA12 AA14 AD18 AA18 AL30 AK30 AK31 AL31 AL11 AL21 F1020 F1508 AA16 AA18 AA22 AA24 AB17 AB19 AB21 AB23 AB25 AC16 AC18 AC20 AC22 AC24 AD15 AD17 AD19 AD21 AD23 AD25 AE16 AE18 AE20 AE24 AK22 AL21 AV39 AV38 AW38 AW13 AW27 AG39 AK20 AN21 DIFFIO
Speed
AD17 AF17 AA16 AA17 AC32 AL31 AL32 AM10 AM23 AM31
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function Optional Function(s) Configuration Function B956 F1020 AB16 AA17 F1508 AU37 AK30 AK10 AM32 DIFFIO
Speed
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function Optional Function(s) Configuration Function B956 AA15 AA17 AA23 AB16 AB18 AB20 AB22 AB24 AC15 AC17 AC19 AC21 AC23 AC25 AD16 AD18 AD20 AD22 AD24 AE15 F1020 F1508 DIFFIO
Speed
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function Optional Function(s) Configuration Function B956 F1020 F1508 AE17 AE21 AE23 AE25 AA14 AE10 AE31 AF18 AF27 AG16 AG26 AH25 AP34 AV37 AB14 AE12 AF19 AF28 AG17 AG27 AH26 AL34 AP35 AC13 AE13 AF10 AF20 AF30 AG18 AG28 AH27 AL35 DIFFIO
Speed
AB18 AB10
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
Page
List
Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function Optional Function(s) Configuration Function B956 F1020 F1508 AC14 AE14 AF12 AF21 AF31 AG19 AH12 AH28 AD13 AE26 AF13 AF22 AG12 AG22 AH13 AJ11 AT36 AD14 AE27 AF14 AF24 AG13 AG23 AH14 AJ22 AN34 AT37 AD26 AE28 DIFFIO
Speed
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Bank Number VREF Bank Name/Function Optional Function(s) Configuration Function B956 F1020 F1508 AF15 AF25 AG14 AG24 AH15 AJ25 AN35 AD27 AE30 AF17 AF26 AG15 AG25 AH22 AU38 DIFFIO
Speed
Note Pin-List: wire bond flip-chip packages will have different data rates high speed differential channels. following table shows data rates supported each package. Package Type flip chip flip chip High Speed Differential Channel Performance (DIFFIO Speed) High
Package B956 F1020
Units Mbps Mbps
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Bank Number F1508 VREF Bank flip chip Name/Function Optional Function(s) Configuration Function Mbps B956 F1020 F1508 DIFFIO
Speed
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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List
Information StratixEP1S60 Device,
Name Type (1st, 2nd, Function) Description Supply Reference Pins Input reference voltage bank bank used voltage-referenced standard, then these pins used voltage-reference pins bank. VREF pins used, designers should connect them either Gnd. These supply voltage pins banks through Each bank support different voltage level. VCCIO supplies power output buffers standards. VCCIO also supplies power input buffers used LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, 3.3-V PCI-X standards. These internal logic array voltage supply pins. VCCINT also supplies power input buffers used LVDS, LVPECL, 3.3-V PCML, HyperTransporttechnology, differential HSTL, GTL, GTL+, HSTL, SSTL, CTT, 3.3-V standards. External clock output buffer power PLL5 clock outputs PLL5_OUT[1.0]. designer must connect this VCCIO bank External clock output buffer power PLL5 clock outputs PLL5_OUT[3.2]. designer must connect this VCCIO bank External clock output buffer power PLL6 clock outputs PLL6_OUT[1.0]. designer must connect this VCCIO bank External clock output buffer power PLL6 clock outputs PLL6_OUT[3.2]. designer must connect this VCCIO bank Analog power PLLs[1.12]. designer must connect this even used. Analog ground PLLs[1.12]. designer connect this plane board. Guard ring power PLLs[1.12]. designer must connect this even used. Guard ring ground PLLs[1.12]. designer connect this plane board. drive signals into these pins. Dedicated Configuration/JTAG Pins This dedicated configuration status pin; available user pin. This dedicated configuration status pin; available user pin. Dedicated configuration control input. transition resets target device; low-to-high transition begins configuration. pins tri-state when nCONFIG driven low. Clock input used clock configuration data from external source into Stratix device. This dedicated used configuration. nIO_PULLUP driven high during configuration, weak pull-ups user pins disabled. driven low, weak pull-ups enabled during configuration. nIO_PULLUP pulled either 1.5, 1.8, 2.5, Dedicated input used select delay times during powerup. When PORSEL connected ground, time When PORSEL connected time VCCSEL used select which input buffer used configuration pins. VCCSEL will control whether 3.3-/2.5-V input buffer 1.8-/1.5-V input buffer used. means 3.3/2.5 means 1.8/1.5 powerup, VCCSEL accepts 3.3V 2.5V Levels. VCCSEL affects following pins: TDI, TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, CONF_DONE, nSTATUS, PLL_ENA. Active-low chip enables. Dedicated chip enable input used detect which device active chain devices. When low, device enabled. When high, device disabled. Output that drives when device configuration complete. During multi-device configuration, this feeds subsequent device's pin. This dedicated JTAG input pin. This dedicated JTAG input pin. This dedicated JTAG input pin. This dedicated JTAG input pin. This dedicated JTAG input pin. Active input, used asynchronously reset JTAG boundary scan circuit. Dedicated mode select control pins that configuration mode device. used conjunction with temperature sensing diode (bias-high input) inside Stratix device. temperature sensing diode used then connect this GND. used conjunction with temperature sensing diode (bias-low input) inside Stratix device. temperature sensing diode used then connect this GND. Clock Pins
VREF[1.4]B[1.8]
Input
VCCIO[1.8]
Power
VCCINT VCC_PLL5_OUTA VCC_PLL5_OUTB VCC_PLL6_OUTA VCC_PLL6_OUTB VCCA_PLL[1.12] GNDA_PLL[1.12] VCCG_PLL[1.12] GNDG_PLL[1.12]
Power Power Power Power Power Power Ground Power Ground Connect Bidirectional (opendrain) Bidirectional (opendrain) Input Input
CONF_DONE nSTATUS nCONFIG DCLK
nIO_PULLUP
Input
PORSEL
Input
VCCSEL
Input
nCEO TRST MSEL[2.0] TEMPDIODEp TEMPDIODEn
Input Output Input Input Input Output Input Input Input Input
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
Page
Definitions
Information StratixEP1S60 Device,
Name Type (1st, 2nd, Function) Description Dedicated input that drives optional pllena port PLLs. uses pllena port, drive PLL_ENA reset PLLs including counters their default state. VCCSEL then must drive PLL_ENA with 3.3/2.5 signal enable PLLs. VCCSEL connect PLL_ENA 1.8/1.5 enable PLLs. Dedicated fast regional clock pins. FCLK pins also used type input, output, bidirectional pins. Dedicated global clock inputs fast PLLs (PLLs through 10). Dedicated negative terminal associated with FPLL[10.7]CLKp pins. Dedicated global clock inputs Optional negative terminal input differential global clock input. Optional external clock outputs [3.0] from enhanced These pins differential (four output pairs) single ended (eight clock outputs from PLL6). Optional negative terminal external clock outputs [3.0] from PLL6. clock outputs single ended, then each pair pins (i.e., PLL6_OUT0p PLL6_OUT0n considered pair) either phase degrees phase. Optional external clock outputs [3.0] from enhanced These pins differential (four output pairs) single ended (eight clock outputs from PLL5). Optional negative terminal external clock outputs [3.0] from clock outputs single ended, then each pair pins (i.e., PLL5_OUT0p PLL5_OUT0n considered pair) either phase degrees phase. Optional/Dual-Purpose Pins Dual-purpose configuration data input pin. used after configuration complete. Dual-purpose differential transmitter channels. These channels used transmitting LVDS HyperTransport compatible signals. Pins with suffix carry positive signal differential channel. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins. Dual-purpose differential receiver channels. These channels used receiving LVDS HyperTransport compatible signals. Pins with suffix carry positive signal differential channel. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins. This used pin, CLK6n, PLL12_OUT pin. Only EP1S40 larger devices have this pin. This used pin, CLK13n, used PLL11_OUT pin. Only EP1S40 larger devices have this pin. External feedback input PLL5. This used user external feedback mode used. Negative terminal input external feedback input PLL5_FBp External feedback input PLL6 Negative terminal input external feedback input PLL6_FBp This dual-purpose used when enabled INIT_DONE. When enabled, indicates when device entered user mode. INIT_DONE output enabled, INIT_DONE cannot used user after configuration. Dual-purpose configuration input data pins. These pins used configuration regular pins. These pins also used user pins after configuration. Read strobe input pin. This used user after configuration. Optional that allows override clears device registers. When this driven low, registers cleared; when this driven high, registers behave defined users design. Optional that allows override tri-states device. When this driven low, pins tri-stated; when this driven high, pins behave defined design. Optional user-supplied clock input. Synchronizes initialization more devices. This used user after configuration. Ready busy output. high output indicates that target device ready accept another data byte. output indicates that target device ready receive another data byte. This used user after configuration. These chip-select inputs that enable Stratix device passive parallel asynchronous configuration mode. Drive high target device configuration. design requires active high enable, drive low. design requires active enable, drive high. Configuration will paused when either signal inactive. Hold pins active during configuration initialization. design these pins user pins after configuration. Active-low write strobe input latch byte data DATA pins. This used user after configuration.
PLL_ENA FCLK[7.0] FPLL[10.7]CLKp FPLL[10.7]CLKn CLK[15.0]p CLK[15.0]n PLL6_OUT[3.0]p
Input Bidirectional Input Input Input I/O, Input I/O, Output
PLL6_OUT[3.0]n PLL5_OUT[3.0]p
I/O, Output I/O, Output
PLL5_OUT[3.0]n
I/O, Output
DATA0
I/O, Input
DIFFIO_TX[0.115]p/n
I/O, channel
DIFFIO_RX[0.115]p/n CLK6n, PLL12_OUT CLK13n, PLL11_OUT PLL5_FBp PLL5_FBn PLL6_FBp PLL6_FBn
I/O, channel I/O, Input (CLK6n), Output (PLL12_OUT) I/O, Input (CLK13n), Output (PLL11_OUT) I/O, Input I/O, Input I/O, Input I/O, Input
INIT_DONE DATA[7.1]
I/O, Output I/O, Input I/O, Input
DEV_CLRn DEV_OE CLKUSR
I/O, Input I/O, Input I/O, Input
RDYnBSY
I/O, Output
nCS,CS
I/O, Input I/O, Input
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Definitions
Information StratixEP1S60 Device,
Name Type (1st, 2nd, Function) Description These output pins control eight pages EPC16 configuration device when using remote update local update configuration modes. When using remote update local update configuration modes, these pins user pins. Reference pins banks external precision resistors must connected designated that bank. required, these pins regular pins. Reference pins banks external precision resistors must connected designated that bank. required, these pins regular pins. Input control select remote update local update modes. MSEL2 this input control select remote update (RUnLU local update (RUnLU modes. MSEL2=0, RUnLU user pin. Active high signal that indicates that error detection circuit detected errors configuration SRAM bits. This optional used when error detection circuit enabled.
PGM[2.0] RUP[8.1] RDN[8.1]
I/O, Output I/O, Input I/O, Input
RUnLU
I/O, Input
CRC_ERROR
I/O, Output
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
Page
Definitions
Information StratixEP1S60 Device,
PLL7
VREF3B2 VREF2B2 VREF1B2 VREF0B2
DQST9 VREF4B3
DQST8 VREF3B3
DQST7 VREF2B3
DQST6 VREF1B3
DQST5 VREF0B3
PLL5
PLL11
DQST4 VREF4B4
DQST3 VREF3B4
DQST2 VREF2B4
DQST1 VREF1B4
DQST0 VREF0B4
PLL10
VREF0B5 VREF1B5 VREF2B5 VREF3B5 VREF0B6 VREF1B6 VREF2B6 VREF3B6
PLL1 PLL2
VREF3B1 VREF2B1 VREF1B1 VREF0B1
PLL8
VREF0B8 DQSB9 VREF1B8 DQSB8 VREF2B8 DQSB7 VREF3B8 DQSB6 VREF4B8 DQSB5
PLL6 PLL12
VREF0B7 DQSB4 VREF1B7 DQSB3
VREF2B7 DQSB2 VREF3B7 DQSB1 VREF4B7 DQSB0
Notes: 1.This view silicon die. flip chip packages mounted up-side down package. 2.This pictoral representation only idea placement device. Refer pin-list Quartus exact locations.
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Bank Diagram
PLL4 PLL3
PLL9
Information StratixEP1S60 Device,
STRATIX EP1S60 B956 Device Package Diagram
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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B956 Package Diagram
Information StratixEP1S60 Device,
STRATIX EP1S60 F1020 Device Package Diagram
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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F1020 Package Diagram
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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F1020 Package Diagram
Information StratixEP1S60 Device,
STRATIX EP1S60 F1508 Device Package Diagram
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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F1508 Package Diagram
Information StratixEP1S60 Device,
Clock Resources High Speed Differential (DIFFIO) Receiver Transmitter channels. Notes (5), Device Count Source Channels channels Overlapped Overlapped Note Note FAST Channels Channels Note Note High High High High EP1S60 PLL1 [30-49] [38-49] [38-49] [38-49] PLL2 [10-29] [10-19] [10-19] [10-19] PLL3 [86-105] [96-105] [96-105] [96-105] PLL4 [66-85] [66-77] [66-77] [66-77] PLL7 [38-49] [38-57] [38-49] [38-49] PLL8 [10-19] [0-19] [10-19] [10-19] PLL9 [96-105] [96-115] [96-105] [96-105] PLL10 [66-77] [58-77] [66-77] [66-77] 1020 PLL1 [30-49] [38-49] [36-37] [38-49] [38-49] PLL2 [10-29] [10-19] [20-23] [10-19] [10-19] PLL3 [86-105] [96-105] [92-95] [96-105] [96-105] PLL4 [66-85] [66-77] [78-79] [66-77] [66-77] PLL7 [38-49] [50-51] [38-57] [38-49] [38-49] PLL8 [10-19] [7-9] [0-19] [10-19] [10-19] PLL9 [96-105] [106-108] [96-115] [96-105] [96-105] PLL10 [66-77] [64-65] [58-77] [66-77] [66-77] 1508 PLL1 [30-49] [38-49] [30-37] [38-49] [38-49] PLL2 [10-29] [10-19] [20-29] [10-19] [10-19] PLL3 [86-105] [96-105] [86-95] [96-105] [96-105] PLL4 [66-85] [66-77] [78-85] [66-77] [66-77] PLL7 [38-49] [50-57] [38-57] [38-49] [38-49] [10-19] PLL8 [10-19] [0-9] [0-19] [10-19] PLL9 [96-105] [106-115] [96-115] [96-105] [96-105] PLL10 [66-77] [58-65] [58-77] [66-77] [66-77] Notes: These channels clocked listed "FAST Source location" column. These channels clocked listed "FAST Source location" column. These channels driven listed "FAST Source location" alternatively driven other adjacent FAST PLL. Bank Diagram locations. These channels driven listed "FAST Source location" alternatively driven other adjacent FAST PLL. Bank Diagram locations. Each range channel numbers shown brackets. Data channels designated "high" speed support maximum data rate Mbps speed grade devices Mbps speed grade devices. Data channels designated "low" speed support maximum data rate Mbps speed grades. high speed differential (DIFFIO) channels span across banks both sides device. Each Fast normally only feed channels bank. However, center PLLs also clock channels associated with adjacent center same side device through that shown figures 5-16 5-17 volume Stratix Device Handbook. These channels called "cross-bank" channels. When cross-bank channels used only center each side used.
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
Page
Fast HSIO Connections
Information StratixEP1S60 Device,
Version Number
Date 2/4/2005 11/14/2005 3/2/2006
Changes Made Revised package diagrams. Update package diagram EP1S60. Added CRC_ERROR List Definition
PT-EP1S60-3.6 Copyright 2006 Altera Corp.
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Revision History
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