EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name
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Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0
VCCD_PLL7 VCCA_PLL7 GNDA_PLL7 GNDA_PLL7 FPLL7CLKp FPLL7CLKn VREFB2N0
INPUT INPUT DIFFIO_TX41p DIFFIO_TX41n DIFFIO_RX40p DIFFIO_RX40n DIFFIO_TX40p DIFFIO_TX40n DIFFIO_RX39p DIFFIO_RX39n DIFFIO_TX39p DIFFIO_TX39n VREFB2N0 DIFFIO_RX38p DIFFIO_RX38n DIFFIO_TX38p DIFFIO_TX38n DIFFIO_RX37p DIFFIO_RX37n DIFFIO_TX37p DIFFIO_TX37n DIFFIO_RX36p DIFFIO_RX36n DIFFIO_TX36p DIFFIO_TX36n DIFFIO_RX35p DIFFIO_RX35n DIFFIO_TX35p
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
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Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N2 VREFB2N2
VREFB2N1
DIFFIO_TX35n DIFFIO_RX34p DIFFIO_RX34n DIFFIO_TX34p DIFFIO_TX34n DIFFIO_RX33p DIFFIO_RX33n DIFFIO_TX33p DIFFIO_TX33n DIFFIO_RX32p DIFFIO_RX32n DIFFIO_TX32p DIFFIO_TX32n VREFB2N1 DIFFIO_RX31p DIFFIO_RX31n DIFFIO_TX31p DIFFIO_TX31n DIFFIO_RX30p DIFFIO_RX30n DIFFIO_TX30p DIFFIO_TX30n DIFFIO_RX29p DIFFIO_RX29n DIFFIO_TX29p DIFFIO_TX29n DIFFIO_RX28p DIFFIO_RX28n DIFFIO_TX28p DIFFIO_TX28n DIFFIO_RX27p DIFFIO_RX27n
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
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Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2
VREFB2N2 CLK1n CLK1p VCCD_PLL1
DIFFIO_TX27p DIFFIO_TX27n DIFFIO_RX26p DIFFIO_RX26n DIFFIO_TX26p DIFFIO_TX26n DIFFIO_RX25p DIFFIO_RX25n DIFFIO_TX25p DIFFIO_TX25n DIFFIO_RX24p DIFFIO_RX24n DIFFIO_TX24p DIFFIO_TX24n VREFB2N2 DIFFIO_RX23p DIFFIO_RX23n DIFFIO_TX23p DIFFIO_TX23n DIFFIO_RX22p DIFFIO_RX22n DIFFIO_TX22p DIFFIO_TX22n DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n CLK0n/DIFFIO_RX_C0n CLK0p/DIFFIO_RX_C0p INPUT INPUT
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
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Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0
VCCA_PLL1 GNDA_PLL1 GNDA_PLL1 GNDA_PLL2 GNDA_PLL2 VCCA_PLL2 VCCD_PLL2 CLK3p CLK3n VREFB1N0
CLK2p/DIFFIO_RX_C1p CLK2n/DIFFIO_RX_C1n INPUT INPUT DIFFIO_RX20p DIFFIO_RX20n DIFFIO_TX20p DIFFIO_TX20n DIFFIO_RX19p DIFFIO_RX19n DIFFIO_TX19p DIFFIO_TX19n VREFB1N0 DIFFIO_RX18p DIFFIO_RX18n DIFFIO_TX18p DIFFIO_TX18n DIFFIO_RX17p DIFFIO_RX17n DIFFIO_TX17p DIFFIO_TX17n DIFFIO_RX16p DIFFIO_RX16n DIFFIO_TX16p DIFFIO_TX16n
AE31 AA32 AA31 AA29 AA28
AA28 AD23 AA26 AA25
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1
VREFB1N1
DIFFIO_RX15p DIFFIO_RX15n DIFFIO_TX15p DIFFIO_TX15n DIFFIO_RX14p DIFFIO_RX14n DIFFIO_TX14p DIFFIO_TX14n DIFFIO_RX13p DIFFIO_RX13n DIFFIO_TX13p DIFFIO_TX13n DIFFIO_RX12p DIFFIO_RX12n DIFFIO_TX12p DIFFIO_TX12n VREFB1N1 DIFFIO_RX11p DIFFIO_RX11n DIFFIO_TX11p DIFFIO_TX11n DIFFIO_RX10p DIFFIO_RX10n DIFFIO_TX10p DIFFIO_TX10n DIFFIO_RX9p DIFFIO_RX9n DIFFIO_TX9p DIFFIO_TX9n DIFFIO_RX8p DIFFIO_RX8n DIFFIO_TX8p
AB31 AB30 AA23 AB23 AB33 AB32 AA26 AA25 AA34 AB34 AB29 AB28 AC32 AC31 AB24 AC24 AC30 AC34 AC33 AB26 AB25 AD32 AD31 AC27 AB27 AE33 AE32 AD26 AD25 AD34 AE34 AC29
AB28 AB27 AC28 AD28 AD26 AD25 AC25 AC24 AB22 AB21 AC27 AC26 AE26 AE25 AB26 AB25 AB24 AB23 AE28 AE27 AC23 AC22 AF28 AF27 AA23
AA22 AB22 AB21 AB20 AB19 AB18 AB17 AA17 AA20 AA19 AA16 AB16
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB1N1 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2
VREFB1N2 FPLL8CLKn FPLL8CLKp
DIFFIO_TX8n DIFFIO_RX7p DIFFIO_RX7n DIFFIO_TX7p DIFFIO_TX7n DIFFIO_RX6p DIFFIO_RX6n DIFFIO_TX6p DIFFIO_TX6n DIFFIO_RX5p DIFFIO_RX5n DIFFIO_TX5p DIFFIO_TX5n DIFFIO_RX4p DIFFIO_RX4n DIFFIO_TX4p DIFFIO_TX4n VREFB1N2 DIFFIO_RX3p DIFFIO_RX3n DIFFIO_TX3p DIFFIO_TX3n DIFFIO_RX2p DIFFIO_RX2n DIFFIO_TX2p DIFFIO_TX2n DIFFIO_RX1p DIFFIO_RX1n DIFFIO_TX1p DIFFIO_TX1n INPUT INPUT
AC28 AF32 AF31 AD29 AD28 AF34 AF33 AE30 AE29 AG32 AG31 AE28 AE27 AG34 AH34 AF30 AF29 AH33 AH32 AF28 AF27 AJ34 AJ33 AG29 AG28 AJ32 AJ31 AH31 AH30 AM33 AM34
AA22
AB15
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
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Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB1N2 VREFB1N2
VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0
GNDA_PLL8 GNDA_PLL8 VCCA_PLL8 VCCD_PLL8 TRST nCONFIG VCCSEL VREFB8N0
DIFFIO_TX0p DIFFIO_TX0n
TRST nCONFIG VCCSEL CLKUSR
DQ17B VREFB8N0 DQ17B DQ17B DQ17B DQS17B
DQ16B DQ16B DQ16B
AH29 AH28 AF25 AE26 AF26 AE25 AL31 AM32 AE24 AM31 AL30 AF24 AL29 AH27 AH26 AG26 AG25 AH24 AH25 AM30 AN31 AK28 AN32 AP32 AP30 AP31 AE23 AF23 AP29 AN29 AM29 AP28
AE24 AC21 AE22 AE21
AA14 AB13 AB14 AB12 AA11 AA13 AB11
AF26 AF25 AD22 AG26 AH25 AH26 AG25 AD20 AE20
DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B
DQ3B DQ3B DQ3B DQ3B DQ3B
DQ3B DQ3B DQ3B DQ3B
DQ1B DQ1B DQ1B DQ1B
DQ1B
DQ1B DQ1B
DQ3B DQ3B DQ3B DQ3B
DQ1B DQ1B DQ1B DQ1B
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1
VREFB8N1
DQ16B DQS16B DQ15B DQ15B DQ15B DQ15B DQS15B
DQ14B DQ14B DQ14B DQ14B DQS14B DQ13B VREFB8N1 DQ13B DQ13B DQ13B DQS13B DQ12B DQ12B DQ12B DQ12B DQS12B
AM28 AN28 AC23 AJ27 AL28 AJ28 AM27 AP27 AL27 AF22 AG22 AN26 AL26 AJ26 AK26 AP26 AM26 AC22 AJ24 AL25 AK25 AJ25 AN25 AP25 AM25 AB21 AM24 AL24 AJ23 AK23 AP24 AL23
AC20
DQ8B DQS8B DQ7B DQ7B DQ7B DQ7B DQ7B DQ3B DQ3B DQ3B DQ3B DQS3B
DQ3B
DQ1B
AH24 AF23 AF24 AF22 AH23 AG23
DQ3B DQ3B DQ3B DQ3B DQS3B
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ1B DQ1B DQ1B DQ1B DQ1B
AE19 AB19 AC19
DQ7B DQ7B DQ7B DQ7B DQS7B DQ6B DQ6B DQ6B DQ2B DQ2B DQ2B DQ6B DQ6B DQ2B DQ2B
DQ3B DQ3B DQ3B DQ3B DQ3B
DQ1B DQ1B DQ1B DQ1B DQ1B
AG22 AF20 AD19 AH22 AH21 AF21 AG20 AE18 AC18
DQ1B DQ2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQS1B DQ1B DQ1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B DQ1B
DQ6B DQ6B DQ6B DQ6B DQS6B
DQ2B DQ2B DQ2B DQ2B DQ2B
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2
VREFB8N2
DQ11B DQ11B DQ11B DQ11B DQS11B
DQ10B DQ10B DQ10B DQ10B DQS10B VREFB8N2
RUnLU DEV_OE DEV_CLRn PLL12_FBn/OUT2n PLL12_FBp/OUT2p PLL12_OUT1n PLL12_OUT1p PLL12_OUT0n PLL12_OUT0p CLK5n CLK5p
AC21 AM23 AN23 AP23 AM22 AP22 AN22 AB20 AC20 AJ22 AL22 AM21 AP21 AJ21 AL21 AK22 AB18 AH21 AH23 AH18 AG20 AH20 AJ18 AJ20 AK20 AC18 AL20 AM20 AN20 AP20 AH19 AJ19
AH20 AG19 AF19 AF18 AH18 AH19
DQ5B DQ5B DQ5B DQ5B DQ5B
DQ2B DQ2B DQ2B DQ2B DQS2B
DQ2B DQ2B DQ2B DQ2B DQS2B
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ1B DQ1B DQ1B DQ1B DQ1B
AC17 AB17 AD17
DQ5B DQ5B DQ5B DQ5B DQS5B
DQ2B DQ2B DQ2B DQ2B DQ2B
DQ1B DQ1B DQ1B DQ1B DQ1B
AC16 AD16 AE17 AF17 AE16
AB10
AF16 AB15 AC15
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
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Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB8N2 VREFB8N2
VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0
VCC_PLL12_OUT VCCD_PLL12 VCCA_PLL12 GNDA_PLL12 GNDA_PLL12 GNDA_PLL6 GNDA_PLL6 VCCA_PLL6 VCCD_PLL6 VCC_PLL6_OUT VREFB7N0
CLK4n CLK4p
CLK7p CLK7n CLK6p CLK6n PLL6_OUT1p PLL6_OUT1n PLL6_OUT0p PLL6_OUT0n PLL6_FBp/OUT2p PLL6_FBn/OUT2n
DQ9B VREFB7N0 DQ9B DQ9B DQ9B
AM19 AN19 AE20 AF20 AE18 AF19 AF18 AE17 AF17 AE16 AF16 AG16 AL19 AK19 AP18 AP19 AM18 AL18 AP17 AN17 AM17 AL17 AJ17 AH17 AC16 AH14 AJ16 AL16 AK17 AK16 AN16 AP16
AG17 AH17
AA10
AA14 AF15 AE15 AH16 AG16 AG14 AF14 AH15 AH14 AE14 AD14
AG13 AE13 AB14 AC14 AC13 AD13
DQ4B DQ4B DQ4B DQ4B DQ4B
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ1B DQ1B DQ1B DQ1B
DQ0B DQ0B DQ0B DQ0B
DQ0B
DQ0B DQ0B
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1
VREFB7N1
DQS9B
DQ8B DQ8B DQ8B DQ8B DQS8B DQ7B DQ7B DQ7B DQ7B DQS7B
DQ6B DQ6B DQ6B DQ6B DQS6B
DQ5B VREFB7N1 DQ5B DQ5B DQ5B
AM16 AG14 AF14 AH16 AM15 AH15 AJ15 AP15 AL15 AC15 AP14 AM14 AK14 AJ14 AN14 AL14 AE14 AC14 AP13 AM13 AH13 AJ13 AN13 AL13 AD14 AF13 AP12 AM12 AK13 AH11 AH12 AJ12
AF13
AB13 AH13 AF12 AH12 AG11 AH11 AE12
DQ4B DQ4B DQ4B DQ4B DQS4B DQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQS1B
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ1B DQ1B DQ1B DQ1B DQS1B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQ0B
AB12 AC12
DQ3B DQ3B DQ3B DQ3B DQS3B
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ0B DQ0B DQ0B DQ0B DQ0B
AD11 AF11 AC10 AF10 AG10 AH10
DQ2B DQ2B DQ2B DQ2B DQ2B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2
VREFB7N2
DQS5B DQ4B DQ4B DQ4B DQ4B DQS4B
DQ3B DQ3B DQ3B DQ3B DQS3B
DQ2B DQ2B DQ2B DQ2B DQS2B DQ1B VREFB7N2 DQ1B DQ1B DQ1B DQS1B
AL12 AG11 AP11 AM11 AJ11 AK11 AN11 AL11 AG10 AF11 AP10 AM10 AH10 AJ10 AN10 AL10 AC13 AD13 AE11 AK10
AE11 DQ2B AB11 AC11 DQ2B DQ2B DQ2B DQS2B DQ0B DQ0B DQ0B DQ0B DQ0B
DQS0B
DQS0B DQ0B DQ0B DQ0B DQ0B DQ0B
AE10 AD10
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ0B DQ0B DQ0B DQ0B DQS0B
DQ0B DQ0B DQ0B DQ0B DQS0B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ1B AB10 DQ1B DQ1B DQ1B DQS1B DQ0B DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQ0B
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2
PORSEL nIO_PULLUP PLL_ENA nCEO GND* GND* GND* GND* GND* GND* GND* GND* GND* GND* GND* GND* GND* VCCA VCCA VCCA GND* GND* GND*
RDN7 RUP7 DQ0B DQ0B DQ0B DQ0B DQS0B
AE10 PORSEL nIO_PULLUP PLL_ENA nCEO AC11
DQ0B DQ0B DQ0B DQ0B DQS0B
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
GND* GND* GND* GND* GND* GXB_RX7n GXB_RX7p GXB_TX7n GXB_TX7p GXB_RX6n GXB_RX6p GXB_TX6n GXB_TX6p RREFB14 REFCLK0_B14n REFCLK0_B14p REFCLK1_B14n REFCLK1_B14p VCCA VCCA VCCA GXB_RX4n GXB_RX4p GXB_TX4n GXB_TX4p GXB_RX5n GXB_RX5p GXB_TX5n GXB_TX5p GXB_RX3n GXB_RX3p GXB_TX3n
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0
GXB_TX3p GXB_RX2n GXB_RX2p GXB_TX2n GXB_TX2p RREFB13 REFCLK0_B13n REFCLK0_B13p REFCLK1_B13n REFCLK1_B13p VCCA VCCA VCCA GXB_RX0n GXB_RX0p GXB_TX0n GXB_TX0p GXB_RX1n GXB_RX1p GXB_TX1n GXB_TX1p VCCA TEMPDIODEp TEMPDIODEn MSEL3 MSEL2 MSEL1 MSEL0
MSEL3 MSEL2 MSEL1 MSEL0 DQS0T
DQS0T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1
VREFB4N0
DQ0T DQ0T DQ0T DQ0T RUP4 RDN4 DQS1T DQ1T DQ1T DQ1T VREFB4N0 DQ1T DQS2T DQ2T DQ2T DQ2T DQ2T
DQS3T DQ3T DQ3T DQ3T DQ3T DQS4T DQ4T
DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQS1T DQ1T DQ1T DQ1T DQ1T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ1T DQ1T DQ1T DQ1T DQ1T DQS2T DQ2T
DQS0T DQ0T DQ0T DQ0T DQ0T
DQS0T DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ0T
DQ0T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2
VREFB4N1
DQ4T DQ4T DQ4T
DQS5T DQ5T DQ5T DQ5T VREFB4N1 DQ5T DQS6T DQ6T DQ6T DQ6T DQ6T
DQS7T DQ7T DQ7T DQ7T DQ7T DQS8T DQ8T DQ8T
DQ2T DQ2T DQ2T
DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T
DQ2T DQ2T DQ2T DQ2T DQ2T DQS3T DQ3T DQ3T DQ3T DQ3T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T
DQS0T DQ0T DQ0T DQ0T
DQS0T DQ0T DQ0T DQ0T
DQ0T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ3T DQ3T DQ3T DQ3T DQ3T DQS4T DQ4T DQ4T
DQS1T DQ1T DQ1T DQ1T DQ1T
DQS1T DQ1T DQ1T DQ1T DQ1T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ1T DQ1T
DQ0T DQ0T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2
VREFB4N2 VCC_PLL5_OUT VCCD_PLL5 VCCA_PLL5 GNDA_PLL5 GNDA_PLL5 GNDA_PLL11 GNDA_PLL11
DQ8T DQ8T
DQS9T DQ9T DQ9T DQ9T VREFB4N2 DQ9T
PLL5_FBn/OUT2n PLL5_FBp/OUT2p PLL5_OUT0n PLL5_OUT0p PLL5_OUT1n PLL5_OUT1p CLK12n CLK12p CLK13n CLK13p
DQ4T DQ4T
DQ1T DQ1T DQ1T
DQ0T DQ0T DQ0T
DQ4T DQ4T DQ4T DQ4T DQ4T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ1T DQ1T DQ1T DQ1T
DQ0T DQ0T DQ0T DQ0T
DQ0T DQ0T
DQ0T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0
VCCA_PLL11 VCCD_PLL11 VCC_PLL11_OUT VREFB3N0
CLK14p CLK14n CLK15p CLK15n PLL11_OUT0p PLL11_OUT0n PLL11_OUT1p PLL11_OUT1n PLL11_FBp/OUT2p PLL11_FBn/OUT2n
VREFB3N0 DQS10T DQ10T DQ10T DQ10T DQ10T
DQS11T
PGM2 PGM1 PGM0 ASDO nCSO CRC_ERROR DATA0 DATA1
DQS5T DQ5T DQ5T DQ5T DQ5T DQ2T DQ2T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T
DQS2T
DQS2T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1
VREFB3N1
DQ11T DQ11T DQ11T DQ11T DQS12T DQ12T DQ12T DQ12T DQ12T DQS13T DQ13T DQ13T DQ13T VREFB3N1 DQ13T
DQS14T DQ14T DQ14T DQ14T DQ14T DQS15T DQ15T DQ15T
DQ5T DQ5T DQ5T DQ5T DQ5T DQS6T DQ6T DQ6T DQ6T DQ6T
DQ2T DQ2T DQ2T DQ2T
DQ2T DQ2T DQ2T DQ2T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ2T DQ2T DQ2T DQ2T DQ2T DQS1T DQ1T DQ1T DQ1T
DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQ1T DQ1T DQ1T
DQ6T DQ6T DQ6T DQ6T DQ6T
DQ2T DQ2T DQ2T DQ2T DQ2T
DQ2T DQ2T DQ2T DQ2T
DQ1T
DQS7T DQ7T DQ7T DQ7T DQ7T
DQ3T DQ3T DQ3T DQ3T DQ3T DQS3T DQ3T DQ3T DQS3T DQ3T DQ3T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ7T DQ7T
DQ1T DQ1T
DQ1T DQ1T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB3N1 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2
VREFB3N2 nSTATUS DCLK
DQ15T DQ15T DQS16T DQ16T DQ16T DQ16T DQ16T
DQS17T DQ17T DQ17T DQ17T VREFB3N2 DQ17T
DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 RDYnBSY INIT_DONE nSTATUS DCLK
DQ7T DQ7T DQ7T DQS8T DQ8T DQ8T DQ8T DQ8T
DQ3T DQ3T
DQ3T DQ3T
DQ1T DQ1T DQ1T
DQ1T DQ1T DQ1T
DQ3T DQ3T DQ3T DQ3T DQ3T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ8T DQ8T DQ8T DQ8T DQ8T
DQ3T DQ3T DQ3T DQ3T DQ3T
DQ3T DQ3T DQ3T DQ3T
DQ1T DQ1T DQ1T DQ1T
DQ1T DQ1T
DQ1T
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VREFB3N2
CONF_DONE VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCT_B14 VCCT_B14 VCCH_B14 VCCH_B14 VCCR VCCR VCCA VCCL_B14 VCCT_B14 VCCT_B14 VCCH_B14 VCCH_B14 VCCR VCCR VCCA
CONF_DONE AC25 AC26 AE19 AE21 AF21 AG19 AE12 AE15 AF12 AF15 AA10 AA11
AA16 AA10 AA13
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VCCL_B14 VCCT_B13 VCCT_B13 VCCH_B13 VCCH_B13 VCCR VCCR VCCA VCCL_B13 VCCP VCCP VCCP VCCP VCCP VCCP VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCA VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AA12 AA14 AA16 AA18 AA20 AA22
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AA21 AA24
AA21 AA18
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AA24 AA27 AA30 AA33 AB19 AC12 AD10 AD11 AD12 AD15 AD18 AD21 AD24 AD27 AD30 AD33 AG12 AG15 AG17 AG18
AA27 AD24 AD27 AG27 AG28
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AG21 AG24 AG27 AG30 AG33 AK12 AK15 AK18 AK21 AK24 AK27 AK30 AK33 AN12 AN15 AN18 AN21 AN24 AN27 AN30 AN33 AN34 AP33
AH27 AG24 AG21 AG18 AG15 AG12 AD21 AD18 AD15 AD12 AA20 AA18 AA15 AA12
AA12 AA15
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AB10 AB11 AB12
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AC10
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AA13 AA15 AA17 AA19 AA21
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AB13 AB14
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
VCCPD2 VCCPD2 VCCPD1 VCCPD1 VCCPD8 VCCPD8 VCCPD7 VCCPD7 VCCPD4 VCCPD4 VCCPD3 VCCPD3 PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AB15 AD19 AD20 AD16 AD17 AB16 AB17 AB22 AC17 AJ29 AJ30 AK31 AK32 AK34 AL32 AL33 AL34
AE23 AB20 AA19 AB18 AA17 AB16 AA11
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
AK29 AD23 AD22 AE22 AG23 AC19 AH22 AG13 AE13 AF10
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
EP1AGX50DF1152 EP1AGX50DF780 EP1AGX50CF484 Bank Number VREF Group Name/Function Optional Function(s) Configuration Function x8/x9 Mode group mode (F780, F484) group mode (F1152) x16/x18 Mode group mode (F780, F484) group mode (F1152) Mode group mode (F1152)
Note: DQS/DQ mode shown this column applies largest device package list. Smaller packages have pins support some group. determine supported DQS/DQ groups, check corresponding availability targeted device package. example, EP1AGX50CF484 package, only groups available; group unavailable.
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX50 List
Page
Information ArriaGX EP1AGX50C/D Device Version
Name VCCINT VCCIO[1.4,7,8] Type (1st, 2nd, Function) Description Supply Reference Pins Power internal logic array voltage supply pins. VCCINT also supplies power input buffers used LVDS, LVPECL, differential HSTL, differential SSTL, HSTL, SSTL standards. Power supply voltage pins banks 1-4, Each bank support different voltage level. VCCIO supplies power output buffers standards. VCCIO also supplies power input buffers used LVTTL, LVCMOS, 3.3-V PCI, 3.3-V PCI-X standards. Power Dedicated power pins. This supply used power pre-drivers V/2.5 buffers configuration input pins JTAG pins. VCCPD powers JTAG pins (TCK, TMS, TDI, TRST) following configuration pins: nCONFIG, DCLK (when used input), nIO_Pullup, DATA[7.0], RUnLU, nCE, nWS, nRS, CLKUSR. Ground Device ground pins. Input Input reference voltage each bank. bank used voltage-referenced standard, then these pins used voltage-reference pins that bank. VREF pins within bank shorted together. VREF pins used, designers should connect them either GND. Power External clock output VCCIO power clock outputs PLL5_OUT[1.0]p, PLL5_OUT[1.0]n, PLL5_FBp/OUT2p, PLL5_FBn/OUT2n. This should connected voltage level target device which PLL5 bank driving. Refer data sheet absolute maximum voltage rating this pin. Power External clock output VCCIO power PLL6 clock outputs PLL6_OUT[1.0]p, PLL6_OUT[1.0]n, PLL6_FBp/OUT2p, PLL6_FBn/OUT2n. This should connected voltage level target device which PLL6 bank driving. Refer data sheet absolute maximum voltage rating this pin. External clock output VCCIO power PLL11 clock outputs PLL11_OUT[1.0]p, PLL11_OUT[1.0]n, PLL11_FBp/OUT2p, PLL11_FBn/OUT2n. This should connected voltage level target device which PLL11 bank driving. Refer data sheet absolute maximum voltage rating this pin. External clock output VCCIO power PLL12 clock outputs PLL12_OUT[1.0]p, PLL12_OUT[1.0]n, PLL12_FBp/OUT2p, PLL12_FBn/OUT2n. This should connected voltage level target device which PLL12 bank driving. Refer data sheet absolute maximum voltage rating this pin. analog power PLLs[1,2,5.8,11,12]. digital power PLLs[1,2,5.8,11,12]. Analog ground PLLs[1,2,5.8,11,12]. drive signals into this pin. Reference banks external precision resistor must connected designated within bank required, this regular pin.
VCCPD[1.4,7,8]
VREFB[1.4,7,8]N[2.0]
VCC_PLL5_OUT
VCC_PLL6_OUT
VCC_PLL11_OUT
Power
VCC_PLL12_OUT
Power
VCCA_PLL[1,2,5.8,11,12] VCCD_PLL[1,2,5.8,11,12] GNDA_PLL[1,2,5.8,11,12] RUP4
Power Power Ground Connect I/O, Input
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information ArriaGX EP1AGX50C/D Device Version
Name RDN4 RUP7 RDN7 Type (1st, 2nd, Function) Description I/O, Input Reference banks external precision resistor must connected designated within bank required, this regular pin. I/O, Input Reference banks external precision resistor must connected designated within bank required, this regular pin. I/O, Input Reference banks external precision resistor must connected designated within bank required, this regular pin. Dedicated Configuration/JTAG Pins Input Dedicated input that chooses whether internal pull-ups user pins dual-purpose pins (nCSO, ASDO, DATA[7.0], nWS, nRS, RDYnBSY, nCS, RUnLU, PGM[], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) before during configuration. logic high (1.5 turns weak pull-up, while logic turns them Input Dedicated input that selects which input buffer used configuration input pins: nCONFIG, DCLK (when used input), DATA[7.0], RUnLU, nCE, nWS, nRS, nCS, CLKUSR. V/2.5 input buffer powered VCCPD, while V/1.5 input buffer powered VCCIO. logic high (VCCPD) selects V/1.5 input buffer, while logic selects V/2.5 input buffer. VCCSEL should comply with logic levels driven configuration device device/microprocessor with flash memory. Input Input Input (PS, FPP) Output (AS) Input Input Input used conjunction with temperature sensing diode (bias-high input) inside Arria device. used conjunction with temperature sensing diode (bias-low input) inside Arria device. Dedicated configuration clock pin. configuration, DCLK used clock configuration data from external source into Arria device. mode, DCLK output from Arria device that provides timing configuration interface. Configuration input pins that Arria device configuration scheme. Dedicated active-low chip enable. When low, device enabled. When high, device disabled. Dedicated configuration control input. Pulling this during user-mode will cause FPGA lose configuration data, enter reset state, tri-state pins. Returning this logic high level will initiate reconfiguration. This dedicated configuration Done pin. status output, CONF_DONE drives before during configuration. Once configuration data received without error initialization cycle starts, CONF_DONE released. status input, CONF_DONE goes high after data received. Then device initializes enters user mode. available user pin. Output that drives when device configuration complete.
nIO_PULLUP
VCCSEL
TEMPDIODEp TEMPDIODEn DCLK
MSEL[3.0] nCONFIG
CONF_DONE
Bidirectional (open-drain)
nCEO
Output
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information ArriaGX EP1AGX50C/D Device Version
Name nSTATUS Type (1st, 2nd, Function) Description Bidirectional This dedicated configuration status pin. FPGA drives nSTATUS immediately after power-up (open-drain) releases after time. status output, nSTATUS pulled error occurs during configuration. status input, device enters error state when nSTATUS driven external source during configuration initialization. available user pin. Input Dedicated input which selects between time logic high (1.5 selects time about logic selects time about Optional/Dual-Purpose Configuration Pins Output Output control signal from Arria FPGA serial configuration device mode that enables configuration device. Output I/O, Output I/O, Input I/O, Input I/O, Input I/O, Input I/O, Bidirectional I/O, Output (open-drain) Control signal from Arria FPGA serial configuration device mode used read configuration data. Active high signal that indicates that error detection circuit detected errors configuration SRAM bits. This optional used when error detection circuit enabled. Optional that allows override clears device registers. When this driven low, registers cleared; when this driven high, registers behave programmed. Optional that allows override tri-states device. When this driven low, pins tristated; when this driven high, pins behave defined design. Dual-purpose configuration data input pin. DATA0 used bit-wide configuration after configuration complete. Dual-purpose configuration input data pins. DATA[7.0] pins used byte-wide configuration regular pins. These pins also used user pins after configuration. configuration scheme, DATA7 presents RDYnBSY signal after signal been strobed low. This dual-purpose used when enabled INIT_DONE. When enabled, transition from high indicates when device entered user mode. INIT_DONE output enabled, INIT_DONE cannot used user after configuration. These chip-select inputs that enable Arria device passive parallel asynchronous configuration mode. Drive high target device configuration. design requires active high enable, drive low. design requires active enable, drive high. Configuration will paused when either signal inactive. Hold pins active during configuration initialization. design these pins user pins after configuration. Read strobe input pin. input directs device drive RDYnBSY signal DATA7 pin. non-PPA schemes, functions user during configuration, which means tri-stated. This used user after configuration.
PORSEL
nCSO ASDO CRC_ERROR DEV_CLRn DEV_OE DATA0 DATA[6.1] DATA7 INIT_DONE
nCS,
I/O, Input
I/O, Input
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information ArriaGX EP1AGX50C/D Device Version
Name CLKUSR RDYnBSY Type (1st, 2nd, Function) Description I/O, Input Active-low write strobe input latch byte data DATA pins. This used user after configuration. I/O, Input Optional user-supplied clock input. Synchronizes initialization more devices. this enabled user-supplied configuration clock, used user pin. I/O, Output Ready busy output. high output indicates that target device ready accept another data byte. output indicates that target device ready receive another data byte. This used user after configuration. I/O, Output These output pins control eight pages memory (either flash enhanced configuration device) when using remote system update mode. When using remote update local update configuration modes, these pins user pins. I/O, Input Input that selects between remote update local update. logic high (1.5 selects remote update logic selects local update. When using remote update local update configuration modes, this available general-purpose user pin. Input Dedicated JTAG input pin. JTAG circuitry disabled connecting GND. Input Dedicated JTAG input pin. JTAG circuitry disabled connecting VCC. Input Dedicated JTAG input pin. JTAG circuitry disabled connecting VCC. Output Dedicated JTAG output pin. Input Dedicated active JTAG input pin. TRST used asynchronously reset JTAG boundary-scan circuit. Clock Pins Dedicated clock input pins that also used data inputs. Dedicated negative clock input pins differential clock input that also used data inputs. These pins used pins, clock input pins, positive terminal data pins differential receiver channels. These pins used pins, negative clock input pins differential clock input, negative data pins differential receiver channels. These pins used pins clock input pins. These pins used pins negative clock input pins differential clock inputs. Dedicated input that drives optional pllena port PLLs. Dedicated positive clock inputs fast PLLs (PLLs which also used data inputs. Dedicated negative clock inputs associated with FPLL[7,8]CLKp pins, which also used data inputs. Optional positive external clock outputs [1,0] from enhanced PLL5. These pins differential (two output pairs) single ended (four clock outputs from PLL5). Optional negative external clock outputs [1,0] from enhanced PLL5. clock outputs single ended, then each pair pins (i.e., PLL5_OUT0p PLL5_OUT0n considered pair) either phase degrees phase.
PGM[2.0]
RUnLU
TRST
CLK[1,3]p CLK[1,3]n CLK[2,0]p/DIFFIO_RX_C[1,0]p CLK[2,0]n/DIFFIO_RX_C[1,0]n CLK[4-7,12-15]p CLK[4-7,12-15]n PLL_ENA FPLL[8.7]CLKp FPLL[8.7]CLKn PLL5_OUT[1,0]p PLL5_OUT[1,0]n
Clock, Input Clock, Input I/O, Clock I/O, Clock I/O, Clock I/O, Clock Input Clock, Input Clock, Input Output Output
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information ArriaGX EP1AGX50C/D Device Version
Name PLL6_OUT[1,0]p PLL6_OUT[1,0]n Type (1st, 2nd, Function) Description Output Optional positive external clock outputs [1,0] from enhanced PLL6. These pins differential (two output pairs) single ended (four clock outputs from PLL6). Output Optional negative external clock outputs [1,0] from enhanced PLL6. clock outputs single ended, then each pair pins (i.e., PLL6_OUT0p PLL6_OUT0n considered pair) either phase degrees phase. Output Optional positive external clock outputs [1,0] from enhanced These pins differential (two output pairs) single ended (four clock outputs from PLL11). Output Optional negative external clock outputs [1,0] from enhanced PLL11. clock outputs single ended, then each pair pins (i.e., PLL11_OUT0p PLL11_OUT0n considered pair) either phase degrees phase. Output Optional positive external clock outputs [1,0] from enhanced PLL12. These pins differential (two output pairs) single ended (four clock outputs from PLL12). Output Optional negative external clock outputs [1,0] from enhanced PLL12. clock outputs single ended, then each pair pins (i.e., PLL12_OUT0p PLL12_OUT0n considered pair) either phase degrees phase. I/O, Input, Output These pins used pins, positive external feedback input pins external clock outputs PLL[6,5]. I/O, Input, Output These pins used pins, negative external feedback input PLL[6,5]_FBp negative terminal clock output pins differential clock output. I/O, Input, Output These pins used pins, positive external feedback input pins positive external clock outputs PLL[12.11]. I/O, Input, Output These pins used pins, negative external feedback input PLL[12.11]_FBp negative external clock output pins differential clock output. Dual-Purpose Differential External Memory Interface Pins Input Dual-purpose differential receiver channels. These channels used receiving LVDS-compatible signals. Pins with suffix carry positive signal differential channel. used differential signaling, these pins available user pins. Input Dual-purpose differential receiver channels. These channels used receiving LVDS-compatible signals. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins. Output Dual-purpose differential transmitter channels. These channels used transmitting LVDS-compatible signals. Pins with suffix carry positive signal differential channel. used differential signaling, these pins available user pins. Output Dual-purpose differential transmitter channels. These channels used transmitting LVDS-compatible signals. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins. Optional data strobe signal external memory interfacing. These pins drive dedicated phaseshift circuitry. shifted signal also drive internal logic.
PLL11_OUT[1,0]p PLL11_OUT[1,0]n
PLL12_OUT[1,0]p PLL12_OUT[1,0]n
PLL[6.5]_FBp/OUT2p PLL[6.5]_FBn/OUT2n PLL[12.11]_FBp/OUT2p PLL[12.11]_FBn/OUT2n
DIFFIO_RX[50.1]p
DIFFIO_RX[50.1]n
DIFFIO_TX[51.0]p
DIFFIO_TX[51.0]n
DQS[17.0][T,B]
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Definitions
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Information ArriaGX EP1AGX50C/D Device Version
Name DQ[17.0][T,B] Type (1st, 2nd, Function) Description Optional data signal external memory interfacing. order bits within designated important; however, caution when making assignments plan migrating different memory interface that different width. Analyze available pins across pertinent columns list. Power Power Power Power Power Power Input Input O,Output O,Output Input Input Input Transceiver (I/O Banks) Pins bank [15.13] power. This power connected bank [15.13] receiver analog power. This power connected bank [15.13] transmitter analog power. This power connected bank [15.13] analog power. This power connected bank [15.13] transmitter driver analog power. This power connected bank [15.13] analog power. This power connected High-speed positive differential receiver channels. High-speed negative differential receiver channels. High-speed positive differential transmitter channel. High-speed negative differential transmitter channels. High-speed differential reference clock positive. This powered VCCT_B[15.13]. High-speed differential reference clock negative. This powered VCCT_B[15.13]. Reference resistor side banks.
VCCP VCCR VCCT_B[15.13] VCCA VCCH_B[15.13] VCCL_B[15.13] GXB_RX[11.0]p GXB_RX[11.0]n GXB_TX[11.0]p GXB_TX[11.0]n REFCLK[0,1]_B[15.13]p REFCLK[0,1]_B[15.13]n RREFB[15.13]
Note: These descriptions created based largest density Arria (EP1AGX90E) device.
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Definitions
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Information ArriaGX EP1AGX50C/D Device Version
VREFB3N0 VREFB2N2
VREFB3N1
VREFB3N2
EPLL PLL5 Bank9
VREFB4N0
VREFB4N1
VREFB4N2
VREFB2N1
VREFB2N0
FPLL PLL1 FPLL PLL2
EP1AGX50DF1152
VREFB1N2
VREFB1N1
VREFB1N0
VREFB8N0 VREFB8N1 VREFB8N2
Bank10 EPLL PLL6
VREFB7N0
VREFB7N1 VREFB7N2
Notes: This view silicon die. flip chip packages, mounted upside down package; therefore, obtain package view, flip this diagram vertical axis. This only pictorial representation provide idea placement device. Refer list Quartus software exact locations.
PT-EP1AGX50C/D -1.1 Copyright 2007 Altera Corp.
Bank Diagram
Page
Information ArriaGX EP1AGX50C/D Device Version
VREFB3N0 VREFB2N2
VREFB3N1
VREFB3N2
EPLL PLL5 Bank9
VREFB4N0
VREFB4N1
VREFB4N2
VREFB2N1
VREFB2N0
FPLL PLL1 FPLL PLL2
EP1AGX50DF780
VREFB1N2
VREFB1N1
VREFB1N0
VREFB8N0 VREFB8N1 VREFB8N2
Bank10 EPLL PLL6
VREFB7N0
VREFB7N1 VREFB7N2
Notes: This view silicon die. flip chip packages, mounted upside down package; therefore, obtain package view, flip this diagram vertical axis. This only pictorial representation provide idea placement device. Refer list Quartus software exact locations.
PT-EP1AGX50C/D -1.1 Copyright 2007 Altera Corp.
Bank Diagram
Page
Information ArriaGX EP1AGX50C/D Device Version
VREFB3N0 VREFB2N2
VREFB3N1
VREFB3N2
EPLL PLL5 Bank9
VREFB4N0
VREFB4N1
VREFB4N2
VREFB2N0
VREFB2N1
FPLL PLL1 FPLL PLL2
EP1AGX50CF484
VREFB8N0 VREFB8N1 VREFB8N2
VREFB1N1 VREFB1N0
VREFB1N2
Bank10 EPLL PLL6
VREFB7N0
VREFB7N1 VREFB7N2
Notes: This view silicon die. flip chip packages, mounted upside down package; therefore, obtain package view, flip this diagram vertical axis. This only pictorial representation provide idea placement device. Refer list Quartus software exact locations.
PT-EP1AGX50C/D -1.1 Copyright 2007 Altera Corp.
Bank Diagram
Page
Information ArriaGX EP1AGX50C/D Device Version
Version History Date 6/22/2007 7/27/2007 Changes Made Initial release Added F484 package.
PT-EP1AGX50C/D-1.1 Copyright 2007 Altera Corp.
Revision History
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