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Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0
VREFB2N0
DIFFIO_RX28p DIFFIO_RX28n DIFFIO_TX28p DIFFIO_TX28n DIFFIO_RX27p DIFFIO_RX27n DIFFIO_TX27p DIFFIO_TX27n DIFFIO_RX26p DIFFIO_RX26n DIFFIO_TX26p DIFFIO_TX26n DIFFIO_RX25p DIFFIO_RX25n DIFFIO_TX25p DIFFIO_TX25n VREFB2N0 DIFFIO_RX24p DIFFIO_RX24n DIFFIO_TX24p DIFFIO_TX24n DIFFIO_RX23p DIFFIO_RX23n DIFFIO_TX23p DIFFIO_TX23n DIFFIO_RX22p DIFFIO_RX22n DIFFIO_TX22p
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1
VREFB2N1
DIFFIO_TX22n DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n DIFFIO_RX20p DIFFIO_RX20n DIFFIO_TX20p DIFFIO_TX20n DIFFIO_RX19p DIFFIO_RX19n DIFFIO_TX19p DIFFIO_TX19n DIFFIO_RX18p DIFFIO_RX18n DIFFIO_TX18p DIFFIO_TX18n DIFFIO_RX17p DIFFIO_RX17n DIFFIO_TX17p DIFFIO_TX17n VREFB2N1 DIFFIO_RX16p DIFFIO_RX16n DIFFIO_TX16p DIFFIO_TX16n DIFFIO_RX15p DIFFIO_RX15n
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1
VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0
CLK1n CLK1p VCCD_PLL1 VCCA_PLL1 GNDA_PLL1 GNDA_PLL1 GNDA_PLL2 GNDA_PLL2 VCCA_PLL2 VCCD_PLL2 CLK3p CLK3n
DIFFIO_TX15p DIFFIO_TX15n DIFFIO_RX14p DIFFIO_RX14n DIFFIO_TX14p DIFFIO_TX14n DIFFIO_RX13p DIFFIO_RX13n DIFFIO_TX13p DIFFIO_TX13n CLK0n/DIFFIO_RX_C0n CLK0p/DIFFIO_RX_C0p INPUT INPUT
CLK2p/DIFFIO_RX_C1p CLK2n/DIFFIO_RX_C1n INPUT INPUT DIFFIO_RX12p DIFFIO_RX12n
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1
VREFB1N0
DIFFIO_TX12p DIFFIO_TX12n DIFFIO_RX11p DIFFIO_RX11n DIFFIO_TX11p DIFFIO_TX11n VREFB1N0 DIFFIO_RX10p DIFFIO_RX10n DIFFIO_TX10p DIFFIO_TX10n DIFFIO_RX9p DIFFIO_RX9n DIFFIO_TX9p DIFFIO_TX9n DIFFIO_RX8p DIFFIO_RX8n DIFFIO_TX8p DIFFIO_TX8n DIFFIO_RX7p DIFFIO_RX7n DIFFIO_TX7p DIFFIO_TX7n DIFFIO_RX6p DIFFIO_RX6n DIFFIO_TX6p DIFFIO_TX6n DIFFIO_RX5p
AA28 AA26 AA25 AB28 AB27 AC28 AD28 AD26
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0
VREFB1N1 TRST
DIFFIO_RX5n DIFFIO_TX5p DIFFIO_TX5n DIFFIO_RX4p DIFFIO_RX4n DIFFIO_TX4p DIFFIO_TX4n VREFB1N1 DIFFIO_RX3p DIFFIO_RX3n DIFFIO_TX3p DIFFIO_TX3n DIFFIO_RX2p DIFFIO_RX2n DIFFIO_TX2p DIFFIO_TX2n DIFFIO_RX1p DIFFIO_RX1n DIFFIO_TX1p DIFFIO_TX1n DIFFIO_RX0p DIFFIO_RX0n DIFFIO_TX0p DIFFIO_TX0n TRST
AD25 AC25 AC24 AB22 AB21 AC27 AC26 AE26 AE25 AB26 AB25 AB24 AB23 AE28 AE27 AC23 AC22 AF28 AF27 AA23 AA22
AA22 AB22 AB21 AB20 AB19 AB18 AB17 AA17 AA20 AA19 AA16 AB16 AB15 AA14 AB13 AB14
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0
nCONFIG VCCSEL VREFB8N0
nCONFIG VCCSEL CLKUSR
DQ17B VREFB8N0 DQ17B DQ17B DQ17B DQS17B
DQ15B DQ15B DQ15B DQ15B DQS15B
AE24 AC21 AE22 AE21 AE23 AD20 AB20 AF26 AF25 AD19 AG26 AH25 AH26 AG25 AA19 AB19 AH24 AF23 AF24 AF22 AH23 AG23 AC19 AB18 AE19
AB12 AA11 AA13 AB11
EP1AGX35CF484
DQ3B DQ3B DQ3B DQ3B DQ3B
DQ1B DQ1B DQ1B DQ1B
DQ3B DQ3B DQ3B DQ3B DQS3B
DQ1B DQ1B DQ1B DQ1B DQ1B
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1
VREFB8N1
DQ13B DQ13B DQ13B DQ13B DQS13B AG22 AF20 AH22 AH21 AF21 AG20 AA17 AH20 AG19 AF19 AF18 AH18 AH19 AD17 AB17 AC17 AC16 AD16 AE17 AF17 AB15 AC15 AG17 AH17 DQ2B DQ2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B DQS1B
DQ11B DQ11B DQ11B DQ11B DQS11B VREFB8N1
EP1AGX35CF484
DQ2B DQ2B DQ2B DQ2B DQS2B
DQ1B DQ1B DQ1B DQ1B DQ1B
RUnLU DEV_OE DEV_CLRn CLK5n CLK5p CLK4n CLK4p
AB10 AA10
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0
GNDA_PLL6 GNDA_PLL6 VCCA_PLL6 VCCD_PLL6 VCC_PLL6_OUT VREFB7N0
CLK7p CLK7n CLK6p CLK6n PLL6_OUT1p PLL6_OUT1n PLL6_OUT0p PLL6_OUT0n PLL6_FBp/OUT2p PLL6_FBn/OUT2n
DQ9B VREFB7N0 DQ9B DQ9B DQ9B DQS9B
DQ7B
AA14 AF15 AE15 AH16 AG16 AG14 AF14 AH15 AH14 AE14 AD14 AB13 AG13 AE13 AB14 AC14 AC13 AD13 AF13 AB12 AC12 AH13
EP1AGX35CF484
DQ1B DQ1B DQ1B DQ1B DQ1B
DQ0B DQ0B DQ0B DQ0B
DQ1B
DQ0B
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1
VREFB7N1
DQ7B DQ7B DQ7B DQS7B
DQ5B DQ5B DQ5B DQ5B DQS5B
DQ3B DQ3B DQ3B DQ3B DQS3B VREFB7N1
DQ1B DQ1B
AF12 AH12 AG11 AH11 AE12 AA11 AB11 AC11 AD11 AF11 AF10 AG10 AH10 AE11 AB10 AE10 AD10 AC10
DQ1B DQ1B DQ1B DQS1B
EP1AGX35CF484
DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQ0B
DQ0B DQ0B DQ0B DQ0B DQS0B
DQ0B DQ0B DQ0B DQ0B DQS0B
DQ0B DQ0B DQ0B DQ0B DQ0B
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1
PORSEL nIO_PULLUP PLL_ENA nCEO GXB_RX7n GXB_RX7p GXB_TX7n GXB_TX7p GXB_RX6n GXB_RX6p GXB_TX6n GXB_TX6p RREFB14 REFCLK0_B14n REFCLK0_B14p REFCLK1_B14n REFCLK1_B14p VCCA VCCA VCCA GXB_RX4n
DQ1B DQ1B DQS1B RDN7 RUP7 PORSEL nIO_PULLUP PLL_ENA nCEO
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
GXB_RX4p GXB_TX4n GXB_TX4p GXB_RX5n GXB_RX5p GXB_TX5n GXB_TX5p GXB_RX3n GXB_RX3p GXB_TX3n GXB_TX3p GXB_RX2n GXB_RX2p GXB_TX2n GXB_TX2p RREFB13 REFCLK0_B13n REFCLK0_B13p REFCLK1_B13n REFCLK1_B13p VCCA VCCA VCCA GXB_RX0n GXB_RX0p GXB_TX0n GXB_TX0p GXB_RX1n
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0
GXB_RX1p GXB_TX1n GXB_TX1p VCCA TEMPDIODEp TEMPDIODEn MSEL3 MSEL2 MSEL1 MSEL0 VREFB4N0
MSEL3 MSEL2 MSEL1 MSEL0 RUP4 RDN4 DQS1T DQ1T DQ1T DQ1T DQ1T
VREFB4N0 DQS3T DQ3T DQ3T
DQS0T DQ0T DQ0T DQ0T DQ0T
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1
DQ3T DQ3T
DQS5T DQ5T DQ5T DQ5T DQ5T
DQS7T DQ7T DQ7T DQ7T DQ7T
DQS9T DQ9T DQ9T
EP1AGX35CF484
DQ0T DQ0T
DQ0T DQ0T DQ0T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQS0T DQ0T DQ0T DQ0T DQ0T
DQS1T DQ1T DQ1T DQ1T DQ1T
DQ0T DQ0T DQ0T DQ0T DQ0T
DQ1T DQ1T
DQ0T DQ0T
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1
VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0
VREFB4N1 VCC_PLL5_OUT VCCD_PLL5 VCCA_PLL5 GNDA_PLL5 GNDA_PLL5
DQ9T VREFB4N1 DQ9T
PLL5_FBn/OUT2n PLL5_FBp/OUT2p PLL5_OUT0n PLL5_OUT0p PLL5_OUT1n PLL5_OUT1p CLK12n CLK12p CLK13n CLK13p
CLK14p CLK14n CLK15p CLK15n PGM2 PGM1 PGM0
EP1AGX35CF484
DQ1T DQ1T DQ1T
DQ0T DQ0T
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N1 VREFB3N1 VREFB3N1
VREFB3N0
ASDO nCSO CRC_ERROR DATA0 DATA1
VREFB3N0 DQS11T DQ11T DQ11T DQ11T DQ11T
DQS13T DQ13T DQ13T DQ13T DQ13T
DQS15T DQ15T
EP1AGX35CF484
DQS2T DQ2T DQ2T DQ2T DQ2T
DQ1T DQ1T DQ1T DQ1T DQ1T
DQ2T DQ2T DQ2T DQ2T DQ2T
DQS1T DQ1T DQ1T DQ1T DQ1T
DQS3T DQ3T
DQ1T
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1
VREFB3N1 nSTATUS DCLK
DQ15T DQ15T DQ15T
DQS17T DQ17T DQ17T DQ17T DQ17T VREFB3N1
DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 RDYnBSY INIT_DONE nSTATUS DCLK
EP1AGX35CF484
DQ3T DQ3T DQ3T
DQ1T DQ1T DQ1T DQ1T
DQ3T DQ3T DQ3T DQ3T DQ3T
DQ1T DQ1T DQ1T DQ1T
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VREFB3N1
CONF_DONE VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCT_B14 VCCT_B14 VCCH_B14 VCCH_B14 VCCR VCCR VCCA VCCL_B14 VCCT_B13 VCCT_B13 VCCH_B13 VCCH_B13 VCCL_B13 VCCR VCCR
CONF_DONE
AA16 AA10 AA13
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VCCA VCCP VCCP VCCP VCCP VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCA VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
AA21 AA24 AA27 AD24 AD27 AG27 AG28
AA21 AA18
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
AH27 AG24 AG21 AG18 AG15 AG12 AD21 AD18 AD15 AD12
AA12 AA15
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
AA20 AA18 AA15 AA12
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
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Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
VCCPD2 VCCPD1 VCCPD8 VCCPD7 VCCPD4 VCCPD3
AD22 AD23
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
AE16 AF16 AE20 AC20 AC18 AE18 AB16
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information ArriaGX EP1AGX35C/D Device Version
Bank Number VREF Group Name/Function Optional Function(s) Configuration Function X8/X9 Mode Group Mode (F780, F484) X16/X18 Mode Group Mode (F780, F484)
EP1AGX35DF780
Note: DQS/DQ mode shown this column applies largest device package list. Smaller packages have pins support some groups. determine supported DQS/DQ groups, check availability target device package. example, EP1AGX35CF484 package, only group available; group unavailable.
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
EP1AGX35 List
EP1AGX35CF484
Page
Information Arria GXEP1AGX35C/D Device Version Note
Name VCCINT VCCIO[1.4,7,8] Type (1st, 2nd, Function) Description Supply Reference Pins Power 1.2-V internal logic array voltage supply pins. VCCINT also supplies power input buffers used LVDS, LVPECL, differential HSTL, differential SSTL, HSTL, SSTL standards. Power supply voltage pins banks 1-4, Each bank support different voltage level. VCCIO supplies power output buffers standards. VCCIO also supplies power input buffers used LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, 3.3-V PCI-X standards. Power Dedicated power pins. This 3.3-V supply used power pre-drivers 3.3-V/2.5-V buffers configuration input pins JTAG pins. VCCPD powers JTAG pins (TCK, TMS, TDI, TRST) following configuration pins: nCONFIG, DCLK (when used input), nIO_Pullup, DATA[7.0], RUnLU, nCE, nWS, nRS, nCS, CLKUSR. Ground Input Device ground pins. Input reference voltage each bank. bank used voltage-referenced standard, then these pins used voltage-reference pins that bank. VREF pins within bank shorted together. VREF pins used, connect them either GND. External clock output VCCIO power PLL5 clock outputs PLL5_OUT[1.0]p, PLL5_OUT[1.0]n, PLL5_FBp/OUT2p, PLL5_FBn/OUT2n. This should connected voltage level target device which PLL5 bank driving. Refer data sheet absolute maximum voltage rating this pin. External clock output VCCIO power PLL6 clock outputs PLL6_OUT[1.0]p, PLL6_OUT[1.0]n, PLL6_FBp/OUT2p, PLL6_FBn/OUT2n. This should connected voltage level target device which PLL6 bank driving. Refer data sheet absolute maximum voltage rating this pin. External clock output VCCIO power PLL11 clock outputs PLL11_OUT[1.0]p, PLL11_OUT[1.0]n, PLL11_FBp/OUT2p, PLL11_FBn/OUT2n. This should connected voltage level target device which PLL11 bank driving. Refer data sheet absolute maximum voltage rating this pin. External clock output VCCIO power PLL12 clock outputs PLL12_OUT[1.0]p, PLL12_OUT[1.0]n, PLL12_FBp/OUT2p, PLL12_FBn/OUT2n. This should connected voltage level target device which PLL12 bank driving. Refer data sheet absolute maximum voltage rating this pin. 1.2-V analog power PLLs[1,2,5.8,11,12]. 1.2-V digital power PLLs[1,2,5.8,11,12]. Analog ground PLLs[1,2,5.8,11,12]. drive signals into this pin. Reference banks external precision resistor must connected designated within bank required, this regular pin.
VCCPD[1.4,7,8]
VREFB[1.4,7,8]N[2.0]
VCC_PLL5_OUT
Power
VCC_PLL6_OUT
Power
VCC_PLL11_OUT
Power
VCC_PLL12_OUT
Power
VCCA_PLL[1,2,5.8,11,12] VCCD_PLL[1,2,5.8,11,12] GNDA_PLL[1,2,5.8,11,12] RUP4
Power Power Ground Connect I/O, Input
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information Arria GXEP1AGX35C/D Device Version Note
Name RDN4 RUP7 RDN7 Type (1st, 2nd, Function) Description I/O, Input Reference banks external precision resistor must connected designated within bank required, this regular pin. I/O, Input Reference banks external precision resistor must connected designated within bank required, this regular pin. I/O, Input Reference banks external precision resistor must connected designated within bank required, this regular pin. Input Dedicated Configuration/JTAG Pins Dedicated input that chooses whether internal pull-ups user pins dual-purpose pins (nCSO, ASDO, DATA[7.0], nWS, nRS, RDYnBSY, nCS, RUnLU, PGM[], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) before during configuration. logic high (1.5 turns weak pull-up, while logic turns Dedicated input that selects which input buffer used configuration input pins: nCONFIG, DCLK (when used input), DATA[7.0], RUnLU, nCE, nWS, nRS, nCS, CLKUSR. 3.3-V/2.5-V input buffer powered VCCPD, while 1.8-V/1.5-V input buffer powered VCCIO. logic high (VCCPD) selects 1.8-V/1.5-V input buffer, while logic selects 3.3-V/2.5-V input buffer. VCCSEL should comply with logic levels driven configuration device device/microprocessor with flash memory. used conjunction with temperature-sensing diode (bias-high input) inside Arria device. used conjunction with temperature-sensing diode (bias-low input) inside Arria device. Dedicated configuration clock pin. configuration, DCLK used clock configuration data from external source into Arria device. mode, DCLK output from Arria device that provides timing configuration interface. Configuration input pins that Arria device configuration scheme. Dedicated active-low chip enable. When low, device enabled. When high, device disabled. Dedicated configuration control input. Pulling this during user mode will cause FPGA lose configuration data, enter reset state tri-state pins. Returning this logic high level will initiate reconfiguration. This dedicated configuration Done pin. status output, CONF_DONE drives before during configuration. Once configuration data received without error initialization cycle starts, CONF_DONE released. status input, CONF_DONE goes high after data received. Then device initializes enters user mode. available user pin. Output that drives when device configuration complete. This dedicated configuration status pin. FPGA drives nSTATUS immediately after power-up releases after time. status output, nSTATUS pulled error occurs during configuration. status input, device enters error state when nSTATUS driven external source during configuration initialization. available user pin.
nIO_PULLUP
VCCSEL
Input
TEMPDIODEp TEMPDIODEn DCLK
Input Input Input (PS, FPP) Output (AS) Input Input Input
MSEL[3.0] nCONFIG
CONF_DONE
Bidirectional (open-drain)
nCEO nSTATUS
Output Bidirectional (open-drain)
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Definitions
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Information Arria GXEP1AGX35C/D Device Version Note
Name PORSEL Type (1st, 2nd, Function) Description Input Dedicated input which selects between time logic high (1.5 selects time about logic selects time about Optional/Dual-Purpose Configuration Pins I/O, Output Output control signal from Arria FPGA serial configuration device mode that enables configuration device. I/O, Output Control signal from Arria FPGA serial configuration device mode used read configuration data. I/O, Output Active high signal that indicates that error detection circuit detected errors configuration SRAM bits. This optional used when error detection circuit enabled. I/O, Input Optional that allows override clears device registers. When this driven low, registers cleared; when this driven high, registers behave programmed. I/O, Input Optional that allows override tri-states device. When this driven low, pins tristated; when this driven high, pins behave defined design. I/O, Input Dual-purpose configuration input data pin. DATA0 used bit-wide configuration after configuration complete. I/O, Input Dual-purpose configuration input data pins. DATA[7.0] pins used byte-wide configuration regular pins. These pins also used user pins after configuration. I/O, Bidirectional configuration scheme, DATA7 presents RDYnBSY signal after signal been strobed low. I/O, Output This dual-purpose used when enabled INIT_DONE. When enabled, (open-drain) transition from high indicates when device entered user mode. INIT_DONE output enabled, INIT_DONE cannot used user after configuration. I/O, Input These chip-select inputs that enable Arria device passive parallel asynchronous configuration mode. Drive high target device configuration. design requires active high enable, drive low. design requires active enable, drive high. Configuration will paused when either signal inactive. Hold pins active during configuration initialization. design these pins user pins after configuration. Read strobe input pin. input directs device drive RDYnBSY signal DATA7 pin. non-PPA schemes, functions user during configuration, which means tri-stated. This used user after configuration. Active-low write strobe input latch byte data DATA pins. This used user after configuration. Optional user-supplied clock input. Synchronizes initialization more devices. this enabled user-supplied configuration clock, used user pin.
nCSO ASDO CRC_ERROR DEV_CLRn DEV_OE DATA0 DATA[6.1] DATA7 INIT_DONE
nCS,
I/O, Input
CLKUSR
I/O, Input I/O, Input
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information Arria GXEP1AGX35C/D Device Version Note
Name RDYnBSY Type (1st, 2nd, Function) Description I/O, Output Ready busy output. high output indicates that target device ready accept another data byte. output indicates that target device ready receive another data byte. This used user after configuration. I/O, Output These output pins control eight pages memory (either flash enhanced configuration device) when using remote system update mode. When using remote update local update configuration modes, these pins user pins. I/O, Input Input that selects between remote update local update. logic high (1.5 selects remote update logic selects local update. When using remote update local update configuration modes, this available general-purpose user pin. Input Dedicated JTAG input pin. JTAG circuitry disabled connecting GND. Input Dedicated JTAG input pin. JTAG circuitry disabled connecting VCC. Input Dedicated JTAG input pin. JTAG circuitry disabled connecting VCC. Output Dedicated JTAG output pin. Input Dedicated active JTAG input pin. TRST used asynchronously reset JTAG boundary-scan circuit. Clock Pins Dedicated clock input pins that also used data inputs. Dedicated negative clock input pins differential clock input that also used data inputs. These pins used pins, clock input pins, positive terminal data pins differential receiver channels. These pins used pins, negative clock input pins differential clock input, negative data pins differential receiver channels. These pins used pins clock input pins. These pins used pins negative clock input pins differential clock inputs. Dedicated input that drives optional pllena port PLLs. Dedicated positive clock inputs fast PLLs (PLLs which also used data inputs. Dedicated negative clock inputs associated with FPLL[7,8]CLKp pins which also used data inputs. Optional positive external clock outputs [1,0] from enhanced PLL5. These pins differential (two output pairs) single-ended (four clock outputs from PLL5). Optional negative external clock outputs [1,0] from enhanced PLL5. clock outputs single-ended, then each pair pins (i.e., PLL5_OUT0p PLL5_OUT0n considered pair) either phase degrees phase. Optional positive external clock outputs [1,0] from enhanced PLL6. These pins differential (two output pairs) single-ended (four clock outputs from PLL6).
PGM[2.0]
RUnLU
TRST
CLK[1,3]p CLK[1,3]n CLK[2,0]p/DIFFIO_RX_C[1,0]p CLK[2,0]n/DIFFIO_RX_C[1,0]n CLK[4-7,12-15]p CLK[4-7,12-15]n PLL_ENA FPLL[8.7]CLKp FPLL[8.7]CLKn PLL5_OUT[1,0]p PLL5_OUT[1,0]n
Clock, Input Clock, Input I/O, Clock I/O, Clock I/O, Clock I/O, Clock Input Clock, Input Clock, Input Output Output
PLL6_OUT[1,0]p
Output
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information Arria GXEP1AGX35C/D Device Version Note
Name PLL6_OUT[1,0]n Type (1st, 2nd, Function) Description Output Optional negative external clock outputs [1,0] from enhanced PLL6. clock outputs single-ended, then each pair pins (i.e. PLL6_OUT0p PLL6_OUT0n considered pair) either phase degrees phase. Output Optional positive external clock outputs [1,0] from enhanced PLL11. These pins differential (two output pairs) single-ended (four clock outputs from PLL11). Output Optional negative external clock outputs [1,0] from enhanced PLL11. clock outputs single-ended, then each pair pins (i.e. PLL11_OUT0p PLL11_OUT0n considered pair) either phase degrees phase. Output Optional positive external clock outputs [1,0] from enhanced PLL12. These pins differential (two output pairs) single-ended (four clock outputs from PLL12). Output Optional negative external clock outputs [1,0] from enhanced PLL12. clock outputs single-ended, then each pair pins (i.e. PLL12_OUT0p PLL12_OUT0n considered pair) either phase degrees phase. I/O, Input, Output These pins used pins, positive external feedback input pins, external clock outputs PLL[6,5]. I/O, Input, Output I/O, Input, Output I/O, Input, Output These pins used pins, negative external feedback input PLL[6,5]_FBp, negative terminal clock output pins differential clock output. These pins used pins, positive external feedback input pins, positive external clock outputs PLL[12.11]. These pins used pins, negative external feedback input PLL[12.11]_FBp, negative external clock output pins differential clock output. Dual-Purpose Differential External Memory Interface Pins Dual-purpose differential receiver channels. These channels used receiving LVDS-compatible signals. Pins with suffix carry positive signal differential channel. used differential signaling, these pins available user pins. Dual-purpose differential receiver channels. These channels used receiving LVDS-compatible signals. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins. Dual-purpose differential transmitter channels. These channels used transmitting LVDS-compatible signals. Pins with suffix carry positive signal differential channel. used differential signaling, these pins available user pins. Dual-purpose differential transmitter channels. These channels used transmitting LVDS-compatible signals. Pins with suffix carry negative signal differential channel. used differential signaling, these pins available user pins. Optional data strobe signal external memory interfacing. These pins drive dedicated phase-shift circuitry. shifted signal also drive internal logic.
PLL11_OUT[1,0]p PLL11_OUT[1,0]n
PLL12_OUT[1,0]p PLL12_OUT[1,0]n
PLL[6.5]_FBp/OUT2p PLL[6.5]_FBn/OUT2n PLL[12.11]_FBp/OUT2p PLL[12.11]_FBn/OUT2n
DIFFIO_RX[50.1]p
Input
DIFFIO_RX[50.1]n
Input
DIFFIO_TX[51.0]p
Output
DIFFIO_TX[51.0]n
Output
DQS[17.0][T,B]
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information Arria GXEP1AGX35C/D Device Version Note
Name DQ[17.0][T,B] Type (1st, 2nd, Function) Description Optional data signal external memory interfacing. order bits within designated important; however, caution when making assignments plan migrating different memory interface that different width. Analyze available pins across pertinent columns list. Power Power Power Power Power Power Input Input Output Output Input Input Input Transceiver (I/O Banks) Pins bank [15.13] power. This power connected bank [15.13] receiver analog power. This power connected bank [15.13] transmitter analog power. This power connected bank [15.13] analog power. This power connected bank [15.13] transmitter driver analog power. This power connected bank [15.13] analog power. This power connected High-speed positive differential receiver channels. High-speed negative differential receiver channels. High-speed positive differential transmitter channel. High-speed negative differential transmitter channels. High-speed differential reference clock positive. This powered 1.2-V VCCT_B[15.13]. High-speed differential reference clock negative. This powered 1.2-V VCCT_B[15.13]. Reference resistor side banks.
VCCP VCCR VCCT_B[15.13] VCCA VCCH_B[15.13] VCCL_B[15.13] GXB_RX[11.0]p GXB_RX[11.0]n GXB_TX[11.0]p GXB_TX[11.0]n REFCLK[0,1]_B[15.13]p REFCLK[0,1]_B[15.13]n RREFB[15.13]
Note: These descriptions created based Arria device with largest density, EP1AGX90E.
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Definitions
Page
Information ArriaGX EP1AGX35C/D Device, Version
VREFB3N0 VREFB2N1
VREFB3N1
EPLL PLL5
VREFB4N0
VREFB4N1
Bank9
VREFB2N0
FPLL PLL1 FPLL PLL2
EP1AGX35DF780
VREFB1N1
VREFB1N0
VREFB8N0 VERFB8N1
Bank10 EPLL PLL6
VREFB7N0
VREFB7N1
Notes: This view silicon die. flip chip packages, mounted upside-down package; therefore, obtain package view, flip this diagram vertical axis. This only pictorial representation provide idea placement device. Refer list Quartus® software exact locations.
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Bank Diagram
Page
VREFB3N0 VREFB2N2
VREFB3N1
VREFB3N2
EPLL PLL5
VREFB4N0
VREFB4N1
VREFB4N2
Bank9
VREFB2N0
VREFB2N1
FPLL PLL1 FPLL PLL2
EP1AGX35CF484
VREFB8N0 VREFB8N1 VREFB8N2
VREFB1N1 VREFB1N0
VREFB1N2
Bank10 EPLL PLL6
VREFB7N0
VREFB7N1 VREFB7N2
Notes: This view silicon die. flip chip packages mounted upside-down package; therefore, obtain package view, flip this diagram vertical axis. 2.This only pictorial representation idea placement device. Refer list Quartus software exact locations
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Bank Diagram
Page
Information ArriaGX EP1AGX35C/D Device Version
Version Date 6/22/2007 7/27/2007 Changes Made Initial release. Added F484 package.
PT-EP1AGX35C/D-1.1 Copyright 2007 Altera Corp.
Revision History
Page
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