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Stratix Development Board
This data sheet describes features technical details StratixPCI development board. Slightly different versions board included following development kits: Development Kit, Stratix Edition (ordering code PCI-BOARD/S25). This data sheet refers board shipped with this Starter Board. High-Speed Development Kit, Stratix Professional Edition (ordering code PCI-BOARD/S60). This data sheet refers board shipped with this Professional Board.
This data sheet indicates whenever component functionality unique either Starter Board Professional Board.
Features
Stratix development board evaluation development platform high-speed interfaces including PCI, PCI-X, double data rate (DDR) SDRAM, 10/100 Ethernet, well high-speed differential interfaces (HSDI) such HyperTransportinterface, RapidIOinterface, System Packet Interface Level Phase (SPI-4.2), LVDS-based interface.
Components
Supports following members Stratix device family: EP1S25F1020 (Starter Board) EP1S60F1020 (Professional Board) Short-form universal (3.3 card 32-bit 64-bit 100-MHz PCI-X Revision mode 133-MHz PCI-X Revision mode (Starter Board) Memory 256-MByte PC333 SDRAM (SODIMM) 64-Mbit DL-type, boot-block flash FPGA device configuration User-selectable power-up flash memory EPM3256ATC144 device ByteBlasterII download cable
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DS-PCIDVBD-2.0
Stratix Development Board Data Sheet
Flexible clocking options Socketed 33-MHz system clock oscillator Socketed 100-MHz high-speed clock oscillator connector clock input
Expansion Interfaces
HSDI port 8-bit interface with Samtec connector Broadcom standard pin-out (Professional Board) HSDI port dual 8-bit single 16-bit interfaces with Samtec QTE/QSE connectors HyperTransport Consortium connector pin-out (Professional Board) Expansion Prototype Card (PROTO1) 10/100 Ethernet (RJ-45 connector) Serial RS-232 (DB-9 connector) Optrex connector Switches indicators Four user-definable pushbutton switches Eight-position user-definable switch bank Eight user-definable LEDs Flexible power options connector External power supply adaptor cable HSDI port connector (Professional Board) HSDI port connector (Professional Board)
Debugging Interfaces
Joint Test Action Group (JTAG) interface connector 8-bit Agilent/Samtec differential probe connector 32-bit Mictor probe connector
Handling Board
Observe following precautions when handling board. Static Discharge Precaution-The board damaged without proper anti-static handling; therefore, take anti-static precautions while handling Power Supply Precaution-The board special power supply circuitry that damaged more than power source applied board same time. Environmental Requirements-The board should stored between -40° 100° recommended operating temperature between
Altera Corporation
Stratix Development Board Data Sheet
General Description
Stratix development board allows designers evaluate, demonstrate, develop system-level designs with PCI, PCI-X, SDRAM, 10/100 Ethernet. Additionally, Professional Board allows development HyperTransport, RapidIO SPI-4.2 interfaces. Combined with intellectual property (IP) from Altera Altera® Megafunction Partners Program (AMPPSM) partners, users solve design problems that typically require custom solutions.
Components Interfaces
Figure shows view Stratix development board. Figure Stratix Development Board Components Interfaces
Configuration HSDI Port Connector (J13) Done (D4) System User Pushbutton Reset (PB3) User LEDs Switches (D3, User (PB2, PB4) D10, D12, Reset D14, D15) (PB1) Expansion Prototype User Card (PROTO1) Switch Bank (S2) (J2, SDRAM (J10)
External Power Connector (J18)
HSDI Port Connector (J8, Power LEDs (D11, D13, Agilent/Samtec Probe (J12) Optrex Interface (J5) Optrex Power (J19) Stratix Device VCCIO Jumper (J20)
Board Settings Switch Bank (S1) ByteBlaster Connector (J1) 10/100 Ethernet MAC/PHY (U11) RJ-45 Connector (RJ1) High-Speed Clock Oscillator (J15) RS-232 Activity LEDs (D1, System Clock Oscillator (J14) RS-232 Connector (J7) Configuration Controller (U1) Clock Input (J16) Flash Memory (U3) Back) Level Converters (U13 through U22) Back)
Mictor Probe Connector (J6) Stratix Device (U2)
Universal PCI-X Interface (J11)
JTAG Chain Jumper (J17)
Note Figure
These features only available Professional Board.
Altera Corporation
Stratix Development Board Data Sheet
Table describes major components board interfaces supports.
Table Stratix Development Board Components Interfaces (Part Type
FPGA
Component/ Interface
Stratix device
Board Reference
Description
Configurable Stratix device. Table page EP1S25F1020C5 device installed Starter Board. EP1S60F1020C6 device installed Professional Board.
connector level converters
through
Universal PCI-X interface. Table page Level converters 5.0-V compatibility. SDRAM connector (SODIMM) including preinstalled 256-MByte PC333 SDRAM memory module. 64-Mbit DL-family boot-block flash. Factory-programmed EPM3256ATC144-7 Stratix device configuration. JTAG test control well ByteBlaster configuration interface. JTAG chain jumper. Indicates Stratix configuration complete. 33.333-MHz system clock. 100-MHz high-speed reference clock. Clock input. Reset hardware reconfigure Stratix device. User-defined hardware reset. System settings configuration selection. Table page Table page Table page Table page Table page User configurable. User configurable.
Memory
connector SDRAM Flash
Installed Installed
Configuration
MAX® configuration controller JTAG Configuration done (D4)
Clock
System clock oscillator High-speed clock oscillator clock
Control
System reset pushbutton switch User reset pushbutton switch Board settings switch bank
User Settings
User pushbutton switches
PB2,
User switch bank
Altera Corporation
Stratix Development Board Data Sheet
Table Stratix Development Board Components Interfaces (Part Type
User Indicator
Component/ Interface
User LEDs
Board Reference
D10, D12, D14, TP18 User configurable.
Description
Power Power Indicators
Power connector +2.5-V power +1.5-V power +1.25-V power
External power supply adaptor. 2.5-V power supply indicator. 1.5-V power supply indicator. 1.25-V power supply indicator. 3.3-V power testpoint. 5.0-V power testpoint. 12.0-V power testpoint. -12.0-V power testpoint. Ground test point near SDRAM. Ground test point near clock input. Ground test point near connector.
Test point
+3.3 +5.0 +12.0 -12.0 Ground
Altera Corporation
Stratix Development Board Data Sheet
Table Stratix Development Board Components Interfaces (Part Type
High-Speed Interface Connector
Component/ Interface
HSDI port 8-bit high-speed interface connector
Board Reference
Description
This connector supports bidirectional 8-bit differential interface running maximum 840-Mbits/second. This port configured support HyperTransport interface support SPI-4.2, RapidIO, LVDS-based interfaces. This connector designed meet specifications required plug directly into Broadcom evaluation boards designed BCM1250 BCM112x microprocessors, including BCM91250 BCM91250E evaluation boards.
HSDI port 16-bit high-speed interface connector
(bottom)
These connectors support either eight-bit bidirectional differential interfaces 16-bit bidirectional differential interface running Mbits/second. This port operated support HyperTransport interface support SPI-4.2, RapidIO, other LVDS-based interfaces. This connector designed according connector specifications from HyperTransport Consortium. Table page description this connector capabilities.
Agilent/Samtec Probe
Agilent/Samtec differential probe interface Agilent logic analyzers. Interface Expansion Prototype Card (PROTO1). Optrex interface. +12.0-V output backlight inverter. 10/100 Ethernet MAC/PHY. RJ-45 connector, 25-MHz oscillator. RS-232 serial interface level shifter. connector. RS-232 transmitter active indicator. RS-232 receiver active indicator. Mictor probe interface Agilent logic analyzers.
Nios peripheral Expansion Prototype Card (PROTO1) Display Serial 10/100 Ethernet RS-232 RS-232 RS-232 Debug Note Table
U11, RJ1, OSC1 U10,
Mictor Probe
These features only available Professional Board.
Altera Corporation
Stratix Development Board Data Sheet
Functional Description
This section describes operation Stratix development board. Figure show block diagrams.
Figure Stratix Development Board Block Diagram
PCI, PCI-X 256-MByte SDRAM Memory HSDI Port Connector System Clock Oscillator High-Speed Clock Oscilllator Clock Connector Pushbutton Switches Agilent/Samtec Differential Probe Connector Settings Dipswitches Stratix Device User Dipswitches Jumpers Mictor Probe Debug Connector Display Connector RS-232 64-Mbit Flash Memory JTAG Connector Configuration Controller +2.5 +1.5 +1.25 Power LEDs Status LEDs User LEDs
HSDI Port Connectors
Expansion Prototype Card (PROTO1)
10/100 Ethernet
+3.3
Power Regulators
Note Figure
These features only available Professional Board.
Altera Corporation
Stratix Development Board Data Sheet
Stratix Device
Stratix device (U2), connected components board through appropriate on-chip interfaces board circuitry. device supports PCI, SDRAM memory, high-speed differential interfaces such HyperTransport RapidIO interfaces, SPI-4.2, other LVDS-based interfaces. Users program Stratix device implement their system logic. Table shows Stratix device that installed board.
Table Stratix Device Board
Professional Board
High-Speed Development Kit, Stratix Professional Edition (Ordering code: PCI-BOARD/S60) Development Kit, Stratix Edition (Ordering code: PCI-BOARD/S25)
Device
EP1S60F1020C6
Starter Board
EP1S25F1020C5
more information Stratix devices, refer Data Sheet section Stratix Device Handbook.
Stratix development board compatible with Altera pci_mt64, pci_mt32, pci_t64, pci_t32 MegaCore® functions. also used with PCI-X cores from AMPP partners other third-party vendors. Stratix device connector (J11) support revision PCI-X revision mode local standards. Table details. Table Support Application
PCI-X revision mode Note Table
PCI-X only available Starter Board. Professional Board runs maximum PCI-X applications.
Width (Bits)
Voltage
Speed (MHz)
100,
Altera Corporation
Stratix Development Board Data Sheet
Level Converters
through IDTQS3861Q level converters that convert between 5.0-V backplane signals Stratix 3.3-V signals.
Operating Mode
board settings switch bank (S1) sets operating mode speed shown Tables Table Operating Mode Selection Board Settings Switch Bank (S1) Position (PSEL) Setting
Operating Mode
PCI-X speed shown Table speed shown Table
Table Operating Speed Selection Board Settings Switch Switch Bank (S1) Position (PCIS) Setting
Operating Speed (MHz)
Table PCI-X Operating Speed Selection Board Settings Switch Bank (S1) Position (PCIXS) setting
Note Table
must ensure that your system does attempt operate Professional Board above MHz. Although PCI-X maximum operating frequency Professional Board MHz, this setting indicates operation, which supported Professional Board.
PCI-X Operating Speed (MHz)
Altera Corporation
Stratix Development Board Data Sheet
SDRAM Memory
Stratix development board tested with SDRAM Memory Controller MegaCore function version 1.2.0. 256-MByte SDRAM memory module installed 200-pin SODIMM connector (J10) connects banks Stratix device. Designers other memory modules provided they meet following requirements: 200-pin SODIMM SDRAM bits (non-ECC) bits (ECC)
Flash Memory
flash memory (U3) board connects Stratix device configuration controller. flash memory Advanced Micro Devices AM29DL640D 64-Mbit DL-family boot-block device that connects Stratix device configuration controller using LVTTL signals. flash memory capacity MBytes (67,108,864 bits). flash memory contains factory-programmed Stratix configuration image remaining space used store user-defined Stratix configuration images general-purpose user data such Nios boot code. controller design controls partitioning function flash memory device. Table page shows actual portioning flash memory device shipped from factory. flash memory operate either 16-bit modes. signal that driven configuration controller selects mode which flash memory device runs. default configuration controller shipped with board sets flash memory device operate 8-bit mode. When configuration controller configuring Stratix device, releases control flash memory Stratix device, which then perform write read operations flash memory. Reading, erasing, writing flash memory requires strict adherence required timing flash memory device. example, flash memory read access time flash write operations (erase program) take microseconds longer complete. Therefore, designer must monitor flash memory status register proper operation. review configuration controller PCI-to-DDR SDRAM reference designs sample Register Transfer Language (RTL) source code that demonstrates typical flash memory control operations.
Altera Corporation
Stratix Development Board Data Sheet
Configuration Controller
configuration controller (U1) Altera EPM3256ATC144 device. This device factory-programmed control Stratix device configuration, enable read/write access flash memory, select image used configure Stratix device. configuration controller also partitions flash memory device into functional areas, shown Table larger size configuration data EP1S60F1020 device, number user configuration images available Professional Board less than number available Starter Board. Table Flash Memory Device Partitions Address Range Starter Board Professional Board
User program area Stratix factory default configuration image
0x000000 0x1FFFFF User program area 0x200000 0x2FFFFF Stratix factory default configuration image 0x300000 0x3FFFFF Stratix user configuration image 0x400000 0x4FFFFF Stratix user configuration image 0x500000 0x5FFFFF Stratix user configuration image 0x600000 0x6FFFFF User program area 0x700000 0x7FFFFF User program area
Stratix user configuration image
select which configuration image cofiguration controller device uses configure Stratix device power setting positions board settings switch bank (S1). Table page details selection. configuration controller configures Stratix device when triggered following events: board powers system reset pushbutton (PB3) pressed Stratix device pulses CPLD_USER0 signal
load successful, configuration done (D4) illuminates.
Altera Corporation
Stratix Development Board Data Sheet
When configuration controller configuring Stratix device, releases control flash memory Stratix device. that point, Stratix device perform read write operations flash memory. Reading, erasing, writing flash memory requires flash memory controller designed into Stratix device that meets strict interface timing requirements flash memory device. Refer configuration controller PCI-to-DDR SDRAM memory reference designs sample designs that illustrate required circuitry flash memory interface. size flash memory device used board factory programmed configuration controller designed partition flash memory into several sectors that contain different Stratix device configuration images. board settings switch bank (S1) postions used select configuration image configuring Stratix device. Table more details.
Refer High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide more details flash memory configuration images general-purpose user data.
Table Configuration Image Selection Board Settings Switch Bank Switch Position (MPGM1) Setting
Configuration Image Starter Board
Factory-programmed image User image User image User image
Switch Position (MPGM0) Setting
Professional Board
Factory-programmed image User image Factory-programmed image User image
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Stratix Development Board Data Sheet
Clocks Clock Distribution
Stratix development board multiple clock sources, with most clocks driven directly Stratix device. Using fast enhanced PLLs integrated within Stratix device, designer significant flexibility achieve appropriate clock configuration prototyping.
Clock Sources
Stratix development board three on-board oscillators, connector, several application-specific clock sources located various expansion connectors. Table shows clock sources board.
Refer Using General-Purpose PLLs Stratix Devices chapter Stratix Device Handbook more information. (Part Source Destination
Stratix device (U2.AM15)
Table Stratix Input Clocks Signal Name
PCI_CLK CLK_OSC_A
Primary Used Notes (1),
PLL12
Connector (J11.B16) through level shifter (U14.13 U14.11) Socketed 33.333-MHz oscillator (J14.5)
Stratix device (U2.A19), PLL5 configuration controller (U1.128), Altera expansion prototype connector (PROTO1) (J4.9) Stratix device (U2.C19) Stratix device (U2.T29 U2.AK15) Stratix device (U2.D15) Stratix device (U2.AB4) Stratix device (U2.T6) Stratix device (U2.T27) Stratix device (U2.U3) Stratix device (U2.U4) PLL2, PLL7 PLL5 PLL1, PLL7, PLL12 PLL11 PLL9 PLL4, PLL10 PLL1 PLL3, PLL9
CLK_OSC_B CLK_SMA
Socketed 100-MHz oscillator (J15.5) Clock Input Connector (J16.1)
CLK_FROM_SCRUZ Expansion Prototype Card (PROTO1) (J4.13) B6_REF60_CLK B6_REF25_CLK B1_REF_CLK_IN B6_RX_CLKn B6_RX_CLKp B1A_RX_CLKn B1A_RX_CLKp HSDI port Connector (J13.10) HSDI port Connector (J13.10) HSDI port Connectors (J9.8, J8.153) HSDI port Connector (J13.63) HSDI port Connector (J13.65)
HSDI port Connectors (J9.46, J8.115) Stratix device (U2.U32) HSDI port Connectors (J9.44, J8.117) Stratix device (U2.U31)
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Stratix Development Board Data Sheet
Table Stratix Input Clocks Signal Name
B1B_RX_CLKn B1B_RX_CLKp DDR_CLK_FBIN CLK_25MHZ
(Part Source Destination Primary Used Notes (1),
PLL8 PLL5
HSDI port Connectors (J9.49, J8.112) Stratix device (U2.AB29) HSDI port Connectors (J9.47, J8.114) Stratix device (U2.AB28) Stratix device (D18) On-Board 25-MHz 10/100 Ethernet Oscillator (OSC1.4)) Stratix device (U2.D17) Ethernet MAC/PHY device (U11.127)
Note:
global clock input feed Stratix high-speed PLLs directly. This table shows direct connections does show connection global clock networks. PLL7 through PLL12 available EP1S25 device. Therefore, they only available Professional Board. different PLLs within Stratix device, designer drive CLK_OSC_A signal different input clock pins Stratix device installing different resistors. value shown this table factory default setting. page board schematics complete details various options available board. different PLLs within Stratix device, designer drive CLK_OSC_B signal different input clock pins Stratix device installing different resistors. value shown this table factory default setting. page board schematics complete details various options available board.
Clock Input Requirements
clock input CLK_SMA provided external signal source through connector J16. signal source cable with LVTTL-type signal (square-wave, with voltage swing from +3.3 maximum frequency this input MHz.
Stratix Output Clocks
Table lists Stratix output clocks their distribution board. Table Stratix Output Clocks (Part Signal Name
DDR_CLK0n DDR_CLK0p DDR_CLK1n DDR_CLK1p DDR_CLK2n DDR_CLK2p DDR_CLK_FBOUT CLK_TO_SCRUZ
Stratix Source
U2.A16 U2.B16 U2.A17 U2.B17 U2.A18 U2.B18 U2.D18 U2.AL16
Stratix
PLL5 PLL5 PLL5 PLL5 PLL5 PLL5 PLL5 PLL6
Destination
SDRAM Memory Connector (J10.37) SDRAM Memory Connector (J10.35) SDRAM Memory Connector (J10.158) SDRAM Memory Connector (J10.160) SDRAM Memory Connector (J10.91) SDRAM Memory Connector (J10.89) Stratix device (U2.D17) Expansion Prototype Card (PROTO1) (J4.11)
Altera Corporation
Stratix Development Board Data Sheet
Table Stratix Output Clocks (Part
CLK_TO_MAX_A B1_REF_CLK_OUT B1A_TX_CLKn B1A_TX_CLKp B1B_TX_CLKn B1B_TX_CLKp B6_TX_CLKn B6_TX_CLKp U2.AJ17 U2.AJ16 U2.V23 U2.V24 U2.AA26 U2.AA27 U2.Y5 U2.Y6 PLL6 PLL6 Configuration Controller (U1.125) HSDI port Connector (J9.153, J8.8) HSDI port Connector (J9.115, J8.46) HSDI port Connector (J9.117, J8.44) HSDI port Connector (J9.112, J8.49) HSDI port Connector (J9.114, J8.47) HSDI port Connector (J13.58) HSDI port Connector (J13.56)
Power
board special power supply circuitry that damaged more than power source applied board same time.
Stratix development board powered from following sources: connector supplies +3.3, +5.0, +12.0, -12.0 Power connector supplies +3.3, +5.0, +12.0, -12.0 from external power adaptor cable plugged into optional power supply. HSDI port connector supplies +3.3 HSDI port connector supplies +3.3
+2.5-, +1.5-, +1.25-V power LEDs require -12.0-V supply illuminate. These LEDs only illuminate when connector power connector supplies power board. display installed requires +5.0 +12.0 operate. display only operates when connector power connector supplies power board.
+2.5-V Regulators
board contains voltage regulators that generate +2.5 from +3.3 power SDRAM memory HSDI interfaces. voltage regulators operate parallel supply current required +2.5 supply. Amplifier equalizes current flowing through monitoring matching current flowing through resistors R15. Figure more details.
Altera Corporation
Stratix Development Board Data Sheet
Figure 2.5-V Regulator
+3.3 Voltage Regulator VOUT Voltage Regulator
+2.5
VREF Amplifier
+1.5-V Regulator
Linear regulator generates +1.5 Stratix device from +3.3
+1.25-V Regulator
Linear regulator generates +1.25 SDRAM memory termination reference voltage.
External Power Adaptor Receptacle
receptacle power from standard power supply external power adapter cable. board settings switch bank (S1) enables external power supply, shown Table
Table External Power Supply Enable Board Settings Switch Bank (S1) Position (PWR)
Description
Disable external power supply. Enable external power supply.
Altera Corporation
Stratix Development Board Data Sheet
Stratix Device VCCIO Jumper
selects VCCIO power banks Stratix device board, which turn sets operating voltage HSDI port HSDI port respectively. Because Starter Board does come with HSDI port HSDI port jumper does serve actual function. However, shunts must connected that Bank Stratix device powered ensure proper operation Stratix device. jumpers shown Table Table Stratix Device Jumper Setting Shunt Connects
pins pins pins pins
Bank
Voltage
Description
HSDI port HyperTransport interface. Factory-default setting. HSDI port SPI-4.2 RapidIO interfaces. HSDI port HyperTransport interface. Factory-default setting. HSDI port SPI-4.2 RapidIO interfaces.
Test Points
Table shows power test points. Table Power Supply Test Points Signal Name
3.3V 5.0V +12V -12V
Board Reference
3.3V 5.0V +12V -12V
Reference Designator
TP18 3.3-V power. 5.0-V power. +12.0-V power. -12.0-V power.
Description
Ground, near connector. Ground, near SDRAM memory. Ground, near clock input.
Expansion Interface Power Sourcing Capabilities
Table page shows power sourcing capability HSDI port interface when development board used host board.
Altera Corporation
Stratix Development Board Data Sheet
Table page shows power sourcing capability Expansion Prototype Card (PROTO1) interface.
LEDs
board power indication LEDs, status LEDs, user LEDs.
Power LEDs
Table shows power indication LEDs. power indication LEDs require -12.0-V supply illuminate. These LEDs only illuminate when connector power connector supplies power board.
Table Power LEDs Board Reference
2.5V 1.5V 1.25V
Reference Designator
Color
Blue Blue Blue
Description
2.5-V power 1.5-V power 1.25-V power
Status LEDs
Table shows status LEDs. Table Status LEDs Board Reference
CONF DONE
Reference Designator
Color
Description
Green Stratix device been configured successfully. RS-232 transmission active. RS-232 receive active.
Altera Corporation
Stratix Development Board Data Sheet
User LEDs
D10, D12, D14, user LEDs, shown Table "User LEDs" page instructions using LEDs. Table User LEDs User LEDs
Reference Designator
Color
Description
User defined. User defined. User defined. User defined. User defined. User defined. User defined. User defined.
Board Settings Switch Bank
Table describes board settings switch bank (S1). Table Board Settings Switch Bank Board Reference
PSEL PCIXS PCIS RUnLU MSEL2 MPGM1 MPGM0
Board Settings switch
Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position
Factory Default Setting
Reserved. Reserved.
Description
External power supply enable. Table page Select speed mode. Table page Table page Table page
Stratix configuration image selection. Select flash memory block used configure Stratix device. Table page
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Stratix Development Board Data Sheet
Pushbutton Switches
Table describes pushbutton switches board. Table Pushbutton Switches Board Reference
RESET
Reference Designator
Description
Resets configuration controller configures Stratix device. Resets Expansion Prototype Card (PROTO1), installed. User defined. User defined. User defined.
USER RESET USER_PB1 USER_PB2
User Switch Bank
Table describes user switch bank (S2). "User Switch Bank" page signal connections. Table User Switch Bank User Switch (S2)
Positions through
Description
User defined. These switches directly connected Stratix device.
Expansion Interfaces
Stratix development board includes following interfaces: HSDI port HSDI port Expansion Prototype Card (PROTO1) Interface RS-232 Serial Interface 10/100 Ethernet Display Interface
HSDI port HSDI port interfaces only available Professional Board.
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Stratix Development Board Data Sheet
HSDI Port Interface
HSDI port interface only available Professional Board.
Bank Stratix device contains 8-bit HyperTransport-capable port wired connector that mates with several Broadcom reference boards. connector allows Stratix development board connect other boards with Broadcom-type HyperTransport connector. Compatible boards include: Broadcom BCM91250A evaluation board BCM1250 Broadcom BCM91250E evaluation board BCM1250 Broadcom BCM91125E evaluation board BCM1125/BCM1125H second Stratix development board optional, custom interface cable
Standard
Jumper allows HSDI port operate HyperTransport interface signaling standards such SPI-4.2 RapidIO interfaces. Table shows jumper settings port standard. Table HSDI Port Standard Jumper (J20) Standard
HyperTransport interface SPI-4.2 RapidIO interfaces
Voltage
Shunt Connects
J20.3 J20.5 J20.1 J20.3
HSDI port uses discrete differential receive termination resistors required HyperTransport, SPI-4.2, RapidIO interfaces.
Reference Clock
Stratix device U2.AB4 receives B6_REF_CLK from HSDI port connector J13. This clock connects PLL9.
Optional HSDI Port Interface Cable
optional HSDI port interface cable available from Precision Interconnect (www.precisionint.com). configuration code 023850120015NR20.
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Stratix Development Board Data Sheet
HSDI Port Interface
HSDI port interface only available Professional Board.
Bank Stratix device connected HyperTransport connectors specified HyperTransport Consortium. This bank supports independent bidirectional 8-bit differential interfaces bidirectional 16-bit differential interface. used HyperTransport SPI-4.2, RapidIO, other LVDS-based interfaces. allow Stratix development board connect another board with HyperTransport connector. This interface operates Mbits/second double data rate (DDR) with clock. Compatible HyperTransport boards include second Stratix development board. Figure shows HSDI port interface. Figure HSDI Port Interface
Agilent/Samtec Differential Probe Connector
HSDI Port Link
Altera Corporation
HSDI Port Connector (Bottom)
HSDI Port Link
HSDI Port Connector (Top)
Stratix Bank
Stratix Development Board Data Sheet
16-Bit Operation
HSDI port interface contains 8-bit links, which operated 16-bit port. Although Stratix device used either host slave applications, choice pins layout used board limits options this port subset applications supported Stratix device. When using HSDI port connect another board, consider following items: link with common transmit receive clocks must connect link with separate transmit receive clocks. host application must allow generation transmit clock using separate than used receive clock. slave application either common separate PLL. HSDI port link operate with common transmit receive clocks independent common receive clocks. HSDI port link must operate with common transmit receive clocks; therefore, cannot used host board.
Table shows supported interfaces with Stratix development boards operated host slave boards. Table HSDI Port Supported Interfaces Interface
16-bit 8-bit (link 8-bit (link
Host
supported Supported supported
Slave
Supported Supported Supported
HyperTransport Chains
HyperTransport specification defines board types: Host Tunnel End-chain (cave)
Stratix development board operates host cave board determined application. Tunnel boards have least independent HyperTransport interfaces conduits between hosts, caves, additional tunnels.
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Stratix Development Board Data Sheet
Operation with Stratix Development Boards
Figure shows Stratix development boards connected HyperTransport host/cave configuration. cave board's bottomside connector location inserted into host board's top-side connector cave board rotated 180° with respect host board. Figure HyperTransport Host/Cave Configuration
Power
Table shows power sourcing capability HSDI port interface tunnel cave board when Stratix development board used host board. apply power cave board from connector external power connector both boards will damaged.
Table HSDI Port Host Board Power Sourcing Capability Voltage
Maximum Source Current
Altera Corporation
Stratix Development Board Data Sheet
JTAG Chain
JTAG chain made pass through HSDI port connector. Refer Table page instructions setting JTAG chain bypass jumper.
Standard
Jumper plug allows HSDI port interface operate either HyperTransport applications signaling standards such SPI-4.2 RapidIO interfaces. Table shows jumper settings. Table HSDI Port Interface Signal Standard Jumper (J20) Standard
HyperTransport SPI-4.2, RapidIO
Voltage
Shunt Connects
J20.4 J20.6 J20.2 J20.4
HSDI port interface uses discrete differential receive termination resistors required HyperTransport interface.
Agilent/Samtec Differential Probe Interface
Agilent/Samtec differential probe interface allows user monitor port link receive signals with high-speed test equipment.
Expansion Prototype Card (PROTO1) Interface
through allow Stratix development board accept optional boards with Expansion Prototype Card (PROTO1) interface. Compatible boards include Altera Nios Ethernet Development (EDK) daughter card. Additionally, these connectors used general purpose debugging expansion interface with pins LVTTL signals. Table shows maximum current available Expansion Prototype Card (PROTO1) interface. Table Maximum Allowed Current Draw Expansion Prototype Card (PROTO1) Voltage
12.0
Maximum Current
Altera Corporation
Stratix Development Board Data Sheet
Refer Nios Development Board, Stratix Edition Data Sheet details about Expansion Prototype Card (PROTO1) interface.
10/100 Ethernet
SMSC LAN91C111 10/100 Ethernet MAC/Phy. RJ-45 connector with integrated magnetics activity LEDs.
RS-232 Serial Interface
DB-9 connector wired RS-232 serial device. shifts RS-232 signals LVTTL levels connection Stratix device.
Display Interface
allow Stratix development board accept optional display. Compatible displays include Optrex T-51382D064J-FW-P-AA display (not included with kit). Interface shares Stratix signals with Mictor probe debug interface. Only interfaces used time.
Debugging Interfaces
Stratix development board debugging interfaces described following sections.
JTAG
provides access JTAG chain Stratix development board. Figure shows JTAG chain. factory-default setting JTAG bypass jumper sets chain loop through configuration controller Stratix device. Figure JTAG Chain
JTAG Bypass Jumper JTAG Connector
Configuration Controller
Stratix Device
HyperTransport Connector
Altera Corporation
Stratix Development Board Data Sheet
JTAG Chain Jumper
Table shows JTAG chain jumper. Table JTAG Chain Jumper Shunt Connects
pins pins
Description
Factory-default setting.
Changing JTAG Chain
JTAG chain bypass jumper. JTAG chain changes when Stratix development boards connected HSDI port connector. Insert shunts according configuration shown Table Table JTAG Chain Bypass Jumper Number Boards Chain
(Standalone) (HyperTransport host/cave) Host Cave
Board Position
Shunt Connects
J17.1 J17.3 J17.1 J17.3 J17.3 J17.5
Shunt Connects
J17.4 J17.6 J17.2 J17.4 J17.2 J17.4
SignalTap Logic Analyzer
JTAG debug interface also used Altera's SignalTap logic analyzer.
Refer 280: Design Verification Using SignalTap Embedded Logic Analyzer description SignalTap logic analyzer.
Agilent/Samtec Differential Probe
Agilent/Samtec differential probe header that monitors port link receive signals. Compatible adaptors include Agilent Technologies E5379A differential probe adaptor.
Altera Corporation
Stratix Development Board Data Sheet
Mictor Probe
Mictor header that provides probing capability internal Stratix device signals. Mictor probe compatible with Agilent Technologies E5346A Probe Adapter with Agilent Technologies Logic Analyzers. Mictor Probe Debug Interface shares Stratix signals with Interface. Only interfaces used time.
SignalProbefeature used route internal Stratix signals need recompile Stratix design SignalProbe feature.
Using Board
Refer Technical Brief SignalProbe Compilation Enables Fast System Debugging with Quartus Software description SignalProbe feature. When power applied board, user LEDs flash. this time, Stratix device automatically configured and, upon successful configuration, configuration done (D4) illuminates. configure board with design, designer should perform following steps, which explained later this section. Apply power board. Configure Stratix device.
Apply Power
Power introduced following means: Installing board into universal slot Attaching board power supply with external power adaptor cable Attaching board independently powered board HSDI port Attaching board independently powered board HSDI port board special power supply circuitry that damaged more than power source applied board same time.
Altera Corporation
Stratix Development Board Data Sheet
Operating Board with External Power Supply
operate board with external power supply, perform following steps: Insert small 12-pin connector external power supply adapter cable into J18. Insert 20-pin connector into standard power supply. board settings switch bank (S1), switch position (PWR), position. Table page
Installing Standoffs Bench-top Operation
Stratix development board initially configured installation conventional slot. standoffs four screws included install board bench-top operation (Figure Figure Configuring Board Bench-top Operation
Standoff location (Step Optional standoff location (behind SODIMM module) External Power Connector (J18)
Standoff location (Step
Optional standoff location Standoff location (Step
Standoff location (Step
Altera Corporation
Stratix Development Board Data Sheet
Position board face with bracket left. Insert screw hole next Agilent/Samtec Probe connector (J12) fasten standoff screw. Insert screw through hole next HSDI port connector (J8) fasten standoff screw. Gently place board face down with bracket right. Remove screw adjacent RN4. Turn board face insert screw through same hole, fasten standoff screw. Gently place board face down with bracket right Remove lower screw/nut combination RS-232 connector (J7). Turn board face-up, place screw through same hole, fasten standoff screw.
optional increased stability, perform following steps: Remove upper screw/nut combination RS-232 connector. (J7). Turn board face-up, place screw through same hole, fasten standoff screw. Carefully remove SDRAM SODIMM module SODIMM socket. final standoff hole provided next release right side SODIMM socket.
Configuration JTAG Interface
After power applied Stratix development board, Stratix device configured. JTAG interface permits Quartus® software load Stratix device with user design through ByteBlaster cable. user design remains Stratix device until power removed from board. configure Stratix device using Quartus software ByteBlaster cable, perform following steps: Connect ByteBlaster cable Open Quartus SRAM Object File (.sof) that want load into device, which launches Quartus Programmer.
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Stratix Development Board Data Sheet
Select ByteBlaster hardware. Search "Changing Hardware Setup" Quartus Help instructions. mode JTAG. Click Start. board installed into computer's slot when configured ByteBlaster cable, computer system could lock this happens, reset computer. shutdown configuration will lost. Restart computer re-enumerate bus.
Upon successful configuration, configuration done (D4) illuminates.
Refer Quartus Help instructions ByteBlaster cable.
Configuration from Flash Memory
Stratix device volatile; therefore, must configured each time power applied board. Stratix development board non-volatile configuration scheme that automatically configures Stratix device with factory default design, selected, user design, after power applied. Upon power-up, configuration circuit, comprised EPM3256ATC144 device flash memory, configures Stratix device. board settings switch bank user configuration, circuit attempts load specified user design. load unsuccessful, configuration done (D4) does illuminate Stratix device configured. configuration circuit uses factory-programmed default design EPM3256ATC144 device. Using JTAG interface program EPM3256ATC144 device disable configuration circuit, requiring subsequent Stratix configurations performed with JTAG interface. factory-programmed default Stratix configuration image resides fixed location flash memory. Altering this image result unpredictable board operation upon power-up prevent configuration circuit from operating, thereby requiring subsequent Stratix configurations performed with JTAG interface.
Altera Corporation
Stratix Development Board Data Sheet
Factory Configuration
user LEDs blink CONF DONE illuminates when factory-programmed design loaded into Stratix device.
Refer Development Kit, Stratix Edition Getting Started User Guide High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide details factory-programmed design.
Configuration Data
configure board, perform following steps: Create (.hex) file your design. Refer Quartus Help instructions creating file.
Write contents file into flash memory. Development Kit, Stratix Edition Getting Started User Guide High-Speed Development Kit, Stratix Professional Edition Getting Started User Guide instructions. Select user configuration using board settings switch bank. Force device configure pressing system reset pushbutton (PB3).
Pin-Outs Signal Specifications
This section provides board's pin-out signal specifications.
PCI-X
3.3/5.0-V universal connector. through level converters that reduce 5.0-V backplane signals allowable 3.3-V ranges. Figure shows flow signals between connector Stratix device. Figure Level Converters
Connector Level Converters Stratix Banks
Table shows connection connector Stratix device. level converters shown.
Altera Corporation
Stratix Development Board Data Sheet
Table Signals (Part Signal
PCI_CLK PCI_RSTn PCI_LOCKn PCI_INTAn PCI_IDSEL PCI_REQn PCI_GNTn PCI_REQ64n PCI_ACK64n PCI_FRAMEn PCI_DEVSELn PCI_IRDYn PCI_TRDYn PCI_STOPn PCI_PAR PCI_PAR64 PCI_PERRn PCI_SERRn PCI_CBEn0 PCI_CBEn1 PCI_CBEn2 PCI_CBEn3 PCI_CBEn4 PCI_CBEn5 PCI_CBEn6 PCI_CBEn7 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9
Connector (J11) Stratix (U2)
AM15 (PLL12) AL19 AC12 AD12 AC18 AL15 AL10 AH13 AF10 AJ13 AK13 AL13 AM13 AE12 AJ12 AK12 AL12 AB11 AE11 AG11 AH11 AK11 AL11
Local Signal
LPCI_CLK LPCI_RSTn LPCI_LOCKn LPCI_INTAn LPCI_IDSEL LPCI_REQn LPCI_GNTn LPCI_REQ64n LPCI_ACK64n LPCI_FRAMEn LPCI_DEVSELn LPCI_IRDYn LPCI_TRDYn LPCI_STOPn LPCI_PAR LPCI_PAR64 LPCI_PERRn LPCI_SERRn LPCI_CBEn0 LPCI_CBEn1 LPCI_CBEn2 LPCI_CBEn3 LPCI_CBEn4 LPCI_CBEn5 LPCI_CBEn6 LPCI_CBEn7 LPCI_AD0 LPCI_AD1 LPCI_AD2 LPCI_AD3 LPCI_AD4 LPCI_AD5 LPCI_AD6 LPCI_AD7 LPCI_AD8 LPCI_AD9
Altera Corporation
Stratix Development Board Data Sheet
Table Signals (Part Signal
PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_AD32 PCI_AD33 PCI_AD34 PCI_AD35 PCI_AD36 PCI_AD37 PCI_AD38 PCI_AD39 PCI_AD40 PCI_AD41 PCI_AD42 PCI_AD43 PCI_AD44 PCI_AD45 PCI_AD46
Connector (J11) Stratix (U2)
AM11 AG10 AJ10 AK10 AK22 AL22 AM22 AJ21 AK21 AL21 AH20 AJ20 AK20 AL20 AM20 AB19 AD19 AA18 AH18
Local Signal
LPCI_AD10 LPCI_AD11 LPCI_AD12 LPCI_AD13 LPCI_AD14 LPCI_AD15 LPCI_AD16 LPCI_AD17 LPCI_AD18 LPCI_AD19 LPCI_AD20 LPCI_AD21 LPCI_AD22 LPCI_AD23 LPCI_AD24 LPCI_AD25 LPCI_AD26 LPCI_AD27 LPCI_AD28 LPCI_AD29 LPCI_AD30 LPCI_AD31 LPCI_AD32 LPCI_AD33 LPCI_AD34 LPCI_AD35 LPCI_AD36 LPCI_AD37 LPCI_AD38 LPCI_AD39 LPCI_AD40 LPCI_AD41 LPCI_AD42 LPCI_AD43 LPCI_AD44 LPCI_AD45 LPCI_AD46
Altera Corporation
Stratix Development Board Data Sheet
Table Signals (Part Signal
PCI_AD47 PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 PCI_AD56 PCI_AD57 PCI_AD58 PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63
Connector (J11) Stratix (U2)
AJ18 AK18 AA15 AB15 AC15 AD15 AA14 AB14 AD14 AE14 AK14 AL14 AB13 AC13 AD13 AE13 AA12
Local Signal
LPCI_AD47 LPCI_AD48 LPCI_AD49 LPCI_AD50 LPCI_AD51 LPCI_AD52 LPCI_AD53 LPCI_AD54 LPCI_AD55 LPCI_AD56 LPCI_AD57 LPCI_AD58 LPCI_AD59 LPCI_AD60 LPCI_AD61 LPCI_AD62 LPCI_AD63
System Configuration
Table shows system configuration signals. Table System Configuration Signals Board Reference
PCIS PSEL PCIXS
Board Settings Switch Bank Positions (S1)
Switch Position Switch Position Switch Position
Signal
Connector (J11)
Ground Ground
Attribute
PCI_M66EN PCI_XCAP
10-K resistor ground
Altera Corporation
Stratix Development Board Data Sheet
SDRAM Memory
SDRAM memory module installed uses SSTL-2 signaling termination. reference voltage 1.25 supplied banks SSTL-2 receiver biasing. On-board resistors provide fly-by termination SDRAM memory connector pins. SODIMM connector SDRAM memory. Figure shows SDRAM memory termination connections. Figure SDRAM Memory Termination Connections
Stratix Device Banks SDRAM Memory Connector 256-MByte SDRAM Memory Module
Fly-By Termination Resistors
Table shows SDRAM memory fly-by termination connections. Table SDRAM Memory Fly-By Terminators (Part SDRAM Signal
DDR_CLKEN0 DDR_CLKEN1 DDR_CS0n DDR_CS1n DDR_RASn DDR_CASn DDR_WEn DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10
SDRAM Connector (J10)
Fly-By Terminator
RN29.13 RN29.14 RN12.16 RN12.15 RN33.11 RN33.9 RN33.10 RN33.15 RN33.16 RN31.9 RN31.10 RN31.11 RN31.12 RN31.13 RN31.14 RN31.15 RN31.16 RN33.14
Stratix (U2)
Altera Corporation
Stratix Development Board Data Sheet
Table SDRAM Memory Fly-By Terminators (Part SDRAM Signal
DDR_A11 DDR_A12 DDR_A13 DDR_BA0 DDR_BA1 DDR_BA2 DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 DDR_DQS4 DDR_DQS5 DDR_DQS6 DDR_DQS7 DDR_DQS8 DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 DDR_DM4 DDR_DM5 DDR_DM6 DDR_DM7 DDR_DM8 DDR_DP0 DDR_DP1 DDR_DP2 DDR_DP3 DDR_DP4 DDR_DP5 DDR_DP6 DDR_DP7 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3
SDRAM Connector (J10)
Fly-By Terminator
RN29.9 RN29.10 RN29.12 RN33.12 RN33.13 RN29.11 RN11.12 RN14.10 RN20.16 RN23.14 RN12.10 RN18.16 RN21.14 RN24.12 RN26.12 RN11.11 RN14.9 RN20.15 RN23.13 RN12.9 RN18.15 RN21.13 RN24.11 RN26.11 RN26.16 RN26.14 RN26.10 RN29.16 RN26.15 RN26.13 RN26.9 RN29.15 RN11.16 RN11.14 RN11.10 RN14.16
Stratix (U2)
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Stratix Development Board Data Sheet
Table SDRAM Memory Fly-By Terminators (Part SDRAM Signal
DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39
SDRAM Connector (J10)
Fly-By Terminator
RN11.15 RN11.13 RN11.9 RN14.15 RN14.14 RN14.12 RN17.16 RN17.14 RN14.13 RN14.11 RN17.15 RN17.13 RN17.12 RN17.10 RN20.14 RN20.12 RN17.11 RN17.9 RN20.13 RN20.11 RN20.10 RN23.16 RN23.12 RN23.10 RN20.9 RN23.15 RN23.11 RN23.9 RN12.14 RN12.12 RN15.16 RN15.14 RN12.13 RN12.11 RN15.15 RN15.13
Stratix (U2)
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Stratix Development Board Data Sheet
Table SDRAM Memory Fly-By Terminators (Part SDRAM Signal
DDR_DQ40 DDR_DQ41 DDR_DQ42 DDR_DQ43 DDR_DQ44 DDR_DQ45 DDR_DQ46 DDR_DQ47 DDR_DQ48 DDR_DQ49 DDR_DQ50 DDR_DQ51 DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR_DQ55 DDR_DQ56 DDR_DQ57 DDR_DQ58 DDR_DQ59 DDR_DQ60 DDR_DQ61 DDR_DQ62 DDR_DQ63
SDRAM Connector (J10)
Fly-By Terminator
RN15.12 RN15.10 RN18.14 RN18.12 RN15.11 RN15.9 RN18.13 RN18.11 RN18.10 RN21.16 RN21.12 RN21.10 RN18.9 RN21.15 RN21.11 RN21.9 RN24.16 RN24.14 RN24.10 RN27.16 RN24.15 RN24.13 RN24.9 RN27.15
Stratix (U2)
Clocks
Table shows SDRAM memory clocks. Table SDRAM Memory Clocks Clock Signal
DDR_CLK0N DDR_CLK0P DDR_CLK1N
SDRAM Memory (J10)
Stratix (U2)
Altera Corporation
Stratix Development Board Data Sheet
Table SDRAM Memory Clocks
DDR_CLK1P DDR_CLK2N DDR_CLK2P DDR_CLK_FBIN DDR_CLK_FBOUT B15,
Flash Memory
Table shows connections from flash memory Stratix device configuration controller. Table Flash Memory (Part Flash Memory Signal
FLASH_RESETn FLASH_CEn FLASH_WEn FLASH_WPn FLASH_OEn FLASH_RDY_BSYn FLASH_BYTEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15
Flash Memory (U3)
Stratix (U2)
AM27 AM28 AK26 AJ26 AK27 AL28 AJ27 AH26 AL27 AC20 AH19 AL26 AH24 AJ24 AJ25 AK25 AL25 AK24 AM25
Configuration Controller (U1)
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Stratix Development Board Data Sheet
Table Flash Memory (Part Flash Memory Signal
FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15
Flash Memory (U3)
Stratix (U2)
AM26 AJ22 AJ23 AL24 AH22 AM24 AB20 AF22 AD21 AG23 AC21 AD22 AB21 AA21
Configuration Controller (U1)
Configuration Controller
factory programmed EPM3256ATC144 device. Table shows connections between configuration controller, Stratix device, flash memory, which configure Stratix device. Table Configuration Controller Connections (Part Configuration Signal
DCLK EP1S_CONF_DONE EP1S_INIT_DONE
Configuration Controller (U1)
Stratix (U2)
AE15
Flash Memory (U3)
Altera Corporation
Stratix Development Board Data Sheet
Table Configuration Controller Connections (Part Configuration Signal
EP1S_nCONFIG EP1S_nSTATUS FLASH_RESETn FLASH_CEn FLASH_WEn FLASH_OEn FLASH_RDY_BSYn FLASH_BYTEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5
Configuration Controller (U1)
Stratix (U2)
AM27 AM28 AK26 AJ26 AK27 AL28 AJ27 AH26 AL27 AC20 AH19 AL26 AH24 AJ24 AJ25 AK25 AL25 AK24 AM25 AM26 AJ22 AJ23 AL24 AH22 AM24
Flash Memory (U3)
Altera Corporation
Stratix Development Board Data Sheet
Table Configuration Controller Connections (Part Configuration Signal
FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15
Configuration Controller (U1)
Stratix (U2)
AB20 AF22 AD21 AG23 AC21 AD22 AB21 AA21
Flash Memory (U3)
Table shows settings connections between configuration controller board settings switch bank. Table Board Settings Switch Bank (S1) Connections Board Reference
MPGM1 MPGM0
Board Settings Switch Bank Position
Switch Position Switch Position Switch Position
Signal
Configuration Controller (U1)
USE_MPGM MPGM1 MPGM0
Table shows user connections between configuration controller Stratix device. Table User Connections User Signal
CPLD_USER0 CPLD_USER1
Configuration Controller (U1)
Stratix (U2)
AG12
Altera Corporation
Stratix Development Board Data Sheet
User LEDs
Signals USER_LED0 through USER_LED7 driven Stratix device through configuration controller user LEDs shown Figure Table control signal logic illuminate LED. Figure User Drive Control Signals
Configuration Controller Stratix Device Stratix Control Signal
Configuration Controller Drive Signal
Table User LEDs Label Reference Designator Stratix Device Control Signal Stratix (U2) Configuration Controller Input (U1)
Configuration Controller Output (U1)
Configuration Controller Drive Signal
USER_LED_DRV0 USER_LED_DRV1 USER_LED_DRV2 USER_LED_DRV3 USER_LED_DRV4 USER_LED_DRV5 USER_LED_DRV6 USER_LED_DRV7
USER_LED0 USER_LED1 USER_LED2 USER_LED3 USER_LED4 USER_LED5 USER_LED6 USER_LED7
AK28 AH28 AK30 AJ28 AJ29 AK29 AL30 AL29
Altera Corporation
Stratix Development Board Data Sheet
Board Settings Switch Bank
Table describes signal names connections board settings switch bank (S1). Table Board Settings Switch Bank Board Reference
PSEL PCIXS PCIS RUnLU MSEL2 MPGM MPGM1 MPGM0
Board Settings Switch Bank Position
Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position
Signal
MAIN_SW DEV_CLRn PCI_XCAP PCI_M66EN RUnLU SMSEL2 USE_MPGM MPGM1 MPGM0
Destination
External power connector J18.6 Stratix (U2) AH14 connector J11.B38 connector J11.B49 Stratix (U2) AF14 Stratix (U2) AE19 configuration controller U1.36 configuration controller U1.34 configuration controller U1.35
User Switch Bank
Table shows signal names connections user switch bank (S2). Table User Swich Bank (S2) Board Reference
USER DIPSWITCH USER DIPSWITCH USER DIPSWITCH USER DIPSWITCH USER DIPSWITCH USER DIPSWITCH USER DIPSWITCH USER DIPSWITCH
User Switch
Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position Switch Position
Signal
USER_DIPSW0 USER_DIPSW1 USER_DIPSW2 USER_DIPSW3 USER_DIPSW4 USER_DIPSW5 USER_DIPSW6 USER_DIPSW7
Stratix (U2)
AD23 AE24 AE23 AF24 AC22 AG24 AB22 AF23
Altera Corporation
Stratix Development Board Data Sheet
Pushbutton Switches
Table shows signal names connections pushbutton switches. Table Pushbuttons Board Reference
RESET USER RESET USER_PB1 USER_PB2
PB3.2 PB1.2 PB2.2 PB4.2
Signal
SYS_RESETn USER_RESETn USER_PB1 USER_PB2
Stratix (U2)
AG13 AG22
External Power Header
Table shows connections J18, external power header. Table External Power Header Supply Voltage
+12.0 -12.0 MAIN_SW
External Power Header (J18)
HSDI Port Interface
HSDI port only available Professional Board. Table shows HSDI port interface. Table HSDI Port Interface (Part Signal
B6_TX_CLKn B6_TX_CLKp B6_TX_CTLn B6_TX_CTLp B6_TX_CADn0 B6_TX_CADp0
Connector (J13)
Stratix (U2)
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Stratix Development Board Data Sheet
Table HSDI Port Interface (Part Signal
B6_TX_CADn1 B6_TX_CADp1 B6_TX_CADn2 B6_TX_CADp2 B6_TX_CADn3 B6_TX_CADp3 B6_TX_CADn4 B6_TX_CADp4 B6_TX_CADn5 B6_TX_CADp5 B6_TX_CADn6 B6_TX_CADp6 B6_TX_CADn7 B6_TX_CADp7
Connector (J13)
Stratix (U2)
Table shows HSDI port interface. Table HSDI Port Interface (Part Signal
B6_RX_CLKn B6_RX_CLKp B6_RX_CTLn B6_RX_CTLp B6_RX_CADn0 B6_RX_CADp0 B6_RX_CADn1 B6_RX_CADp1 B6_RX_CADn2 B6_RX_CADp2 B6_RX_CADn3 B6_RX_CADp3 B6_RX_CADn4 B6_RX_CADp4 B6_RX_CADn5 B6_RX_CADp5
Connector (J13)
Stratix (U2)
Termination Resistor
R99.2 R99.1 R141.1 R141.2 R133.1 R133.2 R134.1 R134.2 R135.1 R135.2 R136.1 R136.2 R137.1 R137.2 R138.1 R138.2
Altera Corporation
Stratix Development Board Data Sheet
Table HSDI Port Interface (Part Signal
B6_RX_CADn6 B6_RX_CADp6 B6_RX_CADn7 B6_RX_CADp7
Connector (J13)
Stratix (U2)
Termination Resistor
R139.1 R139.2 R140.1 R140.2
Table shows HSDI port control interface. Table HSDI Port Control Interface Signal
B6_RESETn B6_REF_CLK B6_PWROK B6_IO_RESETn B6_IO_CSn B6_IO_WRn B6_IO_OEn B6_IO_RDYn B6_IO_AD24 B6_IO_AD25 B6_IO_AD26 B6_IO_AD27 B6_IO_AD28 B6_IO_AD29 B6_IO_AD30 B6_IO_AD31
Connector (J13)
Stratix (U2)
through resistor R254 through resistor R255
Altera Corporation
Stratix Development Board Data Sheet
HSDI Port Interface
HSDI port only available Professional Board. HSDI port connectors. Table shows HSDI port link connections. Table HSDI Port Link Interface Signal
B1A_TX_CLKn B1A_TX_CLKp B1A_TX_CTLn B1A_TX_CTLp B1A_TX_CADn0 B1A_TX_CADp0 B1A_TX_CADn1 B1A_TX_CADp1 B1A_TX_CADn2 B1A_TX_CADp2 B1A_TX_CADn3 B1A_TX_CADp3 B1A_TX_CADn4 B1A_TX_CADp4 B1A_TX_CADn5 B1A_TX_CADp5 B1A_TX_CADn6 B1A_TX_CADp6 B1A_TX_CADn7 B1A_TX_CADp7
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
AA24 AA25
Table shows HSDI port link connections. Table HSDI Port Link Interface (Part Signal
B1A_RX_CLKn B1A_RX_CLKp B1A_RX_CTLn B1A_RX_CTLp
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
Termination Resistor
R97.2 R97.1 R132.1 R132.2
Altera Corporation
Stratix Development Board Data Sheet
Table HSDI Port Link Interface (Part Signal
B1A_RX_CADn0 B1A_RX_CADp0 B1A_RX_CADn1 B1A_RX_CADp1 B1A_RX_CADn2 B1A_RX_CADp2 B1A_RX_CADn3 B1A_RX_CADp3 B1A_RX_CADn4 B1A_RX_CADp4 B1A_RX_CADn5 B1A_RX_CADp5 B1A_RX_CADn6 B1A_RX_CADp6 B1A_RX_CADn7 B1A_RX_CADp7
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
AA29 AA28 AB30 AB31 AA30 AA31
Termination Resistor
R116.1 R116.2 R118.1 R118.2 R120.1 R120.2 R122.1 R122.2 R124.1 R124.2 R126.1 R126.2 R128.1 R128.2 R130.1 R130.2
Table shows HSDI port link connections. Table HSDI Port Link Interface (Part Signal
B1B_TX_CLKn B1B_TX_CLKp B1B_TX_CTLn B1B_TX_CTLp B1B_TX_CADn0 B1B_TX_CADp0 B1B_TX_CADn1 B1B_TX_CADp1 B1B_TX_CADn2 B1B_TX_CADp2 B1B_TX_CADn3 B1B_TX_CADp3 B1B_TX_CADn4
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
AA26 AA27 AF28 AF27 AC26 AC25 AD25 AD26 AE26 AE25 AF25 AF26 AB26
Altera Corporation
Stratix Development Board Data Sheet
Table HSDI Port Link Interface (Part Signal
B1B_TX_CADp4 B1B_TX_CADn5 B1B_TX_CADp5 B1B_TX_CADn6 B1B_TX_CADp6 B1B_TX_CADn7 B1B_TX_CADp7
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
AB27 AC28 AC27 AD27 AD28 AE27 AE28
Table shows HSDI port link connections. Table HSDI Port Link Interface Signal
B1B_RX_CLKn B1B_RX_CLKp B1B_RX_CTLn B1B_RX_CTLp B1B_RX_CADn0 B1B_RX_CADp0 B1B_RX_CADn1 B1B_RX_CADp1 B1B_RX_CADn2 B1B_RX_CADp2 B1B_RX_CADn3 B1B_RX_CADp3 B1B_RX_CADn4 B1B_RX_CADp4 B1B_RX_CADn5 B1B_RX_CADp5 B1B_RX_CADn6 B1B_RX_CADp6 B1B_RX_CADn7 B1B_RX_CADp7
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
AB29 AB28 AC31 AB32 AG32 AG31 AF31 AF32 AE31 AE32 AD31 AD32 AF29 AF30 AE29 AE30 AD29 AD30 AC30 AC29
Termination Resistor
R98.2 R98.1 R131.1 R131.2 R115.1 R115.2 R117.1 R117.2 R119.1 R119.2 R121.1 R121.2 R123.1 R123.2 R125.1 R125.2 R127.1 R127.2 R129.1 R129.2
Altera Corporation
Stratix Development Board Data Sheet
Table shows HSDI port control connections. Table HSDI Port Control Interface Signal
B1_SYS_RESETn B1_RESETn B1_REF_CLK_IN B1_REF_CLK_OUT B1_PWROK B1_REQn B1_STOPn B1_SMBCLK B1_SMBDAT
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
Table shows HSDI port user signals. Table HSDI Port User Signals Signal
B1_USER_A0 B1_USER_A1 B1_USER_B0 B1_USER_B1 B1_USER_C0 B1_USER_C1 B1_USER_D0 B1_USER_D1 B1_USER_E0 B1_USER_E1
(Bottom) Connector (J9)
(Top) Connector (J8)
Stratix (U2)
Table shows HSDI port miscellaneous signals. Table HSDI Port Miscellaneous Signals (Part Signal
JTAG_SAMTEC_TDO
(Bottom) Connector (Top) Connector (J8) (J9)
Stratix (U2)
Altera Corporation
Stratix Development Board Data Sheet
Table HSDI Port Miscellaneous Signals (Part Signal
JTAG_STRATIX_TDO JTAG_TCK JTAG_TMS JTAG_TRST
(Bottom) Connector (Top) Connector (J8) (J9)
Stratix (U2)
through resistor
Expansion Prototype Card (PROTO1)
Table shows Expansion Prototype Card (PROTO1) interface. Table Expansion Prototype Card (PROTO1) Connectors (Part Signal
SYS_RESETN CLK_TO_SCRUZ CLK_OSC_A
Connector
J3.1 J4.11 J4.9
Stratix (U2)
AG13 AL16 (through resistor R101) (through resistor R111) (through resistor R112) AM19 (through resistor R106) P260 P251 R272
CLK_FROM_SCRUZ SCRUZ_CARDSELN SCRUZ_IO0 SCRUZ_IO1 SCRUZ_IO2 SCRUZ_IO3 SCRUZ_IO4 SCRUZ_IO5 SCRUZ_IO6 SCRUZ_IO7 SCRUZ_IO8 SCRUZ_IO9 SCRUZ_IO10 SCRUZ_IO11 SCRUZ_IO12 SCRUZ_IO13 SCRUZ_IO14 SCRUZ_IO15 SCRUZ_IO16
J4.13 J3.38 J3.3 J3.4 J3.5 J3.6 J3.7 J3.8 J3.9 J3.1 J3.1 J3.1 J3.13 J3.14 J3.15 J3.16 J3.17 J3.18 J3.21
Altera Corporation
Stratix Development Board Data Sheet
Table Expansion Prototype Card (PROTO1) Connectors (Part Signal
SCRUZ_IO17 SCRUZ_IO18 SCRUZ_IO19 SCRUZ_IO20 SCRUZ_IO21 SCRUZ_IO22 SCRUZ_IO23 SCRUZ_IO24 SCRUZ_IO25 SCRUZ_IO26 SCRUZ_IO27 SCRUZ_IO28 SCRUZ_IO29 SCRUZ_IO30 SCRUZ_IO31 SCRUZ_IO32 SCRUZ_IO33 SCRUZ_IO34 SCRUZ_IO35 SCRUZ_IO36 SCRUZ_IO37 SCRUZ_IO38 SCRUZ_IO39 Note Table
Only these resistors installed. R112 factory default.
Connector
J3.23 J3.25 J3.27 J3.28 J3.29 J3.31 J3.32 J3.33 J3.35 J3.36 J3.37 J3.39 J2.4 J2.5 J2.6 J2.7 J2.8 J2.9 J2.10 J2.11 J2.12 J2.13 J2.14
Stratix (U2)
RS-232
Table shows RS-232 Serial interface. Table RS-232 Serial Interface Connector Signal
DB9_TXD DB9_RXD DB9_RTS
Connector
J7.2 J7.3 J7.7
Level Shifter
U10.14 U10.13 U10.8
Level Shifter
U10.11 U10.12 U10.9
Stratix (U2)
AC14 AF12 AF13
Stratix Signal
RS232_TXD RS232_RXD RS232_RTS
Altera Corporation
Stratix Development Board Data Sheet
Table RS-232 Serial Interface Connector Signal
DB9_CTS
Connector
J7.8
Level Shifter
U10.7
Level Shifter
U10.10
Stratix (U2)
AM14
Stratix Signal
RS232_CTS
Header
Table shows header connections. Table Header Signal
MICTOR_CLKE MICTOR_DE0 MICTOR_DE1 MICTOR_DE2 MICTOR_DE3 MICTOR_DE4 MICTOR_DE5 MICTOR_DE6 MICTOR_DE7 MICTOR_DE8 MICTOR_DE9 MICTOR_DE10 MICTOR_DE11 MICTOR_DE12 MICTOR_DE13 MICTOR_DE14 MICTOR_DE15 MICTOR_DO0 MICTOR_DO1 MICTOR_DO2 MICTOR_DO3 MICTOR_DO4 MICTOR_DO5 MICTOR_DO6
Connector (J5)
Stratix (U2)
Altera Corporation
Stratix Development Board Data Sheet
JTAG
Table shows connections JTAG header. Table JTAG JTAG Signal
JTAG_TCK JTAG_CONN_TDO JTAG_CONN_TDI JTAG_TMS 3.3V
JTAG Connector (J1)
Agilent/Samtec Differential Probe
Table shows connections from HSDI port link receive signals Agilent/Samtec differential probe. Table Agilent/Samtec Differential Probe (Part Probe Signal
SAMTEC_RX_CLKn SAMTEC_RX_CLKp SAMTEC_RX_CTLn SAMTEC_RX_CTLp SAMTEC_RX_CADn0 SAMTEC_RX_CADp0 SAMTEC_RX_CADn1 SAMTEC_RX_CADp1 SAMTEC_RX_CADn2 SAMTEC_RX_CADp2 SAMTEC_RX_CADn3 SAMTEC_RX_CADp3 SAMTEC_RX_CADn4 SAMTEC_RX_CADp4 SAMTEC_RX_CADn5 SAMTEC_RX_CADp5 SAMTEC_RX_CADn6 SAMTEC_RX_CADp6
(J12)
Termination Resistor
R95.1 R96.1 R93.1 R94.1 R77.1 R78.1 R79.1 R80.1 R81.1 R82.1 R83.1 R84.1 R85.1 R86.1 R87.1 R88.1 R89.1 R90.1
Isolation Resistor
R75.1 R76.1 R73.1 R74.1 R57.1 R58.1 R59.1 R60.1 R61.1 R62.1 R63.1 R64.1 R65.1 R66.1 R67.1 R68.1 R69.1 R70.1
Stratix (U2)
AA29 AA28 AB30 AB31 AA30 AA31
Signal
B1A_RX_CLKn B1A_RX_CLKp B1A_RX_CTLn B1A_RX_CTLp B1A_RX_CADn0 B1A_RX_CADp0 B1A_RX_CADn1 B1A_RX_CADp1 B1A_RX_CADn2 B1A_RX_CADp2 B1A_RX_CADn3 B1A_RX_CADp3 B1A_RX_CADn4 B1A_RX_CADp4 B1A_RX_CADn5 B1A_RX_CADp5 B1A_RX_CADn6 B1A_RX_CADp6
Altera Corporation
Stratix Development Board Data Sheet
Table Agilent/Samtec Differential Probe (Part Probe Signal
SAMTEC_RX_CADn7 SAMTEC_RX_CADp7
(J12)
Termination Resistor
R91.1 R92.1
Isolation Resistor
R71.1 R72.1
Stratix (U2)
Signal
B1A_RX_CADn7 B1A_RX_CADp7
Mictor Header
Table shows connections Mictor header. Table Mictor Header (Part Signal
MICTOR_CLKO MICTOR_CLKE MICTOR_DE0 MICTOR_DE1 MICTOR_DE2 MICTOR_DE3 MICTOR_DE4 MICTOR_DE5 MICTOR_DE6 MICTOR_DE7 MICTOR_DE8 MICTOR_DE9 MICTOR_DE10 MICTOR_DE11 MICTOR_DE12 MICTOR_DE13 MICTOR_DE14 MICTOR_DE15 MICTOR_DO0 MICTOR_DO1 MICTOR_DO2 MICTOR_DO3 MICTOR_DO4 MICTOR_DO5 MICTOR_DO6 MICTOR_DO7
Mictor Header (J6)
Stratix (U2)
Altera Corporation
Stratix Development Board Data Sheet
Table Mictor Header (Part Signal
MICTOR_DO8 MICTOR_DO9 MICTOR_DO10 MICTOR_DO11 MICTOR_DO12 MICTOR_DO13 MICTOR_DO14 MICTOR_DO15
Mictor Header (J6)
Stratix (U2)
Schematics
subsequent pages provide schematics Stratix development board.
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com
Copyright 2003 Altera Corporation. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation
NOTES:
Altera Stratix Schematic Symbol Breakdown: Bank1 HSDI Bank2 HSDI Bank3 GPIO/DDR/PCI Bank4 GPIO/DDR/PCI Bank5 HSDI Bank6 HSDI Bank7 GPIO/DDR/PCI Bank8 GPIO/DDR/PCI Configuration/GPIO Clocks/GPIO VCCINT/GND VCCIO/GND Board powered from following interfaces time: Edge Connector Power Connector Related Documents 100-0216200-01 Gerber Files 110-0216200-01 Design Files 120-0216200-01 Assembly Drawing 130-0216200-01 Drawing 140-0216200-01 Schematic 150-0216200-01 Film 160-0216200-01 170-0216200-01
Parts, Library Parts, Nets, 3967 Pins
DATE
12/02/2002 02/12/2003
PAGES
13-14, 16-18
DESCRIPTION
Changed first fabricated revision. Modified J8/J9 symbols chamfer, Changed symbol TX/RX naming, Pulled down LAN_ADSn LAN_LCLK, Labelled RS-232 RX/TX LEDs, Modified 2.5V Regulator Circuit, Changed B1/B6 VCCIO select fuses jumpers, Separated CONF_DONEn signal from CONF_DONE config signal, Changed C1/C2 47uF.
Stratix Package View
BANK VCCIO 2.5V
SDRAM DATA LANES SDRAM ADDRESS, PARITY BITS
BANK VCCIO 2.5V
SDRAM DATA LANES SDRAM ADDRESS, MASK BITS
PAGE BANK VCCIO 3.3V
DESCRIPTION Title, Notes, Revision History Primary Voltage Limit Switches Voltage Switch Bypass Resistors Stratix Bank LEDs SDRAM SO-DIMM DDR-SDRAM Terminations Stratix Bank Stratix Bank Bank HSDI Top/Bottom Connectors Bank Debug, Bank HSDI Connector Stratix Bank 10/100 Ethernet Interface Santa Cruz Card, RS-232, Header Clocking, JTAG Bypass Jumper Power CPLD, Flash, Board-Specific Switches Decoupling
BANK VCCIO 3.3V
MICTOR, HEADER PUSHBUTTONS SANTA CRUZ DAUGHTERCARD
10/100 MAC/PHY RS-232 SIGNALS
BANK VCCIO 2.5V -or- 3.3V
BANK VCCIO 2.5V -or- 3.3V
SAMTEC QTE-080 TOP/BOT CONNECTORS 8-BIT HIGH-SPEED PORTS
SAMTEC QTE-060 EDGE CONNECTOR 8-BIT HIGH-SPEED PORT
BANK VCCIO 3.3V
BANK VCCIO 3.3V
SIGNALS FLASH ADDRESS, DATA USER LEDS
Analog Ground Ground
Copyright 2003, Altera Corporation. Rights Reserved.
SIGNALS USER DIPSWITCH
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Date: Document Number
150-0216200-01
Wednesday, February 2003
Sheet
Notes:
PCI-XCAP PCI-X. grounded pullup here. 3.3Vauxin PCI2.2 unused board core. Pins power requirement strapping pins. strapped maximum power. M66EN selectable 66MHz DIPswitch PMEn connected. Board does support Power Management features.
Primary
3.3V
5.0V
-12V J11A
32-Bit Standard Connector
-12V GND1 +5V1 +5V2 INTBn INTDn PRSNT1n RESERVED1 PRSNT2n RESERVED2 GND2 GND3 REQn VCCIO1 AD(31) AD(29) GND4 AD(27) AD(25) +3.3V1 CBEn(3) AD(23) GND5 AD(21) AD(19) +3.3V2 AD(17) CBEn(2) GND6 IRDYn +3.3V3 DEVSELn PCIXCAP LOCKn PERRn +3.3V4 SERRn +3.3V5 CBEn(1) AD(14) GND7 AD(12) AD(10) M66EN AD(8) AD(7) +3.3V6 AD(5) AD(3) GND10 AD(1) VCCIO2 ACK64n +5V3 +5V4
PCI64_CONN
+12V
5.0V
3.3V
TRSTn +12V +5V5 INTAn INTCn +5V6 RESERVED3 VCCIO3 RESERVED4 RESERVED5 RSTn VCCIO4 GNTn GND11 PMEn AD(30) +3.3V7 AD(28) AD(26) GND12 AD(24) IDSEL +3.3V8 AD(22) AD(20) GND13 AD(18) AD(16) +3.3V9 FRAMEn GND14 TRDYn GND15 STOPn +3.3V10 RESERVED6 RESERVED7 GND16 AD(15) +3.3V11 AD(13) AD(11) GND17 AD(9) CBEn(0) +3.3V12 AD(6) AD(4) GND20 AD(2) AD(0) VCCIO5 REQ64n +5V7 +5V8
PCI_AD[63.0] PCI_CBEn[7.0] PCI_INTAn
64-bit Extensions
J11B PCI_RSTn PCI_GNTn PCI_AD63 PCI_AD61 PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCI_IDSEL PCI_AD22 PCI_AD20 PCI_AD18 PCI_AD16 PCI_FRAMEn PCI_TRDYn PCI_STOPn PCI_AD35 PCI_AD33 PCI_PAR PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9 PCI_CBEn0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_REQ64n PCI_XCAP C234 0.1uF C235 0.1uF PCI_M66EN PCI_AD59 PCI_AD57 PCI_AD55 PCI_AD53 PCI_AD51 PCI_AD49 PCI_AD47 PCI_AD45 PCI_AD43 PCI_AD41 PCI_AD39 PCI_AD37 PCI_CBEn6 PCI_CBEn4
3.3V Keyway PCI_CLK PCI_REQn PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 PCI_CBEn3 PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17 PCI_CBEn2 PCI_IRDYn PCI_DEVSELn PCI_XCAP PCI_LOCKn PCI_PERRn PCI_SERRn PCI_CBEn1 PCI_AD14
RESERVED8 GND21 CBEn(6) CBEn(4) GND22 AD(63) AD(61) VCCIO6 AD(59) AD(57) GND23 AD(55) AD(53) GND24 AD(51) AD(49) VCCIO7 AD(47) AD(45) GND25 AD(43) AD(41) GND26 AD(39) AD(37) VCCIO8 AD(35) AD(33) GND27 RESERVED9 RESERVED10 GND28
PCI64_CONN
GND29 CBEn(7) CBEn(5) VCCIO9 PAR64 AD(62) GND30 AD(60) AD(58) GND31 AD(56) AD(54) VCCIO10 AD(52) AD(50) GND32 AD(48) AD(46) GND33 AD(44) AD(42) VCCIO11 AD(40) AD(38) GND34 AD(36) AD(34) GND35 AD(32) RESERVED11 GND36 RESERVED12
PCI_CBEn7 PCI_CBEn5 PCI_PAR64 PCI_AD62 PCI_AD60 PCI_AD58 PCI_AD56 PCI_AD54 PCI_AD52 PCI_AD50 PCI_AD48 PCI_AD46 PCI_AD44 PCI_AD42 PCI_AD40 PCI_AD38 PCI_AD36 PCI_AD34 PCI_AD32
PCI_AD12 PCI_AD10 PCI_M66EN PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1 PCI_ACK64n
Keyway
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Date:
Sheet
Voltage Translation Switch Threshold (gate) Voltage
5.0V 4.3V_VCC MMSD701T1
Voltage Limit Switches
NOTE: Systems without power source must either: Remove these switches populate bypass resistor packs next page. (3.3V signalling only) Connect 4.3V acceptable voltage desired application (see manufacturer's datasheet specs).
PCI_AD[63.0] LPCI_AD[63.0] PCI_CBEn[7.0] LPCI_CBEn[7.0]
4.7K
BOTTOM
LPCI_AD19 LPCI_AD21 LPCI_AD23 LPCI_CBEn3 LPCI_AD25 LPCI_AD27 LPCI_AD29 LPCI_AD31 LPCI_REQn LPCI_CLK 4,15
4.3V_VCC PCI_AD19 PCI_AD21 PCI_AD23 PCI_CBEn3 PCI_AD25 PCI_AD27 PCI_AD29 PCI_AD31 PCI_REQn PCI_CLK LPCI_AD49 LPCI_AD51 LPCI_AD53 LPCI_AD55 LPCI_AD57 LPCI_AD59 LPCI_AD61 LPCI_AD63 LPCI_CBEn4 LPCI_CBEn6
4.3V_VCC PCI_AD49 PCI_AD51 PCI_AD53 PCI_AD55 PCI_AD57 PCI_AD59 PCI_AD61 PCI_AD63 PCI_CBEn4 PCI_CBEn6
LPCI_INTAn LPCI_RSTn LPCI_GNTn LPCI_AD30 LPCI_AD28 LPCI_AD26 LPCI_AD24 LPCI_IDSEL LPCI_AD22 LPCI_AD20
4.3V_VCC PCI_INTAn PCI_RSTn PCI_GNTn PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCI_IDSEL PCI_AD22 PCI_AD20
BOTTOM
LPCI_CBEn7 LPCI_CBEn5 LPCI_PAR64 LPCI_AD62 LPCI_AD60 LPCI_AD58 LPCI_AD56 LPCI_AD54 LPCI_AD52 LPCI_AD50
4.3V_VCC PCI_CBEn7 PCI_CBEn5 PCI_PAR64 PCI_AD62 PCI_AD60 PCI_AD58 PCI_AD56 PCI_AD54 PCI_AD52 PCI_AD50
QS3861_SO_2
QS3861_SO_2
QS3861_SO_2
BOTTOM
LPCI_AD12 LPCI_AD14 LPCI_CBEn1 LPCI_SERRn LPCI_PERRn LPCI_LOCKn LPCI_DEVSELn LPCI_IRDYn LPCI_CBEn2 LPCI_AD17
4.3V_VCC PCI_AD12 PCI_AD14 PCI_CBEn1 PCI_SERRn PCI_PERRn PCI_LOCKn PCI_DEVSELn PCI_IRDYn PCI_CBEn2 PCI_AD17
4.3V_VCC
LPCI_AD18 LPCI_AD16 LPCI_FRAMEn LPCI_TRDYn 4,15 LPCI_STOPn LPCI_PAR LPCI_AD15 LPCI_AD13 LPCI_AD11 LPCI_AD9
4.3V_VCC PCI_AD18 PCI_AD16 PCI_FRAMEn PCI_TRDYn PCI_STOPn PCI_PAR PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9
LPCI_AD33 LPCI_AD35 LPCI_AD37 LPCI_AD39 LPCI_AD41 LPCI_AD43 LPCI_AD45 LPCI_AD47
PCI_AD33 PCI_AD35 PCI_AD37 PCI_AD39 PCI_AD41 PCI_AD43 PCI_AD45 PCI_AD47
QS3861_SO_2
BOTTOM
QS3861_SO_2
QS3861_SO_2
QS3861_SO_2
LPCI_AD48 LPCI_AD46 LPCI_AD44 LPCI_AD42 LPCI_AD40 LPCI_AD38 LPCI_AD36 LPCI_AD34 LPCI_AD32
4.3V_VCC PCI_AD48 PCI_AD46 PCI_AD44 PCI_AD42 PCI_AD40 PCI_AD38 PCI_AD36 PCI_AD34 PCI_AD32
BOTTOM
4.3V_VCC PCI_ACK64n PCI_AD1 PCI_AD3 PCI_AD5 PCI_AD7 PCI_AD8 PCI_AD10
4.3V_VCC PCI_CBEn0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_REQ64n
LPCI_ACK64n 4,52 LPCI_AD1 LPCI_AD3 LPCI_AD5 LPCI_AD7 LPCI_AD8 LPCI_AD10
LPCI_AD6 LPCI_AD4 LPCI_AD2 LPCI_AD0 LPCI_REQ64n
LPCI_CBEn0
QS3861_SO_2
QS3861_SO_2
QS3861_SO_2
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
Copyright 2003, Altera Corporation. Rights Reserved.
150-0216000-01
Wednesday, February 2003 Sheet
Date:
NOTE: These resistor packs installed default. They ONLY installed when proceeding page's switches installed (mutually exclusive).
Voltage Switch Bypass Resistors
PCI_AD[63.0] LPCI_AD[63.0] PCI_CBEn[7.0] LPCI_CBEn[7.0]
RN36
RN38 LPCI_AD49 LPCI_AD51 LPCI_AD53 LPCI_AD55 LPCI_AD57 LPCI_AD59 LPCI_AD61 LPCI_AD63 LPCI_CBEn4 LPCI_CBEn6
LPCI_AD19 LPCI_AD21 LPCI_AD23 LPCI_CBEn3 LPCI_AD25
PCI_AD19 PCI_AD21 PCI_AD23 PCI_CBEn3 PCI_AD25 PCI_AD27 PCI_AD29 PCI_AD31 PCI_REQn PCI_CLK
BOTTOM
RN37 LPCI_INTAn LPCI_RSTn LPCI_GNTn LPCI_AD30 LPCI_AD28 LPCI_AD26 LPCI_AD24 LPCI_IDSEL LPCI_AD22 LPCI_AD20 RN40
PCI_AD49 PCI_AD51 PCI_AD53 PCI_AD55 PCI_AD57 PCI_AD59 PCI_AD61 PCI_AD63 PCI_CBEn4 PCI_CBEn6
LPCI_AD27 LPCI_AD29 LPCI_AD31 LPCI_REQn LPCI_CLK 3,15
RN41
RN39
PCI_INTAn PCI_RSTn PCI_GNTn PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCI_IDSEL PCI_AD22 PCI_AD20
BOTTOM
RN42 LPCI_CBEn7 LPCI_CBEn5 LPCI_PAR64 LPCI_AD62 LPCI_AD60 LPCI_AD58 LPCI_AD56 LPCI_AD54 LPCI_AD52 LPCI_AD50
RN45 LPCI_AD12 LPCI_AD14 LPCI_CBEn1 LPCI_SERRn LPCI_PERRn LPCI_LOCKn LPCI_DEVSELn LPCI_IRDYn LPCI_CBEn2 LPCI_AD17 RN49
RN43
BOTTOM
RN44 LPCI_AD18 LPCI_AD16 LPCI_FRAMEn LPCI_TRDYn 3,15 LPCI_STOPn LPCI_PAR LPCI_AD15 LPCI_AD13 LPCI_AD11 LPCI_AD9
PCI_CBEn7 PCI_CBEn5 PCI_PAR64 PCI_AD62 PCI_AD60
PCI_AD58 PCI_AD56 PCI_AD54 PCI_AD52 PCI_AD50
PCI_AD12 PCI_AD14 PCI_CBEn1 PCI_SERRn PCI_PERRn PCI_LOCKn PCI_DEVSELn PCI_IRDYn PCI_CBEn2 PCI_AD17
LPCI_AD33 LPCI_AD35 LPCI_AD37 LPCI_AD39 LPCI_AD41 LPCI_AD43 LPCI_AD45 LPCI_AD47
PCI_AD33 PCI_AD35 PCI_AD37 PCI_AD39 PCI_AD41 PCI_AD43 PCI_AD45 PCI_AD47
PCI_AD18 PCI_AD16 PCI_FRAMEn PCI_TRDYn PCI_STOPn PCI_PAR PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9
RN46
RN48
BOTTOM
RN50
RN52 LPCI_ACK64n 3,51 LPCI_AD1 LPCI_AD3 LPCI_AD5 LPCI_AD7 LPCI_AD8 LPCI_AD10 PCI_ACK64n PCI_AD1 PCI_AD3 PCI_AD5 PCI_AD7 PCI_AD8 PCI_AD10 LPCI_CBEn0
BOTTOM
RN51 LPCI_AD6 LPCI_AD4 LPCI_AD2 LPCI_AD0 LPCI_REQ64n
LPCI_AD48 LPCI_AD46 LPCI_AD44 LPCI_AD42 LPCI_AD40 PCI_CBEn0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_REQ64n LPCI_AD38 LPCI_AD36 LPCI_AD34 LPCI_AD32
PCI_AD48 PCI_AD46 PCI_AD44 PCI_AD42 PCI_AD40 PCI_AD38 PCI_AD36 PCI_AD34 PCI_AD32
RN53
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Date:
Sheet
BANK
(3.3V 3.3V LVTTL)
LPCI_AD31 LPCI_REQn LPCI_AD26 LPCI_AD27 LPCI_AD30 LPCI_INTAn CPLD_USER0 LPCI_GNTn LPCI_AD28 LPCI_CBEn3 LPCI_IDSEL LPCI_AD29 LPCI_AD21 USER_PB2 LPCI_AD20 LPCI_AD25 LPCI_AD24 LPCI_CBEn2 LPCI_AD22 LPCI_AD19 LPCI_AD23 LPCI_PERRn LPCI_AD18 LPCI_AD14 LPCI_LOCKn LPCI_AD17 LPCI_AD16 LPCI_AD7 LPCI_AD12 LPCI_DEVSELn LPCI_FRAMEn LPCI_AD13 LPCI_AD9 LPCI_AD8 LPCI_STOPn CPLD_CSn
Stratix Bank Bank LEDs
RS232_RXD RS232_CTS RS232_TXD RS232_RTS LPCI_AD42 LPCI_AD41 LPCI_AD40 LPCI_AD38 LPCI_AD37 LPCI_AD36 LPCI_AD35 LPCI_AD34 LPCI_AD39 LPCI_AD33 LPCI_AD32 FLASH_A21 FLASH_A20 FLASH_A19 FLASH_A18 FLASH_A17 FLASH_A16 FLASH_A15 FLASH_A14 FLASH_A13 FLASH_A12 FLASH_A11 FLASH_A10 FLASH_A9 FLASH_A8 FLASH_OEn FLASH_WEn FLASH_CEn FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 USER_LED7 USER_LED6 USER_LED5 USER_LED4 USER_LED3 USER_LED2 USER_LED1 USER_LED0
BANK
(3.3V 3.3V LVTTL)
LPCI_AD[63.0] LPCI_CBEn[7.0] FLASH_A[21.0] FLASH_D[15.0] FLASH_A6 FLASH_A7 LPCI_AD43 USER_LED[7.0] USER_LED_DRV[7.0]
AH11 AJ10 AK10 AL11 AK11 AL10 AJ11 AM11 AL12 AK12 AK13 AJ13 AH13 AM13 AL13 AJ12
DQ0B0 DQ0B1 DQ0B2 DQ0B3 DQ0B4 DQ0B5 DQ0B6 DQ0B7 DQS0B DQ1B0 DQ1B1 DQ1B2 DQ1B3 DQ1B4 DQ1B5 DQ1B6 DQ1B7 DQS1B DQ2B0 DQ2B1 DQ2B2 DQ2B3 DQ2B4 DQ2B5 DQ2B6 DQ2B7 DQS2B DQ3B0 DQ3B1 DQ3B2 DQ3B3 DQ3B4 DQ3B5 DQ3B6 DQ3B7 DQS3B DQ4B0 DQ4B1 DQ4B2 DQ4B3 DQ4B4 DQ4B5 DQ4B6 DQ4B7 DQS4B
EP1S40F1020
FCLK4 FCLK5 RDN7 RUP7 GPIO_B7_0 GPIO_B7_1 GPIO_B7_2 GPIO_B7_3 GPIO_B7_4 GPIO_B7_5 GPIO_B7_6 GPIO_B7_7 GPIO_B7_8 GPIO_B7_9 GPIO_B7_10 GPIO_B7_11 GPIO_B7_12 GPIO_B7_13 GPIO_B7_14 GPIO_B7_15 GPIO_B7_16 GPIO_B7_17 GPIO_B7_18 GPIO_B7_19 GPIO_B7_20 GPIO_B7_21 GPIO_B7_22 GPIO_B7_23 GPIO_B7_24 GPIO_B7_25 GPIO_B7_26 GPIO_B7_27 GPIO_B7_28 GPIO_B7_29 GPIO_B7_30 GPIO_B7_31 GPIO_B7_32 GPIO_B7_33 GPIO_B7_34 GPIO_B7_35 GPIO_B7_36 GPIO_B7_37 GPIO_B7_38
AF12 AM14 AC14 AF13 AE12 AC12 AA12 AD12 AB11 AE11 AF10 AG10 AG11 AD14 AB13 AG13 AC13 AE13 AD13 AG12 AA18 AB15 AA15 AD15 AC15 AK14 AC18 AL14 AB14 AA14 AE14 AA13 AB12 AC11 AD10 AD11 AE10 AF11
LPCI_AD0 LPCI_REQ64n LPCI_AD63 LPCI_ACK64n LPCI_AD4 LPCI_AD5 LPCI_CBEn0 LPCI_AD11 LPCI_AD6 LPCI_CBEn1 USER_PB1 LPCI_AD15 LPCI_PAR LPCI_SERRn LPCI_AD55 LPCI_AD59 SYS_RESETn LPCI_AD60 LPCI_AD62 LPCI_AD61 CPLD_USER1 LPCI_AD45 LPCI_AD50 LPCI_AD49 LPCI_AD52 LPCI_AD51 LPCI_AD57 LPCI_IRDYn LPCI_AD58 LPCI_AD54 LPCI_AD53 LPCI_AD56 (n/c (n/c (n/c (n/c (n/c (n/c (n/c 1S25) 1S25) 1S25) 1S25) 1S25) 1S25) 1S25)
AM20 AL20 AK20 AH20 AL21 AK21 AJ21 AM22 AJ20 AL22 AK22 AL23 AK23 AM24 AH22 AL24 AJ23 AJ22 AM26 AM25 AK24 AL25 AK25 AJ25 AJ24 AH24 AL26 AK26 AM28 AM27 AJ26 AK27 AL28 AJ27 AH26 AL27 AM29 AL29 AL30 AK29 AJ29 AJ28 AK30 AH28 AK28
DQ5B0 DQ5B1 DQ5B2 DQ5B3 DQ5B4 DQ5B5 DQ5B6 DQ5B7 DQS5B DQ6B0 DQ6B1 DQ6B2 DQ6B3 DQ6B4 DQ6B5 DQ6B6 DQ6B7 DQS6B DQ7B0 DQ7B1 DQ7B2 DQ7B3 DQ7B4 DQ7B5 DQ7B6 DQ7B7 DQS7B DQ8B0 DQ8B1 DQ8B2 DQ8B3 DQ8B4 DQ8B5 DQ8B6 DQ8B7 DQS8B DQ9B0 DQ9B1 DQ9B2 DQ9B3 DQ9B4 DQ9B5 DQ9B6 DQ9B7 DQS9B
EP1S40F1020
FCLK2 FCLK3 RDN8 RUP8 GPIO_B8_0 GPIO_B8_1 GPIO_B8_2 GPIO_B8_3 GPIO_B8_4 GPIO_B8_5 GPIO_B8_6 GPIO_B8_7 GPIO_B8_8 GPIO_B8_9 GPIO_B8_10 GPIO_B8_11 GPIO_B8_12 GPIO_B8_13 GPIO_B8_14 GPIO_B8_15 GPIO_B8_16 GPIO_B8_17 GPIO_B8_18 GPIO_B8_19 GPIO_B8_20 GPIO_B8_21 GPIO_B8_22 GPIO_B8_23 GPIO_B8_24 GPIO_B8_25 GPIO_B8_26 GPIO_B8_27 GPIO_B8_28 GPIO_B8_29 GPIO_B8_30
AF21 AE21 AC20 AH19 AB19 AD20 AG21 AG20 AE20 AD19 AJ18 AH18 AK18 AA21 AB21 AD22 AC21 AG23 AD21 AF22 AB20 AG22
16,17 AB24 16,17 AC24 AC23 AD24 AD23 AE24 AE23 AF24 AC22 AG24 AB22 AF23
LPCI_AD44 LPCI_AD47 LPCI_AD46 LPCI_AD48 FLASH_D15 FLASH_D14 FLASH_D13 FLASH_D12 FLASH_D11 FLASH_D10 FLASH_D9 FLASH_D8 USER_RESETn OVERTEMPn ALERTn SMB_CLK SMB_DATA USER_DIPSW0 USER_DIPSW1 USER_DIPSW2 USER_DIPSW3 USER_DIPSW4 USER_DIPSW5 USER_DIPSW6 USER_DIPSW7
8,14,17 8,17 8,17
SYS_RESETn USER_RESETn CPLD_USER[1.0] USER_PB[2.1]
LPCI_AD10 LPCI_AD3 LPCI_AD2 LPCI_CBEn5 LPCI_CBEn4 LPCI_PAR64 LPCI_CBEn7 LPCI_CBEn6 LPCI_AD1
AE22
(n/c 1S25)
USER_LED_DRV0 USER_LED_DRV1 USER_LED_DRV2 USER_LED_DRV3 USER_LED_DRV4 USER_LED_DRV5 USER_LED_DRV6 USER_LED_DRV7
3.3V USER_LED_RES0 RN34
POWER CONFIG LEDs
3.3V GREEN CONF_DONE_RESn
USER DIPSWITCH
USER_DIPSW0 USER_DIPSW1 USER_DIPSW2 USER_DIPSW3 USER_DIPSW4 USER_DIPSW5 USER_DIPSW6 USER_DIPSW7
EP1S_CONF_DONEn
USER_LED_RES1
USER_LED_RES2
CRC_ERRORn USER_LED_RES3
YELLOW BLUE BLUE BLUE
3.3V
CRC_ERROR_LED 1.25V VCC_1.25_LED 2.5V VCC_2.5_LED 1.5V VCC_1.5_LED RN35
TDA08H0SK1
USER LEDs
USER_LED_RES4
USER_LED_RES5
USER_LED_RES6 -12V USER_LED_RES7
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Date: Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Sheet
SDRAM SO-DIMM
DDR_DQ[63.0] 2.5V
2.5V J10B
DDR_BA[2.0] DDR_A[13.0]
DDR_DQ32 DDR_DQ33 2.5V 2.5V DDR_DQS4 DDR_DQ34 DDR_DQ35 DDR_DQ40 J10A SSTL2_VREF C227 0.1uF
DDR_DQ0 DDR_DQ1 DDR_DQS0 DDR_DQ2 DDR_DQ3 DDR_DQ8 DDR_DQ9 DDR_DQS1 DDR_DQ10 DDR_DQ11 DDR_CLK0p DDR_CLK0n
VREF1 VSS1 VDD1 DQS0 VSS3 VDD3 DQS1 VSS5 DQ10 DQ11 VDD5 CK0_n VSS8 DQ16 DQ17 VDD8 DQS2 DQ18 VSS10 DQ19 DQ24 VDD10 DQ25 DQS3 VSS12 DQ26 DQ27 VDD12 VSS14 DQS8 VDD14 VSS16 CK2_n VDD17 CKE1 VSS19 VDD19 A10_AP WE_n S0_n VSS34
VREF2 VSS2 VDD2 VSS4 DQ12 VDD4 DQ13 VSS6 DQ14 DQ15 VDD6 VDD7 VSS7 VSS9 DQ20 DQ21 VDD9 DQ22 VSS11 DQ23 DQ28 VDD11 DQ29 VSS13 DQ30 DQ31 VDD13 VSS15 VDD15 VSS17 VSS18 VDD16 VDD18 CKE0 VSS20 VDD20 RAS_n CAS_n S1_n VSS35
DDR_DQ41 DDR_DQS5 DDR_DQ4 DDR_DQ5 DDR_DM0 DDR_DQ6 DDR_DQ7 DDR_DQ12 DDR_DQ13 DDR_DM1 DDR_DQ14 DDR_DQ15 DDR_DQ48 DDR_DQ49 DDR_DQS6 DDR_DQ50 DDR_DQ51 DDR_DQ56 DDR_DQ57 DDR_DQS7 DDR_DQ58 DDR_DQ59 DDR_DQ20 DDR_DQ21 DDR_DM2 DDR_DQ22 DDR_DQ23 DDR_DQ28 DDR_DQ29 DDR_DM3 DDR_DQ30 DDR_DQ31 DDR_DP4 DDR_DP5 SSTL2_VREF DDR_DM8 DDR_DP6 DDR_DP7 SSTL2_VREF C231 0.1uF C232 0.1uF C233 0.1uF SPD_SDA SPD_SCL DDR_DQ42 DDR_DQ43
DDR_DQ16 DDR_DQ17 DDR_DQS2 DDR_DQ18 DDR_DQ19 DDR_DQ24 DDR_DQ25 DDR_DQS3 DDR_DQ26 DDR_DQ27 DDR_DP0 DDR_DP1 DDR_DQS8 DDR_DP2 DDR_DP3
DQ32 DQ33 VDD21 DQS4 DQ34 VSS23 DQ35 DQ40 VDD23 DQ41 DQS5 VSS25 DQ42 DQ43 VDD25 VDD27 VSS27 VSS28 DQ48 DQ49 VDD28 DQS6 DQ50 VSS30 DQ51 DQ56 VDD30 DQ57 DQS7 VSS32 DQ58 DQ59 VDD32 VDDSPD
DQ36 DQ37 VDD22 DQ38 VSS24 DQ39 DQ44 VDD24 DQ45 VSS26 DQ46 DQ47 VDD26 CK1_n VSS29 DQ52 DQ53 VDD29 DQ54 VSS31 DQ55 DQ60 VDD31 DQ61 VSS33 DQ62 DQ63 VDD33 NC10
DDR_DQ36 DDR_DQ37 DDR_DM4 DDR_DQ38 DDR_DQ39 DDR_DQ44 DDR_DQ45 DDR_DM5 DDR_DQ46 DDR_DQ47 DDR_CLK1n DDR_CLK1p DDR_DQ52 DDR_DQ53 DDR_DM6 DDR_DQ54 DDR_DQ55 DDR_DQ60 DDR_DQ61 DDR_DM7 DDR_DQ62 DDR_DQ63 SPD_A
DDR_DQS[8.0] DDR_DM[8.0] DDR_CLKEN[1.0] DDR_DP[7.0]
Byte Lane Byte Lane
2.5V
Byte Lane Byte Lane Byte Lane Byte Lane Byte Lane
SO_DIMM_200
Byte Lane Byte Lane EEPROM
1.25V
DDR_CLK2p DDR_CLK2n DDR_CLKEN1 DDR_A13 DDR_A12 DDR_A9 DDR_A7 DDR_A5 DDR_A3 DDR_A1 DDR_A10 DDR_BA0 DDR_WEn DDR_CS0n
PVIN VSENSE AVIN VREF VDDQ
LP2995M
C228 100uF Tantalum C229 100uF Tantalum
C230 100uF Tantalum
DDR_CLKEN0 DDR_BA2 DDR_A11 DDR_A8 DDR_A6 DDR_A4 DDR_A2 DDR_A0 DDR_BA1 DDR_RASn DDR_CASn DDR_CS1n
SSTL2 TERMINATION VOLTAGE REGULATOR
(1.5A 3.0A Peak)
SO_DIMM_200
Copyright 2003, Altera Corporation. Rights Reserved.
Address Control
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Date: Document Number
150-0216200-01
Wednesday, February 2003
Sheet
SDRAM TERMINATIONS
DDR_CS0n DDR_CS1n
FLY-BY TERMINATION RESISTORS
FLY-BY TERMINATION RESISTORS
1.25V
DDR_WEn DDR_CLKEN0
FLY-BY TERMINATION BYPASSING CAPS
1.25V RN11
1.25V CN1A
1.25V CN1B
1.25V CN1C
1.25V CN1D
CN2A
CN2B
CN2C
CN2D
CN3A
CN3B
CN3C
CN3D
RN14
CN4A
CN4B
CN4C
CN4D
CN5A
CN5B
CN5C
CN5D
RN17
CN6A
CN6B
CN6C
CN6D
CN7A
CN7B
CN7C
CN7D
RN20
CN8A
CN8B
CN8C
CN8D
CN9A
CN9B
CN9C
CN9D
RN23
CN10A
CN10B
CN10C
CN10D
CN11A
CN11B
CN11C
CN11D
RN26
CN12A
CN12B
CN12C
CN12D
CN13A
CN13B
CN13C
CN13D
RN29
CN14A
CN14B
CN14C
CN14D
CN15A
CN15B
CN15C
CN15D
RN31
RN33
NOTE: FOLLOWING 0.1uF BYPASS CAPS PLACED PARALLEL WITH EVERY OTHER PULL RESISTOR.
DDR_DQ6 DDR_DQ2 DDR_DM0 DDR_DQS0 DDR_DQ5 DDR_DQ1 DDR_DQ4 DDR_DQ0 DDR_DM1 DDR_DQS1 DDR_DQ13 DDR_DQ9 DDR_DQ12 DDR_DQ8 DDR_DQ7 DDR_DQ3 DDR_DQ21 DDR_DQ17 DDR_DQ20 DDR_DQ16 DDR_DQ15 DDR_DQ11 DDR_DQ14 DDR_DQ10 DDR_DQ28 DDR_DQ24 DDR_DQ23 DDR_DQ19 DDR_DQ22 DDR_DQ18 DDR_DM2 DDR_DQS2 DDR_DQ31 DDR_DQ27 DDR_DQ30 DDR_DQ26 DDR_DM3 DDR_DQS3 DDR_DQ29 DDR_DQ25 DDR_DP6 DDR_DP2 DDR_DM8 DDR_DQS8 DDR_DP5 DDR_DP1 DDR_DP4 DDR_DP0 DDR_A11 DDR_A12 DDR_BA2 DDR_A13 DDR_CLKEN0 DDR_CLKEN1 DDR_DP7 DDR_DP3 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_CASN DDR_WEn DDR_RASN DDR_BA0 DDR_BA1 DDR_A10 DDR_A0 DDR_A1
RN12
RN15
RN18
RN21
RN24
RN27
DDR_DM4 DDR_DQS4 DDR_DQ37 DDR_DQ33 DDR_DQ36 DDR_DQ32 DDR_CS1n DDR_CS0n DDR_DQ45 DDR_DQ41 DDR_DQ44 DDR_DQ40 DDR_DQ39 DDR_DQ35 DDR_DQ38 DDR_DQ34 DDR_DQ52 DDR_DQ48 DDR_DQ47 DDR_DQ43 DDR_DQ46 DDR_DQ42 DDR_DM5 DDR_DQS5 DDR_DQ55 DDR_DQ51 DDR_DQ54 DDR_DQ50 DDR_DM6 DDR_DQS6 DDR_DQ53 DDR_DQ49 DDR_DQ62 DDR_DQ58 DDR_DM7 DDR_DQS7 DDR_DQ61 DDR_DQ57 DDR_DQ60 DDR_DQ56
DDR_CLKEN1 DDR_RASn DDR_CASn DDR_BA[2.0] DDR_DM[8.0] DDR_A[13.0] DDR_DQS[8.0]
DDR_DP[7.0]
DDR_DQ[63.0]
DDR_DQ63 DDR_DQ59
NOTE: PULL RESISTORS MUST PLACED AFTER SODIMM (i.e. AFTER CONNECTOR) CLOSE POSSIBLE SODIMM.
NOTE: PLACE QUAD CAPACITOR NETWORK CLOSE POSSIBLE ROCTAL RESISTOR PACK.
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Date:
Sheet
BANK
(3.3V LVTTL)
Stratix Bank Bank Buttons
SCRUZ_IO[39.0] LAN_D[31.0] LAN_A[14.0] LAN_BEn[3.0]
BANK
(3.3V LVTTL)
(n/c 1S25) (n/c 1S25) LAN_D2 LAN_D3 LAN_D4 LAN_D5 LAN_D6 LAN_D7 LAN_D8 LAN_D9 LAN_D10 LAN_D11 LAN_D12 LAN_D13 LAN_D14 LAN_D15 LAN_D16 LAN_D17 LAN_D18 LAN_D19 LAN_D20 LAN_D21 LAN_D22 LAN_D23 LAN_D24 LAN_D25 LAN_D26 LAN_D27 LAN_D28 LAN_D29 LAN_D30 LAN_D31 B1_REQn B1_RESETn B1_SYS_RESETn B1_PWROK B1_STOPn B1_SMBDAT B1_SMBCLK LAN_D1 (n/c 1S25) (n/c 1S25) (n/c 1S25) (n/c 1S25) SCRUZ_IO0 SCRUZ_IO1 SCRUZ_IO2 MICTOR_DO15 MICTOR_DO14 MICTOR_DO13 MICTOR_DO12 MICTOR_DO11 MICTOR_DO10 MICTOR_DO9 MICTOR_DO8 MICTOR_DO7 MICTOR_DO6 MICTOR_DO5 MICTOR_DO4 MICTOR_DO3 MICTOR_DO2 MICTOR_DO1 MICTOR_DO0 MICTOR_DE15 MICTOR_DE14 MICTOR_DE13 MICTOR_DE12 MICTOR_DE11 MICTOR_DE10 MICTOR_DE9 MICTOR_DE8 MICTOR_DE7 MICTOR_DE6 MICTOR_DE5 MICTOR_DE4 MICTOR_DE3 MICTOR_DE2 MICTOR_DE1 MICTOR_DE0 MICTOR_CLKO MICTOR_CLKE (n/c (n/c (n/c (n/c (n/c (n/c 1S25) 1S25) 1S25) 1S25) 1S25) 1S25)
(n/c (n/c (n/c (n/c (n/c (n/c LAN_D0 LAN_BEn3 LAN_BEn2 LAN_BEn1 LAN_BEn0 LAN_A0 LAN_A1 LAN_A2 LAN_A3 LAN_A4 LAN_A5 LAN_A6 LAN_A7 LAN_A8
1S25) 1S25) 1S25) 1S25) 1S25) 1S25)
DIFFIO_RX45n DIFFIO_RX45p DIFFIO_RX46n DIFFIO_RX46p DIFFIO_RX47n DIFFIO_RX47p DIFFIO_RX48n DIFFIO_RX48p DIFFIO_RX49n DIFFIO_RX49p DIFFIO_RX50n DIFFIO_RX50p DIFFIO_RX51n DIFFIO_RX51p DIFFIO_RX52n DIFFIO_RX52p DIFFIO_RX53n DIFFIO_RX53p DIFFIO_RX54n DIFFIO_RX54p DIFFIO_RX55n DIFFIO_RX55p DIFFIO_RX56n DIFFIO_RX56p DIFFIO_RX57n/RDN5 DIFFIO_RX57p/RUP5 DIFFIO_RX58n DIFFIO_RX58p DIFFIO_RX59n DIFFIO_RX59p DIFFIO_RX60n DIFFIO_RX60p DIFFIO_RX61n DIFFIO_RX61p DIFFIO_RX62n DIFFIO_RX62p DIFFIO_RX63n DIFFIO_RX63p DIFFIO_RX64n DIFFIO_RX64p DIFFIO_RX65n DIFFIO_RX65p DIFFIO_RX66n DIFFIO_RX66p
EP1S40F1020
DIFFIO_TX45n DIFFIO_TX45p DIFFIO_TX46n DIFFIO_TX46p DIFFIO_TX47n DIFFIO_TX47p DIFFIO_TX48n DIFFIO_TX48p DIFFIO_TX49n DIFFIO_TX49p DIFFIO_TX50n DIFFIO_TX50p DIFFIO_TX51n DIFFIO_TX51p DIFFIO_TX52n DIFFIO_TX52p DIFFIO_TX53n DIFFIO_TX53p DIFFIO_TX54n DIFFIO_TX54p DIFFIO_TX55n DIFFIO_TX55p DIFFIO_TX56n DIFFIO_TX56p DIFFIO_TX57n DIFFIO_TX57p DIFFIO_TX58n DIFFIO_TX58p DIFFIO_TX59n DIFFIO_TX59p DIFFIO_TX60n DIFFIO_TX60p DIFFIO_TX61n DIFFIO_TX61p DIFFIO_TX62n DIFFIO_TX62p DIFFIO_TX63n DIFFIO_TX63p DIFFIO_TX64n DIFFIO_TX64p DIFFIO_TX65n DIFFIO_TX65p DIFFIO_TX66n DIFFIO_TX66p
LAN_A9 LAN_A10 LAN_A11 LAN_A12 LAN_A13 LAN_A14 LAN_RESET LAN_AEN LAN_ IOCHRDY LAN_INTRQ0 LAN_LDEVn LAN_IORn LAN_IOWn LAN_LOOPBACK B1_USER_A0 B1_USER_A1 B1_USER_B0 B1_USER_B1 B1_USER_C0 B1_USER_C1 B1_USER_D0 B1_USER_D1 B1_USER_E0 B1_USER_E1
DIFFIO_RX23n DIFFIO_RX23p DIFFIO_RX24n DIFFIO_RX24p DIFFIO_RX25n DIFFIO_RX25p DIFFIO_RX26n DIFFIO_RX26p DIFFIO_RX27n DIFFIO_RX27p DIFFIO_RX28n DIFFIO_RX28p DIFFIO_RX29n DIFFIO_RX29p DIFFIO_RX30n DIFFIO_RX30p DIFFIO_RX31n DIFFIO_RX31p DIFFIO_RX32n/RDN2 DIFFIO_RX32p/RUP2 DIFFIO_RX33n DIFFIO_RX33p DIFFIO_RX34n DIFFIO_RX34p DIFFIO_RX35n DIFFIO_RX35p DIFFIO_RX36n DIFFIO_RX36p DIFFIO_RX37n DIFFIO_RX37p DIFFIO_RX38n DIFFIO_RX38p DIFFIO_RX39n DIFFIO_RX39p DIFFIO_RX40n DIFFIO_RX40p DIFFIO_RX41n DIFFIO_RX41p DIFFIO_RX42n DIFFIO_RX42p DIFFIO_RX43n DIFFIO_RX43p DIFFIO_RX44n DIFFIO_RX44p
EP1S40F1020
DIFFIO_TX23n DIFFIO_TX23p DIFFIO_TX24n DIFFIO_TX24p DIFFIO_TX25n DIFFIO_TX25p DIFFIO_TX26n DIFFIO_TX26p DIFFIO_TX27n DIFFIO_TX27p DIFFIO_TX28n DIFFIO_TX28p DIFFIO_TX29n DIFFIO_TX29p DIFFIO_TX30n DIFFIO_TX30p DIFFIO_TX31n DIFFIO_TX31p DIFFIO_TX32n DIFFIO_TX32p DIFFIO_TX33n DIFFIO_TX33p DIFFIO_TX34n DIFFIO_TX34p DIFFIO_TX35n DIFFIO_TX35p DIFFIO_TX36n DIFFIO_TX36p DIFFIO_TX37n DIFFIO_TX37p DIFFIO_TX38n DIFFIO_TX38p DIFFIO_TX39n DIFFIO_TX39p DIFFIO_TX40n DIFFIO_TX40p DIFFIO_TX41n DIFFIO_TX41p DIFFIO_TX42n DIFFIO_TX42p DIFFIO_TX43n DIFFIO_TX43p DIFFIO_TX44n DIFFIO_TX44p
(n/c 1S25) (n/c 1S25) (n/c 1S25) (n/c 1S25) SCRUZ_IO3 SCRUZ_IO4 SCRUZ_IO5 SCRUZ_IO6 SCRUZ_IO7 SCRUZ_IO8 SCRUZ_IO9 SCRUZ_IO10 SCRUZ_IO11 SCRUZ_IO12 SCRUZ_IO13 SCRUZ_IO14 SCRUZ_IO15 SCRUZ_IO16 SCRUZ_IO17 SCRUZ_IO18 SCRUZ_IO19 SCRUZ_IO20 SCRUZ_IO21 SCRUZ_IO22 SCRUZ_IO23 SCRUZ_IO24 SCRUZ_IO25 SCRUZ_IO26 SCRUZ_IO27 SCRUZ_IO28 SCRUZ_IO29 SCRUZ_IO30 SCRUZ_IO31 SCRUZ_IO32 SCRUZ_IO33 SCRUZ_IO34 SCRUZ_IO35 SCRUZ_IO36 SCRUZ_IO37 SCRUZ_IO38 SCRUZ_IO39 SCRUZ_CARDSELn (n/c 1S25) (n/c 1S25)
LAN_RESET LAN_INTRQ0 LAN_AEN LAN_IORn LAN_IOWn LAN_IOCHRDY LAN_LDEVn LAN_LOOPBACK
HSDI CONTROL SIGNALS (TTL)
10,17 10,17
B1_STOPn B1_REQn B1_RESETn B1_PWROK B1_SYS_RESETn B1_SMBCLK B1_SMBDAT
HSDI USER DEFINED SIGNALS
B1_USER_A[1.0] B1_USER_B[1.0] B1_USER_C[1.0] B1_USER_D[1.0] B1_USER_E[1.0]
MICTOR_DE[15.0]
MICTOR_DO[15.0] MICTOR_CLKO USER_RESETn 3.3V SYS_RESETn USER_RESETn USER_PB2 USER_PB1 B1_REQn B1_RESETn B1_SYS_RESETn SYS_RESETn MICTOR_CLKE
USER_PB1
Button intended reset internal Stratix logic (analagous soft reset)
2.5V
user-defined pushbuttons use.
5,17 5,14,17 5,17 5,17
USER_PB[2.1] SYS_RESETn USER_RESETn CPLD_USER[1.0]
USER_PB2
Button resets board re-loads Stratix device from flash memory.
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
150-0216200-01
Wednesday, February 2003 Sheet
Copyright 2003, Altera Corporation. Rights Reserved.
Date:
Stratix Bank Bank
Bank Bank (2.5V SSTL-2 2.5V LVTTL)
B6_IO_AD31 B6_IO_AD30 B6_IO_AD29 B6_IO_AD28 DDR_DM4 DDR_DM5 DDR_DM6 DDR_DM7 B6_IO_AD27 DDR_DP0 DDR_DP1 DDR_DP2 DDR_DP3 DDR_DP4 DDR_DP5 DDR_DP6 DDR_DP7 DDR_DQS8 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 DDR_DQS3 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQS2 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQS1 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQS0
(2.5V SSTL-2 2.5V LVTTL)
11,17 B6_RESETn 11,17 B6_PWROK RUP3 DDR_A7 DDR_A6 DDR_A1 DDR_A4 DDR_A0 DDR_A3 DDR_A5 DDR_DQ[63.0]
DQ9T0 DQ9T1 DQ9T2 DQ9T3 DQ9T4 DQ9T5 DQ9T6 DQ9T7 DQS9T DQ8T0 DQ8T1 DQ8T2 DQ8T3 DQ8T4 DQ8T5 DQ8T6 DQ8T7 DQS8T DQ7T0 DQ7T1 DQ7T2 DQ7T3 DQ7T4 DQ7T5 DQ7T6 DQ7T7 DQS7T DQ6T0 DQ6T1 DQ6T2 DQ6T3 DQ6T4 DQ6T5 DQ6T6 DQ6T7 DQS6T DQ5T0 DQ5T1 DQ5T2 DQ5T3 DQ5T4 DQ5T5 DQ5T6 DQ5T7 DQS5T
EP1S40F1020
FCLK0 FCLK1 RDN3 RUP3 GPIO_B3_0 GPIO_B3_1 GPIO_B3_2 GPIO_B3_3 GPIO_B3_4 GPIO_B3_5 GPIO_B3_6 GPIO_B3_7 GPIO_B3_8 GPIO_B3_9 GPIO_B3_10 GPIO_B3_11 GPIO_B3_12 GPIO_B3_13 GPIO_B3_14 GPIO_B3_15 GPIO_B3_16 GPIO_B3_17 GPIO_B3_18 GPIO_B3_19 GPIO_B3_20 GPIO_B3_21 GPIO_B3_22 GPIO_B3_23 GPIO_B3_24 GPIO_B3_25 GPIO_B3_26 GPIO_B3_27 GPIO_B3_30 GPIO_B3_31
DQ4T0 DQ4T1 DQ4T2 DQ4T3 DQ4T4 DQ4T5 DQ4T6 DQ4T7 DQS4T DQ3T0 DQ3T1 DQ3T2 DQ3T3 DQ3T4 DQ3T5 DQ3T6 DQ3T7 DQS3T DQ2T0 DQ2T1 DQ2T2 DQ2T3 DQ2T4 DQ2T5 DQ2T6 DQ2T7 DQS2T DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4 DQ1T5 DQ1T6 DQ1T7 DQS1T DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQS0T
EP1S40F1020
FCLK6 FCLK7 RDN4 RUP4 GPIO_B4_0 GPIO_B4_1 GPIO_B4_2 GPIO_B4_3 GPIO_B4_4 GPIO_B4_5 GPIO_B4_6 GPIO_B4_7 GPIO_B4_8 GPIO_B4_9 GPIO_B4_10 GPIO_B4_11 GPIO_B4_12 GPIO_B4_13 GPIO_B4_14 GPIO_B4_15 GPIO_B4_16 GPIO_B4_17 GPIO_B4_18 GPIO_B4_19 GPIO_B4_20 GPIO_B4_21 GPIO_B4_22 GPIO_B4_23 GPIO_B4_24 GPIO_B4_25 GPIO_B4_26 GPIO_B4_27 GPIO_B4_28 GPIO_B4_29 GPIO_B4_30 GPIO_B4_31 GPIO_B4_32 GPIO_B4_33 GPIO_B4_34 GPIO_B4_35 GPIO_B4_36 GPIO_B4_37 GPIO_B4_38
(n/c (n/c (n/c (n/c (n/c (n/c (n/c RUP4
DDR_DM8 DDR_DP[7.0] DDR_A[13.0] DDR_BA[2.0] DDR_A8 DDR_DM[8.0] DDR_A9 DDR_A13 DDR_A12 B6_IO_AD25 DDR_A10 DDR_CLKEN0 DDR_CLKEN1 DDR_A11 B6_IO_AD24 DDR_DQS[8.0] DDR_CLKEN[1.0]
DDR_DQ56 DDR_DQ57 DDR_DQ58 DDR_DQ59 DDR_DQ60 DDR_DQ61 DDR_DQ62 DDR_DQ63 DDR_DQS7 DDR_DQ48 DDR_DQ49 DDR_DQ50 DDR_DQ51 DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR_DQ55 DDR_DQS6
B6_IO_AD[31.24]
DDR_BA0 DDR_RASn 11,17 B6_IO_OEn DDR_BA1 B6_IO_AD26 DDR_A2 DDR_CASn DDR_CS0n DDR_WEn DDR_CS1n DDR_BA2 B6_IO_CSn SPD_SCL SPD_SDA B6_IO_RDYn B6_IO_RESETn B6_IO_WRn
DDR_DM0 DDR_DM1
DDR_DQ40 DDR_DQ41 DDR_DQ42 DDR_DQ43 DDR_DQ44 DDR_DQ45 DDR_DQ46 DDR_DQ47 DDR_DQS5 DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39 DDR_DQS4
11,17 11,17 11,17 11,17
DDR_DM2 DDR_DM3 1S25) 1S25) 1S25) 1S25) 1S25) 1S25) 1S25)
On-chip termination biasing resistors
2.5V RUP3
On-chip termination biasing resistors
2.5V RUP4
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Date:
Sheet
3.3V
Side
PIN_2 PIN_4 PIN_6 PIN_8 PIN_10 PIN_12 PIN_14 PIN_16 PIN_18 PIN_20 PIN_22 PIN_24 PIN_26 PIN_28 PIN_30 PIN_32 PIN_34 PIN_36 PIN_38 PIN_40 Pins GND3 GND4 PIN_42 PIN_44 PIN_46 PIN_48 PIN_50 PIN_52 PIN_54 PIN_56 PIN_58 PIN_60 PIN_62 PIN_64 PIN_66 PIN_68 PIN_70 PIN_72 PIN_74 PIN_76 PIN_78 PIN_80 Pins GND7 GND8 PIN_82 PIN_84 PIN_86 PIN_88 PIN_90 PIN_92 PIN_94 PIN_96 PIN_98 PIN_100 PIN_102 PIN_104 PIN_106 PIN_108 PIN_110 PIN_112 PIN_114 PIN_116 PIN_118 PIN_120 Pins GND11 GND12 PIN_122 PIN_124 PIN_126 PIN_128 PIN_130 PIN_132 PIN_134 PIN_136 PIN_138 PIN_140 PIN_142 PIN_144 PIN_146 PIN_148 PIN_150 PIN_152 PIN_154 PIN_156 PIN_158 PIN_160 Pins GND15 GND16
3.3V
3.3V
Bottom Side
PIN_2 PIN_4 PIN_6 PIN_8 PIN_10 PIN_12 PIN_14 PIN_16 PIN_18 PIN_20 PIN_22 PIN_24 PIN_26 PIN_28 PIN_30 PIN_32 PIN_34 PIN_36 PIN_38 PIN_40 Pins GND3 GND4 PIN_42 PIN_44 PIN_46 PIN_48 PIN_50 PIN_52 PIN_54 PIN_56 PIN_58 PIN_60 PIN_62 PIN_64 PIN_66 PIN_68 PIN_70 PIN_72 PIN_74 PIN_76 PIN_78 PIN_80 Pins GND7 GND8 PIN_82 PIN_84 PIN_86 PIN_88 PIN_90 PIN_92 PIN_94 PIN_96 PIN_98 PIN_100 PIN_102 PIN_104 PIN_106 PIN_108 PIN_110 PIN_112 PIN_114 PIN_116 PIN_118 PIN_120 Pins GND11 GND12 PIN_122 PIN_124 PIN_126 PIN_128 PIN_130 PIN_132 PIN_134 PIN_136 PIN_138 PIN_140 PIN_142 PIN_144 PIN_146 PIN_148 PIN_150 PIN_152 PIN_154 PIN_156 PIN_158 PIN_160 Pins GND15 GND16
3.3V
JTAG_SAMTEC_TDO B1_USER_A0 B1_USER_B0 B1_USER_D0 B1_USER_E0 JTAG_TRST JTAG_TCK B1B_TX_CADp0 B1B_TX_CADn0 B1B_TX_CADp1 B1B_TX_CADn1 B1B_TX_CADp2 B1B_TX_CADn2
B1B_TX_CADp3 B1B_TX_CADn3
B1B_TX_CLKp B1B_TX_CLKn B1B_TX_CADp4 B1B_TX_CADn4 B1B_TX_CADp5 B1B_TX_CADn5 B1B_TX_CADp6 B1B_TX_CADn6 B1B_TX_CADp7 B1B_TX_CADn7 B1B_TX_CTLp B1B_TX_CTLn
B1A_RX_CTLn B1A_RX_CTLp B1A_RX_CADn7 B1A_RX_CADp7 B1A_RX_CADn6 B1A_RX_CADp6 B1A_RX_CADn5 B1A_RX_CADp5 B1A_RX_CADn4 B1A_RX_CADp4 B1A_RX_CLKn B1A_RX_CLKp
B1A_RX_CADn3 B1A_RX_CADp3 B1A_RX_CADn2 B1A_RX_CADp2 B1A_RX_CADn1 B1A_RX_CADp1 B1A_RX_CADn0 B1A_RX_CADp0 B1_REQn B1_RESETn B1_USER_C1 B1_SYS_RESETn B1_REF_CLK_IN
3.3V
PIN_1 PIN_3 PIN_5 PIN_7 PIN_9 PIN_11 PIN_13 PIN_15 PIN_17 PIN_19 PIN_21 PIN_23 PIN_25 PIN_27 PIN_29 PIN_31 PIN_33 PIN_35 PIN_37 PIN_39 GND1 Internal Ground GND2 PIN_41 PIN_43 PIN_45 PIN_47 PIN_49 PIN_51 PIN_53 PIN_55 PIN_57 PIN_59 PIN_61 PIN_63 PIN_65 PIN_67 PIN_69 PIN_71 PIN_73 PIN_75 PIN_77 PIN_79 GND5 Internal Ground GND6 PIN_81 PIN_83 PIN_85 PIN_87 PIN_89 PIN_91 PIN_93 PIN_95 PIN_97 PIN_99 PIN_101 PIN_103 PIN_105 PIN_107 PIN_109 PIN_111 PIN_113 PIN_115 PIN_117 PIN_119 GND9 Internal Ground GND10 PIN_121 PIN_123 PIN_125 PIN_127 PIN_129 PIN_131 PIN_133 PIN_135 PIN_137 PIN_139 PIN_141 PIN_143 PIN_145 PIN_147 PIN_149 PIN_151 PIN_153 PIN_155 PIN_157 PIN_159 GND13 Internal Ground GND14
QSE-080
B1_REF_CLK_OUT JTAG_TMS B1_USER_C0 B1_SMBCLK B1_SMBDAT B1A_TX_CADp0 B1A_TX_CADn0 B1A_TX_CADp1 B1A_TX_CADn1 B1A_TX_CADp2 B1A_TX_CADn2 B1A_TX_CADp3 B1A_TX_CADn3
JTAG_STRATIX_TDO B1_USER_A1 B1_USER_B1 B1_USER_D1 B1_USER_E1 JTAG_TRST JTAG_TCK B1B_RX_CADp0 B1B_RX_CADn0 B1B_RX_CADp1 B1B_RX_CADn1 B1B_RX_CADp2 B1B_RX_CADn2
Plane
B1A_TX_CLKp B1A_TX_CLKn B1A_TX_CADp4 B1A_TX_CADn4 B1A_TX_CADp5 B1A_TX_CADn5 B1A_TX_CADp6 B1A_TX_CADn6 B1A_TX_CADp7 B1A_TX_CADn7 B1A_TX_CTLp B1A_TX_CTLn
B1B_RX_CADp3 B1B_RX_CADn3 B1B_RX_CLKp B1B_RX_CLKn B1B_RX_CADp4 B1B_RX_CADn4 B1B_RX_CADp5 B1B_RX_CADn5 B1B_RX_CADp6 B1B_RX_CADn6 B1B_RX_CADp7 B1B_RX_CADn7 B1B_RX_CTLp B1B_RX_CTLn
Plane
B1B_RX_CTLn B1B_RX_CTLp B1B_RX_CADn7 B1B_RX_CADp7 B1B_RX_CADn6 B1B_RX_CADp6 B1B_RX_CADn5 B1B_RX_CADp5 B1B_RX_CADn4 B1B_RX_CADp4 B1B_RX_CLKn B1B_RX_CLKp B1B_RX_CADn3 B1B_RX_CADp3
B1A_TX_CTLn B1A_TX_CTLp B1A_TX_CADn7 B1A_TX_CADp7 B1A_TX_CADn6 B1A_TX_CADp6 B1A_TX_CADn5 B1A_TX_CADp5 B1A_TX_CADn4 B1A_TX_CADp4 B1A_TX_CLKn B1A_TX_CLKp
Plane
B1B_RX_CADn2 B1B_RX_CADp2 B1B_RX_CADn1 B1B_RX_CADp1 B1B_RX_CADn0 B1B_RX_CADp0 B1_STOPn B1_PWROK B1_USER_E1 B1_USER_D1 B1_USER_B1 B1_USER_A1 JTAG_STRATIX_TDO
B1A_TX_CADn3 B1A_TX_CADp3 B1A_TX_CADn2 B1A_TX_CADp2 B1A_TX_CADn1 B1A_TX_CADp1 B1A_TX_CADn0 B1A_TX_CADp0 B1_REQn B1_RESETn B1_USER_C0 B1_SYS_RESETn B1_REF_CLK_OUT
3.3V
3.3V
Plane
PIN_1 PIN_3 PIN_5 PIN_7 PIN_9 PIN_11 PIN_13 PIN_15 PIN_17 PIN_19 PIN_21 PIN_23 PIN_25 PIN_27 PIN_29 PIN_31 PIN_33 PIN_35 PIN_37 PIN_39 GND1 Internal Ground GND2 PIN_41 PIN_43 PIN_45 PIN_47 PIN_49 PIN_51 PIN_53 PIN_55 PIN_57 PIN_59 PIN_61 PIN_63 PIN_65 PIN_67 PIN_69 PIN_71 PIN_73 PIN_75 PIN_77 PIN_79 GND5 Internal Ground GND6 PIN_81 PIN_83 PIN_85 PIN_87 PIN_89 PIN_91 PIN_93 PIN_95 PIN_97 PIN_99 PIN_101 PIN_103 PIN_105 PIN_107 PIN_109 PIN_111 PIN_113 PIN_115 PIN_117 PIN_119 GND9 Internal Ground GND10 PIN_121 PIN_123 PIN_125 PIN_127 PIN_129 PIN_131 PIN_133 PIN_135 PIN_137 PIN_139 PIN_141 PIN_143 PIN_145 PIN_147 PIN_149 PIN_151 PIN_153 PIN_155 PIN_157 PIN_159 GND13 Internal Ground GND14
QTE-080
Bank HSDI Connectors
B1_REF_CLK_IN JTAG_TMS B1_USER_C1 B1_SMBCLK B1_SMBDAT B1A_RX_CADp0 B1A_RX_CADn0 B1A_RX_CADp1 B1A_RX_CADn1 B1A_RX_CADp2 B1A_RX_CADn2 B1A_RX_CADp3 B1A_RX_CADn3 11,15 11,15 11,12 11,12
HSDI BANK INTERFACE
B1A_TX_CLKp B1A_TX_CLKn B1A_TX_CTLp B1A_TX_CTLn
B1A_TX_CADp[7.0] B1A_TX_CADn[7.0]
HSDI BANK INTERFACE
B1A_RX_CLKp B1A_RX_CLKn B1A_RX_CTLp B1A_RX_CTLn
Plane
B1A_RX_CLKp B1A_RX_CLKn B1A_RX_CADp4 B1A_RX_CADn4 B1A_RX_CADp5 B1A_RX_CADn5 B1A_RX_CADp6 B1A_RX_CADn6 B1A_RX_CADp7 B1A_RX_CADn7 B1A_RX_CTLp B1A_RX_CTLn
11,12 B1A_RX_CADp[7.0] 11,12 B1A_RX_CADn[7.0]
HSDI BANK INTERFACE
B1B_TX_CLKp B1B_TX_CLKn B1B_TX_CTLp B1B_TX_CTLn
B1B_TX_CADp[7.0] B1B_TX_CADn[7.0]
HSDI BANK INTERFACE
B1B_RX_CLKp B1B_RX_CLKn B1B_RX_CTLp B1B_RX_CTLn
Plane
B1B_TX_CTLn B1B_TX_CTLp B1B_TX_CADn7 B1B_TX_CADp7 B1B_TX_CADn6 B1B_TX_CADp6 B1B_TX_CADn5 B1B_TX_CADp5 B1B_TX_CADn4 B1B_TX_CADp4 B1B_TX_CLKn B1B_TX_CLKp B1B_TX_CADn3 B1B_TX_CADp3
B1B_RX_CADp[7.0] B1B_RX_CADn[7.0]
OTHER HSDI CONTROL SIGNALS
8,17 8,17 B1_REF_CLK_IN B1_REF_CLK_OUT B1_STOPn B1_REQn B1_SYS_RESETn B1_RESETn B1_PWROK B1_SMBCLK B1_SMBDAT
Plane
HSDI JTAG INTERFACE
B1B_TX_CADn2 B1B_TX_CADp2 B1B_TX_CADn1 B1B_TX_CADp1 B1B_TX_CADn0 B1B_TX_CADp0 B1_STOPn B1_PWROK B1_USER_E0 B1_USER_D0 B1_USER_B0 B1_USER_A0 JTAG_SAMTEC_TDO Title 3.3V 15,17 JTAG_TMS JTAG_SAMTEC_TDO JTAG_TRSTn JTAG_TCK JTAG_STRATIX_TDO
HSDI USER SIGNALS
B1_USER_A[1.0] B1_USER_B[1.0] B1_USER_C[1.0] B1_USER_D[1.0] B1_USER_E[1.0]
Altera Corporation, 9330 Scranton #400, Diego, 92121
Plane
Stratix Development Board
Size Date: Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Sheet
Bank Debug, Bank HSDI Connector
BANK HDSI DEBUG
10,12 B1A_RX_CADp[7.0] 10,12 B1A_RX_CADn[7.0] 10,15 B1A_RX_CLKp 10,15 B1A_RX_CLKn 3.3V 10,12 B1A_RX_CTLp 10,12 B1A_RX_CTLn
PLACE RESISTORS CLOSE DATAPATH POSSIBLE (MINIMIZE STUB LENGTH) B1A_RX_CADn0 B1A_RX_CADp0 B1A_RX_CADn1 B1A_RX_CADp1 B1A_RX_CADn2 B1A_RX_CADp2 B1A_RX_CADn3 B1A_RX_CADp3 B1A_RX_CADn4 B1A_RX_CADp4 B1A_RX_CADn5 B1A_RX_CADp5 B1A_RX_CADn6 B1A_RX_CADp6 B1A_RX_CADn7 B1A_RX_CADp7 SAMTEC_RX_CADn0 SAMTEC_RX_CADp0 SAMTEC_RX_CADn1 SAMTEC_RX_CADp1 SAMTEC_RX_CADn2 SAMTEC_RX_CADp2 SAMTEC_RX_CADn3 SAMTEC_RX_CADp3 SAMTEC_RX_CADn4 SAMTEC_RX_CADp4 SAMTEC_RX_CADn5 SAMTEC_RX_CADp5 SAMTEC_RX_CADn6 SAMTEC_RX_CADp6 SAMTEC_RX_CADn7 SAMTEC_RX_CADp7
3.3V
Edge-Mount
B1A_RX_CTLn B1A_RX_CTLp B1A_RX_CLKn B1A_RX_CLKp
SAMTEC_RX_CTLn SAMTEC_RX_CTLp SAMTEC_RX_CLKn SAMTEC_RX_CLKp
PLACE RESISTORS CLOSE SAMTEC CONNECTOR TERMINATION POSSIBLE. SAMTEC_RX_CADn0 SAMTEC_RX_CADp0 SAMTEC_RX_CADn1 SAMTEC_RX_CADp1 SAMTEC_RX_CADn2 SAMTEC_RX_CADp2 SAMTEC_RX_CADn3 SAMTEC_RX_CADp3 SAMTEC_RX_CADn4 SAMTEC_RX_CADp4 SAMTEC_RX_CADn5 SAMTEC_RX_CADp5 SAMTEC_RX_CADn6 SAMTEC_RX_CADp6 SAMTEC_RX_CADn7 SAMTEC_RX_CADp7 SAMTEC_RX_CTLn SAMTEC_RX_CTLp SAMTEC_RX_CLKn SAMTEC_RX_CLKp
D10N D10P D11N D11P D12N D12P D13N D13P D14N D14P D15N D15P CLKN CLKP NC10 NC11 NC12 NC13 NC14 NC15 NC16
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50
B6_RESETn 9,17 B6_PWROK 9,17 B6_RX_CTLn B6_RX_CTLp B6_RX_CADn7 B6_RX_CADp7 B6_RX_CADn6 B6_RX_CADp6 B6_RX_CADn5 B6_RX_CADp5 B6_RX_CADn4 B6_RX_CADp4 B6_RX_CLKn B6_RX_CLKp B6_RX_CADn3 B6_RX_CADp3 B6_RX_CADn2 B6_RX_CADp2 B6_RX_CADn1 B6_RX_CADp1 B6_RX_CADn0 B6_RX_CADp0
ASP-65067-01
3.3V
VDD33_1 VDD33_3 VDDLDT_1 GND1 TRST_L LDT_RESET_L LDT_PWROK GND4 LDT_TX_CTLn LDT_TX_CTLp GND6 LDT_TX_CADn7 LDT_TX_CADp7 GND8 GND10 LDT_TX_CADn6 LDT_TX_CADp6 GND12 LDT_TX_CADn5 LDT_TX_CADp5 GND14 LDT_TX_CADn4 LDT_TX_CADp4 GND16 GND18 LDT_TX_CLKn LDT_TX_CLKp GND20 LDT_TX_CADn3 LDT_TX_CADp3 GND22 LDT_TX_CADn2 LDT_TX_CADp2 GND24 GND26 LDT_TX_CADn1 LDT_TX_CADp1 GND28 LDT_TX_CADn0 LDT_TX_CADp0 GND30 GND32 VDDLDT_3 VDD33_5 VDD33_7 GND34 GND36 GND38 GND40 GND42 GND44
VDD33_2 VDD33_4 VDDLDT_2 GND2 CLK100 GND3 OE_L WR_L CS_L0 CS_L1 RESET_L GND5 LDT_RX_CADp0 LDT_RX_CADn0 GND7 LDT_RX_CADp1 LDT_RX_CADn1 GND9 GND11 LDT_RX_CADp2 LDT_RX_CADn2 GND13 LDT_RX_CADp3 LDT_RX_CADn3 GND15 LDT_RX_CLKp LDT_RX_CLKn GND17 GND19 LDT_RX_CADp4 LDT_RX_CADn4 GND21 LDT_RX_CADp5 LDT_RX_CADn5 GND23 LDT_RX_CADp6 LDT_RX_CADn6 GND25 GND27 LDT_RX_CADp7 LDT_RX_CADn7 GND29 LDT_RX_CTLp LDT_RX_CTLn GND31 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 GND33 VDDLDT_4 VDD33_6 VDD33_8 GND35 GND37 GND39 GND41 GND43 GND45
BANK HSDI
B6_REF_CLK B6_IO_RDYn B6_IO_OEn B6_IO_WRn B6_IO_CSn B6_IO_RESETn B6_TX_CADp0 B6_TX_CADn0 B6_TX_CADp1 B6_TX_CADn1 B6_TX_CADp2 B6_TX_CADn2 B6_TX_CADp3 B6_TX_CADn3 B6_TX_CLKp B6_TX_CLKn B6_TX_CADp4 B6_TX_CADn4 B6_REF_CLK B6_TX_CADp5 B6_TX_CADn5 B6_TX_CADp6 B6_TX_CADn6 B6_TX_CADp7 B6_TX_CADn7 B6_TX_CTLp B6_TX_CTLn B6_IO_AD24 B6_IO_AD25 B6_IO_AD26 B6_IO_AD27 B6_IO_AD28 B6_IO_AD29 B6_IO_AD30 B6_IO_AD31 3.3V R255 B6_REF25_CLK R254
B6_RX_CADp[7.0] B6_RX_CADn[7.0] B6_TX_CADp[7.0] B6_TX_CADn[7.0]
BANK USER
B6_IO_AD[31.24]
B6_REF60_CLK
Solder-Side (Bottom)
Bank Receive (Inputs this board)
Internal Ground Plane Pins
Component-Side (Top)
Bank Transmit (Outputs from this board)
QTE-060-EM
Altera Corporation, 9330 Scranton #400, Diego, 92121
Title
Stratix Development Board
Size Document Number
150-0216200-01
Wednesday, February 2003
Copyright 2003, Altera Corporation. Rights Reserved.
Date:
Sheet
Bank (Switchable 2.5V HyperTransport 3.3V LVDS)
(n/c (n/c (n/c (n/c (n/c (n/c 1S25) 1S25) 1S25) 1S25) 1S25) 1S25)
Stratix Bank Bank
B1B_TX_CADn3 B1B_TX_CADp3 B1B_TX_CTLn B1B_TX_CTLp B1B_TX_CADn2 B1B_TX_CADp2 B1B_TX_CADn7 B1B_TX_CADp7 B1B_TX_CADn1 B1B_TX_CADp1 B1B_TX_CADn6 B1B_TX_CADp6 B1B_TX_CADn5 B1B_TX_CADp5 B1B_TX_CADn0 B1B_TX_CADp0 B1B_TX_CADn4 B1B_TX_CADp4 B1B_TX_CLKn B1B_TX_CLKp B1A_TX_CADn3 B1A_TX_CADp3 B1A_TX_CTLn B1A_TX_CTLp B1A_TX_CADn0 B1A_TX_CADp0 B1A_TX_CADn6 B1A_TX_CADp6 B1A_TX_CADn7 B1A_TX_CADp7 B1A_TX_CLKn B1A_TX_CLKp B1A_TX_CADn2 B1A_TX_CADp2 B1A_TX_CADn1 B1A_TX_CADp1 B1A_TX_CADn5 B1A_TX_CADp5 B1A_TX_CADn4 B1A_TX_CADp4 1S25) 1S25) 1S25) 1S25) 1S25) 1S25)
HSDI BANK INTERFACE
B1A_TX_CLKp B1A_TX_CLKn B1A_TX_CTLp B1A_TX_CTLn
B1B_RX_CADn0 B1B_RX_CADp0 B1B_RX_CADn4 B1B_RX_CADp4 B1B_RX_CADn1 B1B_RX_CADp1 B1B_RX_CADn5 B1B_RX_CADp5 B1B_RX_CADn2 B1B_RX_CADp2 B1B_RX_CADn6 B1B_RX_CADp6 B1B_RX_CADn7 B1B_RX_CADp7 B1B_RX_CADn3 B1B_RX_CADp3 B1B_RX_CTLn B1B_RX_CTLp B1A_RX_CADn0 B1A_RX_CADp0 B1A_RX_CADn4 B1A_RX_CADp4 B1A_RX_CADn5 B1A_RX_CADp5 B1A_RX_CADn1 B1A_RX_CADp1 B1A_RX_CADn6 B1A_RX_CADp6 B1A_RX_CADn2 B1A_RX_CADp2 B1A_RX_CADn7 B1A_RX_CADp7 B1A_RX_CADn3 B1A_RX_CADp3 B1A_RX_CTLn B1A_RX_CTLp
AG28 AH29 AH31 AH32 AG26 AG25 AG29 AG30 AG32 AG31 AF29 AF30 AF31 AF32 AE29 AE30 AE31 AE32 AD29 AD30 AC30 AC29 AD31 AD32 AC31 AB32 AA29 AA28 AB30 AB31 AA30 AA31
DIFFIO_RX00n DIFFIO_RX00p DIFFIO_RX01n DIFFIO_RX01p DIFFIO_RX02n DIFFIO_RX02p DIFFIO_RX03n DIFFIO_RX03p DIFFIO_RX04n DIFFIO_RX04p DIFFIO_RX05n DIFFIO_RX05p DIFFIO_RX06n DIFFIO_RX06p DIFFIO_RX07n DIFFIO_RX07p DIFFIO_RX08n DIFFIO_RX08p DIFFIO_RX09n DIFFIO_RX09p DIFFIO_RX10n DIFFIO_RX10p DIFFIO_RX11n DIFFIO_RX11p DIFFIO_RX12n DIFFIO_RX12p DIFFIO_RX13n/RDN1 DIFFIO_RX13p/RUP1 DIFFIO_RX14n DIFFIO_RX14p DIFFIO_RX15n DIFFIO_RX15p DIFFIO_RX16n DIFFIO_RX16p DIFFIO_RX17n DIFFIO_RX17p DIFFIO_RX18n DIFFIO_RX18p DIFFIO_RX19n DIFFIO_RX19p DIFFIO_RX20n DIFFIO_RX20p DIFFIO_RX21n DIFFIO_RX21p DIFFIO_RX22n DIFFIO_RX22p
DIFFIO_TX00n DIFFIO_TX00p DIFFIO_TX01n DIFFIO_TX01p DIFFIO_TX02n DIFFIO_TX02p DIFFIO_TX03n DIFFIO_TX03p DIFFIO_TX04n DIFFIO_TX04p DIFFIO_TX05n DIFFIO_TX05p DIFFIO_TX06n DIFFIO_TX06p DIFFIO_TX07n DIFFIO_TX07p DIFFIO_TX08n DIFFIO_TX08p DIFFIO_TX09n DIFFIO_TX09p DIFFIO_TX10n DIFFIO_TX10p DIFFIO_TX11n DIFFIO_TX11p DIFFIO_TX12n DIFFIO_TX12p DIFFIO_TX13n DIFFIO_TX13p DIFFIO_TX14n DIFFIO_TX14p DIFFIO_TX15n DIFFIO_TX15p DIFFIO_TX16n DIFFIO_TX16p DIFFIO_TX17n DIFFIO_TX17p DIFFIO_TX18n DIFFIO_TX18p DIFFIO_TX19n DIFFIO_TX19p DIFFIO_TX20n DIFFIO_TX20p DIFFIO_TX21n DIFFIO_TX21p DIFFIO_TX22n DIFFIO_TX22p GPIO_2B1_0 GPIO_2B1_1
AF25 AF26 AF28 AF27 AE26 AE25 AE27 AE28 AD25 AD26 AD27 AD28 AC28 AC27 AC26 AC25 AB26 AB27 AA26 AA27 AA24 AA25 AA22 AB23
Bank (Switchable 2.5V HyperTransport 3.3V LVDS)
B1A_TX_CADp[7.0] B1A_TX_CADn[7.0] 1S25) 1S25) 1S25) 1S25) 1S25) 1S25) B6_TX_CADn2 B6_TX_CADp2 B6_TX_CADn7 B6_TX_CADp7 B6_TX_CTLn B6_TX_CTLp B6_TX_CADn6 B6_TX_CADp6 B6_TX_CADn3 B6_TX_CADp3 B6_TX_CADn5 B6_TX_CADp5 B6_TX_CADn1 B6_TX_CADp1 B6_TX_CADn4 B6_TX_CADp4 B6_TX_CLKn B6_TX_CLKp B6_TX_CADn0 B6_TX_CADp0
DIFFIO_RX67n DIFFIO_RX67p DIFFIO_RX68n DIFFIO_RX68p DIFFIO_RX69n DIFFIO_RX69p DIFFIO_RX70n DIFFIO_RX70p DIFFIO_RX71n DIFFIO_RX71p DIFFIO_RX72n DIFFIO_RX72p DIFFIO_RX73n DIFFIO_RX73p DIFFIO_RX74n DIFFIO_RX74p DIFFIO_RX75n DIFFIO_RX75p DIFFIO_RX76n/RDN6 DIFFIO_RX76p/RUP6 DIFFIO_RX77n DIFFIO_RX77p DIFFIO_RX78n DIFFIO_RX78p DIFFIO_RX79n DIFFIO_RX79p DIFFIO_RX80n DIFFIO_RX80p DIFFIO_RX81n DIFFIO_RX81p DIFFIO_RX82n DIFFIO_RX82p DIFFIO_RX83n DIFFIO_RX83p DIFFIO_RX84n DIFFIO_RX84p DIFFIO_RX85n DIFFIO_RX85p DIFFIO_RX86n DIFFIO_RX86p DIFFIO_RX87n DIFFIO_RX87p DIFFIO_RX88n DIFFIO_RX88p DIFFIO_RX89n DIFFIO_RX89p GPIO_B6_0
EP1S40F1020
DIFFIO_TX67n DIFFIO_TX67p DIFFIO_TX68n DIFFIO_TX68p DIFFIO_TX69n DIFFIO_TX69p DIFFIO_TX70n DIFFIO_TX70p DIFFIO_TX71n DIFFIO_TX71p DIFFIO_TX72n DIFFIO_TX72p DIFFIO_TX73n DIFFIO_TX73p DIFFIO_TX74n DIFFIO_TX74p DIFFIO_TX75n DIFFIO_TX75p DIFFIO_TX76n DIFFIO_TX76p DIFFIO_TX77n DIFFIO_TX77p DIFFIO_TX78n DIFFIO_TX78p DIFFIO_TX79n DIFFIO_TX79p DIFFIO_TX80n DIFFIO_TX80p DIFFIO_TX81n DIFFIO_TX81p DIFFIO_TX82n DIFFIO_TX82p DIFFIO_TX83n DIFFIO_TX83p DIFFIO_TX84n DIFFIO_TX84p DIFFIO_TX85n DIFFIO_TX85p DIFFIO_TX86n DIFFIO_TX86p DIFFIO_TX87n DIFFIO_TX87p DIFFIO_TX88n DIFFIO_TX88p DIFFIO_TX89n DIFFIO_TX89p GPIO_B6_1
AB10 AA11 AC10
(n/c (n/c (n/c (n/c (n/c (n/c
HSDI BANK INTERFACE
10,11 B1A_RX_CTLp 10,11 B1A_RX_CTLn 10,11 B1A_RX_CADp[7.0] 10,11 B1A_RX_CADn[7.0]
HSDI BANK INTERFACE
B1B_TX_CLKp B1B_TX_CLKn B1B_TX_CTLp B1B_TX_CTLn
B6_RX_CADn5 B6_RX_CADp5 B6_RX_CADn0 B6_RX_CADp0 B6_RX_CADn4 B6_RX_CADp4 B6_RX_CADn6 B6_RX_CADp6 B6_RX_CADn1 B6_RX_CADp1 B6_RX_CADn7 B6_RX_CADp7 B6_RX_CADn2 B6_RX_CADp2 B6_RX_CTLn B6_RX_CTLp B6_RX_CADn3 B6_RX_CADp3 (n/c (n/c (n/c (n/c (n/c (n/c
B1B_TX_CADp[7.0] B1B_TX_CADn[7.0]<br
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