Stratix® EP1S80 development board included with Development Kit, Strat

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Stratix® EP1S80 development board included with Development Kit, Strat

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Stratix EP1S80 Development Board
Stratix® EP1S80 development board included with Development Kit, Stratix Professional Edition (ordering code: DSP-BOARD/S80). This board powerful development platform digital signal processing (DSP) designs, features Stratix EP1S80 device speed grade (-6) 956-pin package.
Components
Analog 12-bit 125-MHz converters 14-bit 165-MHz converters Single-ended differential inputs, single-ended outputs Memory subsystem Mbytes 7.5-ns synchronous SRAM configured independent 36-bit buses Mbits flash memory Configuration options On-board configuration 64-Mbits flash memory, plus Altera® EPM7064 programmable logic device (PLD) Download configuration data using ByteBlasterMVdownload cables Dual seven-segment display 8-pin dual in-line package (DIP) switch Three user-definable pushbutton switches 9-pin RS-232 connector user-definable LEDs On-board 80-MHz oscillator Single power supply (adapter included)
Debugging Interfaces
Mictor-type connectors Agilent Technologies logic analyzers Several 0.1-inch headers
Expansion Interfaces
connectors Analog Devices converter daughter cards Connector Texas Instruments Evaluation Module (TI-EVM) daughter cards Altera Expansion Prototype Connector
Altera Corporation
DS-STXDVBD-1.3
Stratix EP1S80 Development Board
Footprint front panel data port (FPDP) Prototyping area
General Description
Stratix EP1S80 development board provides hardware platform designers start developing systems based Stratix devices immediately. Combined with intellectual property (IP) from Altera Altera Megafunction Partners Program (AMPPSM) partners, users quickly develop powerful systems. Altera's unique OpenCore® Plus technology allows users these cores hardware prior licensing them. Builder (version 2.2.1) includes library Stratix EP1S80 development board. This library allows algorithm development, simulation, verification board, from within MathWorks MATLAB/Simulink system-level design tools. Additionally, Stratix development board Texas Instruments' (cross-platform) daughter card connector, which enables development verification FPGA co-processors.
Preliminary
Altera Corporation
General Description
Components Interfaces
Figure shows view board components interfaces. Figure Stratix EP1S80 Development Board Components Interfaces
60-Pin Connector (JP8)
JP25 JP23 JP18
JP26
External Clock Inputs (JP1, JP3) External Clock Outputs (JP2, JP4)
64-Mbit Flash Memory (U3)
Configuration Controller (U4) Mictor (EPM7064) Connectors (J9, J10)
Prototyping Area connect other components)
Connector Output from (J2)
14-bit, 165-MHz Converters (U21, U23)
JP10
Altera Expansion Prototype Connector (JP20, JP21, JP24) FPDP Footprint
Connector Output from (J3) Connector Input (JP11) 12-bit, Converters (U10, U30) Connector Input (JP6)
80-MHz Oscillator (U1) TI-EVM Connector (J11) (reverse side) Pushbutton Switches (SW0, SW1, SW2) Dual Seven-segment Display (D4) Joint Test Action Group (JTAG) Connector (JP30)
9-Pin RS-232 Connector (J8)
5.0-V Power Supply Connector (J1) conf_done (D5) banks SRAM (U34, U37; U35, U36) 40-Pin Connectors Analog Devices converters (JP19, JP22) 8-pin Dipswitch (SW3) Power-on (D8) TI-EVM Connector (J12) (reverse side)
User-Defined LEDs (D6,
Table describes components board interfaces supports.
Table Stratix EP1S80 Development Board Components Interfaces (Part Component/ Interface
Components converters converters Mbytes SRAM Memory U10, U21, board 12-bit 125-MHz converters board 14-bit 165-MHz converters
Type
Board Designation
Description
U34, U35, U36, board MBytes 7.5-ns synchronous SRAM configured independent 36-bit buses.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table Stratix EP1S80 Development Board Components Interfaces (Part Component/ Interface
Mbits flash external clock input connectors external clock output connectors Dual seven-segment display DIPswitch Pushbutton switches User-defined LEDs Power-on conf_done RS-232 connector
Type
Memory Input Output Display Display Display Display
Board Designation
JP1, JP2, SW0, SW1,
Description
board Mbits flash memory. board connector inputs connected clocks, terminated board connector outputs with source impedance board dual seven-segment display. board eight switches, which user-definable logic inputs. board three pushbutton switches, which user-definable logic inputs. board user-definable LEDs. board that illuminates when power supplied board. board that illuminates upon successful configuration Stratix device. board connector, which configured serial port. interface voltages converted 3.3-V signals brought Stratix device, which must configured generate accept transmissions. board socked on-board 80-MHz oscillator. 5.0-V power supply board adapter included. board ninety general-purpose pins 0.1-inch headers JP8; JP7). Stratix pins that drive header also drive headers JP20, JP21, JP24. Similarly, Stratix pins that drive header also drive headers JP19, JP22.
On-board 80MHz oscillator Single 5.0-V power supply User pins
Clock Input
(adapter) JP7,
Debugging Interfaces Mictor connectors board Mictor headers, each connected Stratix pins data, clock) with external logic analyzer.
Expansion Interfaces Analog Devices connector TI-EVM connectors Expansion Expansion JP19, JP22 J11, board provides interface Analog Device's converters 40-pin connectors. board provides interface TI-EVM. connectors found reverse side board, shown Figure
Preliminary
Altera Corporation
Using Board
Table Stratix EP1S80 Development Board Components Interfaces (Part Component/ Interface
Altera Expansion Prototype Header FPDP Footprint Prototyping area
Type
Expansion Expansion Expansion
Board Designation
JP20, JP21, JP24
Description
board provides custom interface Altera expansion cards 74-pin header. Four rows pins comprise footprint FPDP, which added board. board provides grid plated through-holes 0.1-inch centers. Thirty Stratix pins connected grid.
Note Table
debug headers designated this table used interface Analog Devices converter evaluation boards. They designated JP19 JP22, interface Analog Devices AD6645/9433/9430 external converters. Note that JP19 JP22 headers share Stratix pins with JP7.
Environmental Requirements
Stratix EP1S80 development board must stored between -40° 100° recommended operating temperature between Stratix EP1S80 development board damaged without proper anti-static handling.
Using Board
When power applied board, Power illuminates. this time, Stratix device automatically configured and, upon successful configuration, conf_done illuminates. JP18 allows user load Stratix configuration images upon power-up. jumper JP18 present, factory configuration loads. jumper present, user configuration loads. "Non-Volatile Configuration" page more details.
configure board with design, designer should perform following steps, explained detail this section. Apply power board. Configure Stratix device.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Apply Power
Apply power board connecting 5.0-V power supply adapter, provided Development Kit, Stratix Professional Edition, connector (see Figure page board components draw power either directly from this 5.0-V supply, through 3.3-V 1.5-V regulators that powered from 5.0-V supply. 3.3-V supply provides VCCIO Stratix device LVTTL board components. 1.5-V supply provides VCCINT Stratix device.
When power applied board, Power (D8) illuminates. Stratix EP1S80 device, converters, board's heat sink become board used. Because their surface temperature significantly increase, touch these devices while there power applied board.
Configure Stratix Device Directly
configure Stratix device directly, without turning power, using Quartus® software ByteBlasterMV cable, follows. Attach cable JP30. Open Quartus SRAM Object File (.sof), which launches Quartus Programmer. Select ByteBlasterMV hardware. mode JTAG. Click Start.
successful configuration, conf_done (D5) illuminates.
instructions ByteBlasterMV cable, Quartus Help.
Preliminary
Altera Corporation
Non-Volatile Configuration
Non-Volatile Configuration
Stratix device SRAM-based, therefore, designer must reconfigure each time power applied Stratix development board. designers want power board have design immediately present Stratix device, board non-volatile configuration scheme. This scheme consists configuration controller (U4), which Altera EPM7064 PLD, flash memory. configuration controller device non-volatile (that does lose configuration data when board powered down) comes factory-programmed with logic that configures Stratix EP1S80B956C6 device (U2) from data stored flash (U3) power-up. Upon power-up, configuration controller begins reading data from flash memory. flash memory, Stratix device, configuration controller connected that data from flash configures Stratix device fast passive-parallel mode.
Configuration Data
Quartus software (optionally) produce Hexadecimal Output Files (.hexout) that suitable download storage flash memory configuration data. designer create .hexout file using Quartus version 4.2. software following ways:
Write .hexout compilation Convert .hexout
Write .hexout Compilation
project that Quartus software writes .hexout compilation, perform following steps: Choose Settings (Assignments menu). Click Device under Compiler Settings. Click Device Options. Click Programming Files tab. Turn Hexadecimal (Intel-Format) Output File (.hexout) option. With this option turned Quartus software generates .hexout successful compilation.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Convert .sof .hexout
designer convert .sof file into .hexout performing following steps Quartus software: Choose Convert Programming Files (File menu). Under Output programming file, choose Hexadecimal (IntelFormat) Output File SRAM (.hexout) from Programming file type list box. Specify output file name File name box. default output_file.hexout. Click Data under Input files convert. Click File. Browse .sof convert click Quartus software converts file saves output file directory specified. Intel-format .hexout contain data that actually written flash memory. Write2Flash executable file (provided <installation directory) parses .hexout creates .hexout.flash that contains data written flash memory. designer then send this file serially board RS-232 cable write flash memory factory configuration described "Factory User Configurations".
Factory User Configurations
configuration controller manage separate Stratix device configurations (.hexout) stored flash memory, user configuration factory configuration. Upon power-up configuration controller reads (user factory) configurations from flash memory into Stratix device. user select which configuration loads into Stratix device adding removing jumper JP18. jumper present JP18, controller configures Stratix device with user configuration. jumper removed, factory configuration loaded. factory-provided user configuration, which loads into flash JP18 jumper present power applied board, simple design that exercises seven segment display. Switches (SW1 SW2) board control what/how display exercised. either counts from loops illuminates edges seven segment display round-robin fashion. switches back
Preliminary Altera Corporation
Non-Volatile Configuration
forth between counter edge illuminations, controls speed counting illuminating, depending which currently running. This test design allows designer verify that board working correctly with user configuration. factory configuration contains design that allows designer write user configuration flash memory. download Quartus II-generated .hexout board, Altera-provided Write2Flash.exe utility, which located Flash_Programmer directory. This utility downloads .hexout development board PC's serial port. factory configuration loaded, writes .hexout flash memory. When jumper JP18 place power board cycled, user configuration read from flash memory written Stratix device. download user configuration into flash memory, perform following steps: Quartus software generate .hexout file described "Configuration Data" page Connect serial cable from board (note whether using Remove jumper JP18 present. Power board. factory configuration loaded Stratix device. seven segment display should read Press board erase previous user configuration from flash memory. seven-segment display should read actually counts backwards from value decimal) Depending fast configuration erases, counting. Write2Flash.exe utility <installation directory. Write2Flash user interface, select .hexout store flash memory user configuration.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Select appropriate port
Region Setting option must turned that have operating system with double byte code (DBCS), unicode characters. example, Microsoft Windows uses DBCS, instead ASCII, some language versions, including Chinese, Korean, Japanese.
Click Begin. Transmission begins takes about minutes. seven segment display counts when data transmission begins. counts digits Write2Flash utility reports that successfully downloaded .hexout.
Ensure that jumper JP18 place cycle power Stratix board. user configuration loaded Stratix device.
Preliminary
Altera Corporation
Functional Description
Functional Description
This section describes elements Stratix EP1S80 development board. Figure shows block diagram board and, mentioned earlier this data sheet, Figure page shows photograph board indicating names locations components interfaces. Figure Stratix EP1S80 Development Board Block Diagram
Converter Converter 256K SRAM
256K SRAM
Mictor Connector Converter Converter Stratix EP1S80 Device Analog Devices Converters Connector Prototyping Area Dual Seven-Segment Display TI-EVM Connector 0.1-inch Digital Headers
80-MHz Oscillator JTAG Connector
RS-232
LEDs Configuration Controller Mbit Flash External Clock Input External Clock Output Regulators Vccint (1.5 Vccio (3.3-V)
Switches
Pushbutton Switches
Power
12-layer development board eight signal layers four ground/VCC planes. board powered from single, well-regulated 5.0-V supply. Regulators board used develop VCCINT (1.5 VCCIO (3.3 voltages. board includes Power that indicates presence VCCIO.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
following board elements
LEDs Switches Crystal oscillator
Table presents specifications power supply, which connects from wall socket development board.
Table Power Supply Specifications Item
Board reference Part number Device description
Description
(power supply adapter) DTS050400UDC-P5-SZ Model EPA-201DA-05 5.0-VDC power supply Input: 45-60VA Output: 4A/20W www.cui.com
Manufacturer Manufacturer site
Stratix Device
EP1S80 device board features 79,040 logic elements (LEs) speed-grade (-6) 956-pin package. device 7,427,520 total bits.
more information Stratix devices, Stratix Programmable Logic Device Family Data Sheet. Table describes Stratix device features.
Table Stratix Device Features (Part Feature
Logic elements (LEs) M512 Blocks bits) Blocks (128 bits) M-RAM Blocks Total bits Blocks Embedded multipliers (based PLLs
EP1S80B956-6
79,040 7,427,520
Preliminary
Altera Corporation
Functional Description
Table Stratix Device Features (Part Feature
Maximum user pins Package type Board reference Voltage
EP1S80B956-6
956-pin 1.5-V internal, 3.3-V
Clocks Clock Distribution
Table lists clocks their signal distribution throughout board.
Table Clock Signal Distribution Signals Signal Name
CLK_DEBUGA CLK_DEBUGB CLK_TI_OUT/2 CLK_DTOA1_STRATIX CLK_DTOA2_STRATIX CLK_SRAM1 CLK_SRAM2 CLK_OPT_A2D CLK_OSC
Comes From
Stratix AL17 (PLL6_OUT_3n) Stratix (PLL5_OUT_3p) (TI-EVM connector) Stratix AL16 (PLL6_OUT_0n) Stratix AK16 (PLL6_OUT_0p) Stratix AK15 (PLL6_OUT_1p) Stratix AL15 (PLL6_OUT_1n) Stratix (PLL5_OUT_0p) 80-MHz oscillator
Goes
pins (Mictor pins (Mictor Stratix (CLK0p) JP26 (D/A1 converter) JP26 (D/A2 converter) (SRAM Bank (SRAM Bank JP23 Stratix (CLK14p) Stratix AL18 (CLK4p) JP23 JP26 pins Stratix (CLK15p) Stratix AJ18 (CLK5p) JP23 Stratix (CLK15n) Stratix AH18 (CLK5n) Stratix (CLK1P)
CLK_DTOA_SMA_IN CLK_SMA_IN1
JP25
CLK_SMA_IN2 CLK_SMA_OUT1 CLK_SMA_OUT2 CLK_EVALIO_IN44 CLK_EVALIO_OUT44
Note Table
Stratix (PLL5_OUT_2n) Stratix (PLL5_OUT_2p) Stratix AK17 (PLL6_OUT_3p)
JP23 controls which clock routed converters after passes through differential LVPECL buffer. Table page details.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Stratix EP1S80 development board obtain clock source from more following sources:
on-board crystal oscillator external clock (through connector Stratix pin)
board provide independent clocks from both enhanced fast PLLs converters, converters, other components that require stable clock sources. implement this concept, enhanced PLL5-dedicated pins drive converters associated functions, enhanced PLL6-dedicated pins drive converters associated functions. Figure diagram each clock their distribution throughout board. Figure Clock Distribution
CLK_SMA_IN1 CLK_SMA_IN1 CLK_SMA_IN2 CLK_SMA_IN2 CLK_TI_OUT/2 CLK_OSC Oscillator CLK_OSC CLK15p CLK5P CLK5n CLK15n CLK0p PLL5_OUT2p CLK14p CLK4p PLL5_OUT2n CLK_SRAM1 CLK_SRAM2 CLK_EVALIO_IN44 CLK_EVALIO_OUT44 JP25 CLK_DTOA_SMA_IN JP26 CLK_DTOA2 CLK_DTOA1 PLL6_OUT0p PLL6_OUT0n PLL5_OUT3n CLK_TI_OUT/2 PLL6_OUT1p PLL6_OUT1n PLL5_OUT3p CLK1P PLL6_OUT3p PLL6_OUT3n CLK_DEBUGB CLK_DEBUGA CLK_SMA_OUT2 CLK_SMA_OUT1 Stratix EP1S80 Device CLK_OSC PLL5_OUT0p CLK_OPT_ATOD A/D1CLK A/D2CLK JP23
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Altera Corporation
Board Components
Table lists reference information 80-MHz on-board oscillator.
Table 80-MHz On-Board Oscillator Reference Item
Board reference Part number Device description Manufacturer Manufacturer site ECS-2200B Oscillator Inc. www.ecsxtal.com
Description
Board Components
following sections describe development board components.
Switch Inputs
board eight switches three pushbutton switches, which user-definable logic inputs shown Table Each pushbutton signal defined logic when normal state; when pressed, becomes logic when released goes back logic switches drive logic Stratix device when position, logic into Stratix device when position.
Table Switch Pin-Outs Signal Name
Pushbuttons
Stratix
AF14 AK13 AK12
Switches
SW3p1 SW3p2 SW3p3 SW3p4 SW3p5 SW3p6 SW3p7 SW3p8
AK11 AK10
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Dual Seven-Segment Display LEDs
dual seven-segment display LEDs provided shown Table segments LEDs illuminate Stratix which they connected drives logic-0. They will appear unlit when Stratix which they connected drives logic-1.
Table Seven Segment Display Pin-Outs Signal Name
Dual Seven Segment Display
Stratix
HEX_0A HEX_0B HEX_0C HEX_0D HEX_0E HEX_0F HEX_0G HEX_0DP HEX_1A HEX_1B HEX_1C HEX_1D HEX_1E HEX_1F HEX_1G HEX_1DP
LEDs
LED0 LED1
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Altera Corporation
Board Components
Figure shows name allocation seven-segment display. Figure Pin-Out Diagram Dual Seven-Segment Display
HEX_0A HEX_0F HEX_0B HEX_1F HEX_1A HEX_1B
HEX_1G
HEX_0G
HEX_0D
HEX_0C
HEX_0E
HEX_0DP
HEX_1D
HEX_1C HEX_1DP
Serial Interface
board contains connector, which provides bidirectional RS-232C serial interface. board contains transceiver, however Stratix device must implement logic controller.Table describes device used implement RS-232C interface.
Table RS-232C Interface Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site None MAX221E RS-232 transceiver Maxim www.maxim-ic.com
HEX_1E
Description
Table shows pin-outs RS-232 interface.
Table RS-232 Serial Interface Pin-Out Signal Name
ROUT
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Converters
Stratix EP1S80 development board 12-bit converters that produce samples maximum rate million-samples second (MSPS). subsystem board following features:
data output format from each converter Stratix device two's complement format. circuit wideband, AC-coupled, differential input useful sampling. analog inputs transformer-coupled converter order create balanced input. maximize performance, transformers used series. Analog Devices data sheet AD9433 describes detailed operation this circuit. converters' analog inputs configured single-ended differential, with resistor (R28, R74). default configuration single-ended with resistor installed. required anti-aliasing filtering performed externally. needed, users purchase in-line filters from variety manufacturers, such Mini-Circuits (www.minicircuits.com). transformer-coupled circuit lower 3-dB frequency, approximately MHz. converter recommended analog bandwidths MHz.
clock signal that drives converters originate from Stratix device, external clock input, on-board 80-MHz oscillator. Jumper JP23 controls which clock used. Table provides explanation select these three clock signals. selected clock will pass through differential LVPECL buffer before arriving clock input both converters.
Table JP23 Clock Source Settings JP23 Setting
Pins Pins Pins
Clock Source
On-board 80-MHz oscillator Stratix connector
Signal Name
CLK_OSC CLK_OPT_ATOD CLK_SMA1_IN
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Altera Corporation
Board Components
Table lists reference information converters.
Table Converter Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site JP6, JP11 AD9433 12-bit, 125-MSPS converter 3.3-V digital VDD, 5.0-V analog Analog Devices www.analog.com
Description
Stratix Pin-Outs
Table Table show A/D1 (U10, JP6) A/D2 (U30, JP11) Stratix pin-outs.
Table (U10, JP6) Stratix Pin-Outs Signal Name
ATOD1_b0 (LSB) ATOD1_b1 ATOD1_b2 ATOD1_b3 ATOD1_b4 ATOD1_b5 ATOD1_b6 ATOD1_b7 ATOD1_b8 ATOD1_b9 ATOD1_b10 ATOD1_b11 (MSB)
Notes Table
least significant bit. most significant bit.
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table A/D2 (U30, JP11) Stratix Pin-Outs Signal Name
ATOD2_b0 (LSB) ATOD2_b1 ATOD2_b2 ATOD2_b3 ATOD2_b4 ATOD2_b5 ATOD2_b6 ATOD2_b7 ATOD2_b8 ATOD2_b9 ATOD2_b10 ATOD2_b11 (MSB)
Stratix
Converters
Stratix EP1S80 development board converters. subsystem board following features:
converters produce 14-bit samples maximum rate MSPS. analog output from each converter single-ended. converters expect data unsigned binary format.
clock signals output directly from Stratix device converters. Figure shows on-board circuitry after converter. output converter chip, DAC904, consists current source whose maximum value This output connected ground board using resistor, creating Thevenin equivalent voltage source series with resistor. When loaded with external termination, output swing reduced VPP. Additionally there 27-pF capacitor parallel with output resistor resulting single-pole, low-pass with upper 3-dB frequency approximately when externally loaded. output then brought connector through series capacitor, providing lower 3-dB frequency approximately 16-KHz when externally loaded. This output capacitor default, bypassed, resulting response down jumper removed, output AC-coupled.
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Altera Corporation
Board Components
Figure On-Board Circuitry after Converter
JP10
Converter
Output
contains SLP-50 anti-aliasing filter from Mini-Circuits. This filter provides 55-MHz cut-off frequency. systems with other bandwidth requirements, variety anti-aliasing filters available from commercial manufacturers suit system requirements.
Table shows reference information anti-aliasing filter. This filter included with development connected board.
Table Anti-Aliasing Filter Reference Item
Board reference Manufacturer Description Part number Manufacturer site Mini-circuits Anti-aliasing filter SLP-50 www.minicircuits.com
Description
Table lists reference information converters.
Table Converter Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site DAC904 14-bit, 165-MSPS converter 3.3-V digital VDD, 5.0-V analog Texas Instruments www.ti.com
Description
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
clocks convertor originate from either connector JP25 from Stratix device. JP26 controls this clock selection. Table
Table D/A1 JP26 Clock Source Settings JP26 Setting
Pins Pins
Clock Source
Stratix AL16 connector JP25
Signal Name
CLK_DTOA1_STRATIX CLK_DTOA_SMA_IN
Stratix Pin-Outs
Table Table show D/A1 (U21, D/A2 (U23, Stratix pin-outs.
Table D/A1 (U21, Stratix Pin-Outs Signal Name
DTOA1_b13 (MSB) DTOA1_b12 DTOA1_b11 DTOA1_b10 DTOA1_b9 DTOA1_b8 DTOA1_b7 DTOA1_b6 DTOA1_b5 DTOA1_b4 DTOA1_b3 DTOA1_b2 DTOA1_b1 DTOA1_b0 (LSB)
Note Table
Texas Instruments (TI) naming conventions differ from those Altera Corporation. data sheet converter lists LSB. naming consistency, this data sheet refers MSB, LSB.
Stratix
Preliminary
Altera Corporation
Board Components
Jumper range select converter jumper present, output DC-coupled. jumper removed, output AC-coupled.
Table shows D/A2 clock source settings.
Table D/A2 JP26 Clock Source Settings JP26 Setting
Pins Pins
Clock Source
Stratix AK16 connector JP25
Signal Name
CLK_DTOA2_STRATIX CLK_DTOA_SMA_IN
Table shows Stratix pin-outs.
Table D/A2 (U23, Stratix Pin-Outs Signal Name
DTOA2_b13 (MSB) DTOA2_b12 DTOA2_b11 DTOA2_10 DTOA2_b9 DTOA2_b8 DTOA2_b7 DTOA2_b6 DTOA2_b5 DTOA2_b4 DTOA2_b3 DTOA2_b2 DTOA2_b1 DTOA2_b0 (LSB)
Note Table
Texas Instruments (TI) naming conventions differ from those Altera Corporation. data sheet converter lists LSB. naming consistency, this data sheet refers MSB, LSB.
Stratix
Jumper JP10 range select Converter jumper present, output DC-coupled. jumper removed, output AC-coupled.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Memory
Stratix EP1S80 development board banks 7.5-ns synchronous SRAM, using four 18-bit wide memory chips. SRAM used independently, combined have 36-bit wide organization. support high data rates multiple concurrent processing, memory independent 36-bit wide memory buses. second component memory subsystem comprised single on-board 64-Mbit flash memory device.
SRAM
Table lists reference information SRAM memories.
Table Memory Reference Note Item
Board reference Part number Device description Manufacturer Manufacturer site Note Table
Periodically, SRAM devices from Alliance Corporation used. Both these devices pin-to-pin compatible with Cypress Semiconductor SRAM devices. equivalent Alliance part number AS7C33256PFS18A-TOC. equivalent part number 71V3578.
Description
U34, U35, U36, CY7C1325A 3.3V, 7.5-ns 128K SRAM Cypress Semiconductor www.cypress.com
Table lists characteristics SRAM memories board.
Table Memory Characteristics Type
SRAM SRAM
Address Lines
Data Lines
Memory Organization
256K 256K
Size (MB)
Preliminary
Altera Corporation
Memory
SRAM Bank
Table lists pin-outs SRAM Bank
Table SRAM Bank (U34, U35) (Part Signal Name
CLK_SRAM1 SRAM1_A0 SRAM1_A1 SRAM1_A2 SRAM1_A3 SRAM1_A4 SRAM1_A5 SRAM1_A6 SRAM1_A7 SRAM1_A8 SRAM1_A9 SRAM1_A10 SRAM1_A11 SRAM1_A12 SRAM1_A13 SRAM1_A14 SRAM1_A15 SRAM1_A16 SRAM1_A17 SRAM1_ADSC_n SRAM1_ADSP_n SRAM1_ADV_n SRAM1_D0 SRAM1_D1 SRAM1_D2 SRAM1_D3 SRAM1_D4 SRAM1_D5 SRAM1_D6 SRAM1_D7
AK15
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table SRAM Bank (U34, U35) (Part Signal Name
SRAM1_D8 SRAM1_D9 SRAM1_D10 SRAM1_D11 SRAM1_D12 SRAM1_D13 SRAM1_D14 SRAM1_D15 SRAM1_D16 SRAM1_D17 SRAM1_D18 SRAM1_D19 SRAM1_D20 SRAM1_D21 SRAM1_D22 SRAM1_D23 SRAM1_D24 SRAM1_D25 SRAM1_D26 SRAM1_D27 SRAM1_D28 SRAM1_D29 SRAM1_D30 SRAM1_D31 SRAM1_D32 SRAM1_D33 SRAM1_D34 SRAM1_D35 SRAM1A_BWE_n SRAM1A_CE2_n SRAM1A_OE_n SRAM1A_WEH_n SRAM1A_WEL_n
Stratix
Preliminary
Altera Corporation
Memory
Table SRAM Bank (U34, U35) (Part Signal Name
SRAM1B_BWE_n SRAM1B_CE2_n SRAM1B_OE_n SRAM1B_WEH_n SRAM1B_WEL_n MODE
Stratix
SRAM Bank consists devices U35. control signals denoted with "A," control signals denoted with "B." example, SRAM1A_OE_n output enable U34, SRAM1B_OE_n output enable U35. shown Figure data bits [17.0] U35, data bits [35.18] U34. address lines shared. Figure SRAM1 Data Bits
SRAM1_D16 SRAM1_D17 SRAM1_D18 SRAM1_D19 SRAM1_D20 SRAM1_D21 SRAM1_D34 SRAM1_D35
SRAM1_D0 SRAM1_D1 SRAM1_D2 SRAM1_D3 SRAM1_A0 SRAM1_A1 SRAM1_A2 SRAM1_A3 SRAM1_A16 SRAM1_A17
SRAM1_A0 SRAM1_A1 SRAM1_A2 SRAM1_A3 SRAM1_A16 SRAM1_A17
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
SRAM Bank
Table lists pin-outs SRAM bank
Table SRAM Bank Pin-Outs (U36, U37) (Part Signal Name
CLK_SRAM2 SRAM2_A0 SRAM2_A1 SRAM2_A2 SRAM2_A3 SRAM2_A4 SRAM2_A5 SRAM2_A6 SRAM2_A7 SRAM2_A8 SRAM2_A9 SRAM2_A10 SRAM2_A11 SRAM2_A12 SRAM2_A13 SRAM2_A14 SRAM2_A15 SRAM2_A16 SRAM2_A17 SRAM2_ADSC_n SRAM2_ADSP_n SRAM2_ADV_n SRAM2_D0 SRAM2_D1 SRAM2_D2 SRAM2_D3 SRAM2_D4 SRAM2_D5 SRAM2_D6 SRAM2_D7
AL15
Stratix
Preliminary
Altera Corporation
Memory
Table SRAM Bank Pin-Outs (U36, U37) (Part Signal Name
SRAM2_D8 SRAM2_D9 SRAM2_D10 SRAM2_D11 SRAM2_D12 SRAM2_D13 SRAM2_D14 SRAM2_D15 SRAM2_D16 SRAM2_D17 SRAM2_D18 SRAM2_D19 SRAM2_D20 SRAM2_D21 SRAM2_D22 SRAM2_D23 SRAM2_D24 SRAM2_D25 SRAM2_D26 SRAM2_D27 SRAM2_D28 SRAM2_D29 SRAM2_D30 SRAM2_D31 SRAM2_D32 SRAM2_D33 SRAM2_D34 SRAM2_D35 SRAM2C_BWE_n SRAM2C_CE2_n SRAM2C_OE_n SRAM2C_WEH_n SRAM2C_WEL_n
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table SRAM Bank Pin-Outs (U36, U37) (Part Signal Name
SRAM2D_BWE_n SRAM2D_CE2_n SRAM2D_OE_n SRAM2D_WEH_n SRAM2D_WEL_n MODE
Stratix
SRAM Bank consists chips U37. control signals denoted with "C," control signals denoted with "D." example, SRAM1C_OE_n output enable U36, SRAM1D_OE_n output enable U37. shown Figure data bits [17.0] U37, data bits [35.18] U36. address lines shared. Figure SRAM2 Data Bits
SRAM2_D16 SRAM2_D17 SRAM2_D18 SRAM2_D19 SRAM2_D20 SRAM2_D21 SRAM2_D34 SRAM2_D35 SRAM2_D0 SRAM2_D1 SRAM2_D2 SRAM2_D3 SRAM2_A0 SRAM2_A1 SRAM2_A2 SRAM2_A3 SRAM2_A16 SRAM2_A17
SRAM2_A0 SRAM2_A1 SRAM2_A2 SRAM2_A3 SRAM2_A16 SRAM2_A17
Preliminary
Altera Corporation
Memory
Flash Device Description
specifications pin-outs 64-Mbit flash memory device Stratix EP1S80 development board given this section. Table gives details specifications manufacturer flash memory device.
Table Flash Memory Device Reference Feature
Board reference Part number Device description Voltage Manufacturer Manufacturer site AM29DL640D Mbit flash memory 3.3-V www.amd.com
Flash Memory
Flash Pin-Outs
Table lists pin-outs flash memory device.
Table Flash Pin-Outs (Part Signal Name
Flash_addr1 Flash_addr2 Flash_addr3 Flash_addr4 Flash_addr5 Flash_addr6 Flash_addr7 Flash_addr8 Flash_addr9 Flash_addr10 Flash_addr11 Flash_addr12 Flash_addr13 Flash_addr14
AJ26 AJ25 AJ24 AJ23 AJ22 AJ21 AJ20 AJ19 AH27 AJ30 AJ29 AJ28 AJ27
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table Flash Pin-Outs (Part Signal Name
Flash_addr15 Flash_addr16 Flash_addr17 Flash_addr18 Flash_addr19 Flash_addr20 Flash_addr21 Flash_addr22 Flash_byte_n Flash_CS_n Flash_data0 Flash_data1 Flash_data2 Flash_data3 Flash_data4 Flash_data5 Flash_data6 Flash_data7 Flash_data8 Flash_data9 Flash_data10 Flash_data11 Flash_data12 Flash_data13 Flash_data14 Flash_data15 Flash_OE_n Flash_R/W_n Flash_rdy/bsy_n Flash_reset_n
AH30 AH28 AH26 AH25 AG30 AK29 AK28 AK27 AK26 AK25 AK24 AK23 AK22 AK21
Stratix
Preliminary
Altera Corporation
Debugging Interfaces
Table Flash Pin-Outs (Part Signal Name
Flash_WP_ACC_n
Notes Table
Flash address connected jumper JP18. this jumper place, signal Flash_addr22 pulled down GND. connector removed, Flash_addr22 pulled VCCIO. Stratix AG30 over-power pull-up pull-down. Flash_data15 doubles flash address when flash byte mode.
Stratix
Debugging Interfaces
Stratix EP1S80 development board following interfaces allow users debug their designs:
Mictor-type connectors support Agilent logic analyzers digital signals, available 0.1-inch headers, connected directly Stratix device
Logic Analyzer Interface (Mictor Connectors)
Stratix EP1S80 development board Mictor-type connectors support Agilent logic analyzers, high-speed off-board solution.
Mictor Connector
Table provides pin-outs Mictor connector
Table Mictor Connector (J9) Stratix Pin-Outs (Part Signal Name
DEBUG_A0 DEBUG_A1 DEBUG_A2 DEBUG_A3 DEBUG_A4 DEBUG_A5 DEBUG_A6 DEBUG_A7 DEBUG_A8 DEBUG_A9
AA24 AA25 AA26 AA27 AA28 AC19 AC20 AC21
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table Mictor Connector (J9) Stratix Pin-Outs (Part Signal Name
DEBUG_A10 DEBUG_A11 DEBUG_A12 DEBUG_A13 DEBUG_A14 DEBUG_A15 DEBUG_A16 DEBUG_A17 DEBUG_A18 DEBUG_A19 DEBUG_A20 DEBUG_A21 DEBUG_A22 DEBUG_A23 DEBUG_A24 DEBUG_A25 DEBUG_A26 DEBUG_A27 DEBUG_A28 DEBUG_A29 DEBUG_A30 DEBUG_A31 CLK_DEBUGA
AC22 AC24 AC25 AC26 AC27 AD19 AD20 AD21 AD22 AD24 AD25 AD26 AD27 AD28 AD29 AA21 AH13 AH12 AC13 AC12 AL17
Stratix
Mictor Connector
Table gives pin-outs Mictor connector
Table Mictor Connector (J10) Stratix Pin-Outs (Part Signal Name
DEBUG_B0 DEBUG_B1 DEBUG_B2
AF15 AF13
Stratix
Preliminary
Altera Corporation
Debugging Interfaces
Table Mictor Connector (J10) Stratix Pin-Outs (Part Signal Name
DEBUG_B3 DEBUG_B4 DEBUG_B5 DEBUG_B6 DEBUG_B7 DEBUG_B8 DEBUG_B9 DEBUG_B10 DEBUG_B11 DEBUG_B12 DEBUG_B13 DEBUG_B14 DEBUG_B15 DEBUG_B16 DEBUG_B17 DEBUG_B18 DEBUG_B19 DEBUG_B20 DEBUG_B21 DEBUG_B22 DEBUG_B23 DEBUG_B24 DEBUG_B25 DEBUG_B26 DEBUG_B27 DEBUG_B28 DEBUG_B29 DEBUG_B30 DEBUG_B31 CLK_DEBUGB
AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF10 AE28 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AE14 AE13 AE12
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
0.1-Inch Digital Headers
board total digital signals, available 0.1-inch headers, connected directly Stratix device. Additionally, connectors contain ground signals ensure integrity signals, provide Analog Devices external connectors. matched pair right-angle connectors, which allow user join boards connecting connector board connector second. Stratix pins connected JP19 also connected JP7. Similarly, Stratix pins which drive also drive JP20, JP21, JP24. Table Table details which Stratix pins connected both places. When connecting these pins external circuitry, user must adhere voltage restrictions specified Stratix Programmable Logic Device Family Data Sheet. Specifically, pins 5.0-V tolerant should directly connected logic powered from 5.0-V supply.
Digital Headers (JP7, JP19, JP22)
Table shows pin-outs digital headers JP7, JP19, JP22.
Table Digital Headers (JP7, JP19, JP22) (Part Signal Name
EVALIO_IN0 EVALIO_IN1 EVALIO_IN2 EVALIO_IN3 EVALIO_IN4 EVALIO_IN5 EVALIO_IN6 EVALIO_IN7 EVALIO_IN8 EVALIO_IN9 EVALIO_IN10 EVALIO_IN11
Stratix
JP19
JP22
Preliminary
Altera Corporation
Debugging Interfaces
Table Digital Headers (JP7, JP19, JP22) (Part Signal Name
EVALIO_IN12 EVALIO_IN13 EVALIO_IN14 EVALIO_IN15 EVALIO_IN16 EVALIO_IN17 EVALIO_IN18 EVALIO_IN19 EVALIO_IN20 EVALIO_IN21 EVALIO_IN22 EVALIO_IN23 EVALIO_IN24 EVALIO_IN25 EVALIO_IN26 EVALIO_IN27 EVALIO_IN28 EVALIO_IN29 EVALIO_IN30 EVALIO_IN31 EVALIO_IN32 EVALIO_IN33 EVALIO_IN34 EVALIO_IN35 EVALIO_IN36 EVALIO_IN37 EVALIO_IN38 EVALIO_IN39 EVALIO_IN40 EVALIO_IN41 EVALIO_IN42 EVALIO_IN43
Stratix
AG13
JP19
JP22
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table Digital Headers (JP7, JP19, JP22) (Part Signal Name
CLK_EVALIO_IN44
Notes Table
Pins which listed, tied ground. Pins which listed, tied ground. Pins which listed, tied ground.
Stratix
JP19
JP22
Preliminary
Altera Corporation
Debugging Interfaces
Digital Headers (JP20, JP21, JP24, JP8)
Table lists pin-outs digital headers JP20, JP21, JP24, JP8.
Table Digital Headers (JP20, JP21, JP24, JP8) (Part Signal Name
EVALIO_OUT0 EVALIO_OUT1 EVALIO_OUT2 EVALIO_OUT3 EVALIO_OUT4 EVALIO_OUT5 EVALIO_OUT6 EVALIO_OUT7 EVALIO_OUT8 EVALIO_OUT9 EVALIO_OUT10 EVALIO_OUT11 EVALIO_OUT12 EVALIO_OUT13 EVALIO_OUT14 EVALIO_OUT15 EVALIO_OUT16 EVALIO_OUT17 EVALIO_OUT18 EVALIO_OUT19 EVALIO_OUT20 EVALIO_OUT21 EVALIO_OUT22 EVALIO_OUT23 EVALIO_OUT24 EVALIO_OUT25 EVALIO_OUT26 EVALIO_OUT27 EVALIO_OUT28 EVALIO_OUT29
Stratix
AA31 AA30 AB30 AB31
JP20(1) JP21 JP24
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table Digital Headers (JP20, JP21, JP24, JP8) (Part Signal Name
EVALIO_OUT30 EVALIO_OUT31 EVALIO_OUT32 EVALIO_OUT33 EVALIO_OUT34 EVALIO_OUT35 EVALIO_OUT36 EVALIO_OUT37 EVALIO_OUT38 EVALIO_OUT39 EVALIO_OUT40 EVALIO_OUT41 EVALIO_OUT42 EVALIO_OUT43 CLK_2p
Stratix
AC31 AC30 AD31 AD30 AE31 AE30 AF31 AE29 AG29 AF30 AF29 AG28 AG27 AH29
JP20(1) JP21 JP24
CLK_EVALIO_OUT44 AK17
Notes Table
Pins which listed, tied ground. Pins through which listed, tied ground. Even-numbered pins tied ground. tied +5.0 V-VCC. Pins tied +3.3 V-VCC. Pins open. Pins which listed, tied ground. Pins which listed, tied ground.
Expansion Interfaces
There five ways which Stratix EP1S80 development board designed interface with other boards devices. board equipped with following interfaces:
TI-EVM, located underside board (J11, J12) Front Panel Data Port (FPDP) Footprint (J4) 0.1-inch headers specifically designed used with external analog-to-digital devices made Analog Devices Corporation (JP19, JP22) Altera expansion prototype connector breadboard/prototype area that allows connection custom components
Preliminary
Altera Corporation
Expansion Interfaces
TI-EVM
TI-EVM specifically designed work with boards that have interface. Texas Instruments site details which their boards feature this connector. portion Stratix pins routed TI-EVM connector (J11, J12) also routed four rows through-holes, labeled These four rows pins comprise footprint FPDP, which added board.
TI-EVM Connector FPDP Connector
Table lists pin-outs TI-EVM FPDP connectors.
Table TI-EVM Connector (J11, J12) FPDP Connector (J4) (Part TI-EVM Signal Name
FPDP Signal Name
AG25 AG24 AG22 AG14 AG23 AG21 AG20 AG19
Stratix
TI_CLKX0 TI_FSX0 TI_CLKR0 TI_FSR0 TI_STAT0 TI_DRO CLK_TI_OUT2 TI_DMAC0 TI_CNTL0 TI_INUM0 TI_IACK TI_DX0
TI_ARDY TI_CE1_N TI_AOE_N TI_AWE_N TI_ARE_N TI_A2 TI_A3 TI_A4
AG12 AH24 AH23 AH22
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table TI-EVM Connector (J11, J12) FPDP Connector (J4) (Part TI-EVM Signal Name
TI_A5 TI_A6 TI_A7 TI_A8 TI_A9 TI_A10 TI_A11 TI_A12 TI_A13 TI_A14 TI_A15 TI_A16 TI_A17 TI_A18 TI_A19 TI_A20 TI_A21 TI_BE_N0 TI_BE_N1 TI_BE_N2 TI_BE_N3 TI_D0 TI_D1 TI_D2 TI_D3 TI_D4 TI_D5 TI_D6 TI_D7 TI_D8 TI_D9 TI_D10 TI_D11
FPDP Signal Name
AH21 AH20 AH19 AH16 AH10 AH11 AG10 AG11 AJ10 AK20 AJ11 AJ12
Stratix
FPDP_D0 FPDP_D1 FPDP_D2 FPDP_D3 FPDP_D4 FPDP_D5 FPDP_D6 FPDP_D7 FPDP_D8 FPDP_D9 FPDP_D10 FPDP_D11
Preliminary
Altera Corporation
Expansion Interfaces
Table TI-EVM Connector (J11, J12) FPDP Connector (J4) (Part TI-EVM Signal Name
TI_D12 TI_D13 TI_D14 TI_D15 TI_D16 TI_D17 TI_D18 TI_D19 TI_D20 TI_D21 TI_D22 TI_D23 TI_D24 TI_D25 TI_D26 TI_D27 TI_D28 TI_D29 TI_D30 TI_D31
FPDP Signal Name
FPDP_D12 FPDP_D13 FPDP_D14 FPDP_D15 FPDP_D16 FPDP_D17 FPDP_D18 FPDP_D19 FPDP_D20 FPDP_D21 FPDP_D22 FPDP_D23 FPDP_D24 FPDP_D25 FPDP_D26 FPDP_D27 FPDP_D28 FPDP_D29 FPDP_D30 FPDP_D31 FPDP_STROB FPDP_NRDY_N FPDP_DIR_N FPDP_SUSPEND_N FPDP_P102 FPDP_P101 FPDP_STROBE_N FPDP_PSTROBE FPDP_DVALID_N FPDP_SYNC_N
AA29 AC28 AC29 AB24 AB25 AB26 AB27 AB28 AB29 AJ17 AH16
Stratix
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Analog Devices Corporation External Support
Stratix EP1S80 development board supports Analog Devices converters 40-pin 0.1-inch digital headers (JP19, JP22). Analog Devices converters also require clock, which sourced from CLK_SMAOUT1 (JP2) CLK_SMAOUT2 (JP4) external clock outputs. These dual-purpose digital headers support maximum following three converters.
AD9433 converters AD6645 converters AD9430 converter Stratix pins connected JP19 also connected JP7. Similarly, Stratix pins that drive also drive JP20, JP21, JP24. Table page Table page details which Stratix pins connected both places.
Altera Expansion Prototype Connector
Headers JP20, JP21, JP24 collectively form standard-footprint, mechanically-stable connection that used (for example) interface special-function daughter card. Contact your Altera sales representative list available expansion daughter cards that used with Stratix EP1S80 development board.
3.3-V expansion prototype connector interface includes following.
Stratix device general-purpose signals Stratix device clock-input (for daughter cards that drive clock programmable logic device) regulated 3.3-V power-supply pins (500 total maximum load) unregulated power-supply (connects directly powerinput plug) Numerous ground connections Stratix pins that drive also drive JP20, JP21, JP24. Table page Table page details which Stratix pins connected both places.
Preliminary
Altera Corporation
Expansion Interfaces
JP20, JP21, JP24 Connector Pin-Outs
Figure shows relative orientation connectors pins JP20, JP21, JP24. Figure Pin-Outs Headers JP20, JP21, JP24
JP24 AA31 AA30 AB30
(T29)
JP20 AC30 AD30 AB31 AE30 AE29 AF30
JP21 AG27 AH29
AC31
AD31
AE31
AF31 AG29
Vunreg
3.3-V
Prototyping Area
prototyping area board provides room adding user-selected electronic components. This area grid plated through-holes 0.1inch centers. Thirty Stratix pins connected inside column (the column closest middle board) pins grid. These pins, each column, labeled board easy identification. shown Table column ground pins column VCCIO pins provide power grid. remaining columns (labeled board) connected power pins, available addition custom components.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Table shows column functions prototyping area board.
Table Column Functions Prototyping Area Column
Unconnected Unconnected VCCIO (3.3 Unconnected Unconnected Unconnected
Function
Stratix pins (see Table
Prototyping Area Pin-Out
Table shows pin-outs prototyping area Stratix EP1S80 development board.
Table Prototyping Area Pin-Outs (Part Signal Name
PROTO1 PROTO2 PROTO3 PROTO4 PROTO5 PROTO6 PROTO7 PROTO8 PROTO9 PROTO10 PROTO11 PROTO12 PROTO13 PROTO14 PROTO15 PROTO16 PROTO17
AL28 AL27 AL26 AL25 AL24 AL23 AL10
Stratix
Preliminary
Altera Corporation
Expansion Interfaces
Table Prototyping Area Pin-Outs (Part Signal Name
PROTO18 PROTO19 PROTO20 PROTO21 PROTO22 PROTO23 PROTO24 PROTO25 PROTO26 PROTO27 PROTO28 PROTO29 PROTO30
AL12
Stratix
Jumper Settings
Table summarizes jumper settings Stratix EP1S80 development board.
Table Jumper Settings Number
Function
D/A1 AC/DC coupling select
Setting
Jumpered Jumpered
Selected Option
Coupled Coupled Coupled Coupled 80-MHz oscillator Stratix External Clock Flash Address Flash Address JP25 Stratix AL16 JP25 Stratix AK16
JP10
D/A2 AC/DC coupling select
Jumpered Jumpered
JP23
clock select
JP18 C48)
Flash top/bottom select
Jumpered Jumpered
JP26, pins
D/A1 clock select.
JP26, pins
clock select.
Altera Corporation
Preliminary
Stratix EP1S80 Development Board
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com
Copyright 2004 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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Stratix® EP1S80 development board included with Development Kit, Strat

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