Stratix® EP2S60 development board included with Development Kit, Strat
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Stratix EP2S60 Development Board
Stratix® EP2S60 development board included with Development Kit, Stratix Edition (ordering code DSP-DEVKIT-2S60). This board development platform high-performance digital signal processing (DSP) designs, features Stratix EP2S60 device 1020-pin package.
Components
Analog 12-bit 125-MHz converters 14-bit 165-MHz converters 8-bit, megapixels-per-second triple converter output 96-KHz Stereo Audio coder/decoder (CODEC) Memory subsystem MByte 10-ns asynchronous SRAM configured 32-bit MBytes flash memory configured 8-bit MBytes SDRAM memory configured 64-bit CompactFlash connector supporting access modes Configuration options On-board configuration using MBytes flash memory Altera® EPM7256 MAX® device Download configuration data using Blasterdownload cable Single-ended differential inputs outputs accessed Mictor connector Dual seven-segment display Four user-defined push-button switches female 9-pin RS-232 connector 10/100 Ethernet MAC/PHY Eight user-defined LEDs Socketed 100-MHz oscillator Single 16-V power supply (adapter included) Active heat sink
Altera Corporation DS-S29804-1.1
Preliminary
Stratix EP2S60 Development Board
Debugging Interfaces
Mictor-type connector Agilent Tektronix logic analyzers Several 0.1-inch headers
Expansion Interfaces
connectors Analog Devices converter daughter cards Connector Texas Instruments Evaluation Module (TI-EVM) daughter cards Expansion Prototype connectors
General Description
Stratix EP2S60 development board provides hardware platform that designers start developing systems based Stratix devices. Combined with intellectual property (IP) from Altera Altera Megafunction Partners Program (AMPPSM) partners, users quickly develop powerful systems. Altera's unique OpenCore® Plus technology allows users evaluate MegaCore® functions hardware prior licensing them. Builder, version includes library Stratix EP2S60 development board. This library allows algorithm development, simulation, verification board, from within MathWorks MATLAB/Simulink system-level design tool. Additionally, Stratix development board includes Texas Instruments' (crossplatform) daughter card connector, which enables development verification FPGA co-processors loading accelerating compute-bound algorithms from programmable processors.
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General Description
Components Interfaces
Figure shows view board components interfaces. Figure Stratix EP2S60 Development Board Components Interfaces
External Clock Input (J12) External Clock Inputs (J10, J11) Connector (J35) 40-Pin Connectors Analog Devices Converters (J5, Converter Clock Selector (J3, Power Regulator (U22) Input Connector (J1) 9-Pin RS-232 Connector (J9) Socketed 100-MHz Oscillator (Y1) Mictor Connector (J20) Joint Test Action Group (JTAG) Connectors (J21, J13) 8-Pin Switch (SW2) 16.0-V Power Supply Connector (J22)
Input Connector (J2) Output Connector (J15) Output Connector (J17) Line (J7) Line (J8) Amplified Line Audio Connector (J9)
Expansion Prototype Connector (J23, J24, J25)
Configuration-Status LEDs (LED1-LED4)
Expansion Prototype Connector (J26, J27, J28)
Dual Seven-segment Display (U12, U13) Converter Clock Selector (J18 J19) Compact Flash (CON1) Reverse Side Board) Power Switch (SW9) Ethernet (RJ-45) Connector (RJ1) User LEDs (D1-D8) CONF_DONE (LED5) User Push-button Switches (SW4, SW5, SW6, SW7)
Note Figure
TI-EVM/FPDP connector (J31, J33) found reverse side board.
Altera Corporation
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Stratix EP2S60 Development Board
Table describes components board interfaces supports.
Table Stratix EP2S60 Development Board Components Interfaces (Part Component/ Interface Components
Stratix device Device converters converters MByte SRAM MBytes flash memory MBytes SDRAM external clock input connectors FPGA Memory Memory Memory Input U14, U43, U39, J10, J11, U12, SW4, SW5, SW6, LED7 LED5 EP2S60 Stratix device
Type
Board Designation
Description
EPM7256ETC144 device
12-bit 125-MHz converters 14-bit 165-MHz converters MByte 10-ns asynchronous SRAM configured 32-bit bus. Mbytes flash memory configured 8-bit bus. MBytes SDRAM memory configured 64-bit connectors inputs external clock signals, terminated Dual seven-segment display. Four push-button switches, which user-defined logic inputs. Eight user-defined LEDs. that illuminates when power supplied board. that illuminates upon successful configuration Stratix device. connector, configured serial port. interface voltages converted 3.3-V signals brought Stratix device, which must configured generate accept transmissions. Socketed on-board 100-MHz oscillator. Board adapter included 16-V power supply JTAG Connector used configure Stratix device directly JTAG connector used configure configuration controller
Dual seven-segment Display display Push-button switches User-defined LEDs Power-on CONF_DONE RS-232 connector Display Display Display
100-MHz oscillator Single 16-V power supply
Clock Input
(adapter)
Stratix device Joint Test Action Group (JTAG) Connector Configuration controller JTAG Connector
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General Description
Table Stratix EP2S60 Development Board Components Interfaces (Part Component/ Interface
Converter Audio CODEC CompactFlash card connector
Type
Board Designation
CON1
Description
8-bit, megapixels-per-second triple converter output 96-KHz stereo audio CODEC CompactFlash card connector
Debugging Interfaces
Mictor connectors Mictor header connected pins Stratix device data signals, clock signal) with external logic analyzer.
Expansion Interfaces
Analog Devices connector TI-EVM connectors Expansion Expansion J31, J25, Interface Analog Device's converters 40-pin connectors. Interface TI-EVM. (The connectors reverse side board.) board provides custom interfaces daughter cards 74-pin headers. (These pins also used general I/O.) These connectors referred board "Santa Cruz Daughter Card "Santa Cruz Daughter Card Note Table
These headers used interface Analog Devices converter evaluation boards. They designated interface Analog Devices AD6645/9433/9430 external converters.
Expansion Prototype Expansion Connectors
Environmental Requirements
Stratix EP2S60 development board must stored between -40° 100° recommended operating temperature between Stratix EP2S60 development board damaged without proper anti-static handling.
Development Kit, Stratix Edition includes heat sink combination, also known active heat sink. Depending specific requirements your application, this level cooling necessary. Refer "Install Active Heat Sink" page more information.
Altera Corporation
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Stratix EP2S60 Development Board
Using Board
When power applied board "ON" position, Power-on (LED7) illuminates. that time, device (U10) programs Stratix device (U18) from flash memory spaces reserved configuration information. configuration successful, CONF_DONE (LED5) illuminates. Stratix device programmed with design user configuration memory spaces using JTAG connector (J21), both CONF_DONE (LED5) USER (LED1) illuminate. more information, refer "Configuration-Status LEDs" page
configure board with design, designer should perform following steps, explained detail this section. Apply power board. Re-configure Stratix device.
Apply Power
Apply power board connecting 16-V power supply adapter, provided Development Kit, Stratix edition, on-board power adapter connector (J22), switching position. board components draw power either directly from this 16-V supply from 3.3-V, 1.2-V, regulators that powered 16-V supply. 3.3-V supply provides VCCIO Stratix device LVTTL board components. 1.2-V supply provides VCCINT Stratix device.
When power applied board, Power (LED7) illuminates. Stratix EP2S60 device, converters, power regulator become board used. Because their surface temperature significantly increase, touch these devices while power applied board.
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Non-Volatile Configuration
Configure Stratix Device Directly
configure Stratix device directly, without turning power, using Quartus® software Blaster cable, follows. Attach cable J21, also labeled "JTAG Stratix II". Open Quartus SRAM Object File (.sof), which starts Quartus Programmer. Select Blaster hardware. mode JTAG. Click Start.
After successful configuration, CONF_DONE (LED5) illuminates.
Non-Volatile Configuration
Refer Quartus Help instructions Blaster cable. designer must reconfigure Stratix device each time power applied Stratix development board. designers want power board have design immediately present Stratix device, board non-volatile configuration scheme. This scheme consists configuration controller (U10), which Altera EPM7256 PLD, flash memory. configuration controller device non-volatile (i.e., does lose configuration data when board powered down) comes factory-programmed with logic that configures Stratix EP2S60F1020C4 device (U18) from data stored flash (U17) power-up. Upon power-up, configuration controller begins reading data from flash memory. flash memory, Stratix device, configuration controller connected that data from flash configures Stratix device fast passive-parallel mode.
Altera Corporation
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Stratix EP2S60 Development Board
Configuration Data
Quartus software produce Hexadecimal (Intel format) Output (.hexout) files suitable download storage flash memory configuration data. designer create HEXOUT file using Quartus software following ways:
Create HEXOUT file compilation Convert SRAM Object File (.sof) HEXOUT file.
Write HEXOUT file Compilation
project that Quartus software writes HEXOUT file compilation, perform following steps: Choose Settings (Assignments menu). Click Device under Compiler Settings. Click Device Options. Click Programming Files tab. Turn Hexadecimal (Intel-Format) Output File (.hexout) option. With this option turned Quartus software generates .hexout successful compilation.
Convert HEXOUT File
designer convert HEXOUT file performing following steps Quartus software: Choose Convert Programming Files (File menu). Under Output programming file, choose Hexadecimal (IntelFormat) Output File SRAM (.hexout) from Programming file type list box. Specify output file name File name box. default output_file.hexout. Click Data under Input files convert. Click File. Browse convert click Quartus software converts file saves output file specified directory.
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Non-Volatile Configuration
Intel-format HEXOUT files contain data that actually written flash memory. Write2Flash executable file (provided <installation directory>/utilities/ Flash_Programmer directory) parses HEXOUT file creates file with extension .hexout.flash that contains data written flash memory. designer then send this file serially board RS-232 cable write flash memory factory configuration described next section.
Factory User Configurations
configuration controller manage four separate Stratix device configurations HEXOUT data stored flash memory: three user designs factory design. power-up, configuration controller reads four (user factory) designs from flash memory programs Stratix device accordingly. user select which design Stratix device programmed with setting switches SW2. switches through select four possible Stratix configuration images upon power-up. When switch "OPEN" position configuration controller enabled. switch "OPEN" position there valid user-defined images, Stratix device programmed with factory configuration. Table shows switch combinations used select available images. "Non-Volatile Configuration" page more details. alternative method configuring device with factory design press push-button switch SW3.
Table Configuration Switch (SW2) Combinations Image
User0 User1 User2 Factory
Switch
Closed Open Closed Open
Switch
Closed Closed Open Open
Switch
Closed Closed Closed Open
Switch
Open Open Open Open
Switch must "OPEN" enable configuration controller.
download Quartus II-generated HEXOUT file flash memory board, refer Nios Flash Programmer User Guide included Development Kit, Stratix Edition CD-ROM.
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Stratix EP2S60 Development Board
Factory Design
When Stratix device programmed with factory design, LEDs through behave binary counter that counts down zero. This power-up indication that board functional device successfully programmed with factory design. Along with counter, factory design includes blocks generated Altera Compiler. these oscillators running times frequency other, both them have same amplitude, covering bits dynamic range. sine waves generated these blocks added together output converted from complement representation into unsigned integer format. This combined sine wave signal 14-bits dynamic range sent 14-bit converter. When analog output converter connected, included cable, with analog input 12-bit converters, converter's digital output looped back Stratix device. design converts this loopback input from complement format unsigned integer format. converted loopback data captured instance SignalTap® logic analyzer design display analysis.
step-by-step instructions factory design test functionality board, refer Development Kit, Stratix Edition Getting Started User Guide.
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Non-Volatile Configuration
Functional Description
This section describes elements Stratix EP2S60 development board. Figure shows block diagram board. Figure Stratix EP2S60 Development Board Block Diagram
Converter Converter 256K SRAM
256K SRAM
Mictor Connector Converter Converter Stratix EP2S60 Device Analog Devices Converters Connector Prototyping Area Dual Seven-Segment Display TI-EVM Connector 0.1-inch Digital Headers
80-MHz Oscillator JTAG Connector
RS-232
LEDs Configuration Controller Mbit Flash External Clock Input External Clock Output Regulators Vccint (1.5 Vccio (3.3-V)
Switches
Pushbutton Switches
Power
16-layer development board signal layers ground/VCC planes. board powered from single, well-regulated 16-V supply. Regulators board used develop VCCINT (1.2 VCCIO (3.3 VCC5 (5.0 voltages. board includes Power-on that indicates presence VCCIO. following board elements powered supply:
LEDs Switches Crystal oscillator
Altera Corporation
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Stratix EP2S60 Development Board
Table lists reference information 16-V power supply, which connects from wall socket development board.
Table Power Supply Specifications Item
Board reference Part number Device description Description (power supply adapter) TR9KT3750LCP-Y Switching power supply, Input: 100-240 ~1.2 max., 50-60 Output: 3.75 max. GlobTek Inc. www.globtek.com
Manufacturer Manufacturer site
Clocks Clock Distribution
Table lists clocks their signal distribution throughout board.
Table Clock Distribution Signals (Part Signal Name
dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 dac_PLLCLK2_n sdram_CLK adc_PLLCLK1 adc_PLLCLK2 audio_CLK pld_MICTORCLK pld_CLKOUT
Comes From
Stratix device (PLL5_OUT0p) Stratix device (PLL5_OUT0n) Stratix device (PLL5_OUT1p) Stratix device (PLL5_OUT1n)
Goes
(U14 (U14 (U15 (U15
Stratix device AK16 SDRAM (U39 pins (PLL6_OUT0p) Stratix device (PLL11_OUT0p) Stratix device D18(PLL11_OUT0n) Stratix device AL18(PLL12_OUT0p) Stratix device Stratix device pins pins Audio CODEC Mictor Connector (J20 PROTO1 (J25 PROTO2 (J28 buffer (U7)
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Non-Volatile Configuration
Table Clock Distribution Signals (Part Signal Name
pld_CLKIN0,pld_CLK pld_CLKIN0_n,pld_C LKIN1_n proto1_OSC, proto2_OSC cpld_CLKOSC adc_CLK_IN1, adc_CLK_IN2 dac_CLKIN1, dac_CLKIN2 pld_CLKFB adc_CLK_IN1_n, adc_CLK_IN2_n dac_DACCLKIN1, dac_DACCLKIN2 pld_DACCLKIN proto1_CLKOUT, proto2_CLKOUT Notes Table
control which clock routed converters. Table details. control which clock routed converters. Table details.
Comes From
100-MHz oscillator External CLKIN_n input (J11) 100-MHz oscillator
Goes
Stratix device pins AM17 Stratix device pins AL17 PROTO1 (J25 PROTO2 (J28 buffer (U7) CPLD (U10 125) pins pins (U14 (U15
100-MHz oscillator 100-MHz oscillator 100-MHz oscillator
pld_CLKOUT signal from Stratix device Stratix External CLKIN_n input (J11) External DA_EXT_CLK input (J12) External DA_EXT_CLK input (J12) pins pins (U14 (U15 Stratix device
Stratix device pins PROTO1 (J25 PROTO2 (J28 buffer (U7)
Stratix EP2S60 development board obtain clock source from more following sources:
on-board crystal oscillator external clock (through connector Stratix pin)
board provide independent clocks from both enhanced fast PLLs converters, converters, other components that require stable clock sources. implement this concept, enhanced PLL5-dedicated pins drive converters associated functions, enhanced PLL6-dedicated pins drive converters associated functions.
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Stratix EP2S60 Development Board
Figure diagram each clock their distribution throughout board. Figure Clock Distribution
100-MHz Oscillator Configuration Controller Expansion Prototype Connector
Clock Distribution
Clock Distribution
Expansion Prototype Connector
CLK_IN_p
SDRAM
Stratix EP2S60F1020C4 Device
Audio CODEC
CLK_IN_n Clock Distribution
Jumper
Buffer
Jumper DA_EXT_CLK Clock Distribution Jumper
Buffer
Jumper
Table lists reference information 100-MHz socketed oscillator.
Table 100-MHz Socketed Oscillator Reference Item
Board reference Part number Device description Manufacturer Manufacturer site ECS-UPO-8PIN 100MHz Oscillator Inc. www.ecsxtal.com
Description
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Board Components
Clock Distribution source either oscillator (Y1) external clock inserted using J10. external clock signal, remove crystal oscillator from socket. Make sure note correct orientation oscillator before removing
Board Components
following sections describe development board components.
Stratix Device (U18)
Stratix EP2S60 device board features 24,176 adaptive logic modules (ALMs) speed grade (-4) 1020-pin FineLine BGA® package. device 2,544,192 total bits.
more information Stratix devices, refer Stratix Device Handbook. Table describes features Stratix EP2S60F1020C4 device.
Table Stratix Device Features Feature
ALMs Adaptive look-up tables (ALUTs) M512 Blocks bits) Blocks (128 bits) M-RAM Blocks Total bits Blocks Embedded multipliers (based mode operation) Enhanced PLLs Fast PLLs Maximum user pins Package type Board reference Voltage EP2S60F1020 24,176 48,352 2,544,192 1020-pin FineLine (internal), (I/O)
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Stratix EP2S60 Development Board
Switch Inputs
board four push-button switches user-defined logic input. Each push-button signal when pressed, drives logic when released goes back driving logic high. Table shows pin-outs push-button switches.
Table Push-button Switch Pin-Outs Signal Name
Stratix
Configuration-Status LEDs
configuration controller connected four status LEDs that show configuration status board glance. tell which configuration, any, loaded into FPGA power-on looking LEDs. configuration downloaded into Stratix device JTAG interface, then USER (LED1) remains illuminated. rest configuration-status LEDs turn unused pins configured inputs, tri-stated Stratix device. Table shows behavior configuration-status LEDs.
Table Configuration Status Indicators
LED3 LED4
Name
Loading Error
Color
Green
Description
This blinks while configuration controller actively transferring data from flash memory into Stratix FPGA. Error then configuration transferred from flash memory into Stratix device. This happen example, flash memory contains neither valid user factory configuration. This turns when user configuration being transferred from flash memory stays illuminated when user configuration data successfully loaded into Stratix device. This turns when factory configuration being transferred from flash memory stays illuminated factory configuration successfully loaded into Stratix device.
LED1
User
Green
LED2
Factory
Amber
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Board Components
Dual Seven-Segment Display LEDs
dual seven-segment display LEDs provided. segments illuminate Stratix which they connected drives low. They appear unlit when connected Stratix device drives high. LEDs illuminate connected Stratix device drives high, unlit when connected Stratix device drives low. Table shows pin-outs seven-segment display LEDs.
Table Seven-Segment Display Pin-Outs Signal Dual Seven-Segment Display
HEX_0A HEX_0B HEX_0C HEX_0D HEX_0E HEX_0F HEX_0G HEX_0DP HEX_1A HEX_1B HEX_1C HEX_1D HEX_1E HEX_1F HEX_1G HEX_1DP
Stratix
LEDs
pld_LED0 (board designation: pld_LED1 (board designation: pld_LED2 (board designation: pld_LED3 (board designation: pld_LED4 (board designation: pld_LED5 (board designation: pld_LED6 (board designation: pld_LED7 (board designation:
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Stratix EP2S60 Development Board
Figure shows pin-outs seven-segment display. Figure Pin-Out Diagram Dual Seven-Segment Display
HEX_0A HEX_0F HEX_0B HEX_1F HEX_1A HEX_1B
HEX_1G
HEX_0G
HEX_0D
HEX_0C
HEX_0E
HEX_0DP
HEX_1D
HEX_1C HEX_1DP Altera Corporation
Converters
Stratix EP2S60 development board 12-bit converters that produce samples maximum rate mega-samples second (MSPS). subsystem board following features:
data output format from each converter Stratix device two's complement format. circuit wideband, AC-coupled, differential input useful sampling. analog inputs transformer-coupled converter order create balanced input. maximize performance, transformers used series. Analog Devices data sheet AD9433 device describes detailed operation this circuit. required anti-aliasing filtering installed externally. needed, users purchase in-line filters from variety manufacturers, such Mini-Circuits (www.minicircuits.com). transformer-coupled circuit lower 3-dB frequency, approximately MHz.
clock signal that drives converters originate from Stratix device, external clock input, on-board 100-MHz oscillator. Jumper controls which clock used used
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HEX_1E
Board Components
select clock Table explains select these three clock signals. selected clock will pass through differential LVPECL buffer before arriving clock input both converters
Table Clock Source Settings Setting
Pins Pins Pins
Clock Source
Stratix circuitry External input clock positive
Signal Name
adc_PLLCLK1, adc_PLLCLK2 adc_CLK_IN1, adc_CLK_IN2
External adc_CLK_IN1_n, input clock negative adc_CLK_IN2_n
Table lists reference information converters.
Table Converter Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site AD9433BSQ 12-bit, 125-MSPS converter 3.3-V digital VDD, 5.0-V analog Analog Devices www.analog.com
Description
Altera Corporation
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Stratix EP2S60 Development Board
Converter Stratix Pin-Outs
Tables show (U1) (U2) Stratix pin-outs.
Table (U1) Stratix Pin-Outs Signal Name
adcA_D0 (LSB) adcA_D1 adcA_D2 adcA_D3 adcA_D4 adcA_D5 adcA_D6 adcA_D7 adcA_D8 adcA_D9 adcA_D10 adcA_D11 (MSB)
Stratix
Table (U2) Stratix Pin-Outs Signal Name
adcB_D0 (LSB) adcB_D1 adcB_D2 adcB_D3 adcB_D4 adcB_D5 adcB_D6 adcB_D7 adcB_D8 adcB_D9 adcB_D10 adcB_D11 (MSB)
Stratix
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Board Components
Converters
Stratix EP2S60 development board converters. subsystem board following features:
converters produce 14-bit samples maximum rate MSPS analog output from each converter single-ended converters expect data unsigned integer format.
clock signals output directly from Stratix device converters. Figure shows on-board circuitry after converter. output converter chip, DAC904, consists current source whose maximum value This differential output converted single -ended output using transformer board uses ratio transformer interface impedance load. Each outputs terminated with 49.9 resistor ground. This circuit results outputs being coupled inherently isolated transformer's magnetic coupling. output transformer then brought connector. Figure On-Board Circuitry after Converter
development includes SLP-50 anti-aliasing filter from Mini-Circuits. This filter provides 55-MHz cut-off frequency. systems with other bandwidth requirements, variety anti-aliasing filters available from commercial manufacturers suit system requirements.
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Stratix EP2S60 Development Board
Table shows reference information anti-aliasing filter.
Table Anti-Aliasing Filter Reference Item
Board reference Manufacturer Description Part number Manufacturer site Mini-circuits Anti-aliasing filter SLP-50 www.minicircuits.com
Description
Table lists reference information converters.
Table Converter Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site
Description
U14, DAC904 14-bit, 165-MSPS converter 3.3-V digital VDD, 5.0-V analog Texas Instruments www.ti.com
Table lists clock source settings converters.
Table Clock Source Settings J18, Setting
Pins Pins Pins Pins
Clock Source
Stratix Circuitry Stratix Circuitry External input clock (J10) External input clock (J12)
Signal Name
dac_PLLCLK1, dac_PLLCLK2 dac_PLLCLK1_n, dac_PLLCLK2_n dac_CLK_IN1, dac_CLK_IN2 dac_DACCLKIN1, dac_DACCLKIN2
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Board Components
Converter Stratix Pin-Outs
Tables show (U14) (U15) Stratix pin-outs.
Table (U14, J15) Stratix Pin-Outs Signal Name
dacA_D1 (MSB) dacA_D2 dacA_D3 dacA_D4 dacA_D5 dacA_D6 dacA_D7 dacA_D8 dacA_D9 dacA_D10 dacA_D11 dacA_D12 dacA_D13 dacA_D14 (LSB)
Stratix
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Stratix EP2S60 Development Board
Table (U15, J17) Stratix Pin-Outs Signal Name
dacB_D1 (MSB) dacB_D2 dacB_D3 dacB_D4 dacB_D5 dacB_D6 dacB_D7 dacB_D8 dacB_D9 dacB_D10 dacB_D11 dacB_D12 dacB_D13 dacB_D14 (LSB) Note Table
Texas Instruments (TI) naming conventions differ from those Altera Corporation. data sheet converter lists most significant (MSB) least significant (LSB).
Stratix
AA10 AA11
SRAM Memory (U43 U44)
Kbyte 16-bit asynchronous SRAM devices. They connected Stratix device they used Nios® embedded processor general-purpose memory. 16-bit devices used parallel implement 32-bit wide memory subsystem. Refer Table Stratix device pin-outs SRAM devices U44.
Table SRAM Memory (U43 U44) (Part Name
SE_A0 SE_A1 SE_A2 SE_A3 SE_A4 SE_A5
Number
AM27 AM28 AJ27 AK27 AL29
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Board Components
Table SRAM Memory (U43 U44) (Part Name
SE_A6 SE_A7 SE_A8 SE_A9 SE_A10 SE_A11 SE_A12 SE_A13 SE_A14 SE_A15 SE_A16 SE_A17 SE_A18 SE_A19 SE_D0 SE_D1 SE_D2 SE_D3 SE_D4 SE_D5 SE_D6 SE_D7 SE_D8 SE_D9 SE_D10 SE_D11 SE_D12 SE_D13 SE_D14 SE_D15 SE_D16 SE_D17 SE_D18 SE_D19
Number
AM29 AJ28 AH28 AK20 AJ20 AL21 AL22 AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AD18 AB18 AB19 AC20 AD20 AE20 AB20 AF20 AC21 AD21 AB21 AE21 AG20 AF21 AD22 AF22 AE22 AC17 AE19 AD19
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Stratix EP2S60 Development Board
Table SRAM Memory (U43 U44) (Part Name
SE_D20 SE_D21 SE_D22 SE_D23 SE_D24 SE_D25 SE_D26 SE_D27 SE_D28 SE_D29 SE_D30 SE_D31 SRAM_BE_N0 SRAM_BE_N1 SRAM_BE_N2 SRAM_BE_N3 SRAM_CS_N SRAM_OE_N SRAM_WE_N
Number
AC18 AB17 AC19 AL26 AL27 AL28 AK28 AK29 AC13 AD10 AC11 AE11 AG11 AK10 AK11 AL11 AL12 AG14 AH14
Table lists reference information SRAM memory.
Table SRAM Memory Reference Item
Board reference Part Number Device description Manufacturer Manufacturer site
Description
U43, IDT71V416S10PH SRAM Memory www.idt.com
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Board Components
Flash Memory (U17)
16-Mbyte AM29LV128M flash memory device connected Stratix device. used purposes:
Nios embedded processor implemented Stratix device flash general-purpose readable memory non-volatile storage. flash memory hold Stratix device configuration file that used configuration controller load Stratix device power-up.
Refer Table Stratix pin-outs flash memory device U17. Hardware configuration data that implements sines reference design prestored this flash memory configures Stratix device with this design boot Nios reference design identify 16Mbyte flash memory address space, program data (either Stratix configuration data, Nios embedded processor software, both) into flash memory. Nios integrated development environment (IDE) provides Flash Programmer feature, which program flash memory. Altera also provides Nios routines writing erasing flash memory. program erase flash memory, need install Nios development tools from Nios Embedded Processor Windows, version CD-ROM included your kit, Nios Flash Programmer. Flash Programmer with board, must specify SOPC Builder setting that locates board description file board. Perform following: Start Quartus software. Choose Tools SOPC Builder. start SOPC Builder from Quartus software. SOPC Builder choose File->SOPC Builder Setup Componet/Kit Library Search Path enter path Stratix board component. delineate multiple paths. Specify following path:
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Stratix EP2S60 Development Board
more information Flash Programmer refer Nios help system Nios Flash Programmer User Guide.
Table Flash Memory (U17) (Part Name
FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7
Number
AF30 AF29 AE30 AE29 AG32 AG31 AF32 AF31 AE32 AE31 AD32 AD31 AB28 AB27 AC32 AC31 AB30 AB29 AA30 AA29 AB32 AB31 AH30 AH29 AJ32 AJ31 AG30 AG29 AH32 AH31
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Board Components
Table Flash Memory (U17) (Part Name
FLASH_CS_N FLASH_OE_N FLASH_RW_N flash_WP_n
Number
AA32 AA31
Table lists reference information Flash memory.
Table Flash Memory Reference Item
Board reference Part number Device description Manufacturer Manufacturer site AM29LV128MH103REI Flash Memory www.amd.com
Description
SDRAM Memory (U39 U40)
SDRAM devices (U39 U40) Micron MT48LC4M32B2 devices with PC100 functionality self refresh mode. SDRAM fully synchronous with signals registered positive edge system clock. SDRAM device pins connected Stratix device. SDRAM controller peripheral included with Stratix Development Kit, allowing Nios processor view SDRAM devices large, linearly-addressable memory. Table lists Stratix device pin-outs SDRAM device U39.
Table SDRAM Device (U39) Pin-Outs (Part Name
Number Connects Stratix
AD11 AD13 AB13 AE14 AB14
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table SDRAM Device (U39) Pin-Outs (Part Name
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24
Number Connects Stratix
AC14 AD14 AE10 AB15 AC16 AB16 AE13 AF11 AJ10 AF12 AG10 AF10 AG12 AJ11
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Altera Corporation
Board Components
Table SDRAM Device (U39) Pin-Outs (Part Name
DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 RAS_N CAS_N CS_N WE_N
Number Connects Stratix
AH11 AL10 AM10 AK12 AJ12 AM11 AM12 AK16
Table lists Stratix device pin-outs SDRAM device U40.
Table SDRAM Device (U40) Pin-Outs (Part Name
Number
Connects Stratix
AD11 AD13 AB13 AE14 AB14 AC14 AD14 AE10 AB15 AC16 AB16 AE13
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table SDRAM Device (U40) Pin-Outs (Part Name
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Number
Connects Stratix
AF11 AH13 AG13 AF13 AG15 AL14 AJ14 AJ13 AM14 AL20 AH19 AJ19 AH20 AM21 AK21 AJ21 AM22 AJ23 AK22 AG22 AG23 AM23 AK23 AK24 AM24 AK25 AH24 AH26 AG24 AM26 AM25 AJ26 AK26
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Altera Corporation
Board Components
Table SDRAM Device (U40) Pin-Outs (Part Name
DQM0 DQM1 DQM2 DQM3 RAS_N CAS_N CS_N
Number
Connects Stratix
AK13 AL13 AB12 AC12
Table lists reference information SDRAM memory.
Table SDRAM Memory Reference Item
Board reference Part number Device description Manufacturer Manufacturer site
Description
U39, MT48LC4M32B2TG-7 SDRAM Memory Micron www.micron.com
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Ethernet MAC/PHY (U16)
LAN91C111 (U16) mixed signal analog/digital device that implements protocols Mbps Mbps. control pins connected Stratix device that user logic (e.g., Nios processor) access Ethernet RJ-45 connector (RJ1). Refer Table Stratix pin-outs Ethernet MAC/PHY device U16.t
Table Ethernet MAC/PHY (U16) (Part Name
ENET_ADS_N ENET_AEN ENET_BE_N0 ENET_BE_N1 ENET_BE_N2 ENET_BE_N3 ENET_DATACS_N ENET_INTRQ0 ENET_IOCHRDY ENET_IOR_N ENET_IOW_N ENET_LDEV_N enet_RESET_n ENET_SRDY_N ENET_W_R_N SE_A0 SE_A1 SE_A2 SE_A3 SE_A4 SE_A5 SE_A6 SE_A7 SE_A8 SE_A9 SE_A10 SE_A11 SE_A12 AM27 AM28 AJ27 AK27 AL29 AM29 AJ28 AH28 AK20 AJ20 AL21 AL22
Number
AA25 AC25 AE26 AE25 AD25 AD24 AB23 AC24 AB26
Preliminary
Altera Corporation
Board Components
Table Ethernet MAC/PHY (U16) (Part Name
SE_A13 SE_A14 SE_A15 SE_A16 SE_A17 SE_A18 SE_A19 SE_D0 SE_D1 SE_D2 SE_D3 SE_D4 SE_D5 SE_D6 SE_D7 SE_D8 SE_D9 SE_D10 SE_D11 SE_D12 SE_D13 SE_D14 SE_D15 SE_D16 SE_D17 SE_D18 SE_D19 SE_D20 SE_D21 SE_D22 SE_D23 SE_D24 SE_D25 SE_D26
Number
AJ22 AH22 AL23 AL24 AJ25 AH25 AL25 AD18 AB18 AB19 AC20 AD20 AE20 AB20 AF20 AC21 AD21 AB21 AE21 AG20 AF21 AD22 AF22 AE22 AC17 AE19 AD19 AC18 AB17 AC19 AL26 AL27 AL28 AK28
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table Ethernet MAC/PHY (U16) (Part Name
SE_D27 SE_D28 SE_D29 SE_D30 SE_D31
Number
AK29 AC13 AD10 AC11 AE11
Table lists reference information Ethernet MAC/PHY.
Table Ethernet MAC/PHY Reference Item
Board reference Part Number Device description Manufacturer Manufacturer site LAN91C111-NE Ethernet MAC/PHY SMSC www.smsc.com
Description
CompactFlash Connector (CON1)
CompactFlash connector header (CON1) enables hardware designs access CompactFlash card. following access modes supported:
(hot-swappable mode) (IDE hard-disk mode)
Most pins CON1 connect pins FPGA. following pins have special connections:
CON1 (VCC) driven power MOSFET that controlled FPGA pin. This allows FPGA control power CompactFlash card connection mode. CON1 (CD1#) pulled through 10-K resistor. This signal used detect presence CompactFlash card. When card present, signal pulled high through pull-up resistor. CON1 (RESET) pulled through 10-K resistor, controlled EPM7128AE configuration controller. FPGA cause configuration controller assert RESET, FPGA does drive this signal directly.
Preliminary
Altera Corporation
Board Components
Table provides CompactFlash pin-out details.
Table CompactFlash (CON1) Table (Part CompactFlash (CON1)
CompactFlash Function (U60)
CS0# ATA_SEL# IOCS16# CD2# CD1#
Connects
AD12 AC15
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table CompactFlash (CON1) Table (Part CompactFlash (CON1)
Notes Table
numbers represent pins FPGA, unless otherwise noted. This FPGA controls power MOSFET that supplies CON1. This does connect FPGA directly. RESET driven EPM7256AE configuration controller device.
CompactFlash Function (U60)
CS1# VS1# IORD# IOWR# INTRQ CSEL# VS2# RESET WAIT# INPACK# REG# DASP# PDIAG#
Connects
AB10 AE12
Preliminary
Altera Corporation
Board Components
Table lists reference information CompactFlash connector.
Table CompactFlash Connector Reference Item
Board reference Part Number Device description Manufacturer Manufacturer site
Description
CON1 53856-5010 CompactFlash connector Molex www.molex.com
general information CompactFlash, www.compactflash.org.
Mictor Connector (J20)
Mictor connector (J20) used transmit high-speed signals with very noise shielded Mictor cable. used debug port. Twenty-five Mictor connector signals used data, signals used clock input clock output. Most pins connect pins Stratix device (U18). systems that Mictor connector debugging Nios processor, on-chip signals routed pins probed Mictor cable. External scopes logic analyzers connect analyze large number signals simultaneously.
details Nios debugging products that Mictor connector, www.altera.com. Figure shows example in-target system analyzer ISA-Nios/T (sold separately) First Silicon Solutions (FS2) Inc. connected Mictor connector. details www.fs2.com.
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Figure ISA-Nios/T Connecting Mictor Connector (J20)
BUSY COMM POWER
Five signals connect both JTAG pins Stratix device (U18) Stratix device's JTAG connector (J24). JTAG signals have special usage requirements. cannot same time. Figure below shows connections from Mictor connector Stratix device. Figure shows pin-out J20. Unless otherwise noted, labels indicate Stratix device numbers. Figure Mictor Connector Signaling
Mictor Connector (J20)
JTAG Connector
(J21)
Stratix Device (U18)
Figure Debug Mictor Connector
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Altera Corporation
Board Components
Table lists reference information Mictor connector.
Table Mictor Connector Reference Item
Board reference Part number Device description Manufacturer Manufacturer site
Description
2-767004-2 Mictor connector Tyco www.tyco.com
Interface (J35)
board contains high density DP15 connector, which outputs VGA, well Triple Video converter which following features:
bit, megapixels second ±2.5% gain matching ±0.5 linearity error Internal bandgap voltage reference glitch energy Single 3.3-V power supply
Table shows pin-outs interface.
Table Interface (U45, J35) Pin-Outs (Part Signal
vga_B0 vga_B1 vga_B2 vga_B3 vga_B4 vga_B5 vga_B6 vga_B7 vga_G0 vga_G1 vga_G2 vga_G3
Stratix
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table Interface (U45, J35) Pin-Outs (Part Signal
vga_G4 vga_G5 vga_G6 vga_G7 vga_R0 vga_R1 vga_R2 vga_R3 vga_R4 vga_R5 vga_R6 vga_R7 vga_BLANK_n vga_CLOCK vga_HSYNC vga_VSYNC vga_SYNC_n
Stratix
Table describes device used implement interface.
Table Interface Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site
Description
FMS3818KRC Triple Video Converter Fairchild www.fairchildsemi.com
Preliminary
Altera Corporation
Expansion Interfaces
Audio CODEC (U5)
board contains three stereo jack connectors, which serve stereo input, amplified stereo output non-amplified stereo output. stereo jacks driven Stereo Audio CODEC running 8-96 KHz. Table shows pin-outs CODEC.
Table Audio CODEC (U5) Pin-Outs Signal
audio_BCLK audio_CS_n audio_SDIN audio_SCLK audio_MODE audio_DOUT audio_DIN audio_LRCIN audio_LRCOUT audio_CLK
Stratix
AL18
Table describes device used implement CODEC.
Table Audio CODEC Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site
Description
TLV320AIC23PW Stereo Audio CODEC, 8-96 Texas Instruments www.ti.com
Expansion Interfaces
Stratix EP2S60 development board includes following interfaces:
TI-EVM/FPDP connector (J31, J33), located reverse side board RS-232C Serial interface (J29)
Altera Corporation
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Stratix EP2S60 Development Board
0.1-inch headers specifically designed used with external analog-to-digital devices made Analog Devices Corporation (J6, Altera Expansion Prototype Connectors (J23, J24, J25; J26, J27, J28)
TI-EVM/FPDP Connector (J31, J33)
TI-EVM interface specifically designed work with boards that have interface. Refer Texas Instruments site details which their boards feature this connector. Table lists pin-outs TI-EVM FPDP connectors.
Table TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part TI-EVM Signal Name
evm_DX0 evm_DR0 evm_IAK evm_INUM0 evm_CNTL0 evm_STAT0 evm_DMAC0 evm_CLKOUT2 evm_CLKX0 evm_FSX0 evm_CLKR0 evm_FSR0 evm_RESET evm_INT0 evm_INT1 evm_INT2 evm_INT3
Stratix
evm_A2 evm_A3 evm_A4
Preliminary
Altera Corporation
Expansion Interfaces
Table TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part TI-EVM Signal Name
evm_A5 evm_A6 evm_A7 evm_A8 evm_A9 evm_A10 evm_A11 evm_A12 evm_A13 evm_A14 evm_A15 evm_A16 evm_A17 evm_A18 evm_A19 evm_A20 evm_A21 evm_D0 evm_D1 evm_D2 evm_D3 evm_D4 evm_D5 evm_D6 evm_D7 evm_D8 evm_D9 evm_D10 evm_D11 evm_D12 evm_D13 evm_D14 evm_D15 evm_D16
Stratix
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part TI-EVM Signal Name
evm_D17 evm_D18 evm_D19 evm_D20 evm_D21 evm_D22 evm_D23 evm_D24 evm_D25 evm_D26 evm_D27 evm_D28 evm_D29 evm_D30 evm_D31 evm_BE_n0 evm_BE_n1 evm_BE_n2 evm_BE_n3 evm_AWE_n evm_ARDY evm_ACE2_n evm_ARE_n evm_AOE_n evm_ACE3_n
Stratix
RS-232C Serial Interface
board contains connector (J29), which provides bidirectional RS-232C serial interface. board contains transceiver (U41), however logic controller (UART) must implemented Stratix device. Table describes device used implement RS-232C interface.
Preliminary
Altera Corporation
Expansion Interfaces
standard DB-9 serial connector. This connector typically used communication with host computer using standard 9-pin serial cable connected (for example) port. Level-shifting buffers (U52 U58) used between Stratix device, because Stratix device cannot interface RS-232 voltage levels directly. able transmit RS-232 signals. Stratix design only signals needs, such J29's TXD. LEDs connected signals, giving visual indication when data being transmitted received. Figure shows connections between serial connector Stratix device. Figure Serial Connector
Function Direction Stratix Connector
DTR1 RXD1 TXD1 DCD1
Connector StratixII Direction Function
CTS1 RTS1 DSR1
Table shows pin-outs RS-232C interface.
Table RS-232C Serial Interface Pin-Outs Signal
Stratix
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Table lists reference information RS-232C transciever device.
Table RS-232C Interface Device Reference Item
Board reference Part number Device description Voltage Manufacturer Manufacturer site
Description
MAX221E RS-232 transceiver Maxim www.maxim-ic.com
Analog Devices Corporation External Support
Stratix EP2S60 development board supports Analog Devices converters 40-pin 0.1-inch digital headers (J5, J6). These dual-purpose digital headers support maximum following three converters.
AD9433 converters AD6645 converters AD9430 converter
Table lists pin-outs connectors.
Table Connector (J5, Pin-Outs (Part Signal Name
Adi_D0 Adi_D1 Adi_D2 Adi_D3 Adi_D4 Adi_D5 Adi_D6 Adi_D7 Adi_D8 Adi_D9 Adi_D10
Stratix
Preliminary
Altera Corporation
Expansion Interfaces
Table Connector (J5, Pin-Outs (Part Signal Name
Adi_D11 Adi_D12 Adi_D13 Adi_D14 Adi_D15 Adi_D16 Adi_D17 Adi_D18 Adi_D19 Adi_D20 Adi_D21 Adi_D22 Adi_D23 Adi_D24 Adi_D25 Adi_D26 Adi_D27 Adi_D28 Adi_D29 Adi_D30 Adi_D31 Adi_D32 Adi_D33
Stratix
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Expansion Prototype Connector (J23, J24, J25)
Headers J23, J24, collectively form standard-footprint, mechanically-stable connection that used (for example) interface special-function daughter card.
list available expansion daughter cards that used with Stratix EP2S60 development board refer www.altera.com/devkits. expansion prototype connector interfaces include:
pins prototyping. pins connect user pins Stratix device. Each signal passes through analog switches (U19, U20, U21, U25) protect Stratix device from logic levels. These analog switches permanently enabled. output logic-level expansion prototype connector pins buffered, zero-skew copy on-board output from buffered, zero-skew copy Stratix device's phase-locked loop (PLL)-output from U60. logic-negative power-on reset signal. Five regulated 3.3-V power-supply pins total maximum load both connectors. regulated power-supply total maximum load both connectors. Numerous ground connections.
Figures show connections from expansion prototype connector Stratix device. Unless otherwise noted, labels indicate Stratix device numbers. Figure Expansion Prototype Connector J23, J24,
Preliminary
Altera Corporation
Expansion Interfaces
Figure Expansion Prototype Connector Information J23, J24,
VCC5
RESET_n
Vunreg (U54
+3.3V +3.3V
PROTO1_OSC
PROTO1_CLKIN PROTO1_CLKOUT (AC14)
+3.3V +3.3V +3.3V
Notes Figure
Unregulated voltage from power transformer from board oscillator from Stratix device buffer output from card Stratix device
Expansion Prototype Connector (J26, J27, J28)
Headers J26, J27, collectively form standard-footprint, mechanically-stable connection that used (for example) interface special-function daughter card. expansion prototype connector interface includes:
pins prototyping. pins connect user pins Stratix device. Each signal passes through analog switches (U27, U28, U29, U31) protect Stratix device from logic levels. These analog switches permanently enabled. output logic-level expansion prototype connector pins buffered, zero-skew copy on-board output (from U2).
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
buffered, zero-skew copy Stratix device's phase-locked loop (PLL)-output (from U60). logic-negative, power-on reset signal. Five regulated 3.3-V power-supply pins total load both expansion prototype connectors). regulated power-supply total load both expansion prototype connectors). Numerous ground connections.
Figures show connections from expansion prototype Stratix device. Unless otherwise noted, labels indicate Stratix device numbers. Figure Expansion Prototype Connector J26, J27,
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Altera Corporation
Expansion Interfaces
Figure Expansion Prototype Connector -Pin Information J26, J27,
AJ17 AK17
RESET_n AC27 AD27
AC26 AD26
AA26
AA27
AF19
Vunreg (U54
+3.3V +3.3V
PROTO2_OSC(U2
PROTO2_CLKIN PROTO2_CLKOUT (B14)
+3.3V +3.3V +3.3V
Notes Figure
Unregulated voltage from power transformer from board oscillator from Stratix device buffer output from card connected Stratix device.
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Install Active Heat Sink
Development Kit, Stratix Edition includes heat sink combination, also known active heat sink. This active heat sink maintains Stratix device within thermal operating range, independent design size, clock frequency, operating conditions, allowing evaluate larger high-speed designs hardware before completing thermal analysis your system. Depending specific requirements your application, this level cooling necessary. further information, refer Application Note 355: Stratix Device System Power Considerations. mount active heat sink board, perform following steps: Center heat sink Stratix FPGA. active heat sink mounted directions; mount wires close possible connector. When connected, these wires supply power fan. Tilt heat sink shown Figure attach clip under FPGA.
Figure Tilt Heat Sink
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Altera Corporation
Expansion Interfaces
Insert thin, flat tool (small flat-head screwdriver, tweezers, clip tool) into clip's hole, gently push clip edge FPGA. Snap clip down secure heat sink. Figure
Figure Attach Clip
Attach heat sink power connector connector, power.
Altera Corporation
Preliminary
Stratix EP2S60 Development Board
Remove Active Heat Sink
remove heat sink from board, perform following steps: Disconnect heat sink power connector from connector. Insert thin, flat tool into clip's holes. Using tool, slightly push away lift plastic clip from FPGA detach side heat sink. Repeat step other side plastic clip remove heat sink completely.
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