Altera® Stratix® Video Demonstration Board evaluation platform that de

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Stratix Video Demonstration Board
Altera® Stratix® Video Demonstration Board evaluation platform that demonstrates superior video performance features Altera's Stratix devices. Stratix board Altera's video reference designs help video customers evaluate SMPTE-292M high-definition serial digital interface (HD-SDI), SMPTE-259M SDI, digital video broadcast asynchronous serial interface (DVB-ASI) video solutions. Stratix board easy reference designs integrated into your video FPGA applications. Stratix device internal dedicated transceiver interfaces with analog PLLs high speed interfaces. more information reference design location reference design files, refer 339: Serial Digital Interface Reference Design Stratix Devices; more information reference design, refer 344: Reference Design. On-board cable drivers equalizers, with standard connectors, allow direct connection test equipment. Altera supplies demonstration design, which allows analysis transmit receive performance solution. board offers following features:
Voltage controlled crystal oscillators (VCXOs) recovered clock cleanup. These VCXOs generate transmit reference clock, which frequency locked received video. Connections external system reference clock, such that generated genlock circuit. board supports variety clocking modes. DIMM socket, which supports external memory applications such image processing frame synchronization. backplane connector. Spare connectors unused transceiver port.
This compact, stand-alone system serves complete evaluation environment rapid engineering test development.
External Connections
Altera Corporation DS-SDIVDBRD-1.0
Figure shows external connections.
Preliminary
Stratix Video Demonstration Board
Figure Connections
Backplane Connector Output Video Clock Input Spare LVDS Santa Cruz Connector
Input
Port Input REFCLK3 Input Port Output Port Output Input Ground UART
Port Input Port Output Port Output
Programming Connector
Spare Transceiver Spare Clock Input
Power Switch
Power
board requires external power supply rated minimum. connect ground On-board voltage regulators generate required 3.3-V, 2.5-V 1.5-V levels. There protection power supply. Check voltage polarity before applying power board.
power switch, enables power board. Diodes illuminate when power
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External Connections
Programming Connector
program Stratix device using ByteBlasterII cable connected programming connector, JF1. Programming object files (POFs) also stored on-board EPC16 configuration device.
Ports
board inputs outputs with associated cable driver cable equalizer circuitry. board supports both standard definition (SD) SDI. ports connected different transceiver quads FPGA they independently different rates. Table shows ports.
Table Ports
Port receive. Port transmit. Port transmit (complimentary output). Port receive. Port transmit. Port transmit (complimentary output).
Connection
FPGA controls slew rate cable driver. Control output high SDI. There tri-color each port. These LEDs controlled FPGA off, green, yellow, red.
Port
board asynchronous serial interface (ASI) input output. These ASIs connected voltage differential signalling (LVDS) FPGA. Table shows ports.
Table Ports
Receive. Transmit.
Connection
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Preliminary
Stratix Video Demonstration Board
output buffered cable driver. also used megabits second (Mbps) transmission. There tri-color each port. These LEDs controlled FPGA off, green, yellow, red.
Backplane Connections
backplane connector provides four transmit four receive ports backplane application. These ports connected transceiver quads FPGA. connections provided further transceiver transmit ports receive ports. connections also provided LVDS output LVDS input. Table shows connections.
Table Connections
LVDS output LVDS input Spare transceiver transmit port Spare transceiver transmit port Spare transceiver receive port Spare transceiver receive port
Connection
Santa Cruz Connector
Santa Cruz connector Altera defined interface that provides interface expansion daughter card general purpose signals, control signals, clocks, 3.3-V power ground compatible.
User Interface
user interface following features:
Push button switches Dual inline package (DIP) switches LEDs Header DIMM socket UART
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User Interface
Push-Button Switches
There four push-button switches user control. Table shows push-button switches.
Table Push-Button Switches Switch
Label
Pressing switch results pin.
Switches
There eight switches (S7), which signal logic FPGA. Table shows switches.
Table Switches Switch
open switch produces Stratix pin.
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Preliminary
Stratix Video Demonstration Board
LEDs
addition tri-color LEDs ports, there eight general purpose LEDs that controlled FPGA. Table shows LEDs.
Table LEDs
drive illuminate LED.
Header
There 20-pin header connector (J32), which used general purpose debugging.
SDRAM
board provides DIMM socket DDR333 SDRAM.
UART
connector interface provided RS232 universal asynchronous receiver transmitter (UART). UART interface logic must implemented FPGA.
Clocks
board following clocks:
Transmitter reference clock-SD Transmitter reference clock-HD Receiver reference clock-SD Receiver reference clock-HD Additional clocks
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Clocks
clock Santa Cruz clock
Transmiter Reference Clock-SD
transmitter reference clock requires 135-MHz (for 10-bit transceiver interface) 67.5-MHz (for 20-bit) reference clock. This clock provided externally direct transceiver, synthesized from different frequency using on-chip PLLs. following clock options available:
on-board 27-MHz oscillator on-chip PLL. 27-MHz clock connected enhanced (ref27_e, B18) fast PLLs (ref27_f ref27_d AL18). these onchip PLLs provide multiplication external video-clock signal connected (ext_video_clk). This input (pin C19) drive enhanced used directly transceiver external LVTTL clock connected (spare_clock). This input (pin AG16) drive fast PLL, used directly transceiver clock from MK2069 VCXO (clock_ref). This clock 27-MHz signal that frequency locked number reference signals. connected fast (pin T31) that provide multiplication LVDS clock (refclk3) connected (J36 J37) directly transceiver REFCLKB16 reference clock input (AM7 AL7). This input clock quads.
Transmitter Reference Clock-HD
transmitter reference clock requires 74.25 74.175 reference clock, depending serial data rate required. 20-bit transceiver interface always used best jitter performance clock should connected direct transceiver reference clock inputs. However, following clock options available:
On-board 74.25-MHz 74.175-MHz oscillator, which connect global clock inputs, also enhanced External video clock (ext_video_clk), External LVTTL clock (spare_clock),
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Preliminary
Stratix Video Demonstration Board
Discrete VCXO (X5), which provides 74.175MHz signal that connects transceiver REFCLKB13 reference clock input through multiplexer. exact frequency VCXO controlled Stratix Discrete VCXO (X1) (not fitted default board), which directly connects transceiver REFCLKB14 reference clock input. This input only clock port LVDS clock (refclk3),
Receiver Reference Clock-SD
receiver reference clock requires 135-MHz (for 10-bit transceiver interface) 67.5-MHz (for 20-bit) reference clock. options same transmit reference clock.
Receiver Reference Clock-HD
receiver reference clock requires reference clock that nominally 1/20th data rate. However, addition options available transmit, same 67.5-MHz frequency that used This frequency allows supported data rates handled with common receive reference clock.
Additional Clocking Options
following external connections transceiver reference clock inputs driven outputs from FPGA:
REFCLKB15 driven R25. This signal routed multiplexer normally used multirate transmit design (the multiplexer switches between reference clocks). REFCLKB16 drive F18. This signal multiplexed with LVDS input.
Also, there clock input from backplane connector.
Clock
clock generated enhanced typically multiple clock from on-board 27-MHz oscillator.
Santa Cruz Clocks
There clock outputs Santa Cruz connector, both from Typically, these multiples clock from on-board 27-MHz oscillator.
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Clocks
There also input from Santa Cruz connector, which connect global clock fast PLLs.
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Preliminary
Copyright 2004 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Printed recycled paper
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Altera Corporation DS-SDIVDBRD-1.0

Altera® Stratix® Video Demonstration Board evaluation platform that de

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