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C51013-1.7 configure Cyclone® FPGAs using several configuration s


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Configuring Cyclone FPGAs
C51013-1.7
configure Cyclone® FPGAs using several configuration schemes, including active serial (AS) configuration scheme. This scheme used with cost serial configuration devices. Passive serial (PS) Joint Test Action Group (JTAG)-based configuration schemes also supported Cyclone FPGAs. Additionally, Cyclone FPGAs receive compressed configuration stream decompress this data real-time, reducing storage requirements configuration time. This chapter describes configure Cyclone devices using each three supported configuration schemes.
more information setting device configuration options generating configuration files, Software Settings chapter Volume Configuration Handbook. Cyclone FPGAs SRAM cells store configuration data. Since SRAM memory volatile, configuration data must downloaded Cyclone FPGAs each time device powers download configuration data Cyclone FPGAs using JTAG interfaces (see Table 13-1).
Device Configuration Overview
Table 13-1. Cyclone FPGA Configuration Schemes Configuration Scheme
Active serial (AS) configuration
Description
Configuration using: Serial configuration devices (EPCS1, EPCS4, EPCS16)
Passive serial (PS) configuration Configuration using: Enhanced configuration devices (EPC4, EPC8, EPC16) EPC2, EPC1 configuration devices Intelligent host (microprocessor) Download cable JTAG-based configuration Configuration JTAG pins using: Download cable Intelligent host (microprocessor) JamStandard Test Programming Language (STAPL) Ability SignalTap® Embedded Logic Analyzer.
Altera Corporation January 2007
13-1
Device Configuration Overview
select Cyclone FPGA configuration scheme driving MSEL1 MSEL0 pins either high (0), shown Table 13-2. your application only requires single configuration mode, MSEL pins connected (the bank's VCCIO voltage where MSEL resides) ground. your application requires more than configuration mode, MSEL pins switched after FPGA been configured successfully. Toggling these pins during user mode does affect device operation. However, MSEL pins must valid before initiating reconfiguration.
Table 13-2. Selecting Cyclone Configuration Schemes MSEL1
Note Table 13-2:
JTAG-based configuration takes precedence over other schemes, which means that MSEL settings ignored.
MSEL0
Configuration Scheme
JTAG-based
After configuration, Cyclone FPGAs will initialize registers pins, then enter user mode function user design. Figure 13-1 shows configuration waveform. Figure 13-1. Configuration Waveform
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
ASDO
Read Address
DATA0
Cycles
INIT_DONE
User
User Mode
Tri-stated with internal pull-up resistor.
13-2 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
configure Cyclone FPGAs using 3.3-, 2.5-, 1.8-, 1.5-V LVTTL standard configuration JTAG input pins. These devices feature VCCSEL pin; therefore, should connect VCCIO pins banks containing configuration JTAG pins according standard specifications. Table 13-3 summarizes approximate uncompressed configuration file size each Cyclone FPGA. calculate amount storage space required multi-device configurations, file size each device together.
Table 13-3. Cyclone Binary File (.rbf) Sizes Device
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
Data Size (Bits)
627,376 924,512 1,167,216 2,323,240 3,559,608
Data Size (Bytes)
78,422 115,564 145,902 290,405 435,000
should only numbers Table 13-3 estimate configuration file size before design compilation. Different file formats, such .hex .ttf files, have different file sizes. specific version Quartus® software, design targeted same device same uncompressed configuration file size. compression used, file size vary after each compilation.
Data Compression
Cyclone FPGAs first FPGAs support decompression configuration data. This feature allows store compressed configuration data configuration devices other memory, transmit this compressed stream Cyclone FPGAs. During configuration, Cyclone FPGA decompresses stream real time programs SRAM cells. Cyclone FPGAs support compression configuration schemes. Compression supported JTAG-based configuration. Preliminary data indicates that compression reduces configuration stream size 60%.
Altera Corporation January 2007
13-3 Cyclone Device Handbook, Volume
Data Compression
When enable compression, Quartus software generates configuration files with compressed configuration data. This compression reduces storage requirements configuration device flash, decreases time needed transmit stream Cyclone FPGA. There methods enable compression Cyclone bitstreams: before design compilation Compiler Settings menu) after design compilation Convert Programming Files window). enable compression project's compiler settings, select Device under Assignments menu bring settings window. After selecting your Cyclone device open Device Options window, General settings enable check Generate compressed bitstreams shown Figure 13-2).
13-4 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-2. Enabling Compression Cyclone Bitstreams Compiler Settings
Altera Corporation January 2007
13-5 Cyclone Device Handbook, Volume
Data Compression
Compression also enabled when creating programming files from Convert Programming Files window. Figure 13-3. Click Convert Programming Files (File menu). Select programming file type (POF, SRAM HEXOUT, RBF, TTF). output files, select configuration device. Select File Cyclone file(s). Select name file added Data area click Properties. Check Compression checkbox.
Figure 13-3. Enabling Compression Cyclone Bitstreams Convert Programming Files
13-6 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
When multiple Cyclone devices cascaded, compression feature selectively enabled each device chain. Figure 13-4 depicts chain Cyclone FPGAs. first Cyclone FPGA compression feature enabled therefore receives compressed stream from configuration device. second Cyclone FPGA compression feature disabled receives uncompressed data. Figure 13-4. Compressed Uncompressed Configuration Data Same Programming File Note
Serial Data Serial Enhanced Configuration Device Compressed Uncompressed
Decompression Controller Cyclone FPGA nCEO
Decompression Controller Cyclone FPGA nCEO N.C.
Note Figure 13-4:
first device chain should configuration mode (MSEL[1.0]="00"). remaining devices chain must configuration mode (MSEL[1.0]="01").
generate programming files this setup from Convert Programming Files window (File menu) Quartus software. decompression feature supported Cyclone FPGAs separate from decompression feature enhanced configuration devices (EPC16, EPC8, EPC4 devices). data compression feature enhanced configuration devices allows them store compressed data decompress stream before transmitting target devices. When using Cyclone FPGAs with enhanced configuration devices, Altera recommends using compression devices, both (preferably Cyclone FPGA since transmitting compressed data reduces configuration time).
Altera Corporation January 2007
13-7 Cyclone Device Handbook, Volume
Configuration Schemes
Configuration Schemes
This section describes various configuration schemes configure Cyclone FPGAs. Descriptions include overview protocol, connections, timing information. schemes discussed are:
configuration (serial configuration devices) configuration JTAG-based configuration
Active Serial Configuration (Serial Configuration Devices)
configuration scheme, Cyclone FPGAs configured using serial configuration devices. These configuration devices cost devices with non-volatile memory that feature simple four-pin interface small form factor. These features make serial configuration devices ideal solution configuring low-cost Cyclone FPGAs.
more information programming serial configuration devices, Cyclone Literature page Serial Configuration Devices (EPCS1, EPCS4, EPCS16 EPCS64) Data Sheet. Serial configuration devices provide serial interface access configuration data. During device configuration, Cyclone FPGAs read configuration data serial interface, decompress data necessary, configure their SRAM cells. This scheme referred configuration scheme because FPGA controls configuration interface. This scheme contrast configuration scheme where configuration device controls interface. Serial configuration devices have four-pin interface: serial clock input (DCLK), serial data output (DATA), data input (ASDI), activelow chip select (nCS). This four-pin interface connects Cyclone FPGA pins shown Figure 13-5.
13-8 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-5. Configuration Single Cyclone FPGA
Serial Configuration Device
Cyclone FPGA nSTATUS CONF_DONE nCONFIG nCEO N.C.
DATA DCLK ASDI
DATA0 DCLK nCSO ASDO MSEL1 MSEL0
Notes Figure 13-5:
Connect pull-up resistors 3.3-V supply. Cyclone FPGAs ASDO ASDI path control configuration device.
Connecting MSEL[1.0] pins selects configuration scheme. Cyclone chip enable signal, nCE, must also connected ground driven successful configuration. During system power both Cyclone FPGA serial configuration device enter power-on reset (POR) period. soon Cyclone FPGA enters POR, drives nSTATUS indicate busy drives CONF_DONE indicate that been configured. After POR, which typically lasts Cyclone FPGA releases nSTATUS enters configuration mode when this signal pulled high external 10-k resistor. Once FPGA successfully exits POR, user pins tri-stated. Cyclone devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Chapter Switching Characteristics. serial clock (DCLK) generated Cyclone FPGA controls entire configuration cycle (see Figure 13-1 page 13-2) this clock signal provides timing serial interface. Cyclone FPGAs
Altera Corporation January 2007
13-9 Cyclone Device Handbook, Volume
Configuration Schemes
internal oscillator generate DCLK. After configuration, this internal oscillator turned off. Table 13-4 shows active serial DCLK output frequencies.
Table 13-4. Active Serial DCLK Output Frequency Minimum
Typical
Maximum
Units
serial configuration device latches input/control signals rising edge DCLK drives configuration data falling edge. Cyclone FPGAs drive control signals falling edge DCLK latch configuration data falling edge DCLK. configuration mode, Cyclone FPGA enables serial configuration device driving nCSO output that connected chip select (nCS) configuration device. Cyclone FPGA's serial clock (DCLK) serial data output (ASDO) pins send operation commands read-address signals serial configuration device. configuration device provides data serial data output (DATA) that connected DATA0 input Cyclone FPGAs. After Cyclone FPGA receives configuration bits, releases open-drain CONF_DONE allowing external 10-k resistor pull this signal high level. Initialization begins only after CONF_DONE line reaches high level. CONF_DONE must have external 10-k pull-up resistor order device initialize. select clock used initialization using User Supplied Start-Up Clock option Quartus software. Quartus software uses 10-MHz (typical) internal oscillator (separate from internal oscillator) default initialize Cyclone FPGA. After initialization, internal oscillator turned off. When enable User Supplied Start-Up Clock option, software uses CLKUSR initialization clock. Supplying clock CLKUSR does affect configuration process. After configuration data accepted CONF_DONE signal goes high, Cyclone devices require clock cycles initialize properly. optional INIT_DONE available. This signals initialization start user mode with low-to-high transition. Enable INIT_DONE output option available Quartus software. INIT_DONE used, high external 10-k pull-up resistor when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data),
13-10 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
INIT_DONE goes low. When initialization complete, INIT_DONE released pulled high. This low-to-high transition signals that FPGA entered user mode. user mode, user pins have weak pull-ups functions assigned your design. error occurs during configuration, Cyclone FPGA asserts nSTATUS signal indicating data frame error, CONF_DONE signal stays low. With Auto-Restart Configuration Frame Error option enabled Quartus software, Cyclone FPGA resets configuration device pulsing nCSO, releases nSTATUS after reset time-out period (about retries configuration. this option turned off, system must monitor nSTATUS errors then pulse nCONFIG least restart configuration. After successful configuration, CONF_DONE signal tri-stated target device then pulled high pull-up resistor. configuration pins, DATA0, DCLK, nCSO, ASDO, have weak internal pull-up resistors. These pull-up resistors always active. When Cyclone FPGA user mode, initiate reconfiguration pulling nCONFIG low. nCONFIG should least When nCONFIG pulled low, FPGA also pulls nSTATUS CONF_DONE pins tri-stated. Once nCONFIG returns logic high level nSTATUS released Cyclone FPGA, reconfiguration begins.
Configuring Multiple Devices (Cascading)
configure multiple Cyclone FPGAs using single serial configuration device. cascade multiple Cyclone FPGAs using chip-enable (nCE) chip-enable-out (nCEO) pins. first device chain must have connected ground. must connect nCEO next device chain. When first device captures configuration data from stream, drives nCEO enabling next device chain. must leave nCEO last device unconnected. nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0 pins each device chain connected (see Figure 13-6). This first Cyclone FPGA chain configuration master controls configuration entire chain. must connect MSEL pins select configuration scheme. remaining Cyclone FPGAs configuration slaves must connect their MSEL pins select configuration scheme. Figure 13-6 shows connections this setup.
Altera Corporation January 2007
13-11 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-6. Configuring Multiple Devices Using Serial Configuration Device (AS)
Serial Configuration Device
Cyclone FPGA Master nSTATUS CONF_DONE nCONFIG nCEO
Cyclone FPGA Slave nSTATUS CONF_DONE nCONFIG nCEO N.C.
DATA0 DCLK nCSO ASDO MSEL1 MSEL0 DATA0 DCLK MSEL1 MSEL0
DATA DCLK ASDI
Note Figure 13-6:
Connect pull-up resistors 3.3-V supply.
shown Figure 13-6, nSTATUS CONF_DONE pins target FPGAs connected together with external pull-up resistors. These pins open-drain bidirectional pins FPGAs. When first device asserts nCEO (after receiving configuration data), releases CONF_DONE pin. subsequent devices chain keep this shared CONF_DONE line until they have received their configuration data. When target FPGAs chain have received their configuration data have released CONF_DONE, pull-up resistor drives high level this line devices simultaneously enter initialization mode. error occurs point during configuration, nSTATUS line driven failing FPGA. enable Auto Restart Configuration Frame Error option, reconfiguration entire chain begins after reset time-out period maximum option turned off, external system must monitor nSTATUS errors then pulse nCONFIG restart configuration. external system pulse nCONFIG under system control rather than tied VCC. While cascade Cyclone FPGAs, serial configuration devices cannot cascaded chained together.
13-12 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
configuration stream size exceeds capacity serial configuration device, must select larger configuration device and/or enable compression feature. While configuring multiple devices, size stream individual devices' configuration streams.
Configuring Multiple Devices with Same Data
Certain applications require configuration multiple Cyclone devices with same design through configuration stream file. This actually done methods they shown below. both methods, serial configuration devices cannot cascaded chained together. Method method serial configuration device stores copies file. first copy configures master Cyclone device, second copy configures remaining slave devices concurrently. setup similar Figure 13-7 where master setup mode (MSEL=00) slave devices setup mode (MSEL01). configure four identical Cyclone devices with same file, could setup chain similar example shown Figure 13-6, except connect three slave devices concurrent configuration. nCEO from master device drives input pins three slave devices, DATA DCLK pins connect parallel four devices. During first configuration cycle, master device reads configuration data from serial configuration device while holding nCEO high. After completing configuration cycle, master drives transmits second copy configuration data three slave devices, configuring them simultaneously. advantage using setup Figure 13-7 have different file Cyclone master device. However, Cyclone slave devices must configured with same file.
Altera Corporation January 2007
13-13 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-7. Configuring Multiple Devices with Same Design Using Serial Configuration Device
Cyclone FPGA Slave nSTATUS CONF_DONE nCONFIG Data0 DCLK MSEL0 MSEL1 Cyclone FPGA Master nSTATUS CONF_DONE nCONFIG Data DCLK ASDI Serial Configuration Device Data0 DCLK nCSO ASDO MSEL0 MSEL1 Cyclone FPGA Slave nSTATUS CONF_DONE nCONFIG nCEO N.C. Data0 DCLK Data0 DCLK MSEL0 MSEL1 nCEO Cyclone FPGA Slave nSTATUS CONF_DONE nCONFIG nCEO N.C. nCEO N.C.
MSEL0 MSEL1
Note Figure 13-7:
pull-up resistor should connected same supply voltage configuration device.
Method Method configures multiple Cyclone devices with same SOFs storing only copy serial configuration device. This saves memory space serial configuration device generalpurpose reduce costs. This method shown Figure 13-8 where master device mode (MSLE=00), slave
13-14 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
devices mode (MSEL=01). could more slave devices chain slave devices same design shown Figure 13-8. Figure 13-8. Configuring Multiple Devices with Same Design Using Serial Configuration Device
Master Cyclone Device nSTATUS CONF_DONE nCONFIG EPCS4 Device Data DCLK ASDI Data0 DCLK nCS0 ASDO MSEL0 MSEL1 Data0 DCLK nCS0 ASDO
Slave Cyclone Device nSTATUS CONF_DONE nCONFIG
MSEL0 MSEL1
Buffer
this setup, Cyclone devices chain connected concurrent configuration. This reduces active serial configuration time because Cyclone devices configured only configuration cycle. achieve this, input pins Cyclone devices connected ground nCEO output pins Cyclone devices left unconnected. DATA DCLK pins connect parallel Cyclone devices. recommended buffer before DATA DCLK output from master Cyclone avoid signal strength signal integrity issues. buffer should significantly change DATA-to-DCLK relationships delay them with respect other ASMI signals, which
Altera Corporation January 2007
13-15 Cyclone Device Handbook, Volume
Configuration Schemes
ASDI signals. Also, buffer should only drive slave Cyclone devices, that timing between master Cyclone device serial configuration device unaffected. This setup support both compressed uncompressed SOFs. Therefore, configuration stream size exceeds capacity serial configuration device, enable compression feature used select larger serial configuration device.
Estimating Active Serial Configuration Time
Active serial configuration time dominated time takes transfer data from serial configuration device Cyclone FPGA. This serial interface clocked Cyclone DCLK output (generated from internal oscillator). listed Table 13-4, DCLK minimum frequency ns). Therefore, maximum configuration time estimate EP1C3 device (0.628 MBits uncompressed data) (0.628 MBits typical configuration time Enabling compression reduces amount configuration data that transmitted Cyclone device, reducing configuration time. average, compression reduces configuration time 50%.
Programming Serial Configuration Devices
Serial configuration devices non-volatile, flash-memory-based devices. program these devices in-system using ByteBlasterII download cable. Alternatively, program them using Altera Programming Unit (APU) supported third-party programmers. perform in-system programming serial configuration devices programming interface. During in-system programming, download cable disables FPGA access interface driving high. Cyclone FPGAs also held reset level nCONFIG. After programming complete, download cable releases nCONFIG, allowing pull-down pull-up resistor drive VCC, respectively. Figure 13-9 shows download cable connections serial configuration device.
more information ByteBlaster cable, ByteBlaster Download Cable Data Sheet.
13-16 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
serial configuration devices programmed in-system external microprocessor using SRunner. SRunner software driver developed embedded serial configuration device programming that customized different embedded systems. SRunner read Programming Data file (.rpd) write serial configuration devices. programming time comparable Quartus software programming time.
more information about SRunner, "SRunner: Embedded Solution Serial Configuration Device Programming" white paper source code Altera site (www.altera.com).
Figure 13-9. In-System Programming Serial Configuration Devices
Cyclone FPGA CONF_DONE nSTATUS Serial Configuration Device DATA DCLK ASDI DATA0 DCLK nCSO ASDO MSEL1 MSEL0 nCONFIG nCEO N.C.
ByteBlaser 10-Pin Male Header
Notes Figure 13-9:
Connect these pull-up resistors 3.3-V supply. nCEO left unconnected. Power ByteBlaster cable's with 3.3-V supply.
Altera Corporation January 2007
13-17 Cyclone Device Handbook, Volume
Configuration Schemes
program serial configuration devices using Quartus software with appropriate configuration device programming adapter. serial configuration devices offered eight-pin small outline integrated circuit (SOIC) package programmed using PLMSEPC-8 adapter. production environments, serial configuration devices programmed using multiple methods. Altera programming hardware (APU) other third-party programming hardware used program blank serial configuration devices before they mounted onto PCBs. Alternatively, on-board microprocessor program serial configuration device in-system using C-based software drivers provided Altera.
more information programming serial configuration devices, Cyclone Literature page Serial Configuration Devices (EPCS1, EPCS4, EPCS16 EPCS64) Data Sheet. Device configuration options create configuration files discussed further Software Settings chapter Volume Configuration Handbook.
Passive Serial Configuration
Cyclone FPGAs also feature configuration scheme supported Altera FPGAs. scheme, external host (configuration device, embedded processor, host controls configuration. Configuration data clocked into target Cyclone FPGAs DATA0 each rising edge DCLK. configuration waveforms this scheme shown Figure 13-10.
13-18 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-10. Configuration Cycle Waveform
nCONFIG nSTATUS CONF_DONE DCLK DATA High-Z High-Z User
User Pins Tri-stated with internal pull-up resistor INIT_DONE MODE Configuration Configuration Initialization
User
Notes Figure 13-10:
During initial power configuration, CONF_DONE low. After configuration, CONF_DONE goes high indicate successful configuration. device reconfigured, CONF_DONE goes after nCONFIG driven low. User pins tri-stated during configuration. Cyclone FPGAs also have weak pull-up resistor pins during configuration. After initialization, user pins perform function assigned user's design. When used, optional INIT_DONE signal high when nCONFIG before configuration during first clock cycles configuration. user mode, DCLK should driven high when using configuration scheme. When using configuration scheme, DCLK Cyclone output should driven externally. user mode, DATA0 should driven high low.
Configuration Using Configuration Device
configuration device scheme, nCONFIG usually tied (when using EPC16, EPC8, EPC4, EPC2 devices, connect nCONFIG nINIT_CONF). Upon device power-up, target Cyclone FPGA senses low-to-high transition nCONFIG initiates configuration. target device then drives open-drain CONF_DONE low, which in-turn drives configuration device's low. When exiting POR, both target configuration device release open-drain nSTATUS (typically Cyclone lasts ms). Before configuration begins, configuration device goes through delay (maximum) allow power supply stabilize. must power Cyclone FPGA before during time enhanced configuration device. During POR, configuration device drives low. This signal delays configuration because connected target device's nSTATUS pin. When target configuration devices complete POR, they both release nSTATUS line, which then pulled high pull-up resistor.
Altera Corporation January 2007
13-19 Cyclone Device Handbook, Volume
Configuration Schemes
When configuring multiple devices, configuration does begin until devices release their nSTATUS pins. When devices ready, configuration device clocks DATA DCLK target devices using internal oscillator. After successful configuration, Cyclone FPGA starts initialization using 10-MHz internal oscillator reference clock. After initialization, this internal oscillator turned off. CONF_DONE released target device then pulled high pull-up resistor. When initialization complete, target Cyclone FPGA enters user mode. CONF_DONE must have external 10-k pull-up resistor order device initialize. error occurs during configuration, target device drives nSTATUS low, resetting itself internally resetting configuration device. turn Auto-Restart Configuration Frame Error option, device reconfigures automatically error occurs. this option, select Compiler Settings (Processing menu), click Chips Devices tab. Select Device Options, click Configuration tab. Auto-Restart Configuration Frame Error option turned off, external system (configuration device microprocessor) must monitor nSTATUS errors then pulse nCONFIG restart configuration. external system pulse nCONFIG under system control rather than tied VCC. When configuration complete, target device releases CONF_DONE, which disables configuration device driving high. configuration device drives DCLK before after configuration. addition, configuration device sends data then detects that CONF_DONE gone high, recognizes that target device configured successfully. (For CONF_DONE reach high state, enhanced configuration devices wait DCLK cycles after last configuration bit. EPC2 devices wait DCLK cycles.) this case, configuration device pulses microseconds, driving target device's nSTATUS low. Auto-Restart Configuration Frame Error option Quartus software, target device resets then releases nSTATUS after reset timeout period. When nSTATUS returns high, configuration device reconfigures target device. should pull CONF_DONE delay initialization. Instead, Quartus software's User-Supplied Start-Up Clock option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain initialize together since their CONF_DONE pins tied together.
13-20 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
CONF_DONE goes high during first clock cycles initialization. Hence, when using CLKUSR feature would CONF_DONE signal high until start clocking CLKUSR. However, device does retain configuration data waits these initialization clocks release CONF_DONE into user mode. Figure 13-11 shows configure Cyclone FPGA with configuration device. Figure 13-11. Single Device Configuration Circuit
Cyclone FPGA
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCEO N.C.
Configuration Device
DCLK DATA nINIT_CONF
Notes Figure 13-11:
pull-up resistor should connected same supply voltage configuration device. This pull-up resistor EPC16, EPC8, EPC4, EPC2 devices' pins have internal, user-configurable pull-up resistors. internal pull-up resistors, external pull-up resistors these pins. nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices internal pull-up resistor that always active. nINIT_CONF used, nCONFIG pulled directly through resistor. nCEO left unconnected last device chain. Connect MSEL0 supply voltage bank resides
Configuring Multiple Cyclone FPGAs
single configuration device configure multiple Cyclone FPGAs. this setup, nCEO first device connected second device chain. there additional devices, connect next device nCEO previous device. should leave nCEO last device chain unconnected. configure properly, target device CONF_DONE nSTATUS pins must tied together. Figure 13-12 shows example configuring multiple Cyclone FPGAs using single configuration device.
Altera Corporation January 2007
13-21 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-12. Configuring Multiple Cyclone FPGAs with Single Configuration Device
Cyclone FPGA DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Cyclone FPGA DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device DCLK DATA nCASC nINIT_CONF (4),
MSEL0 MSEL1 N.C. nCEO
MSEL0 MSEL1
nCEO
Notes Figure 13-12:
pull-up resistor should connected same supply voltage configuration device. EPC16, EPC8, EPC4, EPC2 devices' pins have internal, user-configurable pull-up resistors. internal pull-up resistors, external pull-up resistors these pins. EPC16, EPC8, EPC4 configuration devices cannot cascaded. nCEO left unconnected last device chain. nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. nINIT_CONF used, nCONFIG must pulled directly through resistor. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC4, EPC2 devices. These devices need external pull-up resistor nINIT_CONF pin. Connect MSEL0 supply voltage bank resides
When performing multi-device configuration, must generate configuration device programming file (.sof) from each project. Then must combine multiple .sof files using Quartus software through Convert Programming Files dialog box.
more information create Programmer Object Files (.pof) enhanced configuration devices, 218: Using Enhanced Configuration Devices. After first Cyclone FPGA completes configuration during multidevice configuration, nCEO activates second device's pin, prompting second device begin configuration. Because device CONF_DONE pins tied together, devices initialize enter user mode same time.
13-22 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
addition, nSTATUS pins tied together; therefore, device (including configuration device) detects error, configuration stops entire chain. Also, configuration device does detect CONF_DONE going high configuration, resets chain pulsing microseconds. CONF_DONE reach high state, enhanced configuration devices wait DCLK cycles after last configuration bit. EPC2 devices wait DCLK cycles. Auto-Restart Configuration Frame Error option turned Quartus software, Cyclone FPGA releases nSTATUS pins after reset time-out period (about When nSTATUS pins released pulled high, configuration device reconfigures chain. Auto-Restart Configuration Frame Error option turned devices drive nSTATUS until they reset with pulse nCONFIG. also cascade several EPC2 EPC1 configuration devices configure multiple Cyclone FPGAs. When data from first configuration device sent, drives nCASC low, which turn drives subsequent EPC2 EPC1 device. Because configuration device requires less than clock cycle activate subsequent configuration device, data stream uninterrupted. cannot cascade EPC16, EPC8, EPC4 configuration devices. Figure 13-13 shows configure multiple devices using cascaded EPC2 EPC1 devices.
Altera Corporation January 2007
13-23 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-13. Multi-Device Configuration Using Cascaded EPC2 EPC1 Devices
Cyclone Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Cyclone Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
EPC2 EPC1 Device
DCLK DATA nCASC nINIT_CONF
EPC2 EPC1 Device
DCLK DATA nINIT_CONF
MSEL1 MSEL0
MSEL1 MSEL0
N.C.
nCEO
nCEO
Notes Figure 13-13:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active, meaning external pull-up resistor should used nINIT_CONFnCONFIG line. nINIT_CONF does need connected function used. nINIT_CONF used available (such EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. External 10-k pull-up resistors should used. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files.
Configuration Using Download Cable
Using download cable configuration, intelligent host (for example, your transfers data from storage device (for example, your hard drive) Cyclone FPGA through Blaster, ByteBlaster MasterBlaster, ByteBlasterMV cable. initiate configuration this scheme, download cable generates low-to-high transition nCONFIG pin. programming hardware then sends configuration data time device's DATA0 pin. data clocked into target device using DCLK until CONF_DONE goes high. When using programming hardware Cyclone FPGA, turning Auto-Restart Configuration Frame Error option does affect configuration cycle because Quartus software must restart configuration when error occurs. Figure 13-14 shows configuration setup Cyclone FPGA using Blaster, ByteBlaster MasterBlaster, ByteBlasterMV cable.
13-24 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-14. Configuration Circuit with Download Cable
MSEL0 MSEL1
Cyclone Device
CONF_DONE nSTATUS
nCEO
N.C. 10-Pin Male Header Mode)
DCLK DATA0 nCONFIG
Shield
Notes Figure 13-14:
should connect pull-up resistor same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable. header reference voltage MasterBlaster output driver. should match device's VCCIO. This no-connect ByteBlasterMV header. pull-up resistors DATA0 DCLK only needed download cable only configuration scheme used your board. This ensure that DATA0 DCLK left floating after configuration. example, also using configuration device, pull-up resistors DATA0 DCLK needed. Connect MSEL0 supply voltage bank resides
download cable configure multiple Cyclone FPGAs connecting each device's nCEO subsequent device's pin. other configuration pins connected each device chain. Because CONF_DONE pins tied together, devices chain initialize enter user mode same time. addition, because nSTATUS pins tied together, entire chain halts configuration device detects error. this situation, Quartus software must restart configuration; Auto-Restart Configuration Frame Error option does affect configuration cycle. Figure 13-15 shows configure multiple Cyclone FPGAs with ByteBlaster MasterBlaster, ByteBlasterMV cable.
Altera Corporation January 2007
13-25 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-15. Multi-Device Configuration with Download Cable
10-Pin Male Header Mode)
Cyclone FPGA
MSEL0 MSEL1 CONF_DONE nSTATUS DCLK
DATA0 nCONFIG
nCEO
Cyclone FPGA
MSEL0 MSEL1 CONF_DONE nSTATUS DCLK
DATA0 nCONFIG
nCEO
N.C.
Notes Figure 13-15:
should connect pull-up resistor same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. pull-up resistors DATA0 DCLK only needed download cable only configuration scheme used your board. This ensure that DATA0 DCLK left floating after configuration. example, also using configuration device, pull-up resistors DATA0 DCLK needed. Connect MSEL0 supply voltage bank resides
using ByteBlaster MasterBlaster, ByteBlasterMV cable configure device(s) board that also populated with configuration devices, should electrically isolate configuration devices from target device(s) cable. isolate configuration devices logic, such multiplexer, that select between configuration devices cable. multiplexer allows bidirectional transfers nSTATUS CONF_DONE signals. Another option switches five common signals (CONF_DONE, nSTATUS, DCLK,
13-26 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
nCONFIG, DATA0) between cable configuration devices. last option remove configuration devices from board when configuring with cable. Figure 13-16 shows combination configuration device ByteBlaster MasterBlaster, ByteBlasterMV cable configure Cyclone FPGA. Figure 13-16. Configuring with Combined Configuration Device Scheme
Cyclone FPGA CONF_DONE MSEL0 nSTATUS DCLK MSEL1 DATA0 nCONFIG nCEO N.C. Configuration Device DCLK DATA nINIT_CONF Download Cable 10-Pin Male Header Mode)
Notes Figure 13-16:
should connect pull-up resistor same supply voltage configuration device. header reference voltage MasterBlaster output driver. should match target device's VCCIO. This no-connect ByteBlasterMV header. should attempt configuration with ByteBlaster MasterBlaster, ByteBlasterMV cable while configuration device connected Cyclone FPGA. Instead, should either remove configuration device from socket when using download cable place switch five common signals between download cable configuration device. Remove ByteBlaster MasterBlaster, ByteBlasterMV cable when configuring with configuration device. nINIT_CONF used, nCONFIG must pulled either directly through resistor. pull-up resistors DATA0 DCLK only needed download cable only configuration scheme used your board. This ensure that DATA0 DCLK left floating after configuration. example, also using configuration device, pull-up resistors DATA0 DCLK needed. Connect MSEL0 supply voltage bank resides
more information ByteBlaster MasterBlaster, ByteBlasterMV cables, following documents:
ByteBlaster Parallel Port Download Cable Data Sheet MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet
Altera Corporation January 2007
13-27 Cyclone Device Handbook, Volume
Configuration Schemes
Configuration from Microprocessor
configuration with microprocessor, microprocessor transfers data from storage device target Cyclone FPGA. initiate configuration this scheme, microprocessor must generate low-tohigh transition nCONFIG target device must release nSTATUS. microprocessor then places configuration data time DATA0 Cyclone FPGA. least significant (LSB) each data byte must presented first. Data clocked continuously into target device using DCLK until CONF_DONE signal goes high. Cyclone FPGA starts initialization using internal oscillator after configuration data transferred. After initialization, this internal oscillator turned off. device's CONF_DONE goes high show successful configuration start initialization. During configuration initialization before device enters user microprocessor must drive CONF_DONE low. Driving DCLK device after configuration does affect device operation. Since configuration scheme synchronous scheme, configuration clock speed must below specified maximum frequency ensure successful configuration. Maximum DCLK frequency supported Cyclone FPGAs (see Table 13-5 page 13-30). maximum DCLK period (i.e., minimum DCLK frequency) exists. pause configuration halting DCLK indefinite amount time. target device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option turned Quartus software, target device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure target device without needing pulse nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration initialization. microprocessor sends data, CONF_DONE INIT_DONE gone high, must reconfigure target device. Figure 13-17 shows circuit configuration with microprocessor.
13-28 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-17. Configuration Circuit with Microprocessor
Memory
ADDR DATA0
Cyclone Device
MSEL0 MSEL1 nCEO DATA0 nCONFIG DCLK N.C.
CONF_DONE nSTATUS
Microprocessor
Notes Figure 13-17:
nCEO left unconnected. Connect MSEL0 supply voltage bank resides
Configuring Cyclone FPGAs with MicroBlaster Software
MicroBlastersoftware driver allows configure Altera FPGAs, including Cyclone FPGAs, through ByteBlaster ByteBlasterMV cable mode. MicroBlaster software driver supports Binary File (.rbf) programming input file targeted embedded configuration. source code developed Windows operating system, although customize other operating systems. more information MicroBlaster software driver, Configuring MicroBlaster Passive Serial Software Driver White Paper source files Altera site www.altera.com.
Passive Serial Timing
successful configuration using scheme, several timing parameters such setup, hold, maximum clock frequency must satisfied. enhanced configuration EPC2 devices designed meet these interface timing specifications. microprocessor another intelligent host control interface, ensure that meet these timing requirements.
Altera Corporation January 2007
13-29 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-18 shows timing waveform Cyclone FPGAs. Figure 13-18. Timing Waveform Cyclone FPGAs
tCF2ST1 tCFG nCONFIG tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD tST2CK
CONF_DONE
DCLK DATA tDSU User INIT_DONE Tri-stated with internal pull-up resistor User Mode
tCD2UM
Notes Figure 13-18:
Upon power-up, Cyclone FPGA holds nSTATUS about Upon power-up before configuration, CONF_DONE low. user mode, DCLK should driven high when using configuration scheme. When using configuration scheme, DCLK Cyclone output should driven externally. DATA should left floating after configuration. should driven high low, whichever more convenient.
Table 13-5 contains timing information Cyclone FPGAs.
Table 13-5. Timing Parameters Cyclone Devices Note (Part Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG high first rising edge DCLK nSTATUS high first rising edge DCLK
Data setup time before rising edge DCLK Data hold time after rising edge DCLK
Units
DCLK high time
13-30 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Table 13-5. Timing Parameters Cyclone Devices Note (Part Symbol
tCLK fMAX tCD2UM
Parameter
DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
Notes Table 13-5:
This information preliminary. This value applies only internal oscillator selected clock source device initialization. clock source CLKUSR, multiply clock period obtain this value. CLKUSR must running during this period reset device. minimum maximum numbers apply only internal oscillator chosen clock source device initialization. clock source CLKUSR, multiply clock period obtain this value. obtain this value delay configuration extending nSTATUS low-pulse width.
Device configuration options create configuration files discussed further Software Settings chapter Volume Configuration Handbook.
JTAG-Based Configuration
JTAG developed specification boundary-scan testing. This boundary-scan test (BST) architecture offers capability efficiently test components printed circuit boards (PCBs) with tight lead spacing. architecture test connections without using physical test probes capture functional data while device operating normally. also JTAG circuitry shift configuration data into Cyclone FPGAs. Quartus software automatically generates .sof files that used JTAG configuration.
more information JTAG boundary-scan testing, IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices. SignalTap Embedded Logic Analyzer, need connect JTAG pins your Cyclone device download cableheader your PCB.
more information SignalTap Design Debugging Using SignalTap Embedded Logic Analyzer chapter Quartus Handbook. Cyclone devices designed such that JTAG instructions have precedence over device operating modes. JTAG configuration take place without waiting other configuration complete (e.g., configuration with serial enhanced configuration devices).
Altera Corporation January 2007
13-31 Cyclone Device Handbook, Volume
Configuration Schemes
attempt JTAG configuration Cyclone FPGAs during non-JTAG configuration, non-JTAG configuration terminated JTAG configuration initiated. Cyclone configuration data decompression feature supported JTAG-based configuration.
device operating JTAG mode uses four required pins: TDI, TDO, TMS, TCK. Cyclone FPGAs support optional TRST pin. three JTAG input pins, TCK, TDI, TMS, have weak internal pull-up resistors, whose values approximately user pins tri-stated during JTAG configuration. Table 13-6 shows each JTAG pin's function.
Table 13-6. JTAG Descriptions
Description
Test data input
Function
Serial input instructions well test programming data. Data shifted rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this VCC. Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device. JTAG interface required board, JTAG circuitry disabled leaving this unconnected. Input that provides control signal determine transitions Test Access Port (TAP) controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this VCC. clock input circuitry. Some operations occur rising edge, while others occur falling edge. JTAG interface required board, JTAG circuitry disabled, connecting this GND.
Test data output
Test mode select
Test clock input
JTAG Configuration Using Download Cable
During JTAG configuration, data downloaded device board through Blaster, ByteBlaster ByteBlasterMV, MasterBlaster download cable. Configuring devices through cable similar programming devices in-system. Figure 13-19 connection information.
13-32 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-19. JTAG Configuration Single Cyclone FPGA
Cyclone Device
nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 DATA0 DCLK
ByteBlaster MasterBlaster, ByteBlasterMV 10-Pin Male Header (Top View)
Notes Figure 13-19:
should connect pull-up resistor same supply voltage download cable. should connect nCONFIG, MSEL0, MSEL1 pins support non-JTAG configuration scheme. only JTAG configuration, connect nCONFIG MSEL0 VCC, MSEL1 ground. Pull DATA0 DCLK high low. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlaster this connect. Blaster ByteBlaster this connected when used Active Serial programming; otherwise connect. must connected driven successful configuration.
configure single device JTAG chain, programming software places other devices bypass mode. bypass mode, devices pass programming data from through single bypass register without being affected internally. This scheme enables programming software program verify target device. Configuration data driven into device appears clock cycle later. Quartus software verifies successful JTAG configuration upon completion. software checks state CONF_DONE through JTAG port. CONF_DONE high, Quartus software indicates that configuration failed. CONF_DONE high, software indicates that configuration successful. After configuration stream transmitted serially JTAG port, port clocked additional cycles perform device initialization.
Altera Corporation January 2007
13-33 Cyclone Device Handbook, Volume
Configuration Schemes
VCCIO tied 3.3-V, both pins JTAG port drive 3.3-V levels.
Cyclone FPGAs have dedicated JTAG pins. only perform JTAG testing Cyclone FPGAs before after, also during configuration. While other device families support JTAG testing during configuration, Cyclone FPGAs support BYPASS, IDCODE, SAMPLE instructions during configuration without interrupting configuration. other JTAG instructions only issued first interrupting configuration reprogramming pins using CONFIG_IO instruction. CONFIG_IO instruction allows buffers configured JTAG port, when issued, interrupts configuration. This instruction allows perform board-level testing prior configuring Cyclone FPGA waiting configuration device complete configuration. Once configuration been interrupted JTAG testing complete, part must reconfigured JTAG (PULSE_CONFIG instruction) pulsing nCONFIG low. chip-wide reset output enable pins Cyclone FPGAs affect JTAG boundary-scan programming operations. Toggling these pins does affect JTAG operations (other than usual boundary-scan operation).
13-34 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
When designing board JTAG configuration Cyclone FPGAs, should consider dedicated configuration pins. Table 13-7 shows should connect these pins during JTAG configuration.
Table 13-7. Dedicated Configuration Connections During JTAG Configuration Signal
Description
Drive Cyclone devices chain connecting ground, pulling down resistor, driving some control circuitry. devices multi-device configuration chains, connect pins ground during JTAG configuration configure them JTAG same order configuration chain. Cyclone devices chain, nCEO left floating connected next device. description above. Pulled through 10-k resistor. When configuring multiple devices same JTAG chain, pull each nSTATUS individually. Pulled through 10-k resistor. When configuring multiple devices same JTAG chain, pull each CONF_DONE individually. CONF_DONE must have external 10-k pull-up resistor order device initialize. Driven high connecting VCC, pulling through resistor, driving high some control circuitry. leave these pins floating. These pins support whichever non-JTAG configuration used production. only JTAG configuration used, should these pins ground. leave these pins floating. Drive high, whichever more convenient. leave these pins floating. Drive high, whichever more convenient.
nCEO nSTATUS CONF_DONE
nCONFIG MSEL0, MSEL1 DCLK DATA0
JTAG Configuration Multiple Devices
When programming JTAG device chain, JTAG-compatible header, such ByteBlaster header, connected several devices. number devices JTAG chain limited only drive capacity download cable. However, when four more devices connected JTAG chain, Altera recommends buffering TCK, TDI, pins with on-board buffer. JTAG-chain device configuration ideal when system contains multiple devices, when testing your system using JTAG circuitry. Figure 13-20 shows multi-device JTAG configuration.
Altera Corporation January 2007
13-35 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-20. Multi-Device JTAG Configuration Note
Download Cable 10-Pin Male Header (JTAG Mode)
Cyclone FPGA nSTATUS DATA0 DCLK nCONFIG MSEL1 CONF_DONE MSEL0
Cyclone FPGA nSTATUS DATA0 DCLK nCONFIG MSEL1 CONF_DONE MSEL0
Cyclone FPGA nSTATUS DATA0 DCLK nCONFIG MSEL1 CONF_DONE MSEL0
Notes Figure 13-20:
Cyclone, Stratix, Stratix APEXII, APEX 20K, MercuryTM, ACEX® FLEX® devices placed within same JTAG chain device programming configuration. Connect nCONFIG, MSEL0, MSEL1 pins support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. Pull DATA0 DCLK either high low. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlaster this connect. Blaster ByteBlaster, this connected when used Active Serial programming; otherwise connect. must connected driven successful configuration.
Connect ground drive during JTAG configuration. multi-device configuration chains, connect first device's ground connect nCEO next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, it's nCEO drives activate second device's pin, which prompts second device begin configuration. Therefore, these devices also JTAG chain, should make sure pins connected ground during JTAG configuration that devices configured JTAG same order configuration chain. long devices configured same order multi-device configuration chain, nCEO previous device drives next device when successfully been configured. Figure 13-21 shows JTAG configuration Cyclone FPGA with microprocessor.
13-36 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-21. JTAG Configuration Cyclone FPGAs with Microprocessor
Memory
ADDR DATA MSEL1 nCONFIG MSEL0 DATA0 DCLK nCEO N.C. nSTATUS CONF_DONE
Cyclone FPGA
Microprocessor
Notes Figure 13-21:
Connect nCONFIG, MSEL1, MSEL0 pins support non-JTAG configuration scheme. your design only uses JTAG configuration, connect nCONFIG MSEL1 MSEL0 pins ground. Pull DATA0 DCLK either high low. must connected driver succesful JTAG configuration.
more information about JTAG programming embedded environment, refer 122: Using JamSTAPL &ICR Embedded Processor.
Configuring Cyclone FPGAs with JRunner
JRunner software driver that allows configure Altera FPGAs, including Cyclone FPGAs, through ByteBlaster ByteBlasterMV cables JTAG mode. programming input file supported .rbf format. JRunner also requires Chain Description File (.cdf) generated Quartus software. JRunner targeted embedded JTAG configuration. source code been developed Windows operating system (OS). customize code make other platforms. more information JRunner software driver, JRunner Software Driver: Embedded Solution JTAG Configuration source files Altera site.
STAPL
STAPL, JEDEC standard JESD-71, standard file format insystem programmability (ISP) purposes. STAPL supports programming configuration programmable devices testing electronic systems, using IEEE 1149.1 JTAG interface. STAPL freely licensed open standard.
Altera Corporation January 2007
13-37 Cyclone Device Handbook, Volume
Configuration Schemes
Both JTAG connection methods should include space MasterBlaster ByteBlasterMV header connection. header useful during prototyping because allows verify modify Cyclone FPGA's contents. During production, remove header save cost.
Program Flow Player provides interface manipulating IEEE Std. 1149.1 JTAG state machine. controller 16-state, state machine that clocked rising edge TCK, uses control JTAG operation device. Figure 13-22 shows flow IEEE Std. 1149.1 controller state machine.
13-38 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-22. JTAG Controller State Machine
TEST_LOGIC/ RESET
RUN_TEST/ IDLE
SELECT_DR_SCAN
SELECT_IR_SCAN
CAPTURE_DR
CAPTURE_IR
SHIFT_DR
SHIFT_IR
EXIT1_DR
EXIT1_IR
PAUSE_DR
PAUSE_IR
EXIT2_DR
EXIT2_IR
UPDATE_DR
UPDATE_IR
While Player provides driver that manipulates controller, Byte-Code File (.jbc) provides high-level intelligence needed program given device. instructions that
Altera Corporation January 2007
13-39 Cyclone Device Handbook, Volume
Configuration Schemes
send JTAG data device involve moving controller through either data register instruction register state machine. example, loading JTAG instruction involves moving controller SHIFT_IR state shifting instruction into instruction register through pin. Next, controller moved RUN_TEST/IDLE state where delay implemented allow instruction time latched. This process identical data register scans, except that data register state machine traversed. high-level instructions DRSCAN instruction scanning JTAG data register, IRSCAN instruction scanning instruction register, WAIT command that causes state machine idle specified period time. Each controller scanned repeatedly, according instructions .jbc file, until target devices programmed. Figure 13-23 shows functional behavior Player when parses .jbc file. When Player encounters DRSCAN, IRSCAN, WAIT instruction, generates proper data TCK, TMS, complete instruction. flow diagram shows branches DRSCAN, IRSCAN, WAIT instructions. Although Player supports other instructions, they omitted from flow diagram simplicity.
13-40 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Figure 13-23. Player Flow Diagram (Part
Start
Pulse Five Times Test-Logic-Reset Pulse Run-Test/Idle Switch WAIT Read Instruction from File Case[] DRSCAN
IRSCAN Pulse Run-Test/Idle Delay Parse Argument Parse Argument
EOF?
Pulse Twice Select-IR-Scan
Pulse Select-DR-Scan Pulse Twice Shift-DR Pulse Write Shift-DR
Pulse Three Times Test-Logic-Reset
Switch
Pulse Twice Shift-IR Pulse Write Shift-IR
Pulse Exit1-IR Pulse Pause-IR Pulse Twice Update-IR Pulse Run-Test/Idle Switch
Shift-IR Pulse Write
Continued Part Flow Diagram
Altera Corporation January 2007
13-41 Cyclone Device Handbook, Volume
Configuration Schemes
Figure 13-24. Player Flow Diagram (Part
Continued from Part Flow Diagram
Compare
Case[]
Default Capture
Pulse Store Exit1-DR Loop< Length Pulse Store Exit1-DR Pulse Pulse Update-IR Shift-DR Pulse TCK, Write TDI, Store
Loop< Length Pulse TCK, Write TDI, Store
Correct Value Pulse
Report Error
Pulse Store Exit1-DR
Loop< Length
Run-Test/Idle Switch Pulse Update-IR Pulse Write
Update-IR Pulse Run-Test/Idle Pulse Run-Test/Idle Switch
Switch
Execution program starts beginning program. program flow controlled using GOTO, CALL/RETURN, FOR/NEXT structures. GOTO CALL statements refer labels that symbolic names program statements located elsewhere program. language itself enforces almost constraints organizational structure control flow program. language does support linking multiple programs together including contents another file into program.
13-42 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Instructions Each statement begins with instruction names listed Table 13-8. instruction names, including names optional instructions, reserved keywords that cannot variable label identifiers program.
Table 13-8. Instruction Names
BOOLEAN CALL DRSCAN DRSTOP EXIT EXPORT GOTO
Note Table 13-8:
This instruction name optional language extension.
INTEGER IRSCAN IRSTOP NEXT NOTE POSTDR POSTIR PREDR
PREIR PRINT PUSH RETURN STATE WAIT VECTOR VMAP
Table 13-9 shows state names that reserved keywords language. These keywords correspond state names specified IEEE Std. 1149.1 JTAG specification.
Table 13-9. Reserved Keywords (Part IEEE Std. 1149.1 JTAG State Names
Test-Logic-Reset Run-Test-Idle Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR-Scan Capture-IR
Reserved State Names
RESET IDLE DRSELECT DRCAPTURE DRSHIFT DREXIT1 DRPAUSE DREXIT2 DRUPDATE IRSELECT IRCAPTURE
Altera Corporation January 2007
13-43 Cyclone Device Handbook, Volume
Configuration Schemes
Table 13-9. Reserved Keywords (Part IEEE Std. 1149.1 JTAG State Names
Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR
Reserved State Names
IRSHIFT IREXIT1 IRPAUSE IREXIT2 IRUPDATE
Example File that Reads IDCODE
following illustrates flexibility utility STAPL. example code reads IDCODE single device JTAG chain. array variable, I_IDCODE, initialized with IDCODE instruction bits ordered first left) most significant (MSB) right). This order important because array field IRSCAN instruction always interpreted sent, LSB.
Example File Reading IDCODE BOOLEAN read_data[32]; BOOLEAN I_IDCODE[10] 1001101000; `assumed BOOLEAN ONES_DATA[32] FFFFFFFF; INTEGER `Set stop state IRSCAN IRSTOP IRPAUSE; `Initialize device STATE RESET; IRSCAN I_IDCODE[0.9]; `LOAD IDCODE INSTRUCTION STATE IDLE; WAIT USEC, CYCLES; DRSCAN ONES_DATA[0.31], CAPTURE read_data[0.31]; `CAPTURE IDCODE PRINT "IDCODE:"; PRINT read_data[i]; NEXT EXIT
13-44 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Combining Configuration Schemes
This section shows configure Cyclone FPGAs using multiple configuration schemes same board.
Active Serial JTAG
combine configuration scheme with JTAG-based configuration. MSEL[1.0] pins this setup, shown Figure 13-25. This setup uses 10-pin download cable headers board. first header programs serial configuration device insystem programming interface, second header configures Cyclone FPGA directly JTAG interface. configuring device using both schemes simultaneously, JTAG configuration takes precedence configuration terminated.
Figure 13-25. Combining JTAG Configuration
Serial Configuration Device
Cyclone FPGA nSTATUS CONF_DONE nCEO nCONFIG MSEL1 MSEL0 N.C.
DATA DCLK ASDI
DATA DCLK nCSO ASDO
Download Cable (JTAG Mode) 10-Pin Male Header (top View)
Download Cable Mode) 10-Pin Male Header
Note Figure 13-25:
Connect these pull-up resistors
Altera Corporation January 2007
13-45 Cyclone Device Handbook, Volume
Device Configuration Pins
Device Configuration Pins
Tables 13-10 through 13-12 describe connections functionality configuration related pins Cyclone device. Table 13-10 describes dedicated configuration pins. These pins required connected properly your board successful configuration. Some these pins required your configuration schemes.
Table 13-10. Dedicated Cyclone Device Configuration Pins (Part Name
MSEL1 MSEL0
User Mode
Configuration Scheme
Type
Input
Description
Two-bit configuration input that Cyclone device configuration scheme (see Table 13-2). these pins select Cyclone configuration schemes appropriate connections. These pins must remain valid state during power-up before nCONFIG pulled initiate reconfiguration during configuration. This uses Schmitt trigger input buffers. Configuration control input. Pulling this during user-mode causes FPGA lose configuration data, enter reset state, tri-state pins. Returning this logic high initiates reconfiguration. configuration scheme uses enhanced configuration device EPC2 device, nCONFIG tied directly configuration device's nINIT_CONF pin. This uses Schmitt trigger input buffers
nCONFIG
Input
13-46 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Table 13-10. Dedicated Cyclone Device Configuration Pins (Part Name
nSTATUS
User Mode
Configuration Scheme
Type
Description
Bidirectional device drives nSTATUS immediately after open-drain power-up releases within (When using configuration device, configuration device holds nSTATUS ms.) Status output. error occurs during configuration, nSTATUS pulled target device. Status input. external source drives nSTATUS during configuration initialization, target device enters error state. Driving nSTATUS after configuration initialization does affect configured device. design uses configuration device, driving nSTATUS causes configuration device attempt configure FPGA, since FPGA ignores transitions nSTATUS user-mode, FPGA does reconfigure. initiate reconfiguration, nCONFIG must pulled low. pins enhanced configuration devices EPC2 devices have optional internal programmable pull-up resistors. design uses internal pull-up resistors, external 10-k pull-up resistors these pins. This uses Schmitt trigger input buffers
CONF_DONE
Bidirectional Status output. target device drives open-drain CONF_DONE before during configuration. Once configuration data received without error initialization clock cycle starts, target device releases CONF_DONE. Status input. After data received CONF_DONE goes high, target device initializes enters user mode. Driving CONF_DONE after configuration initialization does affect configured device. pins enhanced configuration devices EPC2 devices have optional internal programmable pull-up resistors. design uses internal pull-up resistors, external 10-k pull-up resistors these pins. This uses Schmitt trigger input buffers
Altera Corporation January 2007
13-47 Cyclone Device Handbook, Volume
Device Configuration Pins
Table 13-10. Dedicated Cyclone Device Configuration Pins (Part Name
DCLK
User Mode
Configuration Scheme
Type
Description
Input (PS) configuration, clock input clocks data from Output (AS) external source into target device. Data latched into FPGA rising edge DCLK. configuration, DCLK output from Cyclone FPGA that provides timing configuration interface. After configuration, logic levels this affect Cyclone FPGA. This uses Schmitt trigger input buffers Output Control signal from Cyclone FPGA serial configuration device mode used read configuration data. Output control signal from Cyclone FPGA serial configuration device mode that enables configuration device. Active-low chip enable. activates device with signal allow configuration. must held during configuration, initialization, user mode. single device configuration, low. multi-device configuration, first device's tied while nCEO connected next device chain. Hold programming FPGA JTAG. This uses Schmitt trigger input buffers Output that drives when device configuration complete. single device configuration, this left floating. multi-device configuration, this feeds next device's pin. nCEO last device chain left floating. Data input. serial configuration mode, bit-wide configuration data presented target device DATA0 pin. Toggling DATA0 after configuration does affect configured device. This uses Schmitt trigger input buffers
ASDO
mode, mode mode, mode
nCSO
Output
Input
nCEO
Output
DATA0
Input
13-48 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Table 13-11 describes optional configuration pins. these optional configuration pins enabled Quartus software, they available general-purpose user pins. Therefore during configuration, these pins function user pins tri-stated with weak pull-ups.
Table 13-11. Optional Cyclone Device Configuration Pins Name
CLKUSR
User Mode
Type
Description
Optional user-supplied clock input. Synchronizes initialization more devices. This enabled turning Enable user-supplied start-up clock (CLKUSR) option Quartus software.
Input option option
INIT_DONE option
Output Status pin. used indicate when device option open-drain initialized user mode. INIT_DONE must pulled with 10-k resistor. INIT_DONE drives during configuration. Before after configuration, INIT_DONE released pulled external pull-up resistor. Because INIT_DONE tri-stated before configuration, pulled high external pull-up resistor. Thus, monitoring circuitry must able detect low-tohigh transition. This enabled turning Enable INIT_DONE output option Quartus software. option option off. Input Optional that allows user override tri-states device. When this driven low, pins tri-stated; when this driven high, pins behave programmed. This enabled turning Enable device-wide output enable (DEV_OE) option Quartus software. Optional that allows override clears device registers. When this driven low, registers cleared; when this driven high, registers behave programmed. This enabled turning Enable device-wide reset (DEV_CLRn) option Quartus software.
DEV_OE
DEV_CLRn
option option off.
Input
Table 13-12 describes dedicated JTAG pins. JTAG pins must kept stable before during configuration prevent accidental loading JTAG instructions.
Altera Corporation January 2007
13-49 Cyclone Device Handbook, Volume
Device Configuration Pins
Table 13-12. Dedicated JTAG Pins Name
User Type Mode
Input
Description
Serial input instructions well test programming data. Data shifted rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this This uses Schmitt trigger input buffers Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device. JTAG interface required board, JTAG circuitry disabled leaving this unconnected. Input that provides control signal determine transitions controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this This uses Schmitt trigger input buffers clock input circuitry. Some operations occur rising edge, while others occur falling edge. JTAG interface required board, JTAG circuitry disabled connecting this ground. This uses Schmitt trigger input buffers
Output
Input
Input
13-50 Cyclone Device Handbook, Volume
Altera Corporation January 2007
Configuring Cyclone FPGAs
Document Revision History
Table 13-13 shows revision history this document.
Table 13-13. Document Revision History Date Document Version
January 2007 v1.7
Changes Made
Added document revision history. Removed note from Table 13-2. Updated Figure 13-1. Updated Table 13-3. Updated feetpara note "Active Serial Configuration (Serial Configuration Devices)" section. Updated feetpara note page 13-18. Updated Note Figure 13-11. Updated Note Figure 13-12. Updated Note Figure 13-19.
Summary Changes
July 2006, v1.6 August 2005 v1.5 March 2005 v1.4 February 2005 v1.3 August 2004 v1.2
Updated Figure 13-19.
Updated tables. Minor text updates. Updated Figure 13-1. Updated Figure 13-10.
Updated Figure 13-13.
Deleted sections: Programming Configuration Devices, Connecting JTAG Chain, Passive Serial JTAG, Device Options, Device Configuration Files, Configuration Reliability, Board Layout Tips. Deleted figures: Embedded System Block Diagram, Combining JTAG Configuration, Configuration Options Dialog Box. Deleted table: Cyclone Configuration Option Bits. Added: Blaster cable list; Figure 13-13; text pages 13-14, 13-29, 13-30, information Table 13-6. Changes Figures 13-14 13-16, 13-19, 13-20, 13-25; numbers changed EP1C4 Table 13-3. Added extensive descriptions configuration methods under "Configuring Multiple Devices with Same Data" section.
July 2003 v1.1 2003 v1.0
Updated .rbf sizes. Minor updates throughout document. Added document Cyclone Device Handbook.
Altera Corporation January 2007
13-51 Cyclone Device Handbook, Volume
Document Revision History
13-52 Cyclone Device Handbook, Volume
Altera Corporation January 2007

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