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Chapter Cyclone Device Datasheet: Switching Characteristics Refer


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This section includes following chapter:
Chapter Cyclone Device Datasheet: Switching Characteristics
Refer each chapter specific revision history. information when each chapter updated, refer Chapter Revision Dates section, which appears complete handbook.
Altera Corporation
Section
Cyclone Device Handbook, Volume
Section
Altera Corporation
Cyclone Device Datasheet: Switching Characteristics
CIII52001-1.3
Electrical Characteristics
Operating Conditions
When Cyclone® devices implemented system, they rated according defined parameters. maintain highest possible performance reliability Cyclone devices, system designers must consider operating requirements within this document. Cyclone devices offered both commercial industrial grades. Commercial devices offered (fastest), speed grades.
Absolute Maximum Ratings
Absolute maximum ratings define maximum operating conditions Cyclone devices. values based experiments conducted with device theoretical modeling breakdown damage mechanisms. functional operation device implied these conditions. Conditions beyond those listed Table cause permanent damage device. Additionally, device operation absolute maximum ratings extended periods time have adverse effects device. parameters representing voltages measured with respect ground.
Table 1-1. Cyclone Device Absolute Maximum Ratings Note Symbol
VCCINT VCCIO VCCA VCCD_PLL IOUT TSTG Note Table 1-1:
Supply voltage specifications apply voltage readings taken device pins, power supply.
Parameter
Supply voltage internal logic input buffers Supply voltage output buffers Supply (analog) voltage regulator Supply (digital) voltage input voltage output current, Electrostatic discharge voltage using human body model Electrostatic discharge voltage using charged device model Storage temperature Operating junction temperature
-0.5 -0.5 -0.5 -0.5 -0.5
3.75 3.95 ±2000 ±500
Unit
Maximum Allowed Overshoot/Undershoot Voltage During transitions, input signals overshoot voltage shown Table undershoot -2.0 input currents less than periods shorter than Table lists maximum allowed input overshoot voltage duration overshoot voltage percentage over lifetime device. maximum allowed overshoot duration specified percentage high-time over lifetime device.
Altera Corporation July 2007
Electrical Characteristics
signal equivalent 100% duty cycle. example, signal that overshoots only 10.74% over lifetime device; device lifetime years, this amounts 10.74/10ths year. Figure shows determine overshoot duration.
Table 1-2. Maximum Allowed Overshoot During Transitions over 10-Year Time Frame Symbol
Parameter
Input Voltage
Condition
3.95 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50 4.60 4.70
Overshoot Duration High Time
95.67 55.24 31.97 18.52 10.74 6.23 3.62 1.22 0.71 0.41 0.14 0.047
Unit
Note Table 1-2:
Figure shows methodology determine overshoot duration. example Figure 1-1, overshoot voltage shown present Cyclone input over below From Table 1-1, overshoot percentage high time overshoot high 31.97 over 10-year period. Percentage high time calculated ((delta T)/T) 100. This 10-year period assumes device always turned with 100% toggle rate duty cycle signal. lower toggle rates situations where device idle state, lifetimes increased.
Figure 1-1. Overshoot Duration
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Electrical Characteristics
Recommended Operating Conditions
This section lists functional operation limits parameters Cyclone devices. steady-state voltage current values expected from Cyclone devices provided Table 1-3. supplies must strictly monotonic without plateaus.
Table 1-3. Recommended Operating Conditions Notes (1), Symbol
VCCINT VCCIO
Parameter
Supply voltage internal logic input buffers Supply voltage output buffers, 3.3-V operation Supply voltage output buffers, 3.0-V operation Supply voltage output buffers, 2.5-V operation Supply voltage output buffers, 1.8-V operation Supply voltage output buffers, 1.5-V operation Supply voltage output buffers, 1.2-V operation
Conditions
commercial industrial
1.15 3.15 2.85 2.375 1.71 1.425 1.14 2.375 1.15 -0.5
1.25 3.45 3.15 2.625 1.89 1.575 1.26 2.625 1.25 VCCIO
Unit
VCCA VCCD_PLL tRAMP
Supply (analog) voltage regulator Supply (digital) voltage Input voltage Output voltage Operating junction temperature
Power supply ramptime
Standard Fast
Notes Table 1-3:
VCCIO banks should powered during device operation. VCCA pins must powered (even when PLLs used), must powered-up powered-down same time. VCCD_PLL must always connected VCCINT through decoupling capacitor ferrite bead. must rise monotonically. time Standard will range between supplies must stable within time Fast will range between supplies must stable within
Characteristics
This section lists leakage currents, capacitance, chip termination tolerance hold specifications Cyclone devices. Supply Current Standby current current device draws after device configured with inputs/outputs toggling activity device. Since these currents vary largely with resources used, Excel based Early Power Estimator supply current estimates your design. Table lists leakage current Cyclone III.
Table 1-4. Cyclone Leakage Current Notes (1), (Part Symbol
Parameter
Input Leakage Current Tri-stated Leakage Current
Conditions
VCCIOMAX VCCIOMAX
Unit
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-4. Cyclone Leakage Current Notes (1), (Part Symbol
Parameter
supply current (standby)
Conditions
ground, load, toggling inputs,
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
11.3 11.3 11.4 18.4 18.6 18.7 18.9 19.2
Unit
supply current (standby)
ground, load, toggling inputs,
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
supply current (standby)
ground, load, toggling inputs,
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
supply current (standby)
ground, load, toggling inputs,
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120
Notes Table 1-4:
This value specified normal device operation. value vary during power-up. This applies VCCIO settings (3.3, 3.0, 2.5, 1.8, leakage current limit applicable when internal clamping diode off. higher current observed when diode Maximum values depend actual design utilization. Refer Excel-based PowerPlay Early Power Estimator (available Quartus PowerPlay Power Analyzer feature maximum values. Refer "Power Consumption" page 1-11" more information.
Cyclone Device Handbook, Volume
Altera Corporation July 2007
Electrical Characteristics
Hold hold retains last valid logic state after source driving either enters high impedance state removed. Each option enable hold user mode. hold always disabled configuration mode. Table lists hold specifications Cyclone III. Also listed input capacitances on-chip termination tolerance specifications.
Table 1-5. Cyclone Hold Parameter Note VCCIO Parameter Condition
Bus-hold low, sustaining current Bus-hold high, sustaining current Bus-hold low, overdrive current Bus-hold high, overdrive current Bus-hold trip point (maximum) (minimum) VCCIO VCCIO
Unit
0.375
0.68
-125
-175
1.125
-200
1.07
-300
-500
-500
Note Table 1-5:
bus-hold trip points based calculated input voltages from JEDEC standard.
On-Chip Termination (OCT) Specifications Table lists variation uncalibrated across process, temperature voltage.
Table 1-6. Uncalibrated On-Chip Series Termination Specifications Resistance Tolerance Symbol VCCIO Commercial
Series Termination without calibration Note Table 1-6:
Pending silicon characterization
Preliminary
Industrial
Unit
calibration automatically performed power enabled I/Os.
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Electrical Characteristics
Table lists calibration accuracy power
Table 1-7. On-Chip Series Termination Power-up Calibration Specifications Calibration Accuracy Symbol
Series Termination with power-up calibration
Preliminary
VCCIO
Commercial
±10% ±10% ±10% ±10% ±10%
Industrial
Unit
Note Table 1-7:
Pending silicon characterization
Table lists percentage change resistance with voltage temperature. Table Equation determine variation after power-up calibration.
Table 1-8. On-Chip Termination Variation After Power-up Calibration Nominal Voltage
Note Table 1-8:
This table needed calculate final resistance with variation temperature voltage.
dR/dT (%Ohm/°C)
0.262 0.234 0.219 0.199 0.161
dR/dmV (%Ohm/mV)
-0.026 -0.039 -0.086 -0.136 -0.288
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Electrical Characteristics
Equation 1-1. Notes (1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12)
1000 dR/dmV dR/dT (|Rx|/100 Rx/100 Rfinal Rinitial
Notes Equation 1-1:
(10) (11) (12) variation resistance with voltage. variation resistance with temperature. dR/dT percentage change resistance with temperature. dR/dmV percentage change resistance with voltage. final voltage. initial voltage. final temperature. initial temperature. multiplication factor. Rfinal final resistance. Rinitial initial resistance. Subscript refers both
example, calculate change impedance from 3.15 (3.15 1000 -0.026 -3.83 0.262 15.72 Since negative, 3.83/100 0.963 Since positive, 15.72/100 1.157 0.963 1.157 1.114 Rfinal 1.114 55.71 Capacitance Table shows Cyclone device family capacitance.
Table 1-9. Cyclone Device Capacitance Note (Part Symbol
CIOTB CIOLR CLVDSLR CVREFLR CVREFTB CCLKTB
Preliminary Typical
Parameter
Input capacitance top/bottom pins Input capacitance left/right pins Input capacitance left/right pins with Dedicated LVDS output Input capacitance left/right pins with VREF Input capacitance top/bottom pins with VREF Input capacitance top/bottom dedicated clock input pins
Typical FBGA
Unit
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-9. Cyclone Device Capacitance Note (Part Symbol
CCLKLR
Preliminary Typical
Parameter
Input capacitance left/right dedicated clock input pins
Typical FBGA
Unit
Notes Table 1-9:
Pending silicon characterization. EP3C25
Internal Weak Pull-up Weak Pull-down Resistor Table 1-10 lists weak pull-up pull-down resistor values Cyclone devices.
Table 1-10. Cyclone Internal Weak Pull-Up Weak Pull-Down Resistor Note Symbol
RCONF_PU
Parameter
Value pull-up resistor before during configuration
Conditions
VCCIO 5%(3), VCCIO (3), VCCIO (3), VCCIO (3), VCCIO (3), VCCIO (3),
Unit
RCONF_PD
Value pull-down resistor before during configuration
VCCIO (3), VCCIO (3), VCCIO (3), VCCIO (3), VCCIO (3),
Notes Table 1-10:
pins have option enable weak pull-up except configuration, test JTAG pin. Weak pull-down feature only available JTAG TCK. RCONF values based characterization. RCONF VCCIO/IRCONF. RCONF values different value refers input voltage pin. pull-up resistance values lower external source drives higher than VCCIO. Minimum condition -40° high VCC, typical condition nominal maximum condition 125° RCONF values.
Socketing Table 1-11 lists hot-socketing specifications Cyclone devices.
Table 1-11. Cyclone Socketing Specifications Symbol
IIOPIN(DC) IIOPIN(AC) Note Table 1-11:
ramp rate more. ramp rates faster than |IIOPIN| dv/dt, where capacitance dv/dt slew rate.
Parameter
current current
Maximum
Cyclone Device Handbook, Volume
Altera Corporation July 2007
Electrical Characteristics
Standard Specifications
following tables list input voltage sensitivities (VIH VIL), output voltage (VOH VOL), current drive characteristics (IOH IOL) various standards supported Cyclone devices. Table 1-12 Table 1-17 show Cyclone device family standard specifications. Refer "Single-ended Voltage referenced Standard" "Glossary" voltage referenced receiver input waveform explanation terms used Table 1-12.
Table 1-12. Single-Ended Standard Specifications Note VCCIO(V) Standard
3.3-V LVTTL 3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS 2.5-V LVTTL LVCMOS 3.15 3.15 2.85 2.85 2.375
VIL(V)
3.45 3.45 3.15 3.15 2.625
VIH(V)
VOL(V)
VOH(V)
VCCIO VCCIO 0.45
-0.1 -0.1 -0.5
-0.3 -0.3 -0.3
0.45 0.45
(mA) (mA)
VCCIO VCCIO VCCIO
1.8-V LVTTL LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS PCI-X Notes Table 1-12:
1.71 1.425 1.14 2.85
1.89 1.575 1.26 3.15
-0.3 -0.3 -0.3
0.35 VCCIO 0.65 VCCIO
2.25
0.45
0.35 VCCIO 0.65 VCCIO VCCIO 0.25 VCCIO 0.75 VCCIO 0.35 VCCIO 0.65 VCCIO VCCIO 0.25 VCCIO 0.75 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
load more detail interfacing Cyclone devices with 3.3/3.0/2.5-V LVTTL/LVCMOS standards, refer 447: Interfacing Cyclone Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS Systems. Specified valid with lowest current strength setting available respective standards. values correspond selected current strength settings value. example, current drive characteristics 3.3-V LVTTL with current strength setting (IOL) (IOH) 0.45 (VOL) (VOH), respectively.
Refer "Glossary" explanation terms used Table 1-13.
Table 1-13. Single-Ended SSTL HSTL Reference Voltage Specifications Standard
SSTL-2 Class SSTL-18 Class HSTL-18 Class HSTL-15 Class HSTL-12 Class 2.375 1.71 1.425 1.14
VCCIO(V)
VREF(V)
2.625 1.89 1.575 1.26
VTT(V)
1.31 0.969 0.95 0.79 0.52 VCCIO 0.53 VCCIO
1.19 0.833 0.85 0.71 0.48 VCCIO 0.47 VCCIO
1.25 0.75 VCCIO VCCIO
VREF 0.04 VREF 0.04 0.85 0.71
VREF VREF 0.75 VCCIO
VREF 0.04 VREF 0.04 0.95 0.79
Notes Table 1-13:
Value shown refers input reference voltage, VREF(DC). Value shown refers input reference voltage, VREF(AC). transmitting device must track VREF receiving device.
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-14. Single-Ended SSTL HSTL Standards Signal Specifications
Standard
SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class HSTL-18 Class HSTL-18 Class HSTL-15 Class HSTL-15 Class HSTL-12 Class -0.15
VIL(DC)(V)
VREF 0.18 VREF 0.18
VIH(DC)(V)
VREF 0.18 VREF 0.18
VIL(AC)(V)
VIH(AC)(V)
VOL(V)
0.57 0.76
VOH(V)
0.57 0.76
(mA)
16.4 13.4
(mA)
-8.1 -16.4 -6.7 -13.4
VREF 0.35 VREF 0.35 VREF 0.35 VREF 0.35 VREF 0.25 VREF 0.25 VREF 0.25 VREF 0.25 VREF VREF VREF VREF VREF VREF VREF VREF
VREF 0.125 VREF 0.125 VREF 0.125 VREF 0.125 VREF VREF VREF VREF VREF 0.08 VREF 0.08 VREF VREF VREF VREF
0.475 0.475 0.28 VCCIO 0.28 VCCIO VCCIO VCCIO VCCIO
VREF 0.08 VCCIO 0.15 -0.24 VREF 0.15 VREF 0.15 VCCIO 0.24 0.25 VCCIO 0.75 VCCIO VREF 0.08 VCCIO 0.15 -0.24 VREF 0.15 VREF 0.15 VCCIO 0.24 0.25 VCCIO 0.75 VCCIO
HSTL-12 Class -0.15
more illustrations receiver input transmitter output waveforms, other differential standards, refer High-Speed Differential Interfaces chapter volume Cyclone Device Handbook.
Table 1-15. Differential SSTL Standard Specifications Standard
SSTL-2 Class SSTL-18 Class Note Table 1-15:
Pending silicon characterization.
2.375
VCCIO(V)
VSwing(DC)(V)
2.625 1.90 0.36 0.25
VX(DC)(V)
VCCIO/2 VCCIO/2 0.175
VSwing(AC)(V)
VCCIO/2
VOX(AC)(V)
VCCIO/2 0.125
VCCIO VCCIO
VCCIO VCCIO
VCCIO/2 0.125
VCCIO/2 0.175
Table 1-16. Differential HSTL Standard Specifications Standard
HSTL-18 Class HSTL-15 Class HSTL-12 Class
VCCIO(V)
VDIF(DC)(V)
1.89 1.575 1.26
VX(AC)(V)
0.85 0.71 0.48
VCM(DC)(V)
0.95 0.79
VDIF(AC)(V)
0.95 0.79
0.85 0.71
1.71 1.425 1.14
0.16
0.52 0.48
0.52
0.48
1-10 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Electrical Characteristics
Refer "Transmitter Output Waveform" "Glossary" explanation terms used Table 1-17.
Table 1-17. Differential Standard Specifications
Standard
LVPECL (Row I/Os) 2.375
VCCIO(V)
VTH(mV) Condition
1.25V
VIN(V) Condition
DMAX Mbps
VOD(mV)
1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85
VOS(V)
2.625 -100
1.125 1.25 1.375
Mbps DMAX Mbps
DMAX Mbps DMAX Mbps
LVPECL 2.375 (Column I/Os)
2.625 -100
1.25V
1.125 1.25 1.375
Mbps DMAX Mbps
DMAX Mbps DMAX Mbps
LVDS (Row I/Os)
2.375
2.625 -100
=1.25V
1.125 1.25 1.375
Mbps DMAX Mbps
DMAX Mbps DMAX Mbps
LVDS (Column I/Os)
2.375
2.625 -100
1.25V
1.125 1.25 1.375
Mbps DMAX Mbps
DMAX Mbps
mini-LVDS (Row I/Os)
2.375
2.625 2.625 2.625
mini-LVDS 2.375 (Column I/Os) RSDS® (Row I/Os)(3) 2.375
RSDS 2.375 (Column I/Os) 2.375 PPDS® (Row I/Os) PPDS 2.375 (Column I/Os)
2.625 2.625
2.625
Notes Table 1-17:
range LVPECL input standard only supported clock input. Output standard supported. Mini-LVDS, RSDS PPDS standards only supported output pins Cyclone devices. RSDS PPDS registered trademarks National Semiconductor.
Power Consumption
Altera® offers ways estimate power design: Excel-based Early Power Estimator Quartus® PowerPlay Power Analyzer feature. interactive Excel-based Early Power Estimator typically used prior designing device order magnitude estimate device power. Quartus PowerPlay Power Analyzer provides better quality estimates based specifics design after place-and-route complete. PowerPlay Power Analyzer apply combination user-entered, simulation-derived, estimated signal activities which, combined with detailed circuit models, yield very accurate power estimates.
more information power estimation tools, refer Early Power Estimator User Guide PowerPlay Power Analysis chapters Quartus Handbook.
Altera Corporation July 2007
1-11 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Switching Characteristics
This section provides performance characteristics Cyclone core periphery blocks commercial grade devices. These characteristics designated Preliminary Final. Each designation defined below. Preliminary Final
Preliminary characteristics created Final numbers based actual silicon characterization testing. using simulation results, process data, These numbers reflect actual performance device under worst-case silicon process, voltage junction temperature other known parameters. conditions.
upper-right hand corner table shows designation 'Preliminary' 'Final'.
Core Performance Specifications
Clock Tree Specifications
Table 1-18 lists clock tree specifications Cyclone devices.
Table 1-18. Cyclone Clock Tree Performance Performance Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Notes Table 1-18:
EP3C120 offered speed grades only. Pending silicon characterization.
Preliminary
Speed Grade
Speed Grade
437.5
Speed Grade
Unit
Specifications
Table 1-19 describes Cyclone specifications when operating both commercial junction temperature range industrial junction temperature range (-40° 100° more information Block, refer "PLL Block" "Glossary".
Table 1-19. Cyclone Specifications Note (Part Symbol
Preliminary
Parameter
Input clock frequency speed grade) Input clock frequency speed grade) Input clock frequency speed grade)
472.5 472.5 472.5
Unit
fINPFD
input frequency speed grade) input frequency speed grade) input frequency speed grade)
1-12 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Switching Characteristics
Table 1-19. Cyclone Specifications Note (Part Symbol
fVCO fINDUTY tINJITTER
Preliminary
Parameter
internal operating range Input clock duty cycle Input clock period jitter
1300 472.5 472.5 472.5 472.5 402.5
Unit
SCANCLK cycles
fOUT_EXT (external clock output) output frequency speed grade) output frequency speed grade) output frequency speed grade) fOUT global clock) output frequency speed grade) output frequency speed grade) output frequency speed grade) tOUTDUTY tLOCK tDLOCK TJIT R_DEDCLK TJIT R_IO tPLL_PSERR tARESET tCONFIGPLL fSCANCLK Notes Table 1-19:
Duty cycle external clock output (when 50%) Time required lock from device configuration Time required lock dynamically (after switchover reconfiguring non-post-scale counters/delays) Dedicated clock output period jitter Regular period jitter Accuracy phase shift Minimum pulse width areset signal. Time required reconfigure scan chains PLLs scanclk frequency
This parameter limited Quartus software maximum frequency. maximum frequency different each standard. extended temperature devices, maximum lock time With scanclk frequency. Pending silicon characterization. VCCD_PLL should always connected VCCINT through decoupling capacitor ferrite bead.
Embedded Multiplier Specifications
Table 1-20 describes Cyclone embedded multiplier specifications.
Table 1-20. Cyclone Embedded Multiplier Specifications Resources Used Mode Number Multipliers
9-bit multiplier 18-bit multiplier
Preliminary Performance
Speed Grade
Speed Grade
Speed Grade
Unit
Altera Corporation July 2007
1-13 Cyclone Device Handbook, Volume
Switching Characteristics
Memory Block Specifications
Table 1-21 describes Cyclone Memory block specifications.
Table 1-21. Cyclone Memory Block Performance Specifications Note Resources Used Memory
Block FIFO Single-port Simple dual-port True dual port single Note Table 1-21:
Values device speed grade will available after characterization.
Preliminary Performance Speed Grade
Mode
Memory
Unit
Configuration JTAG Specifications
Table 1-22 lists Cyclone Configuration Mode Specifications.
Table 1-22. Cyclone Configuration Mode Specifications Programming Mode
Passive Serial (PS) Fast Passive Parallel (FPP) Note Table 1-22:
EP3C25 smaller family members support MHz.
Preliminary Unit
DCLK Fmax
Table 1-23 lists Cyclone Active Configuration Mode Specifications.
Table 1-23. Cyclone Active Configuration Mode Specifications Programming Mode
Active Parallel (AP) Active Serial (AS)
Preliminary Unit
DCLK Range
Table 1-24 shows JTAG timing parameters values Cyclone III. more information, refer "JTAG Waveform" "Glossary".
Table 1-24. Cyclone JTAG Timing Parameters (Part Symbol
tJCP tJCH tJCL tJPSU_TDI tJPSU_TMS tJPH tJPCO tJPZX clock period clock high time clock time JTAG port setup time TDI(1) JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output
Preliminary
Parameter
Unit
Altera Corporation July 2007
1-14 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-24. Cyclone JTAG Timing Parameters (Part Symbol
tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Preliminary
Parameter
JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Unit
Note Table 1-24:
specification shown LVTTL/LVCMOS operation JTAG pins. 1.8- LVTTL/LVCMOS 1.5- LVCMOS, JTAG port clock output time
Periphery Performance
High-Speed Specification
Table 1-25 Table 1-34 show high-speed timing Cyclone devices. Refer "Glossary" definitions high-speed timing specifications.
Table 1-25. Dedicated RSDS Transmitter Timing Specification Notes (2), Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
Mbps Mbps Mbps Mbps Mbps Mbps
Device operation Mbps
tDUTY TCCS Output jitter (peak peak) tRISE tFALL tLOCK Notes Table 1-25:
Pending silicon characterization. Values device speed grade will available after characterization. Dedicated RSDS only supported output (Banks
Altera Corporation July 2007
1-15 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-26. Single-Resistor RSDS Transmitter Timing Specification Notes (2), Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
Mbps Mbps Mbps Mbps Mbps Mbps
Device operation Mbps
tDUTY TCCS Output jitter (peak peak) tRISE tFALL tLOCK Notes Table 1-26:
Pending silicon characterization. Values device speed grade will available after characterization. Single-resistor RSDS only supported output Column (Banks
Table 1-27. Three-Resistor RSDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
155.5 155.5 155.5 155.5 155.5 155.5 Mbps Mbps Mbps Mbps Mbps Mbps
Device operation Mbps
tDUTY TCCS Output jitter (peak peak) tRISE
Altera Corporation July 2007
1-16 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-27. Three-Resistor RSDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
tFALL tLOCK Notes Table 1-27:
Pending silicon characterization. Values device speed grade will available after characterization. Three-resistor RSDS only supported output Column (Banks
Modes
Unit
Table 1-28. Dedicated PPDS Transmitter Timing Specification Notes (2), Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
Mbps Mbps Mbps Mbps Mbps Mbps
Device operation Mbps
tDUTY TCCS Output jitter (peak peak) tRISE tFALL tLOCK Notes Table 1-28:
Pending silicon characterization. Values device speed grade will available after characterization. Dedicated PPDS only supported output (Banks
Table 1-29. Three-Resistor PPDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
Altera Corporation July 2007
1-17 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-29. Three-Resistor PPDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
Device operation Mbps
Modes
Unit
Mbps Mbps Mbps Mbps Mbps Mbps
tDUTY TCCS Output jitter (peak peak) tRISE tFALL tLOCK Notes Table 1-29:
Pending silicon characterization. Values device speed grade will available after characterization. Three-resistor PPDS only supported output Column (Banks
Table 1-30. Dedicated Mini-LVDS Transmitter Timing Specification Notes (2), Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
1.30 Mbps Mbps Mbps Mbps Mbps Mbps
Device operation Mbps
tDUTY TCCS Output jitter (peak peak) tRISE tFALL tLOCK Notes Table 1-30:
Pending silicon characterization. Values device speed grade will available after characterization. Dedicated mini-LVDS only supported output (Banks
Altera Corporation July 2007
1-18 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-31. Three-Resistor mini-LVDS Transmitter Timing Specification Notes (2), Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
155.5 155.5 155.5 155.5 155.5 155.5 Mbps Mbps Mbps Mbps Mbps Mbps
Device operation Mbps
tDUTY TCCS Output jitter (peak peak) tRISE tFALL tLOCK Notes Table 1-31:
Pending silicon characterization. Values device speed grade will available after characterization. Three-resistor mini-LVDS only supported output Column (Banks
Table 1-32. Dedicated LVDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
Mbps Mbps Mbps Mbps Mbps Mbps
HSIODR
tDUTY TCCS Output jitter (peak peak)
Altera Corporation July 2007
1-19 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-32. Dedicated LVDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
tRISE tFALL tLOCK Notes Table 1-32:
Pending silicon characterization. Values device speed grade will available after characterization. maximum data rate that complies with duty cycle distortion 45-55%. maximum data rate when taking duty cycle absolute into consideration that comply with 45-55% duty cycle distortion. downstream receiver handle duty cycle distortion beyond 45-55% range, higher data rate values from this column. calculate duty cycle distortion percentage using absolute value. example, data rate Mbps 1625 tDUTY duty cycle distortion tDUTY/(UI*2) *100% ps/(1625 100% 7.7%, which gives duty cycle distortion 42.3-57.7%. Dedicated LVDS transmitter only supported output (Banks
Modes
Unit
Table 1-33. Three-Resistor LVDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
402.5 402.5 Mbps Mbps Mbps Mbps Mbps Mbps
HSIODR
tDUTY TCCS Output jitter (peak peak) tRISE tFALL
Altera Corporation July 2007
1-20 Cyclone Device Handbook, Volume
Switching Characteristics
Table 1-33. Three-Resistor LVDS Transmitter Timing Specification Notes (2), (Part Speed Grade Symbol
tLOCK Notes Table 1-33:
Pending silicon characterization. Values device speed grade will available after characterization. maximum data rate that complies with duty cycle distortion 45-55%. maximum data rate when taking duty cycle absolute into consideration that comply with 45-55% duty cycle distortion. downstream receiver handle duty cycle distortion beyond 45-55% range, higher data rate values from this column. calculate duty cycle distortion percentage using absolute value. example, data rate Mbps 1625 tDUTY duty cycle distortion tDUTY/(UI*2) *100% ps/(1625 100% 7.7%, which gives duty cycle distortion 42.3-57.7%. Three-resistor LVDS only supported output Column (Banks
Modes
Unit
Table 1-34. Dedicated LVDS Receiver Timing Specification Notes (2), Speed Grade Symbol
fHSCLK (input clock frequency)
Modes
Unit
437.5 437.5 437.5 437.5 437.5 437.5 437.5 Mbps Mbps Mbps Mbps Mbps Mbps
HSIODR
Input jitter tolerance tLOCK Notes Table 1-34:
Pending silicon characterization. Values device speed grade will available after characterization. Dedicated LVDS Receiver supported banks.
Altera Corporation July 2007
1-21 Cyclone Device Handbook, Volume
Switching Characteristics
External Memory Interface Specifications
Cyclone devices support external memory interfaces MHz. Cyclone external memory interfaces auto-calibrating easy implement. Table 1-35 Table 1-38 list External Memory Interface Specifications Cyclone device family. following tables memory interface timing analysis.
Table 1-35. Cyclone Maximum Clock Rate Support External Memory Interfaces Notes Commercial Memory Standard
DDR2 SDRAM
Standard
SSTL-18 class SSTL-18 class SSTL-2 class SSTL-2 class
Speed Grade (MHz) Column I/Os
Speed Grade (MHz) Column I/Os
Speed Grade (MHz) Column I/Os
I/Os
I/Os
I/Os
SDRAM
QDRII 1.8-V HSTL class SRAM 1.8V HSTL class Notes Table 1-35:
These numbers preliminary until characterization final. values apply interfaces with both modules components. Support will evaluated after characterization. QDRII SRAM also supports 1.5-V HSTL standard. However, Altera recommends using 1.8-V HSTL standard maximum performance because higher Current Strength. Column I/Os refer Bottom I/Os. I/Os refer Right Left I/Os.
Table 1-36. FPGA Sampling Window (SW) Requirement Read Side Note Speed Grade Memory Standards
DDR2 SDRAM SDRAM QDRII SRAM Note Table 1-36:
Column I/Os refer Bottom I/Os. I/Os refer Right Left I/Os.
Preliminary Speed Grade Column I/Os Setup
Speed Grade Column I/Os Setup
Column I/Os Setup
I/Os Setup
I/Os Setup
I/Os Setup
Units
Hold
Hold
Hold
Hold
Hold
Hold
Altera Corporation July 2007
1-22 Cyclone Device Handbook, Volume
Timing
Table 1-37. Transmitter Channel-to-Channel Skew (TCCS) Write Side Note Speed Grade Memory Standards
DDR2 SDRAM SDRAM QDRII SRAM Note Table 1-37:
Column I/Os refer Bottom I/Os. I/Os refer Right Left I/Os.
Preliminary Speed Grade Column I/Os Lead
Speed Grade Column I/Os Lead
Column I/Os Lead
I/Os Lead
I/Os Lead
I/Os Lead
Units
Table 1-38. DDIO Outputs Half-Period Jitter Name
tOUTFULLJITTER Note Table 1-38:
Pending silicon characterization.
Description
Half-period jitter (PLL driving DDIO outputs)
Unit
Specifications
Table 1-39 lists worst case duty cycle distortion Cyclone devices. Detailed information duty cycle distortion will published after characterization.
Table 1-39. Duty Cycle Distortion Cyclone Pins Notes Speed Grade Symbol
Output Duty Cycle Notes Table 1-39:
Preliminary specification applies clock outputs from PLLs, global clock tree driving dedicated general purpose pins. Detailed specification pending silicon characterization.
Speed Grade
Speed Grade Unit
Timing
Timing Model
DirectDrivetechnology MultiTrackinterconnect ensure predictable performance, accurate simulation, accurate timing analysis across Cyclone device densities speed grades. This section describes specifies performance I/Os internal timing. specifications representative worst-case supply voltage junction temperature conditions. timing numbers listed tables this section extracted from Quartus software version Build
Altera Corporation July 2007
1-23 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Preliminary, Correlated Final Timing
Timing models have either preliminary, correlated, final status. Quartus software issues informational message during design compilation timing models preliminary. Table 1-40 shows status Cyclone device timing models. Preliminary status means timing model subject change. Initially, timing numbers created using simulation results, process data, other known parameters. These tests used make preliminary numbers close actual timing parameters possible. Correlated numbers based actual device operation testing. These numbers reflect actual performance device under worst-case voltage junction temperature conditions. Final timing numbers based complete correlation actual devices addressing minor deviations from correlated timing model. When timing models final, most Cyclone family devices have been completely characterized further changes timing model expected.
Table 1-40. Cyclone Device Timing Model Status Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Note Table 1-40:
Timing model EP3C5 will available Quartus software 7.1.
Preliminary
Correlated
Final
Timing Measurement Methodology
Altera characterizes timing delays worst-case process, minimum voltage, maximum temperature input register setup time (tSU) hold time (tH). Quartus software uses following equations calculate timing Cyclone devices input signals: data delay from input input register micro setup time input register clock delay from input input register
data delay from input input register
micro hold time input register clock delay from input input register Figure shows setup hold timing diagram input registers.
1-24 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Timing
Figure 1-2. Input Register Setup Hold Timing Diagram
Input Data Delay
micro micro Input Clock Delay
output timing, different standards require different baseline loading techniques reporting timing delays. Altera characterizes timing delays with required termination each standard with (except PCI-X which loading timing specified output FPGA device. Quartus software calculates timing each standard with default baseline loading specified standards. following measurements made during device characterization. Altera measures clock-to-output delays (tCO) worst-case process, minimum voltage, maximum temperature (PVT) default loading conditions shown Table 1-41. following equations calculate clock output timing Cyclone devices. from clock
delay from clock output register output register clock-to-output delay delay from output register output
Figure 1-3. Output Register Clock Output Timing Diagram
output Datain Output Register micro
Clock
Clock output Register delay Output Register output delay
Simulation using IBIS models required determine delays traces addition output delay timing reported Quartus software timing model device handbook. Simulate output driver choice into generalized test setup, using values from Table 1-41. Record time VMEAS. Simulate output driver choice into actual trace load, using appropriate IBIS model capacitance value represent load.
Altera Corporation July 2007
1-25 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Record time VMEAS. Compare results steps increase decrease delay should added subtracted from Standard Output Adder delays yield actual worst-case propagation delay (clock-to-output) trace.
Quartus software reports timing with conditions shown Table 1-41 using above equation. Figure shows model circuit that represented output timing Quartus software.
Figure 1-4. Output Delay Timing Reporting Setup Modeled Quartus Notes (1),
VCCIO Output Buffer
Output
Outputp
VMEAS
Outputn
Notes Figure 1-4:
Output timing reported output FPGA device. Additional delays loading board trace delay need accounted with IBIS model simulations. VCCINT 1.10 unless otherwise specified.
Figure Figure show interface with single multiple external output resistors.
Figure 1-5. Interface with Single External Output Resistor
Differential Outputs Differential Inputs
Figure 1-6. Interface with Three External Output Resistor Network
Differential Outputs Differential Inputs
1-26 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Timing
Table 1-41. Output Timing Measurement Methodology Output Pins Notes (1), (2), (4), Loading Termination Standard
3.3-V LVTTL 3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.0-V 3.0-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL CLASS 1.2-V HSTL CLASS LVDS LVDS_E_3R mini-LVDS mini-LVDS_E_3R PPDS PPDS_E_3R RSDS RSDS_E_1R RSDS_E_3R Notes Table 1-41:
Preliminary Measurement Point
1.1875 1.1875 0.855 0.855 0.855 0.855 0.7125 0.7125 0.575 0.575
VCCIO
3.135 3.135 2.85 2.85 2.375 1.71 1.425 1.15 2.85 2.85 2.375 2.375 1.71 1.71 1.71 1.71 1.425 1.425 1.15 1.15 2.375 2.375 2.375 2.375 2.375 2.375 2.375 2.375 2.375
(pF)
VMEAS
1.5675 1.5675 1.425 1.425 1.1875 0.855 0.7125 0.575 1.425 1.425 1.1875 1.1875 0.855 0.855 0.855 0.855 0.7125 0.7125 0.575 0.575 1.1875 1.1875 1.1875 1.1875 1.1875 1.1875 1.1875 1.1875 1.1875
Input measurement point internal node VCCINT. Output measuring point VMEAS buffer output VCCIO. Input stimulus edge rate (internal signal) from driver preceding buffer. Less than 50-mV ripple VCCIO. VCCINT 1.10 with less than 30-mV ripple. interface external termination termination voltage either supplied independent power supply created through Thevenin equivalent circuit. Pending silicon characterization.
Altera Corporation July 2007
1-27 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Default Capacitive Loading
Refer Table 1-42 default capacitive loading different standards.
Table 1-42. Default Loading Different Standards Cyclone Standard
3.3-V LVTTL 3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.0-V 3.0-V PCI-X SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class 1.8-V HSTL Class 1.8-V HSTL Class 1.5-V HSTL Class 1.5-V HSTL Class 1.2-V HSTL CLASS 1.2-V HSTL CLASS Differential SSTL-2 Class Differential SSTL-2 Class Differential SSTL-18 Class Differential SSTL-18 Class 1.2-V Differential HSTL Class 1.2-V Differential HSTL Class 1.5-V Differential HSTL Class 1.5-V Differential HSTL Class 1.8-V Differential HSTL Class 1.8-V Differential HSTL Class LVDS LVDS_E_3R mini-LVDS mini-LVDS_E_3R PPDS PPDS_E_3R RSDS RSDS_E_1R RSDS_E_3R
Preliminary Unit
Capacitive Load
1-28 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Timing
Maximum Input Output Clock Toggle Rate
maximum clock toggle rate defined maximum frequency achievable clock type signal pin. regular dedicated clock pin. maximum clock toggle rate different from maximum data rate. maximum clock toggle rate regular MHz, maximum data rate dual data rate (DDR) could potentially high Mbps same pin. Table 1-43 specifies maximum input clock toggle rates. Table 1-44 specifies maximum output clock toggle rates load. Table 1-45 specifies derating factors output clock toggle rate load. calculate output toggle rate load, this formula: toggle rate load 1000 (1000/ toggle rate load derating factor load value /1000) example, output toggle rate load SSTL-18 Class standard device clock output pin. derating factor ps/pF. load toggle rate calculated 1000 (1000/260 /1000) (MHz) Table 1-43 through Table 1-45 show toggle rates Cyclone devices.
Table 1-43. Maximum Input Toggle Rate Cyclone Devices (Part Maximum Input Toggle Rate CIII Devices (MHz) Column Pins Standard Speed Grade
Preliminary
Pins Speed Grade
Dedicated Clock Inputs Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
3.3-V LVTTL 3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS SSTL_2_CLASS_I SSTL_2_CLASS_II SSTL_18_CLASS_I SSTL_18_CLASS_II V_HSTL_CLASS_I V_HSTL_CLASS_II V_HSTL_CLASS_I V_HSTL_CLASS_II V_HSTL_CLASS_I V_HSTL_CLASS_II 3.0-V
Altera Corporation July 2007
1-29 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-43. Maximum Input Toggle Rate Cyclone Devices (Part Maximum Input Toggle Rate CIII Devices (MHz) Column Pins Standard Speed Grade
Preliminary
Pins Speed Grade
Dedicated Clock Inputs Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
3.0-V PCI-X DIFFERENTIAL_SSTL_2_CLASS_I DIFFERENTIAL_SSTL_2_CLASS_II DIFFERENTIAL_SSTL_18_CLASS_I DIFFERENTIAL_SSTL_18_CLASS_II V_DIFFERENTIAL_HSTL_CLASS_I V_DIFFERENTIAL_HSTL_CLASS_II V_DIFFERENTIAL_HSTL_CLASS_I V_DIFFERENTIAL_HSTL_CLASS_II V_DIFFERENTIAL_HSTL_CLASS_I V_DIFFERENTIAL_HSTL_CLASS_II LVPECL LVDS Notes Table 1-43:
V_HSTL_CLASS_II only supported column pins. Input differential standard only supported GCLK pin. Input LVPECL only supported GCLK pin.
Table 1-44. Maximum Output Toggle Rate Cyclone Devices (Part Maximum Output Toggle Rate CIII Devices (MHz) Column Pins Standard Speed Grade
3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS
Preliminary
Pins Speed Grade
Dedicated Clock Inputs Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
3.3-V LVTTL
1-30 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Timing
Table 1-44. Maximum Output Toggle Rate Cyclone Devices (Part Maximum Output Toggle Rate CIII Devices (MHz) Column Pins Standard Speed Grade
1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS SSTL_2_CLASS_I SSTL_2_CLASS_II SSTL_18_CLASS_I SSTL_18_CLASS_II V_HSTL_CLASS_I V_HSTL_CLASS_II V_HSTL_CLASS_I V_HSTL_CLASS_II
Preliminary
Pins Speed Grade
Dedicated Clock Inputs Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
2.5-V LVTTL/LVCMOS
Altera Corporation July 2007
1-31 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-44. Maximum Output Toggle Rate Cyclone Devices (Part Maximum Output Toggle Rate CIII Devices (MHz) Column Pins Standard Speed Grade
V_HSTL_CLASS_II 3.0-V 3.0-V PCI-X DIFFERENTIAL_SSTL_2_CLASS_I DIFFERENTIAL_SSTL_2_CLASS_II DIFFERENTIAL_SSTL_18_CLASS_I DIFFERENTIAL_SSTL_18_CLASS_II V_DIFFERENTIAL_HSTL_CLASS_I V_DIFFERENTIAL_HSTL_CLASS_II V_DIFFERENTIAL_HSTL_CLASS_I V_DIFFERENTIAL_HSTL_CLASS_II V_DIFFERENTIAL_HSTL_CLASS_I V_DIFFERENTIAL_HSTL_CLASS_II LVDS LVDS_E_3R mini-LVDS mini-LVDS_E_3R PPDS PPDS_E_3R RSDS RSDS_E_1R RSDS_E_3R 3.0-V LVTTL/LVCMOS OCT_25_ OHMS OCT_50_ OHMS
Preliminary
Pins Speed Grade
Dedicated Clock Inputs Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
V_HSTL_CLASS_I
1-32 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Timing
Table 1-44. Maximum Output Toggle Rate Cyclone Devices (Part Maximum Output Toggle Rate CIII Devices (MHz) Column Pins Standard Speed Grade
OCT_25_ OHMS OCT_50_ OHMS 1.8-V LVTTL/LVCMOS OCT_25_ OHMS OCT_50_ OHMS 1.2-V LVTTL/LVCMOS OCT_25_ OHMS OCT_50_ OHMS Notes Table 1-44:
current version Quartus software does have information standard. V_HSTL_CLASS_I respectively) only supported column pins. Output differential standard only supported PLLCLKOUT pin. Dedicated differential standards supported pins. Differential standards with external resistor network supported column pins. Output dedicated LVDS only supported pins. Input dedicated LVDS supported pins.
Preliminary
Pins Speed Grade
Dedicated Clock Inputs Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
2.5-V LVTTL/LVCMOS
Table 1-45. Maximum Output Clock Toggle Rate Derating Factors Cyclone Devices (Part
Preliminary
Maximum Output Clock Toggle Rate Derating Factors (ps/pf) Standard Current Strength Setting Column Pins Speed Grade
Pins Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
3.3-V LVTTL
3.3V LVCMOS 3.0-V LVTTL
3.0-V LVCMOS
Altera Corporation July 2007
1-33 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-45. Maximum Output Clock Toggle Rate Derating Factors Cyclone Devices (Part
Preliminary
Maximum Output Clock Toggle Rate Derating Factors (ps/pf) Standard Current Strength Setting Column Pins Speed Grade
Pins Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL_2_CLASS_I
SSTL_2_CLASS_II SSTL_18_CLASS_I
SSTL_18_ CLASS_II
V_HSTL_ CLASS_I
V_HSTL_ CLASS_II
1-34 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Timing
Table 1-45. Maximum Output Clock Toggle Rate Derating Factors Cyclone Devices (Part
Preliminary
Maximum Output Clock Toggle Rate Derating Factors (ps/pf) Standard Current Strength Setting Column Pins Speed Grade
Pins Speed Grade
Speed Grade
Speed Grade
Speed Grade
Speed Grade
V_HSTL_ CLASS_I
V_HSTL_ CLASS_II V_HSTL_ CLASS_I
V_HSTL_ CLASS_II 3.0-V 3.0-V PCI-X LVDS LVDS_E_3R mini-LVDS mini-LVDS_E_3R PPDS PPDS_E_3R RSDS RSDS_E_1R RSDS_E_3R 3.0-V
OCT_25_OHMS OCT_50_OHMS
2.5-V LVTTL/LVCMOS
OCT_25_OHMS OCT_50_OHMS
1.8-V LVTTL/LVCMOS
OCT_25_OHMS OCT_50_OHMS
1.2-V LVCMOS
OCT_25_OHMS OCT_50_OHMS
Notes Table 1-45:
Current version Quartus software does have information standard. V_HSTL_CLASS_I/II respectively) only supported column pins. Output differential standard only supported PLLCLKOUT pin. Dedicated differential standards supported pins. Differential standards with external resistor network supported column pins. Output dedicated LVDS only supported pins. Input dedicated LVDS supported pins. Indicate lowest value derating factor.
Altera Corporation July 2007
1-35 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Programmable Delay
Table 1-46 Table 1-47 show programmable delay Cyclone devices.
Table 1-46. Cyclone Programmable Delay Column Pins Notes (1), Fast Corner Speed Grade Speed Grade Speed Grade Parameter
Input Delay from Internal Cells Input Delay from Input Register Delay from Output Register Output Notes Table 1-46:
incremental values settings generally linear. exact values each setting, latest version Quartus software. minimum maximum offset timing numbers reference setting available Quartus software. fast model timing parameter commercial devices.
Paths Affected
dataout core input register output register
Number Settings
Offset
Offset
1.369 1.528 0.582
Offset
Offset
2.267 2.446
Offset
Offset
2.413 2.571 1.098
Offset
Offset
2.526 2.696 1.199
Unit
Table 1-47. Cyclone Programmable Delay Pins Notes (1), Number Settings
Fast Corner Offset
Speed Grade Offset
Speed Grade Offset
Speed Grade Offset
Parameter
Input Delay from Internal Cells Input Delay from Input Register Delay from Output Register Output Notes Table 1-47:
Paths Affected
dataout core input register output register
Offset
1.369 1.538 0.62
Offset
2.244 2.459 1.065
Offset
2.39 2.586 1.171
Offset
2.495 2.716 1.277
Unit
incremental values settings generally linear. exact values each setting, latest version Quartus software. minimum maximum offset timing numbers reference setting available Quartus software. fast model timing parameter commercial devices.
Typical Design Performance
User Timing Parameters
Table 1-48 Table 1-95 show user timing Cyclone devices. buffer tSU, reported cases when clock driven global clock PLL. programmable current strength 1.2-V HSTL Class standard supported I/Os. 1.2-V HSTL Class standard only supported column I/Os. PCI-X support programmable current strength.
more information about programmable current strength, refer Cyclone Device Features chapter Cyclone Handbook. Dedicated LVDS, mini-LVDS, PPDS, RSDS standards supported I/Os. External resistor networks required differential standards used output pins column banks. LVDS standard supported both input output pins. PPDS, RSDS, mini-LVDS standards only supported output pins.
1-36 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
more information about differential interface, refer High-Speed Differential Interfaces Cyclone Devices Cyclone Handbook.
EP3C5 Timing Parameters
Table 1-48 through Table 1-53 show maximum timing parameters EP3C5 devices.
Table 1-48. EP3C5 Column Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689
1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860
1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014
Units
GCLK
GCLK
GCLK
3.3-V LVCMOS
GCLK
GCLK
3.0-V LVTTL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
3.0-V LVCMOS
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-37 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-48. EP3C5 Column Input Timing Parameters Single-Ended Standards (Part Standard
3.0-V LVCMOS
Current Strength
Clock
GCLK
Parameter
1.123 -0.843 2.969 -2.689 1.123 -0.843 2.969 -2.689 1.066 -0.786 2.912 -2.632 1.066 -0.786 2.912 -2.632 1.066 -0.786 2.912 -2.632 1.066 -0.786 2.912 -2.632 1.001 -0.723 2.847 -2.569 1.001 -0.723 2.847 -2.569 1.001 -0.723 2.847 -2.569 1.001 -0.723 2.847 -2.569
1.156 -0.838 3.178 -2.860 1.156 -0.838 3.178 -2.860 1.111 -0.794 3.133 -2.816 1.111 -0.794 3.133 -2.816 1.111 -0.794 3.133 -2.816 1.111 -0.794 3.133 -2.816 1.072 -0.756 3.094 -2.778 1.072 -0.756 3.094 -2.778 1.072 -0.756 3.094 -2.778 1.072 -0.756 3.094 -2.778
1.167 -0.813 3.368 -3.014 1.167 -0.813 3.368 -3.014 1.135 -0.782 3.336 -2.983 1.135 -0.782 3.336 -2.983 1.135 -0.782 3.336 -2.983 1.135 -0.782 3.336 -2.983 1.122 -0.768 3.323 -2.969 1.122 -0.768 3.323 -2.969 1.122 -0.768 3.323 -2.969 1.122 -0.768 3.323 -2.969
Units
GCLK
GCLK
GCLK
2.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.8V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-38 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-48. EP3C5 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK
Parameter
1.001 -0.723 2.847 -2.569 1.001 -0.723 2.847 -2.569 1.001 -0.723 2.847 -2.569 1.070 -0.790 2.916 -2.636 1.070 -0.790 2.916 -2.636 1.070 -0.790 2.916 -2.636 1.070 -0.790 2.916 -2.636 1.070 -0.790 2.916 -2.636 1.070 -0.790 2.916 -2.636 1.070 -0.790 2.916 -2.636
1.072 -0.756 3.094 -2.778 1.072 -0.756 3.094 -2.778 1.072 -0.756 3.094 -2.778 1.164 -0.846 3.186 -2.868 1.164 -0.846 3.186 -2.868 1.164 -0.846 3.186 -2.868 1.164 -0.846 3.186 -2.868 1.164 -0.846 3.186 -2.868 1.164 -0.846 3.186 -2.868 1.164 -0.846 3.186 -2.868
1.122 -0.768 3.323 -2.969 1.122 -0.768 3.323 -2.969 1.122 -0.768 3.323 -2.969 1.239 -0.883 3.440 -3.084 1.239 -0.883 3.440 -3.084 1.239 -0.883 3.440 -3.084 1.239 -0.883 3.440 -3.084 1.239 -0.883 3.440 -3.084 1.239 -0.883 3.440 -3.084 1.239 -0.883 3.440 -3.084
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-39 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-48. EP3C5 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.2V
Current Strength
Clock
GCLK
Parameter
1.222 -0.940 3.068 -2.786 1.222 -0.940 3.068 -2.786 1.222 -0.940 3.068 -2.786 1.222 -0.940 3.068 -2.786 1.222 -0.940 3.068 -2.786 1.222 -0.940 3.068 -2.786 1.057 -0.777 2.901 -2.621 1.057 -0.777 2.901 -2.621 1.057 -0.777 2.901 -2.621
1.344 -1.022 3.366 -3.044 1.344 -1.022 3.366 -3.044 1.344 -1.022 3.366 -3.044 1.344 -1.022 3.366 -3.044 1.344 -1.022 3.366 -3.044 1.344 -1.022 3.366 -3.044 1.133 -0.816 3.151 -2.834 1.133 -0.816 3.151 -2.834 1.133 -0.816 3.151 -2.834
1.445 -1.085 3.646 -3.286 1.445 -1.085 3.646 -3.286 1.445 -1.085 3.646 -3.286 1.445 -1.085 3.646 -3.286 1.445 -1.085 3.646 -3.286 1.445 -1.085 3.646 -3.286 1.188 -0.833 3.385 -3.030 1.188 -0.833 3.385 -3.030 1.188 -0.833 3.385 -3.030
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
1-40 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-48. EP3C5 Column Input Timing Parameters Single-Ended Standards (Part Standard
SSTL-18 Class
Current Strength
Clock
GCLK
Parameter
1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682 1.118 -0.838 2.962 -2.682
1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921 1.222 -0.903 3.240 -2.921
1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143 1.303 -0.946 3.500 -3.143
Units
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
Altera Corporation July 2007
1-41 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-48. EP3C5 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.5-V HSTL Class
Current Strength
Clock
GCLK
Parameter
1.074 -0.794 2.918 -2.638 1.074 -0.794 2.918 -2.638 1.074 -0.794 2.918 -2.638 1.074 -0.794 2.918 -2.638 1.206 -0.924 3.050 -2.768 1.206 -0.924 3.050 -2.768 1.206 -0.924 3.050 -2.768 1.206 -0.924 3.050 -2.768 1.119 -0.839 2.965 -2.685 1.119 -0.839 2.965 -2.685
1.182 -0.864 3.200 -2.882 1.182 -0.864 3.200 -2.882 1.182 -0.864 3.200 -2.882 1.182 -0.864 3.200 -2.882 1.341 -1.019 3.359 -3.037 1.341 -1.019 3.359 -3.037 1.341 -1.019 3.359 -3.037 1.341 -1.019 3.359 -3.037 1.152 -0.834 3.174 -2.856 1.152 -0.834 3.174 -2.856
1.269 -0.913 3.466 -3.110 1.269 -0.913 3.466 -3.110 1.269 -0.913 3.466 -3.110 1.269 -0.913 3.466 -3.110 1.453 -1.093 3.650 -3.290 1.453 -1.093 3.650 -3.290 1.453 -1.093 3.650 -3.290 1.453 -1.093 3.650 -3.290 1.162 -0.808 3.363 -3.009 1.162 -0.808 3.363 -3.009
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
1.2-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.2-V HSTL Class
GCLK
GCLK
3.0-V
GCLK
GCLK
3.0-V PCI-X
GCLK
GCLK
1-42 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717
1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948
1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109
Units
GCLK
GCLK
GCLK
3.3-V LVCMOS
GCLK
GCLK
3.0-V LVTTL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
3.0-V LVCMOS
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-43 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
3.0-V LVCMOS
Current Strength
Clock
GCLK
Parameter
1.148 -0.868 2.997 -2.717 1.148 -0.868 2.997 -2.717 1.091 -0.811 2.940 -2.660 1.091 -0.811 2.940 -2.660 1.091 -0.811 2.940 -2.660 1.091 -0.811 2.940 -2.660
1.186 -0.868 3.266 -2.948 1.186 -0.868 3.266 -2.948 1.142 -0.825 3.222 -2.905 1.142 -0.825 3.222 -2.905 1.142 -0.825 3.222 -2.905 1.142 -0.825 3.222 -2.905
1.205 -0.850 3.464 -3.109 1.205 -0.850 3.464 -3.109 1.176 -0.822 3.435 -3.081 1.176 -0.822 3.435 -3.081 1.176 -0.822 3.435 -3.081 1.176 -0.822 3.435 -3.081
Units
GCLK
GCLK
GCLK
2.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-44 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK
Parameter
1.012 -0.734 2.876 -2.598 1.012 -0.734 2.876 -2.598 1.012 -0.734 2.876 -2.598 1.012 -0.734 2.876 -2.598 1.012 -0.734 2.876 -2.598 1.012 -0.734 2.876 -2.598 1.012 -0.734 2.876 -2.598 1.081 -0.801 2.945 -2.665 1.081 -0.801 2.945 -2.665 1.081 -0.801 2.945 -2.665
1.088 -0.772 3.183 -2.867 1.088 -0.772 3.183 -2.867 1.088 -0.772 3.183 -2.867 1.088 -0.772 3.183 -2.867 1.088 -0.772 3.183 -2.867 1.088 -0.772 3.183 -2.867 1.088 -0.772 3.183 -2.867 1.181 -0.863 3.276 -2.958 1.181 -0.863 3.276 -2.958 1.181 -0.863 3.276 -2.958
1.147 -0.792 3.421 -3.066 1.147 -0.792 3.421 -3.066 1.147 -0.792 3.421 -3.066 1.147 -0.792 3.421 -3.066 1.147 -0.792 3.421 -3.066 1.147 -0.792 3.421 -3.066 1.147 -0.792 3.421 -3.066 1.265 -0.909 3.539 -3.183 1.265 -0.909 3.539 -3.183 1.265 -0.909 3.539 -3.183
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-45 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
1.5V
Current Strength
Clock
GCLK
Parameter
1.081 -0.801 2.945 -2.665 1.081 -0.801 2.945 -2.665 1.081 -0.801 2.945 -2.665 1.081 -0.801 2.945 -2.665 1.234 -0.952 3.098 -2.816 1.234 -0.952 3.098 -2.816 1.234 -0.952 3.098 -2.816 1.234 -0.952 3.098 -2.816 1.234 -0.952 3.098 -2.816
1.181 -0.863 3.276 -2.958 1.181 -0.863 3.276 -2.958 1.181 -0.863 3.276 -2.958 1.181 -0.863 3.276 -2.958 1.361 -1.039 3.456 -3.134 1.361 -1.039 3.456 -3.134 1.361 -1.039 3.456 -3.134 1.361 -1.039 3.456 -3.134 1.361 -1.039 3.456 -3.134
1.265 -0.909 3.539 -3.183 1.265 -0.909 3.539 -3.183 1.265 -0.909 3.539 -3.183 1.265 -0.909 3.539 -3.183 1.472 -1.111 3.746 -3.385 1.472 -1.111 3.746 -3.385 1.472 -1.111 3.746 -3.385 1.472 -1.111 3.746 -3.385 1.472 -1.111 3.746 -3.385
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.2V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-46 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
SSTL-2 Class
Current Strength
Clock
GCLK
Parameter
1.081 -0.801 2.930 -2.650 1.081 -0.801 2.930 -2.650 1.081 -0.801 2.930 -2.650 1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712
1.161 -0.843 3.184 -2.866 1.161 -0.843 3.184 -2.866 1.161 -0.843 3.184 -2.866 1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954
1.224 -0.868 3.480 -3.124 1.224 -0.868 3.480 -3.124 1.224 -0.868 3.480 -3.124 1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239
Units
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-47 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
1.8-V HSTL Class
Current Strength
Clock
GCLK
Parameter
1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712 1.128 -0.848 2.992 -2.712 1.083 -0.803 2.947 -2.667 1.083 -0.803 2.947 -2.667 1.083 -0.803 2.947 -2.667 1.083 -0.803 2.947 -2.667 1.214 -0.932 3.078 -2.796 1.214 -0.932 3.078 -2.796
1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954 1.235 -0.916 3.273 -2.954 1.194 -0.876 3.232 -2.914 1.194 -0.876 3.232 -2.914 1.194 -0.876 3.232 -2.914 1.194 -0.876 3.232 -2.914 1.352 -1.030 3.390 -3.068 1.352 -1.030 3.390 -3.068
1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239 1.326 -0.968 3.597 -3.239 1.289 -0.932 3.560 -3.203 1.289 -0.932 3.560 -3.203 1.289 -0.932 3.560 -3.203 1.289 -0.932 3.560 -3.203 1.474 -1.114 3.745 -3.385 1.474 -1.114 3.745 -3.385
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
1.2-V HSTL Class
GCLK
GCLK
GCLK
GCLK
1-48 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-49. EP3C5 Input Timing Parameters Single-Ended Standards (Part Standard
3.0-V
Current Strength
Clock
GCLK
Parameter
1.144 -0.864 2.993 -2.713 1.144 -0.864 2.993 -2.713
1.182 -0.864 3.262 -2.944 1.182 -0.864 3.262 -2.944
1.201 -0.846 3.460 -3.105 1.201 -0.846 3.460 -3.105
Units
GCLK
3.0-V PCI-X
GCLK
GCLK
Table 1-50. EP3C5 Column Output Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK GCLK
Parameter
5.365 3.516 5.365 3.516 5.324 3.475 5.075 3.226 4.804 2.955 4.707 2.858 4.660 2.811 4.802 2.953 4.661 2.812 4.624 2.775 4.608 2.759
5.861 3.838 5.861 3.838 5.642 3.619 5.564 3.541 5.280 3.257 5.179 3.156 5.127 3.104 5.277 3.254 5.129 3.106 5.089 3.066 5.074 3.051
6.384 4.183 6.384 4.183 5.986 3.785 6.082 3.881 5.783 3.582 5.679 3.478 5.621 3.420 5.780 3.579 5.625 3.424 5.582 3.381 5.567 3.366
Units
GCLK GCLK
3.3-V LVCMOS
GCLK GCLK
3.0-V LVTTL
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
3.0-V LVCMOS
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
Altera Corporation July 2007
1-49 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-50. EP3C5 Column Output Timing Parameters Single-Ended Standards (Part Standard
2.5V
Current Strength
Clock
GCLK GCLK
Parameter
5.133 3.284 4.890 3.041 4.792 2.943 4.753 2.904 6.244 4.395 5.717 3.868 5.492 3.643 5.389 3.540 5.337 3.488 5.280 3.431 5.226 3.377 6.632 4.783 6.157 4.308 5.987 4.138 5.899 4.050 5.840 3.991 5.807 3.958 5.693 3.844
5.650 3.627 5.397 3.374 5.291 3.268 5.251 3.228 6.903 4.880 6.358 4.335 6.100 4.077 5.983 3.960 5.935 3.912 5.868 3.845 5.809 3.786 7.465 5.442 6.904 4.881 6.721 4.698 6.608 4.585 6.548 4.525 6.507 4.484 6.365 4.342
6.196 3.995 5.932 3.731 5.819 3.618 5.778 3.577 7.594 5.393 7.030 4.829 6.738 4.537 6.609 4.408 6.563 4.362 6.488 4.287 6.423 4.222 8.333 6.132 7.685 5.484 7.488 5.287 7.350 5.149 7.289 5.088 7.239 5.038 7.069 4.868
Units
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.8V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1-50 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-50. EP3C5 Column Output Timing Parameters Single-Ended Standards (Part Standard
1.2V
Current Strength
Clock
GCLK GCLK
Parameter
7.805 5.956 7.360 5.511 7.211 5.362 7.142 5.293 7.006 5.157 6.978 5.129 4.752 2.900 4.730 2.878 4.670 2.818 5.186 3.334 5.161 3.309 5.149 3.297 5.120 3.268 5.107 3.255 5.148 3.296 5.137 3.285 5.128 3.276 5.063 3.211
8.993 6.970 8.467 6.444 8.286 6.263 8.206 6.183 8.024 6.001 7.998 5.975 5.244 3.217 5.220 3.193 5.158 3.131 5.757 3.730 5.726 3.699 5.712 3.685 5.683 3.656 5.670 3.643 5.709 3.682 5.702 3.675 5.688 3.661 5.622 3.595
10.222 8.021 9.615 7.414 9.401 7.200 9.311 7.110 9.080 6.879 9.058 6.857 5.764 3.559 5.741 3.536 5.675 3.470 6.359 4.154 6.322 4.117 6.305 4.100 6.277 4.072 6.263 4.058 6.301 4.096 6.297 4.092 6.277 4.072 6.211 4.006
Units
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
SSTL-2 Class
GCLK GCLK
GCLK GCLK
SSTL-2 Class
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
Altera Corporation July 2007
1-51 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-50. EP3C5 Column Output Timing Parameters Single-Ended Standards (Part Standard
1.5-V HSTL Class
Current Strength
Clock
GCLK GCLK
Parameter
5.662 3.810 5.665 3.813 5.653 3.801 5.591 3.739 6.875 5.023 6.813 4.961 6.815 4.963 6.770 4.918 4.955 3.106 4.955 3.106
6.330 4.303 6.330 4.303 6.322 4.295 6.254 4.227 7.868 5.841 7.779 5.752 7.785 5.758 7.732 5.705 5.421 3.398 5.421 3.398
7.032 4.827 7.027 4.822 7.023 4.818 6.948 4.743 8.899 6.694 8.783 6.578 8.792 6.587 8.732 6.527 5.916 3.715 5.916 3.715
Units
GCLK GCLK
GCLK GCLK
1.5-V HSTL Class
GCLK GCLK
1.2-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.2-V HSTL Class
GCLK GCLK
3.0-V
GCLK GCLK
3.0-V PCI-X
GCLK GCLK
Table 1-51. EP3C5 Output Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK GCLK
Parameter
5.305 3.471 5.305 3.471 5.305 3.471 5.019 3.185 4.762 2.928 4.673 2.839 4.627 2.793
5.794 3.786 5.794 3.786 5.620 3.612 5.501 3.493 5.234 3.226 5.139 3.131 5.088 3.080
6.309 4.122 6.309 4.122 5.959 3.772 6.010 3.823 5.733 3.546 5.631 3.444 5.576 3.389
Units
GCLK GCLK
3.3-V LVCMOS
GCLK GCLK
3.0-V LVTTL
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1-52 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-51. EP3C5 Output Timing Parameters Single-Ended Standards (Part Standard
3.0-V LVCMOS
Current Strength
Clock
GCLK GCLK
Parameter
4.760 2.926 4.627 2.793 4.592 2.758 4.577 2.743 5.117 3.283 4.882 3.048 4.783 2.949 4.742 2.908 6.226 4.377 5.713 3.864 5.492 3.643 5.391 3.542 5.340 3.491 5.285 3.436 5.242 3.393 6.620 4.771 6.164 4.315 5.997 4.148 5.921 4.072
5.232 3.224 5.089 3.081 5.053 3.045 5.037 3.029 5.615 3.607 5.371 3.363 5.266 3.258 5.224 3.216 6.866 4.843 6.338 4.315 6.084 4.061 5.970 3.947 5.921 3.898 5.858 3.835 5.811 3.788 7.433 5.410 6.889 4.866 6.711 4.688 6.618 4.595
5.731 3.544 5.579 3.392 5.540 3.353 5.523 3.336 6.140 3.953 5.886 3.699 5.776 3.589 5.733 3.546 7.535 5.333 6.991 4.789 6.704 4.502 6.578 4.376 6.532 4.330 6.459 4.257 6.410 4.208 8.280 6.078 7.647 5.445 7.456 5.254 7.346 5.144
Units
GCLK GCLK
GCLK GCLK
GCLK GCLK
2.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.8V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
Altera Corporation July 2007
1-53 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-51. EP3C5 Output Timing Parameters Single-Ended Standards (Part Standard
1.5V
Current Strength
Clock
GCLK GCLK
Parameter
5.861 4.012 5.827 3.978 5.730 3.881 7.808 5.959 7.373 5.524 7.245 5.396 7.173 5.324 7.042 5.193 4.721 2.864 4.702 2.845 4.647 2.790 5.170 3.298 5.157 3.285 5.144 3.272 5.114 3.242 5.106 3.234 5.134 3.262 5.129 3.257 5.122 3.250 5.060 3.188
6.555 4.532 6.512 4.489 6.404 4.381 8.973 6.950 8.459 6.436 8.305 6.282 8.223 6.200 8.060 6.037 5.208 3.178 5.189 3.159 5.132 3.102 5.738 3.693 5.720 3.675 5.705 3.660 5.676 3.631 5.670 3.625 5.692 3.647 5.688 3.643 5.681 3.636 5.615 3.570
7.280 5.078 7.229 5.027 7.110 4.908 10.176 7.974 9.584 7.382 9.405 7.203 9.310 7.108 9.115 6.913 5.724 3.515 5.703 3.494 5.643 3.434 6.334 4.110 6.313 4.089 6.295 4.071 6.267 4.043 6.262 4.038 6.279 4.055 6.276 4.052 6.269 4.045 6.198 3.974
Units
GCLK GCLK
GCLK GCLK
1.2V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
SSTL-2 Class
GCLK GCLK
GCLK GCLK
SSTL-2 Class
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
1-54 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-51. EP3C5 Output Timing Parameters Single-Ended Standards (Part Standard
1.5-V HSTL Class
Current Strength
Clock
GCLK GCLK
Parameter
5.649 3.777 5.661 3.789 5.649 3.777 5.594 3.722 6.886 5.014 6.825 4.953 4.919 3.085 4.919 3.085
6.313 4.268 6.325 4.280 6.316 4.271 6.259 4.214 7.885 5.840 7.800 5.755 5.380 3.372 5.380 3.372
7.008 4.784 7.019 4.795 7.014 4.790 6.953 4.729 8.921 6.697 8.812 6.588 5.866 3.679 5.866 3.679
Units
GCLK GCLK
GCLK GCLK
1.5-V HSTL Class
GCLK GCLK
1.2-V HSTL Class
GCLK GCLK
GCLK GCLK
3.0-V
GCLK GCLK
3.0-V PCI-X
GCLK GCLK
Table 1-52. EP3C5 Column Differential Timing Parameters Standard
LVDS
Current Strength
Clock
GCLK
Parameter
0.953 -0.675 2.798 -2.520 4.700 2.867 4.700 2.867 5.081 3.248 4.700 2.867 4.700 2.867
1.036 -0.720 3.057 -2.741 5.190 3.183 5.190 3.183 5.569 3.562 5.190 3.183 5.190 3.183
1.096 -0.743 3.295 -2.942 5.711 3.525 5.711 3.525 6.089 3.903 5.711 3.525 5.711 3.525
Units
GCLK
LVDS_E_3R
GCLK GCLK
mini-LVDS_E_3R
GCLK GCLK
PPDS_E_3R
GCLK GCLK
RSDS_E_1R
GCLK GCLK
RSDS_E_3R
GCLK GCLK
Altera Corporation July 2007
1-55 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-53. EP3C5 Differential Timing Parameters Standard
LVDS
Current Strength
Clock
GCLK
Parameter
1.035 -0.757 3.879 2.819 -2.541 2.021 3.879 2.021 3.879 2.021 3.879 2.021
1.120 -0.805 4.265 3.079 -2.764 2.233 4.265 2.233 4.265 2.233 4.265 2.233
1.190 -0.836 4.675 3.329 -2.975 2.462 4.675 2.462 4.675 2.462 4.675 2.462
Units
GCLK
mini-LVDS
GCLK GCLK
PPDS
GCLK GCLK
RSDS
GCLK GCLK
EP3C10 Timing Parameters
Table 1-54 through Table 1-59 show maximum timing parameters EP3C10 devices.
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745
1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914
1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037
Units
GCLK
GCLK
GCLK
3.3-V LVCMOS
GCLK
GCLK
1-56 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
3.0-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745 1.123 -0.843 3.025 -2.745
1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914 1.156 -0.838 3.232 -2.914
1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037 1.167 -0.813 3.391 -3.037
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
3.0-V LVCMOS
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-57 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
2.5V
Current Strength
Clock
GCLK
Parameter
1.066 -0.786 2.968 -2.688 1.066 -0.786 2.968 -2.688 1.066 -0.786 2.968 -2.688 1.066 -0.786 2.968 -2.688 1.001 -0.723 2.903 -2.625 1.001 -0.723 2.903 -2.625 1.001 -0.723 2.903 -2.625 1.001 -0.723 2.903 -2.625 1.001 -0.723 2.903 -2.625 1.001 -0.723 2.903 -2.625
1.111 -0.794 3.187 -2.870 1.111 -0.794 3.187 -2.870 1.111 -0.794 3.187 -2.870 1.111 -0.794 3.187 -2.870 1.072 -0.756 3.148 -2.832 1.072 -0.756 3.148 -2.832 1.072 -0.756 3.148 -2.832 1.072 -0.756 3.148 -2.832 1.072 -0.756 3.148 -2.832 1.072 -0.756 3.148 -2.832
1.135 -0.782 3.359 -3.006 1.135 -0.782 3.359 -3.006 1.135 -0.782 3.359 -3.006 1.135 -0.782 3.359 -3.006 1.122 -0.768 3.346 -2.992 1.122 -0.768 3.346 -2.992 1.122 -0.768 3.346 -2.992 1.122 -0.768 3.346 -2.992 1.122 -0.768 3.346 -2.992 1.122 -0.768 3.346 -2.992
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.8V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-58 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK
Parameter
1.001 -0.723 2.903 -2.625 1.070 -0.790 2.972 -2.692 1.070 -0.790 2.972 -2.692 1.070 -0.790 2.972 -2.692 1.070 -0.790 2.972 -2.692 1.070 -0.790 2.972 -2.692 1.070 -0.790 2.972 -2.692 1.070 -0.790 2.972 -2.692 1.222 -0.940 3.124 -2.842 1.222 -0.940 3.124 -2.842
1.072 -0.756 3.148 -2.832 1.164 -0.846 3.240 -2.922 1.164 -0.846 3.240 -2.922 1.164 -0.846 3.240 -2.922 1.164 -0.846 3.240 -2.922 1.164 -0.846 3.240 -2.922 1.164 -0.846 3.240 -2.922 1.164 -0.846 3.240 -2.922 1.344 -1.022 3.420 -3.098 1.344 -1.022 3.420 -3.098
1.122 -0.768 3.346 -2.992 1.239 -0.883 3.463 -3.107 1.239 -0.883 3.463 -3.107 1.239 -0.883 3.463 -3.107 1.239 -0.883 3.463 -3.107 1.239 -0.883 3.463 -3.107 1.239 -0.883 3.463 -3.107 1.239 -0.883 3.463 -3.107 1.445 -1.085 3.669 -3.309 1.445 -1.085 3.669 -3.309
Units
GCLK
1.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.2V
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-59 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.2V
Current Strength
Clock
GCLK
Parameter
1.222 -0.940 3.124 -2.842 1.222 -0.940 3.124 -2.842 1.222 -0.940 3.124 -2.842 1.222 -0.940 3.124 -2.842 1.055 -0.775 2.954 -2.674 1.055 -0.775 2.954 -2.674 1.055 -0.775 2.954 -2.674 1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735
1.344 -1.022 3.420 -3.098 1.344 -1.022 3.420 -3.098 1.344 -1.022 3.420 -3.098 1.344 -1.022 3.420 -3.098 1.129 -0.812 3.143 -2.826 1.129 -0.812 3.143 -2.826 1.129 -0.812 3.143 -2.826 1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913
1.445 -1.085 3.669 -3.309 1.445 -1.085 3.669 -3.309 1.445 -1.085 3.669 -3.309 1.445 -1.085 3.669 -3.309 1.184 -0.829 3.376 -3.021 1.184 -0.829 3.376 -3.021 1.184 -0.829 3.376 -3.021 1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-60 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
SSTL-18 Class
Current Strength
Clock
GCLK
Parameter
1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735 1.116 -0.836 3.015 -2.735 1.072 -0.792 2.971 -2.691 1.072 -0.792 2.971 -2.691 1.072 -0.792 2.971 -2.691 1.072 -0.792 2.971 -2.691
1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913 1.218 -0.899 3.232 -2.913 1.178 -0.860 3.192 -2.874 1.178 -0.860 3.192 -2.874 1.178 -0.860 3.192 -2.874 1.178 -0.860 3.192 -2.874
1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134 1.299 -0.942 3.491 -3.134 1.265 -0.909 3.457 -3.101 1.265 -0.909 3.457 -3.101 1.265 -0.909 3.457 -3.101 1.265 -0.909 3.457 -3.101
Units
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
Altera Corporation July 2007
1-61 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-54. EP3C10 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.2-V HSTL Class
Current Strength
Clock
GCLK
Parameter
1.204 -0.922 3.103 -2.821 1.204 -0.922 3.103 -2.821 1.204 -0.922 3.103 -2.821 1.204 -0.922 3.103 -2.821 1.119 -0.839 3.021 -2.741 1.119 -0.839 3.021 -2.741
1.337 -1.015 3.351 -3.029 1.337 -1.015 3.351 -3.029 1.337 -1.015 3.351 -3.029 1.337 -1.015 3.351 -3.029 1.152 -0.834 3.228 -2.910 1.152 -0.834 3.228 -2.910
1.449 -1.089 3.641 -3.281 1.449 -1.089 3.641 -3.281 1.449 -1.089 3.641 -3.281 1.449 -1.089 3.641 -3.281 1.162 -0.808 3.386 -3.032 1.162 -0.808 3.386 -3.032
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.2-V HSTL Class
GCLK
GCLK
3.0-V
GCLK
GCLK
3.0-V PCI-X
GCLK
GCLK
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719
1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895
1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056
Units
GCLK
GCLK
GCLK
1-62 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVCMOS
Current Strength
Clock
GCLK
Parameter
1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719 1.155 -0.875 2.999 -2.719
1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895 1.193 -0.875 3.213 -2.895
1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056 1.213 -0.858 3.411 -3.056
Units
GCLK
3.0-V LVTTL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
3.0-V LVCMOS
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-63 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
2.5V
Current Strength
Clock
GCLK
Parameter
1.098 -0.818 2.942 -2.662 1.098 -0.818 2.942 -2.662 1.098 -0.818 2.942 -2.662 1.098 -0.818 2.942 -2.662 1.034 -0.756 2.878 -2.600 1.034 -0.756 2.878 -2.600 1.034 -0.756 2.878 -2.600 1.034 -0.756 2.878 -2.600 1.034 -0.756 2.878 -2.600 1.034 -0.756 2.878 -2.600
1.149 -0.832 3.169 -2.852 1.149 -0.832 3.169 -2.852 1.149 -0.832 3.169 -2.852 1.149 -0.832 3.169 -2.852 1.110 -0.794 3.130 -2.814 1.110 -0.794 3.130 -2.814 1.110 -0.794 3.130 -2.814 1.110 -0.794 3.130 -2.814 1.110 -0.794 3.130 -2.814 1.110 -0.794 3.130 -2.814
1.184 -0.830 3.382 -3.028 1.184 -0.830 3.382 -3.028 1.184 -0.830 3.382 -3.028 1.184 -0.830 3.382 -3.028 1.170 -0.815 3.368 -3.013 1.170 -0.815 3.368 -3.013 1.170 -0.815 3.368 -3.013 1.170 -0.815 3.368 -3.013 1.170 -0.815 3.368 -3.013 1.170 -0.815 3.368 -3.013
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.8V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-64 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK
Parameter
1.034 -0.756 2.878 -2.600 1.103 -0.823 2.947 -2.667 1.103 -0.823 2.947 -2.667 1.103 -0.823 2.947 -2.667 1.103 -0.823 2.947 -2.667 1.103 -0.823 2.947 -2.667 1.103 -0.823 2.947 -2.667 1.103 -0.823 2.947 -2.667
1.110 -0.794 3.130 -2.814 1.203 -0.885 3.223 -2.905 1.203 -0.885 3.223 -2.905 1.203 -0.885 3.223 -2.905 1.203 -0.885 3.223 -2.905 1.203 -0.885 3.223 -2.905 1.203 -0.885 3.223 -2.905 1.203 -0.885 3.223 -2.905
1.170 -0.815 3.368 -3.013 1.288 -0.932 3.486 -3.130 1.288 -0.932 3.486 -3.130 1.288 -0.932 3.486 -3.130 1.288 -0.932 3.486 -3.130 1.288 -0.932 3.486 -3.130 1.288 -0.932 3.486 -3.130 1.288 -0.932 3.486 -3.130
Units
GCLK
1.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-65 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
1.2V
Current Strength
Clock
GCLK
Parameter
1.256 -0.974 3.100 -2.818 1.256 -0.974 3.100 -2.818 1.256 -0.974 3.100 -2.818 1.256 -0.974 3.100 -2.818 1.256 -0.974 3.100 -2.818 1.082 -0.802 2.930 -2.650 1.082 -0.802 2.930 -2.650 1.082 -0.802 2.930 -2.650
1.383 -1.061 3.403 -3.081 1.383 -1.061 3.403 -3.081 1.383 -1.061 3.403 -3.081 1.383 -1.061 3.403 -3.081 1.383 -1.061 3.403 -3.081 1.162 -0.844 3.184 -2.866 1.162 -0.844 3.184 -2.866 1.162 -0.844 3.184 -2.866
1.495 -1.134 3.693 -3.332 1.495 -1.134 3.693 -3.332 1.495 -1.134 3.693 -3.332 1.495 -1.134 3.693 -3.332 1.495 -1.134 3.693 -3.332 1.225 -0.869 3.428 -3.072 1.225 -0.869 3.428 -3.072 1.225 -0.869 3.428 -3.072
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
1-66 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
SSTL-18 Class
Current Strength
Clock
GCLK
Parameter
1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712 1.129 -0.849 2.992 -2.712
1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954 1.236 -0.917 3.273 -2.954
1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187 1.327 -0.969 3.545 -3.187
Units
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
Altera Corporation July 2007
1-67 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-55. EP3C10 Input Timing Parameters Single-Ended Standards (Part Standard
1.5-V HSTL Class
Current Strength
Clock
GCLK
Parameter
1.084 -0.804 2.947 -2.667 1.084 -0.804 2.947 -2.667 1.084 -0.804 2.947 -2.667 1.084 -0.804 2.947 -2.667 1.215 -0.933 3.078 -2.796 1.215 -0.933 3.078 -2.796 1.151 -0.871 2.995 -2.715 1.151 -0.871 2.995 -2.715
1.195 -0.877 3.232 -2.914 1.195 -0.877 3.232 -2.914 1.195 -0.877 3.232 -2.914 1.195 -0.877 3.232 -2.914 1.353 -1.031 3.390 -3.068 1.353 -1.031 3.390 -3.068 1.189 -0.871 3.209 -2.891 1.189 -0.871 3.209 -2.891
1.290 -0.933 3.508 -3.151 1.290 -0.933 3.508 -3.151 1.290 -0.933 3.508 -3.151 1.290 -0.933 3.508 -3.151 1.475 -1.115 3.693 -3.333 1.475 -1.115 3.693 -3.333 1.209 -0.854 3.407 -3.052 1.209 -0.854 3.407 -3.052
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
1.2-V HSTL Class
GCLK
GCLK
GCLK
GCLK
3.0-V
GCLK
GCLK
3.0-V PCI-X
GCLK
GCLK
1-68 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-56. EP3C10 Column Output Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK GCLK
Parameter
5.371 3.512 5.371 3.512 5.330 3.471 5.081 3.222 4.810 2.951 4.713 2.854 4.666 2.807 4.808 2.949 4.667 2.808 4.630 2.771 4.614 2.755 5.139 3.280 4.896 3.037 4.798 2.939 4.759 2.900
5.866 3.831 5.866 3.831 5.647 3.612 5.569 3.534 5.285 3.250 5.184 3.149 5.132 3.097 5.282 3.247 5.134 3.099 5.094 3.059 5.079 3.044 5.655 3.620 5.402 3.367 5.296 3.261 5.256 3.221
6.382 4.181 6.382 4.181 5.984 3.783 6.080 3.879 5.781 3.580 5.677 3.476 5.619 3.418 5.778 3.577 5.623 3.422 5.580 3.379 5.565 3.364 6.194 3.993 5.930 3.729 5.817 3.616 5.776 3.575
Units
GCLK GCLK
3.3-V LVCMOS
GCLK GCLK
3.0-V LVTTL
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
3.0-V LVCMOS
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
2.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
Altera Corporation July 2007
1-69 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-56. EP3C10 Column Output Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK GCLK
Parameter
6.250 4.391 5.723 3.864 5.498 3.639 5.395 3.536 5.343 3.484 5.286 3.427 5.232 3.373 6.638 4.779 6.163 4.304 5.993 4.134 5.905 4.046 5.846 3.987 5.813 3.954 5.699 3.840 7.811 5.952 7.366 5.507 7.217 5.358 7.148 5.289 7.012 5.153 6.984 5.125
6.908 4.873 6.363 4.328 6.105 4.070 5.988 3.953 5.940 3.905 5.873 3.838 5.814 3.779 7.470 5.435 6.909 4.874 6.726 4.691 6.613 4.578 6.553 4.518 6.512 4.477 6.370 4.335 8.998 6.963 8.472 6.437 8.291 6.256 8.211 6.176 8.029 5.994 8.003 5.968
7.592 5.391 7.028 4.827 6.736 4.535 6.607 4.406 6.561 4.360 6.486 4.285 6.421 4.220 8.331 6.130 7.683 5.482 7.486 5.285 7.348 5.147 7.287 5.086 7.237 5.036 7.067 4.866 10.220 8.019 9.613 7.412 9.399 7.198 9.309 7.108 9.078 6.877 9.056 6.855
Units
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.2V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1-70 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-56. EP3C10 Column Output Timing Parameters Single-Ended Standards (Part Standard
SSTL-2 Class
Current Strength
Clock
GCLK GCLK
Parameter
4.754 2.901 4.732 2.879 4.672 2.819 5.188 3.335 5.163 3.310 5.151 3.298 5.122 3.269 5.109 3.256 5.150 3.297 5.139 3.286 5.130 3.277 5.065 3.212 5.664 3.811 5.667 3.814 5.655 3.802 5.593 3.740 6.877 5.024 6.815 4.962 6.817 4.964 6.772 4.919
5.240 3.228 5.216 3.204 5.154 3.142 5.753 3.741 5.722 3.710 5.708 3.696 5.679 3.667 5.666 3.654 5.705 3.693 5.698 3.686 5.684 3.672 5.618 3.606 6.326 4.314 6.326 4.314 6.318 4.306 6.250 4.238 7.864 5.852 7.775 5.763 7.781 5.769 7.728 5.716
5.750 3.570 5.727 3.547 5.661 3.481 6.345 4.165 6.308 4.128 6.291 4.111 6.263 4.083 6.249 4.069 6.287 4.107 6.283 4.103 6.263 4.083 6.197 4.017 7.018 4.838 7.013 4.833 7.009 4.829 6.934 4.754 8.885 6.705 8.769 6.589 8.778 6.598 8.718 6.538
Units
GCLK GCLK
SSTL-2 Class
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
1.5-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.5-V HSTL Class
GCLK GCLK
1.2-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.2-V HSTL Class
GCLK GCLK
Altera Corporation July 2007
1-71 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-56. EP3C10 Column Output Timing Parameters Single-Ended Standards (Part Standard
3.0-V
Current Strength
Clock
GCLK GCLK
Parameter
4.961 3.102 4.961 3.102
5.426 3.391 5.426 3.391
5.914 3.713 5.914 3.713
Units
3.0-V PCI-X
GCLK GCLK
Table 1-57. EP3C10 Output Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK GCLK
Parameter
5.308 3.467 5.308 3.467 5.308 3.467 5.022 3.181 4.765 2.924 4.676 2.835 4.630 2.789 4.763 2.922 4.630 2.789 4.595 2.754 4.580 2.739 5.120 3.279 4.885 3.044 4.786 2.945 4.745 2.904
5.797 3.783 5.797 3.783 5.623 3.609 5.504 3.490 5.237 3.223 5.142 3.128 5.091 3.077 5.235 3.221 5.092 3.078 5.056 3.042 5.040 3.026 5.618 3.604 5.374 3.360 5.269 3.255 5.227 3.213
6.311 4.118 6.311 4.118 5.961 3.768 6.012 3.819 5.735 3.542 5.633 3.440 5.578 3.385 5.733 3.540 5.581 3.388 5.542 3.349 5.525 3.332 6.142 3.949 5.888 3.695 5.778 3.585 5.735 3.542
Units
GCLK GCLK
3.3-V LVCMOS
GCLK GCLK
3.0-V LVTTL
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
3.0-V LVCMOS
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
2.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1-72 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-57. EP3C10 Output Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK GCLK
Parameter
6.214 4.373 5.701 3.860 5.480 3.639 5.379 3.538 5.328 3.487 5.273 3.432 5.230 3.389 6.608 4.767 6.152 4.311 5.985 4.144 5.909 4.068 5.849 4.008 5.815 3.974 5.718 3.877 7.796 5.955 7.361 5.520 7.233 5.392 7.161 5.320 7.030 5.189
6.854 4.840 6.326 4.312 6.072 4.058 5.958 3.944 5.909 3.895 5.846 3.832 5.799 3.785 7.421 5.407 6.877 4.863 6.699 4.685 6.606 4.592 6.543 4.529 6.500 4.486 6.392 4.378 8.961 6.947 8.447 6.433 8.293 6.279 8.211 6.197 8.048 6.034
7.522 5.329 6.978 4.785 6.691 4.498 6.565 4.372 6.519 4.326 6.446 4.253 6.397 4.204 8.267 6.074 7.634 5.441 7.443 5.250 7.333 5.140 7.267 5.074 7.216 5.023 7.097 4.904 10.163 7.970 9.571 7.378 9.392 7.199 9.297 7.104 9.102 6.909
Units
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.5V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.2V
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
GCLK GCLK
Altera Corporation July 2007
1-73 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-57. EP3C10 Output Timing Parameters Single-Ended Standards (Part Standard
SSTL-2 Class
Current Strength
Clock
GCLK GCLK
Parameter
4.720 2.865 4.701 2.846 4.646 2.791 5.169 3.299 5.156 3.286 5.143 3.273 5.113 3.243 5.105 3.235 5.133 3.263 5.128 3.258 5.121 3.251 5.059 3.189 5.648 3.778 5.660 3.790 5.648 3.778 5.593 3.723 6.885 5.015 6.824 4.954 4.922 3.081 4.922 3.081
5.207 3.176 5.188 3.157 5.131 3.100 5.737 3.691 5.719 3.673 5.704 3.658 5.675 3.629 5.669 3.623 5.691 3.645 5.687 3.641 5.680 3.634 5.614 3.568 6.312 4.266 6.324 4.278 6.315 4.269 6.258 4.212 7.884 5.838 7.799 5.753 5.383 3.369 5.383 3.369
5.723 3.513 5.702 3.492 5.642 3.432 6.333 4.108 6.312 4.087 6.294 4.069 6.266 4.041 6.261 4.036 6.278 4.053 6.275 4.050 6.268 4.043 6.197 3.972 7.007 4.782 7.018 4.793 7.013 4.788 6.952 4.727 8.920 6.695 8.811 6.586 5.868 3.675 5.868 3.675
Units
GCLK GCLK
SSTL-2 Class
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
SSTL-18 Class
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.8-V HSTL Class
GCLK GCLK
1.5-V HSTL Class
GCLK GCLK
GCLK GCLK
GCLK GCLK
1.5-V HSTL Class
GCLK GCLK
1.2-V HSTL Class
GCLK GCLK
GCLK GCLK
3.0-V
GCLK GCLK
3.0-V PCI-X
GCLK GCLK
1-74 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-58. EP3C10 Column Differential Timing Parameters Standard
LVDS
Current Strength
Clock
GCLK
Parameter
0.953 -0.675 2.798 -2.520 4.700 2.867 4.700 2.867 5.081 3.248 4.700 2.867 4.700 2.867
1.036 -0.720 3.057 -2.741 5.190 3.183 5.190 3.183 5.569 3.562 5.190 3.183 5.190 3.183
1.096 -0.743 3.295 -2.942 5.711 3.525 5.711 3.525 6.089 3.903 5.711 3.525 5.711 3.525
Units
GCLK
LVDS_E_3R
GCLK GCLK
mini-LVDS_E_3R
GCLK GCLK
PPDS_E_3R
GCLK GCLK
RSDS_E_1R
GCLK GCLK
RSDS_E_3R
GCLK GCLK
Table 1-59. EP3C10 Differential Timing Parameters Standard
LVDS
Current Strength
Clock
GCLK
Parameter
1.035 -0.757 3.879 2.819 -2.541 2.021 3.879 2.021 3.879 2.021 3.879 2.021
1.120 -0.805 4.265 3.079 -2.764 2.233 4.265 2.233 4.265 2.233 4.265 2.233
1.190 -0.836 4.675 3.329 -2.975 2.462 4.675 2.462 4.675 2.462 4.675 2.462
Units
GCLK
mini-LVDS
GCLK GCLK
PPDS
GCLK GCLK
RSDS
GCLK GCLK
Altera Corporation July 2007
1-75 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
EP3C16 Timing Parameters
Table 1-60 through Table 1-71 show maximum timing parameters EP3C16 devices.
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473
1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619
1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752
Units
GCLK
GCLK
GCLK
3.3-V LVCMOS
GCLK
GCLK
3.0-V LVTTL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-76 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
3.0-V LVCMOS
Current Strength
Clock
GCLK
Parameter
1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.100 -0.820 2.753 -2.473 1.043 -0.763 2.696 -2.416 1.043 -0.763 2.696 -2.416 1.043 -0.763 2.696 -2.416 1.043 -0.763 2.696 -2.416
1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.126 -0.808 2.937 -2.619 1.081 -0.764 2.892 -2.575 1.081 -0.764 2.892 -2.575 1.081 -0.764 2.892 -2.575 1.081 -0.764 2.892 -2.575
1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.135 -0.781 3.106 -2.752 1.103 -0.750 3.074 -2.721 1.103 -0.750 3.074 -2.721 1.103 -0.750 3.074 -2.721 1.103 -0.750 3.074 -2.721
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
2.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-77 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.8V
Current Strength
Clock
GCLK
Parameter
0.978 -0.700 2.630 -2.352 0.978 -0.700 2.630 -2.352 0.978 -0.700 2.630 -2.352 0.978 -0.700 2.630 -2.352 0.978 -0.700 2.630 -2.352 0.978 -0.700 2.630 -2.352 0.978 -0.700 2.630 -2.352 1.047 -0.767 2.699 -2.419 1.047 -0.767 2.699 -2.419 1.047 -0.767 2.699 -2.419
1.042 -0.726 2.852 -2.536 1.042 -0.726 2.852 -2.536 1.042 -0.726 2.852 -2.536 1.042 -0.726 2.852 -2.536 1.042 -0.726 2.852 -2.536 1.042 -0.726 2.852 -2.536 1.042 -0.726 2.852 -2.536 1.134 -0.816 2.944 -2.626 1.134 -0.816 2.944 -2.626 1.134 -0.816 2.944 -2.626
1.090 -0.736 3.061 -2.707 1.090 -0.736 3.061 -2.707 1.090 -0.736 3.061 -2.707 1.090 -0.736 3.061 -2.707 1.090 -0.736 3.061 -2.707 1.090 -0.736 3.061 -2.707 1.090 -0.736 3.061 -2.707 1.207 -0.851 3.178 -2.822 1.207 -0.851 3.178 -2.822 1.207 -0.851 3.178 -2.822
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.5V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1-78 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.5V
Current Strength
Clock
GCLK
Parameter
1.047 -0.767 2.699 -2.419 1.047 -0.767 2.699 -2.419 1.047 -0.767 2.699 -2.419 1.047 -0.767 2.699 -2.419 1.199 -0.917 2.851 -2.569 1.199 -0.917 2.851 -2.569 1.199 -0.917 2.851 -2.569 1.199 -0.917 2.851 -2.569 1.199 -0.917 2.851 -2.569 1.199 -0.917 2.851 -2.569
1.134 -0.816 2.944 -2.626 1.134 -0.816 2.944 -2.626 1.134 -0.816 2.944 -2.626 1.134 -0.816 2.944 -2.626 1.314 -0.992 3.124 -2.802 1.314 -0.992 3.124 -2.802 1.314 -0.992 3.124 -2.802 1.314 -0.992 3.124 -2.802 1.314 -0.992 3.124 -2.802 1.314 -0.992 3.124 -2.802
1.207 -0.851 3.178 -2.822 1.207 -0.851 3.178 -2.822 1.207 -0.851 3.178 -2.822 1.207 -0.851 3.178 -2.822 1.413 -1.053 3.384 -3.024 1.413 -1.053 3.384 -3.024 1.413 -1.053 3.384 -3.024 1.413 -1.053 3.384 -3.024 1.413 -1.053 3.384 -3.024 1.413 -1.053 3.384 -3.024
Units
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.2V
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Altera Corporation July 2007
1-79 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
SSTL-2 Class
Current Strength
Clock
GCLK
Parameter
1.032 -0.752 2.685 -2.405 1.032 -0.752 2.685 -2.405 1.032 -0.752 2.685 -2.405 1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465
1.100 -0.783 2.909 -2.592 1.100 -0.783 2.909 -2.592 1.100 -0.783 2.909 -2.592 1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679
1.152 -0.797 3.123 -2.768 1.152 -0.797 3.123 -2.768 1.152 -0.797 3.123 -2.768 1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881
Units
GCLK
GCLK
GCLK
SSTL-2 Class
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
SSTL-18 Class
GCLK
GCLK
GCLK
GCLK
1-80 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical Design Performance
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.8-V HSTL Class
Current Strength
Clock
GCLK
Parameter
1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465 1.093 -0.813 2.745 -2.465 1.049 -0.769 2.701 -2.421 1.049 -0.769 2.701 -2.421 1.049 -0.769 2.701 -2.421 1.049 -0.769 2.701 -2.421
1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679 1.189 -0.870 2.998 -2.679 1.149 -0.831 2.958 -2.640 1.149 -0.831 2.958 -2.640 1.149 -0.831 2.958 -2.640 1.149 -0.831 2.958 -2.640
1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881 1.267 -0.910 3.238 -2.881 1.233 -0.877 3.204 -2.848 1.233 -0.877 3.204 -2.848 1.233 -0.877 3.204 -2.848 1.233 -0.877 3.204 -2.848
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.8-V HSTL Class
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
1.5-V HSTL Class
GCLK
GCLK
Altera Corporation July 2007
1-81 Cyclone Device Handbook, Volume
Cyclone Device Datasheet: Switching Characteristics
Table 1-60. EP3C16 Column Input Timing Parameters Single-Ended Standards (Part Standard
1.2-V HSTL Class
Current Strength
Clock
GCLK
Parameter
1.181 -0.899 2.833 -2.551 1.181 -0.899 2.833 -2.551 1.181 -0.899 2.833 -2.551 1.181 -0.899 2.833 -2.551 1.096 -0.816 2.749 -2.469 1.096 -0.816 2.749 -2.469
1.308 -0.986 3.117 -2.795 1.308 -0.986 3.117 -2.795 1.308 -0.986 3.117 -2.795 1.308 -0.986 3.117 -2.795 1.122 -0.804 2.933 -2.615 1.122 -0.804 2.933 -2.615
1.417 -1.057 3.388 -3.028 1.417 -1.057 3.388 -3.028 1.417 -1.057 3.388 -3.028 1.417 -1.057 3.388 -3.028 1.130 -0.776 3.101 -2.747 1.130 -0.776 3.101 -2.747
Units
GCLK
GCLK
GCLK
GCLK
GCLK
1.2-V HSTL Class
GCLK
GCLK
3.0-V
GCLK
GCLK
3.0-V PCI-X
GCLK
GCLK
Table 1-61. EP3C16 Input Timing Parameters Single-Ended Standards (Part Standard
3.3-V LVTTL
Current Strength
Clock
GCLK
Parameter
1.141 -0.861 2.796 -2.516 1.141 -0.861 2.796 -2.516
1.173 -0.855 2.986 -2.668 1.173 -0.855 2.986 -2.668
1.187 -0.832 3.164 -2.809 1.187 -0.832 3.164 -2.809
Units
GCLK
GCLK
GCLK
1-82 Cyclone Device Handbook, Volume
Altera Corporation July 2007
Typical De

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