CIII51005-1.1 Cyclone® devices offer embedded multiplier blocks s

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Embedded Multipliers Cyclone Devices
CIII51005-1.1
Cyclone® devices offer embedded multiplier blocks support following modes: individual multiplier block, individual multipliers block. addition embedded multipliers, Cyclone FPGAs include combination on-chip resources external interfaces that helps increase performance, reduce system cost, lower power consumption digital signal processing (DSP) systems. Cyclone FPGAs alone, device co-processors improve price-to-performance ratios systems. Particular focus been placed optimizing Cyclone FPGAs applications benefiting from abundance parallel processing resources including video image processing, intermediate frequency (IF) modems used wireless communications systems, multi-channel communications video systems. Cyclone FPGA system design supports following features:
multipliers 3,981 Kbit on-chip embedded memory blocks High-speed interfaces external memory such DDR2 SDRAM intellectual property (IP) cores that include: Common processing functions like finite impulse response (FIR), fast Fourier transform (FFT), numerically controlled oscillator (NCO) functions Video image processing suite Complete reference designs market applications Builder interface between Mathworks Simulink MATLAB design environment Altera® Quartus® software optimized development kits
This chapter focuses Cyclone embedded multiplier blocks. Quartus software makes easy take advantage embedded multipliers instantiating multipliers using dedicated megafunction wizard interfaces inferring multipliers directly VHDL Verilog code. This chapter contains following sections:
"Embedded Multiplier Block Overview" page "Architecture" page "Operational Modes" page "Software Support" page
more information about Quartus software support Cyclone embedded multipliers, refer "Software Support" page 5-7.
Embedded Multiplier Block Overview
Each Cyclone device four columns embedded multipliers that implement multiplication functions. Figure shows embedded multiplier columns with surrounding logic array blocks (LABs). configure each embedded multiplier multiplier multipliers. multiplication greater than Quartus software cascades multiple embedded multiplier blocks together. There restriction data width multiplier, greater data width, slower multiplication process.
Altera Corporation July 2007
Preliminary
Embedded Multipliers Cyclone Devices
Figure 5-1. Embedded Multipliers Arranged Columns with Adjacent LABs
Embedded Multiplier Column
Embedded Multiplier
number embedded multipliers column number columns available increases with device density. Table shows number embedded multipliers each Cyclone device multiplier modes that implement.
Table 5-1. Number Embedded Multipliers Cyclone Devices Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Note Table 5-1:
These columns show number multipliers each device. total number multipliers each device multipliers.
Embedded Multipliers
Multipliers
Multipliers
addition embedded multipliers, also implement soft multipliers using Cyclone memory blocks. blocks look-up tables (LUTs) that contain partial results from multiplication input data with coefficients that implements variable depth/width
Cyclone Device Handbook, Volume
Altera Corporation July 2007
Architecture
high-performance soft multipliers low-cost, high-volume applications. availability soft multipliers increases number multipliers available within device. Table shows total number multipliers available Cyclone devices using embedded multipliers soft multipliers.
Table 5-2. Number Multipliers Cyclone Devices Device
EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Notes Table 5-2:
Soft multipliers implemented multiplication mode. memory blocks configured with 18-bit data widths support 16-bit coefficients. coefficients requires 18-bits resolution account overflow. total number multipliers vary according multiplier mode use.
Embedded Multipliers
Soft Multipliers
Total Multipliers
Refer Memory Blocks chapter volume Cyclone Device Handbook more information about Cyclone memory blocks. Refer 306: Implementing Multipliers FPGA Devices more information about soft multipliers. Each embedded multiplier consists following elements:
Architecture
Multiplier stage Input output registers Input output interfaces
Figure shows multiplier block architecture.
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
Figure 5-2. Multiplier Block Architecture
signa signb aclr clock
Data
Data
CLRN
CLRN
Data
Input Register Output Register
CLRN
Embedded Multiplier Block
Input Registers
send each multiplier input signal into input register directly into multiplier 18-bit sections, depending operational mode multiplier. send each multiplier input signal through register independently each other (for example, send multiplier's data signal through register send data signal directly multiplier). following control signals available each input register within embedded multiplier:
clock clock enable asynchronous clear
input output registers within single embedded multiplier same clock, clock enable, asynchronous clear signals.
Multiplier Stage
multiplier stage embedded multiplier block supports multipliers well other multipliers between these configurations. Depending data width operational mode multiplier, single embedded multiplier perform multiplications parallel. Refer "Operational Modes" page multiplier details. Each multiplier operand unique signed unsigned number. signals, signa signb, control input multiplier determine value signed unsigned. signa signal high, data operand signed number. signa signal low, data operand unsigned number. Table shows sign multiplication result various operand sign representations. result multiplication signed operands signed value.
Table 5-3. Multiplier Sign Representation (Part Data signa Value
Unsigned Unsigned
Data Result Logic Level
signb Value
Unsigned Signed
Logic Level
High Unsigned Signed
Cyclone Device Handbook, Volume
Altera Corporation July 2007
Operational Modes
Table 5-3. Multiplier Sign Representation (Part Data signa Value
Signed Signed
Data Result Logic Level
High High
signb Value
Unsigned Signed
Logic Level
High Signed Signed
Each embedded multiplier block only signa signb signal control sign representation input data block. embedded multiplier block multipliers, data input both multipliers share same signa signal, data input both multipliers share same signb signal. change signa signb signals dynamically modify sign representation input operands time. send signa signb signals through dedicated input register. multiplier offers full precision, regardless sign representation. When signa signb signals unused, Quartus software sets multiplier perform unsigned multiplication default.
Output Registers
choose register embedded multiplier output using output registers 36-bit sections, depending operational mode multiplier. following control signals available each output register within embedded multiplier:
clock clock enable asynchronous clear
input output registers within single embedded multiplier same clock, clock enable, asynchronous clear signals.
Refer MultiTrack Interconnect chapter volume Cyclone Device Handbook more information about embedded multiplier routing interface. embedded multiplier block operational modes, depending application needs:
Operational Modes
18-bit multiplier 9-bit independent multipliers
Quartus software includes megafunctions used control operational modes multipliers. After have made appropriate parameter settings using megafunction's MegaWizard® Plug-In Manager, Quartus software automatically configures embedded multiplier. also Cyclone embedded multipliers implement multiplier adder multiplier accumulator functions where multiplier portion function implemented using embedded multipliers adder accumulator function implemented logic elements (LEs).
more information about Quartus support Cyclone embedded multipliers, refer "Software Support" page 5-7.
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
18-Bit Multipliers
configure each embedded multiplier support single multiplier input widths bits. Figure shows embedded multiplier configured support 18-bit multiplier.
Figure 5-3. 18-Bit Multiplier Mode
signa signb aclr clock
Data [17.0]
Data [35.0]
CLRN
CLRN
Data [17.0]
CLRN
Multiplier Embedded Multiplier
18-bit multiplier inputs results sent independently through registers. multiplier inputs accept signed integers, unsigned integers, combination both. Additionally, change signa signb signals dynamically send these signals through dedicated input registers.
9-Bit Multipliers
configure each embedded multiplier support independent multipliers input widths bits. Figure shows embedded multiplier configured support 9-bit multipliers.
Cyclone Device Handbook, Volume
Altera Corporation July 2007
Software Support
Figure 5-4. 9-Bit Multiplier Mode
signa signb aclr clock
Data [8.0]
Data [17.0]
CLRN
CLRN
Data [8.0]
CLRN
Multiplier
Data [8.0]
Data [17.0]
CLRN
CLRN
Data [8.0]
CLRN
Multiplier Embedded Multiplier
9-bit multiplier inputs results sent independently through registers. multiplier inputs accept signed integers, unsigned integers, combination both. multipliers same embedded multiplier block share same signa signb signal. Therefore, data inputs feeding same embedded multiplier must have same sign representation. Similarly, data inputs feeding same embedded multiplier must have same sign representation.
Software Support
Altera provides methods implementing multipliers your design using embedded multiplier resources: instantiation inference. Both methods following four Quartus megafunctions:
lpm_mult altmult_add altmult_accum altfp_mult
first method, lpm_mult, altmult_add, altfp_mult megafunctions implement multipliers. Additionally, altmult_add megafunction multiplier-adders where embedded multipliers used multiply function configured adders. altfp_mult megafunction floating point multiplier. implements embedded multiplier floating point numbers multiplication.
Altera Corporation July 2007
Cyclone Device Handbook, Volume
Embedded Multipliers Cyclone Devices
altmult_accum megafunction implements multiply accumulate functions where embedded multiplier implements multiplier accumulator function implemented LEs.
instructions megafunction MegaWizard Plug-In Manager, refer megafunction's associated User Guide Quartus Help. second method, infer megafunctions creating design synthesizing using Quartus Native Synthesis, third-party synthesis tool such Cadence Synplify, which recognizes infers appropriate multiplier megafunction. With both options, Quartus software maps multiplier functionality embedded multipliers during compilation.
information about Altera's complete Design intellectual property offerings, refer Altera site (www.altera.com). more information about instantiating inferring Quartus megafunctions, refer Synthesis section volume Quartus Handbook. Cyclone embedded multipliers optimized support multiplier-intensive applications such filters, functions, encoders. configure these embedded multipliers implement multipliers various widths 18-bits suit particular application, resulting efficient resource utilization improved performance data throughput. Quartus software Synplify software provide complete easy-to-use flow implementing multiplier functions using embedded multipliers. This chapter references following documents:
Conclusion
Referenced Documents
Memory Blocks chapter volume Cyclone Device Handbook 306: Implementing Multipliers FPGA Devices MultiTrack Interconnect chapter volume Cyclone Device Handbook Synthesis section volume Quartus Handbook
Document Revision History
Table shows revision history this document.
Table 5-4. Document Revision History Date Document Version
July 2007 v1.1
Changes Made
Summary Changes
Added EP3C120 information. Updated "Introduction" section. Updated Table Table 5-2. Added chapter "Referenced Documents" section.
March 2007 v1.0
Initial Release.
Cyclone Device Handbook, Volume
Altera Corporation July 2007

CIII51005-1.1 Cyclone® devices offer embedded multiplier blocks s

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