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Blocks Stratix Stratix Devices
S52006-2.2
Traditionally, designers make trade-off between flexibility off-the-shelf digital signal processors performance custombuilt devices. Altera® Stratix® Stratix devices eliminate need this trade-off providing exceptional performance combined with flexibility programmable logic devices (PLDs). Stratix Stratix devices have dedicated digital signal processing (DSP) blocks, which have high-speed parallel processing capabilities, that optimized applications. blocks ideal implementing applications that need high data throughput. most commonly used functions finite impulse response (FIR) filters, complex filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions, correlators. These functions building blocks more complex systems such wideband code division multiple access (W-CDMA) basestations, voice over Internet protocol (VoIP), highdefinition television (HDTV). Although these functions complex, they similar building blocks such multiply-adders multiply-accumulators. Stratix Stratix blocks combine five arithmetic operations- multiplication, addition, subtraction, accumulation, summation-to meet requirements complex functions provide improved performance. This chapter describes Stratix Stratix blocks, explains them implement high-performance functions. addresses following topics:
Architecture Operational Modes Software Support
Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume more information Stratix Stratix devices, respectively.
Altera Corporation July 2005
18-1
Block Overview
Block Overview
Each Stratix Stratix device columns blocks that efficiently implement multiplication, multiply accumulate (MAC), filtering functions. Figure 18-1 shows columns with surrounding rows. configure each block support:
Eight multipliers Four multipliers multiplier
Figure 18-1. Blocks Arranged Columns
Block Column
Rows
Block
multipliers then feed adder accumulator block, depending block operational mode. Additionally, block input registers shift registers implement applications such filters efficiently. number blocks column
18-2 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
increases with device density. Tables 18-1 18-2 describe number blocks each Stratix Stratix device, respectively, multipliers that implement.
Table 18-1. Number Blocks Stratix Devices Note Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Blocks
Multipliers
Multipliers Multipliers
Table 18-2. Number Blocks Stratix Devices Note Device
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G Note Tables 18-1 18-2:
Each device either number 18-, 36-bit multipliers shown.The total number multipliers each device multipliers.
Blocks
Multipliers
Multipliers Multipliers
Altera Corporation July 2005
18-3 Stratix Device Handbook, Volume
Block Overview
Figure 18-2 shows block operating multiplier. Figure 18-2. Block Mode
Optional Serial Shift Register Inputs from Previous Block
From Interface Block
Multiplier Block
Adder Output Block
Output Register
CLRN
CLRN
CLRN
Adder/ Subtractor/ Accumulator
CLRN
CLRN Summation Block
Adder
CLRN
CLRN
CLRN
CLRN
Adder/ Subtractor/ Accumulator
Pipeline Register
CLRN
CLRN
CLRN
18-4 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Architecture
block consists following elements:
multiplier block adder/subtractor/accumulator block summation block output interface Output registers Routing control signals
Multiplier Block
Each multiplier block input registers, multiplier stage, pipeline register. Figure 18-3. Figure 18-3. Multiplier Block Architecture
signa signb aclr[3.0] clock[3.0] ena[3.0] shiftinb shiftina
Data
CLRN Data Adder Blocks
CLRN
Data
CLRN
shiftoutb
shiftouta
Altera Corporation July 2005
18-5 Stratix Device Handbook, Volume
Architecture
Input Registers
Each operand feeds input register multiplier directly. block following signals (one each controls every input output register):
clock[3.0] ena[3.0] aclr[3.0]
input registers feed multiplier drive dedicated shift output lines, shiftouta shiftoutb. shift outputs from multiplier block directly feed adjacent multiplier block same block next block), shown Figure 18-4 page 18-7, form shift register chain. This chain terminate block, i.e., create length shift register chain registers. shift register useful applications such filters. When implementing multipliers, need external logic create shift register chain because input shift registers internal block. This implementation greatly reduces required count routing resources, produces repeatable timing.
18-6 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Figure 18-4. Shift Register Chain
Block Data A[n] B[n] CLRN CLRN
Data
CLRN
shiftoutb
shiftouta
CLRN
CLRN
CLRN
shiftoutb
shiftouta Block CLRN CLRN
CLRN
shiftoutb
shiftouta
Altera Corporation July 2005
18-7 Stratix Device Handbook, Volume
Architecture
Multiplier Stage
multiplier stage supports multiplication. (The multiplier stage also support smaller multipliers. "Operational Modes" page 18-18 details.) Based data width, single block perform many multiplications parallel. multiplier operands signed unsigned numbers. signals, signa signb, indicate representation operands. example, logic signa signal indicates that data signed number; logic indicates unsigned number. result multiplication signed operands signed number, shown Table 18-3.
Table 18-3. Multiplier Signed Representation Data
Unsigned Unsigned Signed Signed
Data
Unsigned Signed Unsigned Signed
Result
Unsigned Signed Signed Signed
signa signb signals affect entire block. Therefore, data inputs feeding same block must have same sign representation. Similarly, data inputs feeding same block must have same sign representation. multiplier offers full precision regardless sign representation. default, Altera Quartus® software sets multiplier perform unsigned multiplication when signa signb signals used.
Pipeline Registers
output from multiplier feed pipeline register bypassed. pipeline registers multiplier size; pipelining useful increasing block performance, particularly when using subsequent adder stages. block, pipelining improves performance multipliers. multipliers smaller, pipelining adds latency does improve performance.
18-8 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Adder/Output Block
adder/output block following elements (See Figure 18-5 page 18-10):
adder/subtractor/accumulator block summation block output select multiplexer Output registers
configure adder/output block
pure output interface accumulator simple one-level adder two-level adder with dynamic addition/subtraction control first-level adder final stage 36-bit multiplier
output select multiplexer sets output block. register adder/output block's output using output registers. cannot adder/output block independently multiplier.
Altera Corporation July 2005
18-9 Stratix Device Handbook, Volume
Architecture
Figure 18-5. Adder/Output Block
Accumulator Feedback Output Select Multiplexer
accum_sload0 Result
Output Registers overflow0
addnsub1
Adder/ Subtractor/ Accumulator
Result signa
Adder signb
Result
addnsub3
Adder/ Subtractor/ Accumulator overflow1
Result Accumulator Feedback accum_sload1
Adder/Subtractor/Accumulator Block
adder/subtractor/accumulator first level adder/output block. configure block accumulator adder/subtractor. Accumulator When adder/subtractor/accumulator configured accumulator, output adder/output block feeds back accumulator shown Figure 18-5.
18-10 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
accum_sload[1.0] signals clear accumulator asynchronously. This action same resetting output registers. clear accumulation begin without losing clock cycles. overflow signal goes high positive edge clock when accumulator overflows underflows. next clock cycle, however, overflow signal resets zero even though overflow underflow) occurred previous clock cycle. latch preserve overflow condition indefinitely (until latch cleared). Adder/Subtractor addnsub[1.0] signals select addition subtraction: high addition subtraction. control addnsub[1.0] signals using external logic; therefore, first-level block switch from adder subtractor dynamically, simply changing addnsub[1.0] signals. first stage configured subtractor, output adder/subtractor also uses signals, signa signb, like multiplier block. These signals indicate sign representation both operands together. register signals with latency clock cycles.
Summation Block
output from adder/subtractor feeds optional summation block, which adder block that sums outputs adder/subtractor. summation block important applications such filters.
Output Select Multiplexer
outputs from various elements adder/output block routed through output select multiplexer. Based block operational mode, outputs multiplier block, adder/subtractor/accumulator, summation block feed straight output, bypassing remaining blocks block. output select multiplier configuration configured automatically software.
Output Registers
output registers register block output. Like input registers, output registers controlled four clock[3.0], aclr[3.0], ena[3.0] signals. output registers block operational mode.
Altera Corporation July 2005
18-11 Stratix Device Handbook, Volume
Architecture
output registers form part accumulator multiply-accumulate mode.
Routing Structure Control Signals
This section describes interface between blocks interface blocks. also describes block generates control signals signals route from interface block.
Block Interface
blocks organized columns, which provides efficient horizontal communication between blocks column-based memory blocks. block communicates with other parts device through input output interface. Each block, including input output interface, logic array blocks (LABs) long. block interface blocks consist eight blocks that connect eight adjacent rows left right. Each eight blocks regions: right left, row. block receives data input signals control signals total input signals. This block drives data output signals; data signals used overflow signals (overflow). Figure 18-6 provides overview block interface adjacent LABs. Figure 18-6. Block Interface Adjacent LABs
Block Interface Rows Interfaces through Data Block Control Rows
Block Input Interface
Block Output Interface
Input Interface block input interface input signals from adjacent LABs; data signals control signals block. Output Interface block output interface drives outputs adjacent LABs, signals from rows.
18-12 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Because block outputs communicate horizontally, because each block more outputs than from block compared from LAB), block double number channel drivers compared LAB. block same number channels, channels staggered there were LABs within each block. blocks have same number column channels LABs because blocks communicate primarily through channels. Interface Block Each interface block connects block structure with signals. Because each block eight interface blocks, this block receives signals from eight interfaces. signals, data inputs control signals. Figure 18-7 page 18-14 shows block within block.
Altera Corporation July 2005
18-13 Stratix Device Handbook, Volume
Architecture
Figure 18-7. Interface Block
Interconnects DirectLink Interconnect from Adjacent Interconnects Nine DirectLink Outputs Adjacent LABs DirectLink Interconnect from Adjacent
Block Structure
Control [17.0] [17.0]
Interface Block Block Interface Block Interconnect Region Inputs Outputs
Control Signals Interface Block
block input registers, pipeline register, output register. Each register grouped banks that share same clock clear resources:
9-bit banks input register 18-bit banks pipeline register bits output register
18-14 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
interface block generates control signals routes them block. Each block control signals:
Four clock signals (clock[3.0]), which available each bank blocks Four clear signals (aclr[3.0]), which available each bank blocks Four clock enable signals (ena[3.0]), which whole block signa signb, which specific each block addnsub[1.0] signals accum_sload[1.0] signals
signa, signb, addnsub[1.0], accum_sload[1.0] signals have independent clocks clears registered individually. When each multiplier block splits half multipliers, each multiplier independent control signals. Figure 18-8 shows block interface shows generates data control signals. Figure 18-8. Block Interface
Local Interconnect Signals Unit Control Block Detail Block Interface Input Registers Block Signals Data Input Register
Clocks
Altera Corporation July 2005
18-15 Stratix Device Handbook, Volume
Architecture
block interface generates clock signals from clocks local interconnect. clear signals generated from local interconnects within each block interface from clocks. four clock enable signals generated from local interconnects from same rows that generate clock signals. clock enable paired with clock because enable logic implemented interface. Figure 18-9 shows signal distribution within interface block. Figure 18-9. Block Interface Signal Distribution
ena[3.0] data[17.0] aclr[3.0] clock[3.0] Input Registers
18-Bit Data Routed from Local Interconnects
Multiplier
Four Clock Enable Signals Routed from Local Interconnects Four Clear Signals Routed from Local Interconnects Clock Four Clock Signals Routed from Clock Local Interconnect
Multiplier
18-16 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Each block provides bits data multiplier (i.e., operands multiplier), which routed through local interconnects within each interface block. signal device source 18-bit multiplier data, connecting local interconnect through column. Each control signal routes through eight rows block. Table 18-4 shows control signals which each routes.
Table 18-4. Control Signals Block Signal Name
signa signb addnsub1 addnsub3
Description
block-wide signed unsigned control signals multipliers. multiplier outputs unsigned only both signa signb low. Controls addition subtraction one-level adders.
addnsub0 signal controls one-level adders; addnsub1
signal controls bottom one-level adders. high indicates addition; indicates subtraction. Resets feedback input accumulator. signal asynchronously clears accumulator allows accumulation begin without losing clock cycles. accum_sload0 controls one-level adders, accum_sload1 controls bottom one-level adders. normal accumulation operations high zeroing accumulator. block-wide clock signals.
accum_sload0 accum_sload1
clock0 clock1 clock2 clock3 aclr0 aclr1 aclr2 aclr3 ena[3.0]
block-wide clear signals.
Same rows block-wide clock enable signals. Clock Signals
Input/Output Data Interface Routing
local interconnects generate inputs interface blocks. outputs interface block inputs block (see Figure 18-7 page 18-14).
Altera Corporation July 2005
18-17 Stratix Device Handbook, Volume
Operational Modes
interface block DirectLinkconnections that connect block input output signals left right adjacent LABs each row. (The DirectLink connections provide interconnects between LABs adjacent blocks.) DirectLink connection reduces column interconnects, providing higher performance flexibility. Each interface block receives DirectLink connections from right adjacent LABs from left adjacent LABs. Additionally, interface block receives signals from block, making total local interconnects each interface block. column resources within block access this interconnect region (see Figure 18-7 page 18-14). block nine outputs that drive right adjacent nine that drive left adjacent through DirectLink interconnects. outputs drive column.
Operational Modes
block four operational modes, depending your application needs (see Table 18-4). Quartus software built-in megafunctions that control mode. After have made your parameter settings using megafunction's MegaWizard® Plug-In, Quartus software automatically configures block.
Table 18-5. Block Operational Modes Mode
Simple multiplier Multiply accumulator Two-multiplier adder Four-multiplier adder
multiplier
Eight multipliers with eight Four multipliers with four product outputs product outputs 34-bit multiplyaccumulate blocks 52-bit multiplyaccumulate blocks
Four two-multiplier adders two-multiplier adders four-multiplier adders four-multiplier adder
Simple Multiplier Mode
simple multiplier mode, block performs individual multiplication operations general-purpose multipliers applications such equalizer coefficient updates that require many individual multiplication operations.
18-18 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
18-Bit Multipliers
configure each block multiplier bits. single block support individual 9-bit smaller multipliers, individual multipliers with operand widths between 18-bits. Figure 18-10 shows simple multiplier mode. Figure 18-10. Simple Multiplier Mode
signa
Adder Output Block CLRN CLRN CLRN
shiftoutb
shiftouta signb
multiplier operands accept signed integers, unsigned integers, combination. signa signb signals dynamic registered block. Additionally, register multiplier inputs results independently. Pipelining result, using pipeline registers block, increases performance block.
36-Bit Multiplier
36-bit multiplier subset simple multiplier mode. uses entire block implement 36-bit multiplier. four 18-bit multipliers part each input, shown Figure 18-11 page 18-21. adder/output block adds partial products using
Altera Corporation July 2005
18-19 Stratix Device Handbook, Volume
Operational Modes
summation block. pipeline registers between multiplier stage summation block. 36-bit multiplier supports signed unsigned operation. 36-bit multiplier useful when your application needs more than 18-bit precision, example, mantissa multiplication precision floating-point arithmetic applications.
18-20 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Figure 18-11. 36-Bit Multiplier
signa signb
A[17.0]
CLRN
CLRN
B[17.0]
CLRN
A[35.18]
CLRN Partial Product Summation Block CLRN
Data
CLRN
B[35.18]
CLRN
A[35.18]
CLRN
CLRN
B[17.0]
CLRN
A[17.0]
CLRN
CLRN
B[35.18]
CLRN
Altera Corporation July 2005
18-21 Stratix Device Handbook, Volume
Operational Modes
Multiply Accumulator Mode
multiply accumulator mode, output multiplier stage feeds adder/output block, which configured accumulator subtractor (see Figure 18-12). implement independent 18-bit multiply accumulators block. Quartus software implements smaller multiplier-accumulators tying unused loworder bits 18-bit multiplier ground. Figure 18-12. Multiply Accumulator Mode
signa signb aclr clock
shiftinb
shiftina
Data
Accumulator CLRN CLRN Data
CLRN
Data
overflow
CLRN CLRN
shiftoutb
shiftouta
addnsub1 signa signb accum_sload1
Note Figure 18-12:
signa signb signals same multiplier stage adder/output block.
multiply accumulator output bits wide maximum 36-bit result with 16-bits accumulation. this mode, block uses output registers accum_sload overflow signals. accum_sload[1.0] signal synchronously loads multiplier result accumulator output. This signal unregistered registered once twice. block then begin accumulation without losing clock cycles. overflow signal indicates overflow underflow accumulator. This signal
18-22 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
cleared next accumulation cycle, external latch preserve signal. addnsub[1.0] signals perform accumulation subtraction dynamically. want blocks your design only accumulator, multiply followed accumulator force software implement logic block.
Two-Multiplier Adder Mode
two-multiplier adder mode uses adder/output block subtract outputs multiplier block, which useful applications such functions complex filters. Additionally, this mode, block outputs sums differences multipliers bits, sums differences 9-bit smaller multipliers. single block implement 18-bit complex multiplier 9-bit complex multipliers. complex multiplication written this mode, single block calculates real part using adder/subtractor/accumulator imaginary part using another adder/subtractor/accumulator data bits. Figure 18-13 shows 18-bit complex multiplication. data widths bits, block perform complex multiplications using four one-level adders. Resources outside block route each input multiplier inputs. only adder block follows multiplication operations.
Altera Corporation July 2005
18-23 Stratix Device Handbook, Volume
Operational Modes
Figure 18-13. Complex Multiplier Implemented Using Two-Multiplier Adder Mode
Adder (Imaginary Part) Subtractor (Real Part) Block
Four-Multiplier Adder Mode
four-multiplier adder mode, which 1-dimensional 2-dimensional filtering applications, block adds results adder/subtractor/accumulators final stage (the summation block). only adder block follows multiplication operations.
18-Bit Summation Blocks
single block implement summation blocks (see Figure 18-14 page 18-25). multiplier product widths must same size.
18-24 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Figure 18-14. Four-Multiplier Adder Mode
shiftina shiftinb signa signb aclr clock
Data
CLRN
CLRN
Adder/ Subtractor
Data
CLRN
Data
CLRN Adder CLRN
Data
CLRN
Data
addnsub0 signa signb addnsub1
CLRN
Data
CLRN
CLRN
Adder/ Subtractor
Data
CLRN
Data
CLRN
CLRN
Data
CLRN
shiftoutb
shiftouta
Altera Corporation July 2005
18-25 Stratix Device Handbook, Volume
Operational Modes
Filters
four-multiplier adder mode used filter complex filter applications. block combines four-multiplier adder with input registers configured shift registers. shift inputs contains filter data, while other holds coefficients, which loaded serially parallel (see Figure 18-15). input shift register eliminates need shift registers external block (e.g., implemented device logic elements). This architecture simplifies filter design improves performance because block implements filter circuitry. Serial shift inputs 36-bit simple multiplier mode require external registers.
block implement entire 18-bit filter with four taps. filters larger than four taps, cascade blocks with additional adder stages implemented logic elements.
18-26 Stratix Device Handbook, Volume
Altera Corporation July 2005
Blocks Stratix Stratix Devices
Figure 18-15. Input Shift Registers Configured Filter
Data A[n] B[n] adder) CLRN CLRN
Data
CLRN
Data
Data adder) CLRN CLRN
CLRN
Data
Data adder) CLRN CLRN
CLRN
Altera Corporation July 2005
18-27 Stratix Device Handbook, Volume
Software Support
Software Support
Altera provides distinct methods implementing various modes block your design: instantiation inference. Both methods following three Quartus megafunctions:
lpm_mult altmult_add altmult_accum
instantiate megafunctions Quartus software block. Alternatively, with inference, create design synthesize using third-party synthesis tool like LeonardoSpectrum Synplify Quartus Native Synthesis that infers appropriate megafunction recognizing multipliers, multiplier adders, multiplier accumulators. Using either method, Quartus software maps functionality blocks during compilation.
Implementing High-Performance Functions Stratix Stratix Devices chapter Stratix Device Handbook, Volume Stratix Device Handbook, Volume more information using blocks implement high-performance functions such filters, filters, discreet cosine transforms (DCTs). Quartus On-Line Help instructions using megafunctions MegaWizard Plug-In Manager. more information block inference support, Recommended Coding Styles chapter Quartus Development Software Handbook v4.1, Volume Stratix Stratix device blocks optimized support applications that need high data throughput, such filters, functions, encoders. These blocks flexible configured four operational modes suit application need. block's adder/subtractor/accumulator summation blocks minimize amount logic resources used provide efficient routing. This efficiency results improved performance data throughput applications. Quartus software, together with LeonardoSpectrum Synplify software, provides complete easy-to-use flow implementing functionality block.
Conclusion
18-28 Stratix Device Handbook, Volume
Altera Corporation July 2005

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