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Transitioning APEX Designs Stratix Stratix Devices
S52012-3.0
Stratix® Stratix devices Altera's next-generation, system-ona-programmable-chip (SOPC) solution. Stratix Stratix devices simplify block-based design methodology bridge between system bandwidth requirements programmable logic performance. This chapter highlights features Stratix Stratix devices provides assistance when transitioning designs from APEXII APEX devices Stratix Stratix architecture. Designers using this chapter should familiar with APEX APEX architecture available device features. this chapter conjunction with Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
General Architecture
Stratix Stratix devices offer many features architectural enhancements. Enhanced logic elements (LEs) MultiTrackinterconnect structure offer reduced resource utilization considerable design performance improvement. MultiTrack interconnect uses DirectDrivetechnology ensure availability deterministic routing resources design block, regardless placement within device. architectural changes between Stratix Stratix APEX APEX devices described this section require design changes. However, must resynthesize your design recompile Quartus® software target Stratix Stratix devices.
Altera Corporation February 2005
General Architecture
Logic Elements
Stratix Stratix device include several new, advanced features that improve design performance reduce logic resource consumption (see Table 3-1). Quartus software automatically uses these features improve device utilization.
Table 3-1. Stratix Stratix Features Feature Function Benefit
Conserves resources Register chain interconnects Direct path between register output Provides fast shift register register input adjacent within same logic array implementation Saves local interconnect routing block (LAB) resources within Look-up table (LUT) chain interconnects Direct path between combinatorial Allows LUTs within same output fast input cascade together high-speed wide adjacent within same fan-in functions, such wide operations Bypasses local interconnect faster performance Allows register output feed back into same such that register packed with fanout Uses implementing both adder subtractor Enhanced register packing mode Uses resources more efficiently
Register-to-LUT feedback path
Dynamic arithmetic mode
Improves performance functions that switch between addition subtraction frequently, such correlators
Carry-select chain
Calculates outputs possible carryGives immediate access result parallel both carry-in Increases speed carry functions high-speed operations, such counters, adders, comparators Supports direct asynchronous clear preset functions Conserves resources Does require additional logic resources implement NOT-gate push-back
Asynchronous clear asynchronous preset function
addition features described Table 3-1, there enhancements chains that connect together. Carry chains implemented vertically Stratix Stratix devices, instead horizontally APEX APEX devices, continue across rows, instead across columns, shown Figure 3-1. Also note that Stratix Stratix architectures support cascade primitive. Therefore, Quartus Compiler automatically converts
Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
cascade primitives APEX APEX designs wire primitive when compiled Stratix Stratix devices. These architectural changes transparent user require design changes. Figure 3-1. Carry Chain Implementation APEX APEX Devices Stratix Stratix Devices
APEX APEX Devices Stratix Devices
Carry Chains
Carry-Select Chains
LABs (with Each)
MultiTrack Interconnect
Stratix Stratix devices MultiTrack interconnect structure provide high-speed connection between logic resources using performance-optimized routing channels different lengths. This feature maximizes overall design performance placing critical paths routing lines with greater speed, resulting minimal propagation delay.
Altera Corporation February 2005
Stratix Device Handbook, Volume
General Architecture
Stratix Stratix device MultiTrack interconnect resources described Table 3-2.
Table 3-2. Stratix Stratix Device MultiTrack Interconnect Resources Routing Type
Column Column Column
Interconnect
Direct link
Span
Adjacent LABs and/or blocks Four units horizontally Eight units horizontally Horizontal routing across width device Four units vertically Eight units vertically Vertical routing across length device
Direct link routing saves routing resources while providing fast communication paths between resource blocks. Direct link interconnects allow LAB, digital signal processing (DSP) block, TriMatrixmemory block drive data into local interconnect left right neighbors. LABs, blocks, TriMatrix memory blocks also direct link interconnects drive data back into themselves feedback. Quartus software automatically uses these routing resources enhance design performance.
more information about architecture MultiTrack interconnect structure Stratix Stratix devices, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook, Volume
DirectDrive Technology
When using APEX devices, must place critical paths same MegaLABcolumn improve performance. Additionally, should place critical paths same MegaLAB structure optimal performance. However, this restriction does exist Stratix Stratix devices because they contain MegaLAB structures. With DirectDrivetechnology Stratix Stratix devices, actual distance between source destination path most important criteria meeting timing performance. DirectDrive technology ensures that same routing resources available each design block, regardless location device.
Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
Architectural Element Names
architectural element naming system within Stratix Stratix devices differs from row-column coordinate system (for example, LC1_A2, LAB_B1) used previous Altera device families. Stratix Stratix devices uses naming system based coordinate system, number designates location within block where logic resides, such within LAB. Because Stratix Stratix architectures column-based, this naming simplifies location assignments. Stratix Stratix architectural blocks include:
LAB: logic array block DSP: digital signal processing block DSPOUT: adder/subtractor/accumulator summation block block M512: 512-bit memory block M4K: 4-Kbit memory block M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
logic element IOC: element PLL: phase-locked loop DSPMULT: block multiplier SERDESTX: transmitter serializer/deserializer SERDESRX: receiver serializer/deserializer
Altera Corporation February 2005
Stratix Device Handbook, Volume
General Architecture
Table highlights location syntax used Stratix Stratix devices.
Table 3-3. Stratix Stratix Location Assignment Syntax Architectural Elements
Blocks
Example Location Syntax Element Name Location Syntax Location
LAB, DSP, <element_name>_X<number> LAB_X1_Y1 DSPOUT, M512, _Y<number> M4K, M-RAM IOC, PLL, DSPMULT, SERDESTX, SERDESRX
pins <element_name>_X<number> LC_X1_Y1_N0 _Y<number>_N<number>
Description
Designates column Designates first located column
Logic
Pins
pin_<pin_label>
pin_5
Note Table 3-3:
make assignments pads using
following guidelines with naming system:
anchor point, origin, Stratix Stratix devices bottom-left corner, instead top-left corner APEX APEX devices. anchor point, origin, large block element (e.g., M-RAM block) also bottom-left corner. numbers zero-based, meaning origin bottom-left device pins constitute first last rows columns coordinates. Therefore, bottom pins resides X<number>, first left column pins resides Y<number>. sub-location elements, numbering begins top. Therefore, still numbered from bottom, start zero.
Figure show Stratix Stratix architectural element numbering convention. Figure displays floorplan view Quartus software.
Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
Figure 3-2. Stratix Stratix Architectural Elements Note
Blocks Units Wide Unit High
(1,18)
(11,18)
M512 (12,18)
(13,18)
(14,18)
(16,18)
Block (17,1) Units Wide Eight Units High
(1,17)
(11,17)
M512 (12,17)
(13,17)
(14,17)
(16,17)
(1,16)
(11,16)
M512 (12,16)
(13,16)
(14,16)
(16,16)
DSPMULT (17,7,0) (17,7,1)
(1,15)
(11,15)
M512 (12,15)
(13,15)
(14,15)
(16,15)
(14,14)
(16,14)
DSPMULT (17,5,0) (17,5,1)
(14,13) Mega Block Units Wide Units High
(16,13)
DSPOUT (18,1,0) (18,1,7)
Mega (1,2)
DSPMULT (17,3,0) (17,3,1)
Pins
(14,2)
(16,2) DSPMULT (17,1,0) (17,1,1)
(0,1,0)
(1,1)
(11,1)
M512 (12,1)
(13,1)
(14,1)
(16,1)
Origin
Notes Figure 3-2:
Figure shows part Stratix Stratix device. Large block elements their lower-left corner coordinate location. Stratix architectural elements include transceiver blocks right side device.
Altera Corporation February 2005
Stratix Device Handbook, Volume
TriMatrix Memory
Figure 3-3. Numbering Shown Quartus Software
TriMatrix Memory
TriMatrix memory three different sizes memory blocks, each optimized different purpose application. M512 blocks consist bits plus parity (576 bits), blocks consist bits plus parity (4,608 bits), M-RAM blocks consist 512K bits plus parity (589,824 bits). This structure differs from APEX APEX devices, which feature uniformly sized embedded system blocks (ESBs) either Kbits (APEX devices) Kbits (APEX devices) large. Stratix Stratix TriMatrix memory blocks give advanced control each memory block, with features such byte enables, parity storage, shift-register mode, well mixed-port width support true dual-port mode operation.
Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
Table compares TriMatrix memory with ESBs.
Table 3-4. Stratix Stratix TriMatrix Memory Blocks APEX APEX ESBs Stratix Stratix Features M512
Size (bits) Parity bits Byte enable True dual-port mode Embedded shift register Dedicated contentaddressable memory (CAM) support Pre-loadable initialization with .mif Packed mode Feed-through behavior Output power-up condition
APEX
4,608
APEX
2,048
M-RAM
589,824 4,096
Includes support Includes support Includes support mixed width mixed width mixed width
Rising edge Powers cleared even using .mif
Rising edge Powers cleared even using .mif
Rising edge Powers with unknown state
Falling edge Powers cleared initialized value, using .mif
Falling edge Powers cleared initialized value, using .mif
Notes Table 3-4:
.mif: Memory Initialization File. Packed mode refers combining single-port blocks into single block that placed into true dual-port mode.
Stratix Stratix TriMatrix memory blocks only support pipelined mode, while APEX APEX ESBs support both pipelined flow-through modes. Since TriMatrix memory blocks pipelined, input data address lines registered, while outputs either registered combinatorial. Stratix Stratix memory block registers implement input output registers without utilizing additional resources. compile designs containing pipelined memory blocks (inputs registered) Stratix Stratix devices without modifications. However, APEX
Altera Corporation February 2005
Stratix Device Handbook, Volume
TriMatrix Memory
APEX design contains flow-through memory, must modify memory modules target Stratix Stratix architectures (see "Memory Megafunctions" page 3-12 more information).
more information about TriMatrix memory converting flowthrough memory modules pipelined, TriMatrix Embedded Memory Blocks Stratix Stratix Devices chapter Stratix Device Handbook 210: Converting Memory from Asynchronous Synchronous Stratix Stratix Designs.
Same-Port Read-During-Write Mode
same-port read-during-write mode, block singleport, simple dual-port, true dual-port mode. port from block both reads writes same address location using same clock. When APEX APEX devices perform same-port readduring-write operation, data available falling edge clock cycle which written, shown Figure 3-4. When Stratix Stratix devices perform same-port read-during-write operation, data available rising edge same clock cycle which written, shown Figure 3-5. This holds true TriMatrix memory blocks. Figure 3-4. Falling Edge Feed-Through Behavior (APEX APEX Devices) Note
inclock data_in
wren
data_out
Note Figure 3-4:
Figures assume that address stays constant throughout that outputs registered.
3-10 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
Figure 3-5. Rising Edge Feed-Through Behavior (Stratix Stratix Devices) Note
inclock data_in
wren
data_out
Note Figure 3-5:
Figures assume that address stays constant throughout that outputs registered.
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when block simple true dual-port mode port reading other port writing same address location using same clock. APEX APEX designs, outputs data first half clock cycle data second half clock cycle, indicated Figure 3-6. Figure 3-6. Mixed-Port Feed-Through Behavior (APEX APEX Devices) Note
inclock Port data_in Port wren Port wren Port data_out
Note Figure 3-6:
Figure assumes that outputs registered.
Stratix Stratix device outputs data rising edge clock cycle immediately after data written. When Stratix Stratix M512 blocks, choose whether output data targeted address output don't care value during clock cycle when data written. M-RAM blocks
Altera Corporation February 2005
3-11 Stratix Device Handbook, Volume
TriMatrix Memory
always output don't care value. Figures show feedthrough behavior mixed-port mode. altsyncram megafunction output behavior during mixed-port read-duringwrite mode. Figure 3-7. Mixed-Port Feed-Through Behavior (OLD_DATA) Note
inclock addressA addressB Port data_in Port wren Port wren Port data_out Address
Note Figure 3-7:
Figures assume that address stays constant throughout that outputs registered.
Figure 3-8. Mixed-Port Feed-Through Behavior (DONT_CARE) Note
inclock addressA addressB Port data_in Port wren Port wren Port data_out Unknown Address
Note Figure 3-8:
Figures assume that address stays constant throughout that outputs registered.
Memory Megafunctions
convert originally targeting APEX APEX architecture Stratix Stratix memory, specify Stratix Stratix target family MegaWizard Plug-In Manager. software
3-12 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
updates memory module Stratix Stratix architecture instantiates synchronous memory megafunction, altsyncram, which supports both blocks Stratix Stratix architectures.
FIFO Conditions
First-in first-out (FIFO) functionality slightly different Stratix Stratix devices compared APEX APEX devices. Stratix Stratix devices support simultaneous reads writes from empty FIFO buffer. Also, Stratix Stratix devices support lpm_showahead parameter when targeting FIFO buffer because TriMatrix memory blocks synchronous. lpm_showahead parameter APEX APEX devices puts FIFO buffer "read-acknowledge" mode first data written into FIFO buffer immediately flows through output. Other than these differences, APEX APEX FIFO functions fully compatible with Stratix Stratix architectures.
Design Migration Mode Quartus Software
Quartus software features migration mode simplifying process converting APEX APEX memory functions Stratix Stratix architecture. design Stratix Stratix altsyncram megafunction replacement previous APEX APEX memory function while maintaining functionally similar behavior, Quartus software automatically converts memory. software produces warning message during compilation reminding verify that design migrated correctly. memory blocks with inputs registered, existing megafunction converted altsyncram megafunction. software generates warning when altsyncram megafunction incompatible. example, block with inputs registered except read enable compiles with warning message indicating that read-enable port registered. suppress warning messages entire project individual memory blocks setting parameter "on" global parameter selecting Assignment Organizer (Tools menu). Assignment Organizer window, click Parameters Assignment Categories box. Type Assignment Name type Assignment Setting box. suppress these warning messages per-memory-instance basis, parameter Assignment Organizer "on" memory instance.
Altera Corporation February 2005
3-13 Stratix Device Handbook, Volume
TriMatrix Memory
functionality APEX APEX memory megafunction differs from altsyncram functionality least clock feeds memory megafunction, Quartus software converts APEX APEX memory megafunction Stratix Stratix altsyncram megafunction. This conversion useful initial evaluation design might perform Stratix Stratix devices should only used evaluation purposes. During this process, Quartus software generates warning that conversion functionally incorrect timing results accurate. Since functionality incorrect compilation only intended comparative purposes, Quartus software does generate programming file. functionally correct conversion requires manually instantiating altsyncram megafunction require additional design changes. previous memory function does have clock (fully asynchronous), fitting-evaluation conversion results error message during compilation does successfully convert design.
210: Converting Memory from Asynchronous Synchronous Stratix Stratix Designs more information. Table summarizes possible scenarios when using design migration mode resulting behavior Quartus software. most common cases where design-migration mode have difficulty converting existing design when:
port reading from address that being written another port (mixed-port read-during-write mode). both ports using same clock, read port Stratix Stratix devices data until next clock cycle, after data written.
3-14 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
There differences power-up behavior between APEX APEX 20K, Stratix Stratix devices. should manually account these differences maintain desired operation system.
Table 3-5. Migration Mode Summary Memory Configuration
Single-port
Conditions
Possible Instantiated Megafunctions
altrom lpm_ram_dq lpm_ram_io lpm_rom
Quartus Warning Message(s)
Power-up differences.
Programming File Generated
inputs registered. altram
inputs registered. altdpram Multi-port (two-, three-, four-port lpm_ram_dp functions) altqpram
Power-up differences. Mixed-port read- duringwrite. Power-up differences. Mixed-port read- duringwrite. Read enable will registered.
alt3pram
Dual-port Read-enable ports unregistered. Other inputs registered.
altdpram lpm_ram_dp altqpram alt3pram altdpram lpm_ram_dp altqpram alt3pram altram lpm_ram_dq lpm_ram_io altram altrom altdpram altqpram alt3pram altdpram lpm_ram_dq lpm_ram_io lpm_rom lpm_ram_dp lpm_ram_dp
Dual-port
other unregistered port except read-enable ports. Clock available. least registered input. Clock available. clock.
Compile fitting- evaluation purposes.
Single-port
Compile fitting- evaluation purposes. Error conversion possible.
clock
Note Table 3-5:
parameter turned Quartus software does issue these warnings.
Altera Corporation February 2005
3-15 Stratix Device Handbook, Volume
Block
Block
Stratix Stratix device blocks outperform LE-based implementations common functions. Each block contains several multipliers that configured widths bits. Depending mode operation, these multipliers optionally feed adder/subtractor/accumulator summation unit. configure block's input registers efficiently implement shift registers serial input sharing, eliminating need external shift registers LEs. pipeline registers block accelerated operation. Registers available input output multiplier, output adder/subtractor/accumulator summation block. blocks have four modes operation:
Simple multiplier mode Multiply-accumulator mode Two-multipliers adder mode Four-multipliers adder mode
Associated megafunctions available Quartus software implement each mode block.
Block Megafunctions
lpm_mult megafunction configure block simple multiplier mode. lpm_mult Multiplier Implementation option MegaWizard Plug-In Manager either default implementation, ESBs, blocks. select Default option, compiler first attempts place multiplier blocks. However, under certain conditions, compiler implement multiplier LEs. placement depends factors such block resource consumption, width multiplier, whether operand constant, other options chosen megafunction. Stratix Stratix devices support ESBs option. select this option, Quartus software tries place multiplier unused blocks. recompile APEX APEX designs using lpm_mult megafunction Stratix Stratix devices Quartus software without changing megafunction. This makes converting lpm_mult megafunction designs Stratix Stratix devices straightforward.
3-16 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
APEX APEX designs pipeline stages improve registered performance LE-based multipliers expense latency. However, need pipeline stages when targeting Stratix Stratix high-speed blocks. blocks offer three sets dedicated pipeline registers. Therefore, Altera recommends that reduce number pipeline stages three fewer implement them blocks. Additional pipeline stages implemented LEs, which latency without providing performance benefit. example, configure block 36-bit multiplication using lpm_mult megafunction. specify pipeline stages, software uses block input pipeline registers. specify three pipeline stages, software places third pipeline stage block output registers. This design yields same performance with three pipeline stages because critical path 36-bit operation within multiplier. With four more pipeline stages, device inefficiently uses resources additional pipeline stages. Therefore, multiplier modules APEX APEX designs converted Stratix Stratix designs require same number pipeline stages, surrounding circuitry must modified preserve original functionality design. design with multipliers feeding accumulator altmult_accum (MAC) megafunction block multiplyaccumulator mode. APEX APEX design already uses LEbased multipliers feeding accumulator, Quartus software does automatically instantiate altmult_accum (MAC) megafunction. Therefore, should MegaWizard Plug-In Manager instantiate altmult_accum (MAC) megafunction. also LeonardoSpectrumor Synplify synthesis tools, which have block inference support, instantiate megafunction. Designs that multipliers feeding into adders instantiate altmult_add megafunction configure blocks twomultipliers adder four-multipliers adder mode. also altmult_add megafunction stand-alone multipliers take advantage blocks features such dynamic sign control inputs input shift register connections. These features accessible through lpm_mult megafunction. your APEX APEX designs already multipliers feeding adder/subtractor, Quartus software does automatically infer altmult_add megafunction. Therefore, should step through MegaWizard Plug-In Manager instantiate altmult_add megafunction LeonardoSpectrum Synplify synthesis tools, which have block inference support.
Altera Corporation February 2005
3-17 Stratix Device Handbook, Volume
PLLs Clock Networks
Furthermore, altmult_add altmult_accum (MAC) megafunctions only available Stratix Stratix devices because these megafunctions target Stratix Stratix blocks, which available other device families. attempt these megafunctions designs that target other Altera device families, Quartus software reports error message. lpm_mult lpm_add_sub altaccumulate megafunction similar functionality other device families. third-party synthesis tool, able avoid megafunction conversion process. LeonardoSpectrum Synplify provide inference support lpm_mult, altmult_add, altmult_accum (MAC) blocks. your design does require implement multipliers blocks, must manually global parameter parameter each instance force tool implement lpm_mult megafunction LEs. Depending synthesis tools, inference blocks handled differently.
more information about using blocks Stratix Stratix devices, Blocks Stratix Stratix Devices chapter Stratix Device Handbook. Stratix Stratix devices provide exceptional clock management with hierarchical clock network four enhanced phase-locked loops (PLLs) eight fast PLLs versus four general-purpose PLLs four True-LVDSPLLs APEX devices. providing superior clock interfacing, numerous advanced clocking features, significant enhancements over APEX APEX PLLs, Stratix Stratix device PLLs increase system performance bandwidth.
PLLs Clock Networks
Clock Networks
There global clock networks available throughout each Stratix Stratix device well fast regional four regional clock networks device quadrant, resulting unique clock networks device. increased number dedicated clock resources available Stratix Stratix devices eliminate need general-purpose pins clock inputs. Stratix EP1S25 smaller devices have dedicated clock pins EP1S30 larger devices have four additional clock pins feed various clocking networks. comparison, APEX devices have eight dedicated clock pins APEX 20KE APEX 20KC devices have four dedicated clock pins.
3-18 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
dedicated clock pins Stratix Stratix devices feed clock inputs, global clock networks, regional clock networks. outputs internally-generated signals also drive global clock network. These global clocks available throughout entire device clock device resources. Stratix Stratix devices divided into four quadrants, each equipped with four regional clock networks. regional clock network either dedicated clock pins outputs within device quadrant. regional clock network only feed device resources within particular device quadrant. Each Stratix Stratix device provides eight dedicated fast clock pins FCLK[7.0] versus four dedicated fast pins APEX APEX devices. fast regional clock network these dedicated FCLK[7.0] pins interconnect. interconnect allows internal logic drive fast regional clock network. fast regional clock network available generalpurpose clocking well high fan-out control signals such clear, preset, enable, TRDY IRDY applications, bidirectional output pins. EP1S25 smaller devices have eight fast regional clock networks, device quadrant. quadrants EP1S30 larger devices divided half, each half-quadrant clocked eight fast regional networks. Additionally, each fast regional clock network drive neighboring half-quadrant (within same device quadrant).
PLLs
Table highlights Stratix Stratix enhancements existing APEX APEX 20KE APEX 20KC features.
Table 3-6. Stratix Stratix APEX APEX 20KE APEX 20KC Features (Part Stratix Stratix Feature Enhanced PLLs
Number PLLs (EP1S30 smaller devices); four (EP1S40 larger devices)
APEX PLLs Fast PLLs
Four (EP1S25 Four generalpurpose PLLs smaller devices); four LVDS PLLs eight (EP1S30 larger devices) (10)
APEX 20KE APEX 20KC PLLs
four generalpurpose PLLs. LVDS PLLs.
Minimum input frequency Maximum input frequency
644.5 (11)
Altera Corporation February 2005
3-19 Stratix Device Handbook, Volume
PLLs Clock Networks
Table 3-6. Stratix Stratix APEX APEX 20KE APEX 20KC Features (Part Stratix Stratix Feature Enhanced PLLs
Internal clock outputs External clock outputs Four differential/eight singled-ended single-ended Down 160-ps increments
APEX PLLs Fast PLLs
APEX 20KE APEX 20KC PLLs
Phase Shift Time shift counter values counter values clock input sharing T1/E1 rate conversion Notes Table 3-6:
Down 125-ps increments
500-ps 1-ns resolution
0.4- 1-ns resolution
250-ps increments
EP20K200E smaller devices only have general-purpose PLLs. EP20K400E larger devices have LVDS PLLs four general-purpose PLLs. more information, 115: Using ClockLock ClockBoost Features APEX Devices. maximum input frequency Stratix Stratix enhanced PLLs depends standard used with that input clock pin. more information, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet section Stratix Device Handbook. Fast PLLs have three internal clock output ports PLL. Fast PLLs have internal clock output ports PLL. Every Stratix device enhanced PLLs with eight single-ended four differential outputs each. additional enhanced PLLs EP1S80, EP1S60, EP1S40 devices each have single-ended output. driven fast global regional outputs external clock output pin. smallest phase shift unit determined voltage-controlled oscillator (VCO) period divided There maximum between clock outputs. clock frequency 1.544 clock frequency 2.048 MHz, which violates minimum clock input frequency requirement Stratix PLL. Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX40 contains four. (10) Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX40 contains four. (11) Stratix supports clock rates Gbps using DPA.
Enhanced PLLs
Stratix Stratix devices provide four enhanced PLLs with advanced features. addition feature changes mentioned Table 3-6, Stratix Stratix device PLLs include many new,
3-20 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
advanced features improve system timing management performance. Table shows some features available Stratix Stratix enhanced PLLs.
Table 3-7. Stratix Stratix Enhanced Features Feature
clock outputs feed logic array locked output feed logic array Multiplication allowed zero-delay buffer mode external feedback mode Programmable phase shift allowed zero-delay buffer mode external feedback mode Phase frequency detector (PFD) disable Clock output disable Programmable lock detect gated lock Dynamic clock switchover reconfiguration Programmable bandwidth Spread spectrum Notes Table 3-7:
These features also available fast PLLs. addition delay chains each counter, specify programmable phase shift each output fine coarse levels. Each clock output associated clock enable signal. used external feedback mode, will need relock.
Description
Allows clock outputs feed data ports registers combinatorial logic. Allows locked port feed data ports registers combinatorial logic. clock outputs multiplied divided down ratio input clock. clock outputs phase shifted. phase shift relative clock output.
Programmable duty cycle Allows variable duty cycle each clock output.
Allows operate last control voltage frequency with some long term drift. maintains lock with output clocks disabled. Holds lock signal programmable number input clock cycles. Enables switch between reference input clocks, either clock redundancy dual-clock domain applications. Allows counters delay elements within reconfigured realtime without reloading programmer object file (.pof). Provides advanced control bandwidth using programmable control loop characteristics. Modulates target frequency over frequency range reduce electromagnetic interference (EMI) emissions.
Fast PLLs
Stratix Stratix fast PLLs similar APEX True-LVDS PLLs that setting, which governs relationship between clock input data rate, setting, which controls width
Altera Corporation February 2005
3-21 Stratix Device Handbook, Volume
PLLs Clock Networks
high-speed differential data bus, have equal. Additionally, Stratix Stratix fast PLLs offer three clock outputs, multiplied high-speed clocks drive serializer/deserializer (SERDES) block and/or external pin, low-speed clock drive logic array. fast PLLs both high-speed interfacing general-purpose applications. Table shows differences between Stratix Stratix fast PLLs APEX APEX True-LVDS PLLs.
Table 3-8. Stratix Stratix Fast APEX APEX True-LVDS Feature
Number fast PLLs TrueLVDS PLLs
Stratix Stratix
Four (EP1S25 smaller devices) fast PLLs Eight (EP1S30 larger devices) fast PLLs
APEX
Four True-LVDS PLLs
APEX 20KE APEX 20KC
True-LVDS PLLs
Number channels transmitter/receiver block frequency Minimum input frequency Minimum input frequency Notes Table 3-8:
1GHz
also Stratix Stratix device fast PLLs general-purpose applications. EP20K400E larger devices have True-LVDS PLLs. APEX 20KE APEX 20KC devices, Stratix EP1SGX10 EP1SGX25 contain two. EP1SGX10 contains four. Stratix supports frequency range 300-1000 (using DPA).
Stratix Stratix fast frequency range MHz, APEX True-LVDS frequency range GHz. Therefore, must update designs that data rate less than megabits second (Mbps) enhanced PLLs M512 blocks SERDES bypass mode. Additionally, must update designs that data rate faster than Mbps.
altpll Megafunction
Altera recommends that replace instances altclklock megafunction with altpll megafunction take advantage Stratix Stratix features. Although most cases retarget your APEX APEX design Stratix Stratix
3-22 Stratix Device Handbook, Volume
Altera Corporation February 2005
Transitioning APEX Designs Stratix Stratix Devices
device with altclklock megafunction, there specific cases where must altpll megafunction, explained this section. MegaWizard Plug-In Manager, select altpll megafunction directory from Available Megafunctions (see Figure 3-9). altclklock megafunction also available from Quartus software backward compatibility, instantiates altpll megafunction when targeting Stratix Stratix devices. Quartus Compiler automatically selects whether altpll module uses either enhanced fast based design's needs feature requirements each PLL. Figure 3-9. altpll Megafunction Selection MegaWizard Plug-In Manager
compile APEX APEX 20KE, APEX 20KC designs using altclklock megafunction normal mode Stratix Stratix devices without updating megafunction. However, should replace altclklock megafunction with altpll megafunction. Quartus software cannot implement requested clock multiplication division PLL, compiler reports error message with appropriate reason stated.
Altera Corporation February 2005
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PLLs Clock Networks
APEX APEX 20KE, APEX 20KC devices have only external clock output available PLL. Therefore, when retargeting APEX APEX 20KE, APEX 20KC design that uses PLLs zero delay buffer mode external feedback mode Stratix Stratix device, should replace instances altclklock megafunction. APEX APEX 20KE, APEX 20KC altclklock module only uses clock output (internal external) compiled target Stratix Stratix device, design compiles successfully with warning that design uses Stratix Stratix external clock output, extclk0. However, APEX APEX 20KE, APEX 20KC more than clock output, must replace instances altclklock megafunction with altpll megafunction because Quartus Compiler does know which clock output external output back Stratix Stratix device fbin pin. example, APEX APEX 20KE, APEX 20KC design with altclklock megafunction uses clock0 output port feed external clock output clock1 output port feed internal logic array, Quartus software generates error during compilation must MegaWizard Plug-In Manager instantiate altpll megafunction. using altpll megafunction, choose which four external clock outputs take advantage Stratix Stratix features available zero delay buffer mode external feedback mode.
Timing Analysis
When Quartus software performs timing analysis APEX APEX 20KE, APEX 20KC designs, clock settings override project clock settings. However, during timing analysis Stratix Stratix designs using PLLs, project clock settings override input clock frequency duty cycle settings. MegaWizard Plug-In Manager does project clock settings determine altpll parameters. This saves time with designs that features such clock switchover reconfiguration because Quartus software perform timing analysis without recompiling design. important note following:
warning during compilation reports that project clock settings overrides clock settings. project clock setting overrides clock settings timingdriven compilation. compiler will check lock frequency range PLL. frequency specified project clock settings outside lock frequency range, clock settings will overridden. Performing timing analysis without recompiling your design does change programming files. must recompile your design update programming files.
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Transitioning APEX Designs Stratix Stratix Devices
Default Required fMAX setting does override clock settings. Only individual clock settings override clock settings.
Therefore, enter different project clock settings corresponding settings accelerate timing analysis eliminating full compilation cycle.
more information about using Stratix Stratix PLLs, General-Purpose PLLs Stratix Stratix Devices chapter. Stratix Stratix element (IOE) architecture similar APEX architecture, with total registers latch each IOE. registers organized three sets: output registers drive single double-data rate (DDR) output path, input registers latch support single input path, output enable registers enhance clock-to-output enable timing SDRAM interfacing. synchronous reset signal available each three sets registers preset clear, neither. addition advanced architecture, Stratix Stratix features dedicated circuitry external interfacing, standards, differential on-chip termination, high-speed differential standard support.
Structure
External Interfacing
advanced Stratix Stratix architecture includes dedicated circuitry interface with external RAM. This circuitry provides enhanced support external high-speed memory devices such SDRAM FCRAM. SDRAM interface uses bidirectional signal, DQS, clock data, both transmitting receiving device. Stratix Stratix devices transmit signal with data signals minimize clock data skew. Stratix Stratix devices include groups programmable pins, bottom banks device. Each group consists that supports fixed number pins. number pins depends mode. When using external interfacing circuitry, drives dedicated clock network that feeds pins residing that bank. Stratix Stratix programmable delay chains that phase shift signal ensure data sampled appropriate point time. Therefore, Stratix Stratix devices make full IOEs, remove need build input data path logic array. make these assignments Quartus Assignment Organizer.
Altera Corporation February 2005
3-25 Stratix Device Handbook, Volume
Structure
more information external interfacing, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume Stratix Device Family Data Sheet Stratix Device Family Handbook.
Standard Support
Stratix Stratix devices support standards that APEX APEX devices support, including high-speed differential standards such LVDS, LVPECL, PCML, HyperTransporttechnology, differential HSTL input output clocks, differential SSTL output clocks. Stratix Stratix devices also introduce support SSTL-18 class Similar APEX devices, Stratix Stratix devices only support certain standards designated banks. addition, vref pins dedicated pins Stratix Stratix devices support input pins.
more information about standard support Stratix Stratix devices, Selectable Standards Stratix Stratix Devices chapter.
High-Speed Differential Standards
Stratix Stratix devices support high-speed differential interfaces speeds Mbps using high-speed PLLs that drive dedicated clock network SERDES. Each fast drive highspeed channels. Stratix Stratix devices enhanced PLLs M512 blocks provide Mbps performance SERDES bypass clock interfacing. There restriction number channels that clocked using this scenario. Stratix Stratix devices have different number differential channels than APEX devices. Tables 3-10 highlight number differential channels supported Stratix Stratix devices.
Table 3-9. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1S10
Count
Number Receiver Channels
Number Transmitter Channels
EP1S20
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Transitioning APEX Designs Stratix Stratix Devices
Table 3-9. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1S25
Count
1,020
Number Receiver Channels
Number Transmitter Channels
EP1S30
1,020
EP1S40
1,020
1,508
EP1S60
1,020
1,508
EP1S80
1,508
Note Table 3-9:
information channel speeds, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Differential Interfaces chapter Stratix Device Handbook, Volume
Table 3-10. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1SGX10 EP1SGX10
Count
Number Transceivers
Number SourceSynchronous Channels
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Structure
Table 3-10. Number Dedicated DIfferential Channels Stratix Devices (Part Note Device
EP1SGX25 EP1SGX25 EP1SGX25 EP1SGX40 EP1SGX40 Note Table 3-10:
information channel speeds, Stratix Device Family Data Sheet section Stratix Device Handbook, Volume High-Speed Source-Synchronous Differential Interfaces Stratix Devices chapter Stratix Device Handbook, Volume
Count
672/1,020 1,020 1,020 1,020
Number Transceivers
Number SourceSynchronous Channels
differential within Stratix also provides dynamic phase alignment (DPA). enables differential operate Gbps channel. automatically continuously tracks fluctuations caused system variations self-adjusts eliminate phase skew between multiplied clock serial data. block contains dynamic phase selector phase detection selection, SERDES, synchronizer, data realigner circuit. bypass dynamic phase aligner without affecting basic source-synchronous operation channel using separate deserializer. compile APEX LVDS design that uses clock-data synchronization (CDS) Stratix Stratix device, Quartus software issues warning during compilation that Stratix Stratix devices support CDS. Stratix Stratix devices offer flexible solution using byte realignment circuitry correct byte misalignment shifting, slipping, data bits. Stratix Stratix devices activate byte realignment circuitry when external (rx_data_align) internal custom-made state machine asserts SYNC node high. APEX APEX 20KE, APEX 20KCdevices have dedicated transmitter clock output (LVDSTXOUTCLK). Stratix Stratix devices, transmitter dataout channel with LVDS clock (fast clock) generates transmitter clock output. Therefore, drive channel output clock pin, just dedicated clock output pins. This solution offers better versatility address various applications that require more complex clocking schemes.
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Transitioning APEX Designs Stratix Stratix Devices
more information differential support, data realignment, transmitter clock output Stratix Stratix devices, High-Speed Differential Interfaces Stratix Devices chapter.
altlvds Megafunction
take full advantage high-speed differential standards available Stratix Stratix devices, should update each instance altlvds megafunction APEX APEX 20KE, APEX 20KC designs. MegaWizard Plug-In Manager, choose altlvds megafunction, select Stratix Stratix target device family, update megafunction, recompile your design. altlvds megafunction supports Stratix Stratix parameters that available APEX APEX 20KE, APEX 20KC devices. Tables 3-11 3-12 describe parameters LVDS receiver LVDS transmitter, respectively.
Table 3-11. altlvds Parameters Stratix LVDS Receiver Note Parameter
input_data_rate inclock_data_alignment rx_data_align
Function
Specifies data rate Mbps. This parameter replaces multiplication factor Indicates alignment rx_inclk rx_in data. Drives data alignment port fast enables byte realignment circuitry.
registered_data_align_input Registers rx_data_align input port clocked rx_outclock. common_rx_tx_pll
Indicates fast shared between receiver transmitter applications.
Table 3-12. altlvds Parameters Stratix LVDS Transmitter (Part Note Parameter
output_data_rate inclock_data_alignment outclock_alignment registered_input
Function
Specifies data rate Mbps. This parameter replaces multiplication factor Indicates alignment tx_inclk tx_in data. Specifies alignment tx_outclock tx_out data. Specifies clock source input synchronization registers, which either tx_inclock tx_coreclock. Used only when Registered Inputs option selected.
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Configuration
Table 3-12. altlvds Parameters Stratix LVDS Transmitter (Part Note Parameter
common_rx_tx_pll
Notes Tables 3-11 3-12:
specify these parameters MegaWizard Plug-In Manager. must specify data rate MegaWizard Plug-In Manager instead factor. same fast used clock both receiver transmitter only both running same frequency.
Function
Indicates fast shared between receiver transmitter applications.
Above standard offered APEX APEX 20K, Stratix devices, Stratix devices provide 3.175 Gbps transceivers. transceivers provide high-speed serial links chip-to-chip, backplane, line-side connectivity support number emerging high-speed protocols. find more information Stratix Family Data Sheet Stratix Family Handbook, Volume
Configuration
Stratix Stratix devices supports current configuration schemes, including enhanced configuration devices, passive serial (PS), passive parallel asynchronous (PPA), fast passive parallel (FPP), JTAG. Stratix Stratix devices also provide number configuration enhancements that take advantage when migrating APEX APEX designs Stratix Stratix devices.
Configuration Speed Schemes
configure Stratix Stratix devices maximum clock speed MHz, which faster than 66-MHz 33-MHz maximum configuration speeds APEX APEX devices, respectively. Similar APEX devices, 8-bit parallel data configure Stratix Stratix devices (the target device receive byte-wide configuration data each clock cycle) significantly speeding configuration times. select configuration scheme based MSEL pins driven. Stratix Stratix devices have three MSEL pins (APEX APEX devices have MSEL pins) determining configuration scheme.
more information about Stratix Stratix configuration schemes, Configuring Stratix Stratix Devices chapter.
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Transitioning APEX Designs Stratix Stratix Devices
Remote Update Configuration
APEX device family introduced concept remote update configuration, where could send APEX device configuration files from remote source device would store files flash memory reconfigure itself with configuration data. Stratix Stratix devices enhance support remote update configuration with new, dedicated circuitry handle recover from errors. error occurs either during device configuration user mode, this circuitry reconfigures Stratix Stratix device known state. Additionally, Stratix Stratix devices have user watchdog timer ensure application configuration data executes successfully during user mode. User logic must continually reset this watchdog timer order validate that application configuration data functioning properly.
more information about remote local update modes, Remote System Configuration with Stratix Stratix Devices chapter.
JTAG Instruction Support
Stratix Stratix devices support JTAG instructions, PULSE_NCONFIG CONFIG_IO. PULSE_NCONFIG instruction emulates pulsing nCONFIG signal trigger reconfiguration, while actual nCONFIG device unaffected. CONFIG_IO instruction allows JTAG chain configure standards pins. Because this instruction interrupts device configuration, should reconfigure Stratix Stratix device after finish JTAG testing ensure proper device operation. Table 3-13 compares JTAG instruction support Stratix Stratix devices versus APEX APEX devices. further information about supported JTAG instructions, appropriate device family data sheet.
Table 3-13. JTAG Instruction Support (Part JTAG Instruction
SAMPLE/PRELOAD EXTEST BYPASS USERCODE IDCODE Instructions
Stratix
APEX
APEX
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Conclusion
Table 3-13. JTAG Instruction Support (Part JTAG Instruction
SignalTapII Instructions HIGHZ CLAMP PULSE_NCONFIG CONFIG_IO
Stratix
APEX
APEX
Conclusion
Stratix Stratix devices extend advanced features available APEX APEX device families deliver complete system-on-a-programmable-chip (SOPC) solution. following these guidelines, easily transition current APEX APEX designs take advantage features available Stratix Stratix devices.
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