CF51004-2.1 APEXII devices configured using four configuration sc
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Configuring APEX Devices
CF51004-2.1
APEXII devices configured using four configuration schemes. configuration schemes either microprocessor configuration device. APEX devices configured using passive serial (PS), fast passive parallel (FPP), passive parallel asynchronous (PPA), Joint Test Action Group (JTAG) configuration schemes. configuration scheme used selected driving APEX device MSEL1 MSEL0 pins either high shown Table 6-1. your application only requires single configuration mode, MSEL pins connected (VCCIO bank where MSEL resides) ground. your application requires more than configuration mode, switch MSEL pins after FPGA configured successfully. Toggling these pins during user-mode does affect device operation; however, MSEL pins must valid before reconfiguration initiated.
Table 6-1. APEX Configuration Schemes MSEL1
Notes Table 6-1:
leave MSEL pins floating; connect them low- high-logic level. These pins support non-JTAG configuration scheme used production. only JTAG configuration used, should connect MSEL pins ground. JTAG-based configuration takes precedence over other configuration schemes, which means MSEL settings ignored.
MSEL0
Configuration Scheme
JTAG Based
Altera Corporation August 2005
Passive Serial Configuration
Table shows approximate configuration file sizes APEX devices.
Table 6-2. APEX Binary File (.rbf) Sizes Device
EP2A15 EP2A25 EP2A40 EP2A70
Data Size (Bits)
4,358,512 6,275,200 9,640,528 17,417,088
Data Size (Bytes)
544,814 784,400 1,208,320 2,177,136
data Table only estimate file size before design compilation. Different configuration file formats, such Hexidecimal (.hex) Tabular Text File (.ttf) format, will have different file sizes. However, specific version Quartus® MAX+PLUS® software, designs targeted same device will have same configuration file size. following chapter describes detail configure APEX devices using supported configuration schemes. last section describes device configuration pins available. this chapter, generic term device(s) FPGA(s) will include APEX devices.
more information setting device configuration options creating configuration files, refer Software Settings, chapter volume Configuration Handbook. perform APEX configuration using Altera configuration device, intelligent host (e.g., microprocessor Altera® MAX® device), download cable.
Passive Serial Configuration
Configuration Using Configuration Device
Altera configuration device, such enhanced configuration device, EPC2, EPC1 device, configure APEX devices using serial configuration bitstream. Configuration data stored configuration device. Figure shows configuration interface connections between APEX device configuration device. figures this chapter only show configuration-related pins configuration connections between configuration device FPGA.
Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
more information enhanced configuration device flash interface pins (e.g., PGM[2.0], EXCLK, PORSEL, A[20.0], DQ[15.0]), refer Enhanced Configuration Devices (EPC4, EPC8 EPC16) Data Sheet Configuration Handbook. Figure 6-1. Single Device Configuration Using Enhanced Configuration Device
APEX Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCEO
Enhanced Configuration Device
DCLK DATA nINIT_CONF
N.C.
Notes Figure 6-1:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active, meaning external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pullup resistors, check Disable pull-ups configuration device option when generating programming files.
value internal pull-up resistors enhanced configuration devices EPC2 devices found Operating Conditions table Enhanced Configuration Devices (EPC4, EPC8, EPC16) Data Sheet Configuration Devices SRAM-based Devices Data Sheet. When using enhanced configuration devices EPC2 devices, nCONFIG FPGA connected nINIT_CONF, which allows INIT_CONF JTAG instruction initiate FPGA configuration. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor.
Altera Corporation August 2005
Configuration Handbook, Volume
Passive Serial Configuration
internal pull-up nINIT_CONF always active enhanced configuration devices EPC2 devices, which means external pullup resistor required nCONFIG tied nINIT_CONF. Upon power-up, APEX device goes through Power-On Reset (POR) approximately During POR, device resets holds nSTATUS low, tri-states user pins. configuration device also goes through delay allow power supply stabilize. time EPC2, EPC1, EPC1441 devices (maximum), enhanced configuration devices, time either depending PORSEL setting. PORSEL connected GND, delay During this time, configuration device drives low. This signal delays configuration because connected target device's nSTATUS pin. When both devices complete POR, they release their opendrain nSTATUS pin, which then pulled high pull-up resistor. Once FPGA successfully exits POR, user pins tri-stated. APEX devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Operating Conditions table APEX Programmable Logic Device Family Data Sheet. When power supplies have reached appropriate operating voltages, target FPGA senses low-to-high transition nCONFIG initiates configuration cycle. configuration cycle consists three stages: reset, configuration, initialization. While nCONFIG nSTATUS low, device reset. beginning configuration delayed holding nCONFIG nSTATUS low. VCCINT VCCIO pins banks where configuration JTAG pins reside need fully powered appropriate voltage levels begin configuration process.
When nCONFIG goes high, device comes reset releases nSTATUS pin, which pulled high pull-up resistor. Enhanced configuration EPC2 devices have optional internal pull-up pin. This option available Quartus software from General Device Options dialog box. this internal pullup resistor used, external pull-up resistor OE/nSTATUS line required. Once nSTATUS released, FPGA ready receive configuration data configuration stage begins.
Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
When nSTATUS pulled high, configuration device also goes high configuration device clocks data serially FPGA using internal oscillator. APEX device receives configuration data DATA0 clock received DCLK pin. Data latched into FPGA rising edge DCLK. After FPGA received configuration data successfully, releases open-drain CONF_DONE pin, which pulled high pull-up resistor. Since CONF_DONE tied configuration device's pin, configuration device disabled when CONF_DONE goes high. Enhanced configuration EPC2 devices have optional internal pullup resistor pin. This option available Quartus software from General Device Options dialog box. this internal pull-up used, external pull-up resistor nCS/CONF_DONE line required. low-to-high transition CONF_DONE indicates configuration complete initialization device begin. APEX devices, initialization clock source either APEX internal oscillator (typically MHz) optional CLKUSR pin. default, internal oscillator clock source initialization. internal oscillator used, APEX device will supply itself with enough clock cycles proper initialization. also have flexibility synchronize initialization multiple devices using CLKUSR option. turn Enable user-supplied start-up clock (CLKUSR) option Quartus software from General Device Options dialog box. Supplying clock CLKUSR will affect configuration process. After configuration data accepted CONF_DONE goes high, APEX devices require clock cycles properly initialize.
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Configuration Handbook, Volume
Passive Serial Configuration
optional INIT_DONE available, which signals initialization start user-mode with low-to-high transition. Enable INIT_DONE output option available Quartus software from General Device Options dialog box. INIT_DONE used, will high external pullup resistor when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE goes low. When initialization complete, INIT_DONE released pulled high. This low-to-high transition signals that FPGA entered user mode. user-mode, user pins will longer have weak pull-up resistors will function assigned your design. enhanced configuration device drives DCLK DATA high configuration. error occurs during configuration, FPGA drives nSTATUS low, resetting itself internally. Since nSTATUS tied configuration device will also reset. Auto-Restart Configuration After Error option available Quartus software from General Device Options dialog turned FPGA automatically initiates reconfiguration error occurs. APEX device will release nSTATUS after reset time-out period (maximum µs). When nSTATUS released pulled high pull-up resistor, configuration device reconfigures chain. this option turned off, external system must monitor nSTATUS errors then pulse nCONFIG least restart configuration. external system pulse nCONFIG nCONFIG under system control rather than tied VCC. addition, configuration device sends data then detects that CONF_DONE gone high, recognizes that FPGA configured successfully. Enhanced configuration devices wait DCLK cycles after last configuration sent CONF_DONE reach high state. EPC2 devices wait DCLK cycles. this case, configuration device pulls low, which turn drives target device's nSTATUS low. Auto-Restart Configuration After Error option software, target device resets then releases nSTATUS after reset time-out period (maximum µs). When nSTATUS returns high, configuration device tries reconfigure FPGA.
Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
When CONF_DONE sensed after configuration, configuration device recognizes that target device configured successfully; therefore, your system should pull CONF_DONE delay initialization. Instead, CLKUSR option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain will initialize together their CONF_DONE pins tied together. optional CLKUSR being used nCONFIG pulled restart configuration during device initialization, need ensure that CLKUSR continues toggling during time nSTATUS (maximum µs).
When FPGA user-mode, reconfiguration initiated pulling nCONFIG low. nCONFIG should least When nCONFIG pulled low, FPGA also pulls nSTATUS CONF_DONE pins tri-stated. Since CONF_DONE pulled low, this will activate configuration device since will drive low. Once nCONFIG returns logic high state nSTATUS released FPGA, reconfiguration begins. Figure shows configure multiple devices with configuration device. This circuit similar configuration device circuit single device, except APEX devices cascaded multi-device configuration.
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Configuration Handbook, Volume
Passive Serial Configuration
Figure 6-2. Multi-Device Configuration Using Enhanced Configuration Device
APEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO
APEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Enhanced Configuration Device
DCLK DATA nINIT_CONF
N.C.
nCEO
Notes Figure 6-2:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active, meaning external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files.
Enhanced configuration devices (EPC4, EPC8, EPC16) cannot cascaded.
When performing multi-device configuration, must generate configuration device's Programmer Object File (.pof) from each project's SRAM Object File (.sof). combine multiple SOFs using Quartus software.
more information create configuration files multidevice configuration chains, refer Software Settings, chapter volume Configuration Handbook.
Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
multi-device configuration, first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin configuration. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. When configuring multiple devices, configuration does begin until devices release their nSTATUS pins. Similarly, since device CONF_DONE pins tied together, devices initialize enter user mode same time. Since nSTATUS CONF_DONE pins tied together, device detects error, configuration stops entire chain entire chain must reconfigured. example, first FPGA flags error nSTATUS, resets chain pulling nSTATUS low. This signal drives enhanced configuration device drives nSTATUS FPGAs, which causes them enter reset state. This behavior similar single FPGA detecting error. Auto-Restart Configuration After Error option turned devices will automatically initiate reconfiguration error occurs. FPGAs will release their nSTATUS pins after reset time-out period (maximum µs). When nSTATUS pins released pulled high, configuration device tries reconfigure chain. Auto-Restart Configuration After Error option turned off, external system must monitor nSTATUS errors then pulse nCONFIG least restart configuration. external system pulse nCONFIG nCONFIG under system control rather than tied VCC. enhanced configuration devices also support parallel configuration eight devices. n-bit configuration mode allows enhanced configuration devices concurrently configure FPGAs chain FPGAs. addition, these devices have same device family density; they combination Altera FPGAs. individual enhanced configuration device DATA line available each targeted FPGA. Each DATA line also feed daisy chain FPGAs. Figure shows concurrently configure multiple devices using enhanced configuration device.
Altera Corporation August 2005
Configuration Handbook, Volume
Passive Serial Configuration
Figure 6-3. Concurrent Configuration Multiple Devices Using Enhanced Configuration Device
Enhanced Configuration Device DCLK DATA0 DATA1 DATA[2.6] nINIT_CONF DATA
APEX Device DCLK DATA0 nSTATUS CONF_DONE nCONFIG
N.C.
nCEO MSEL1 MSEL0
APEX Device DCLK DATA0 nSTATUS CONF_DONE nCONFIG
N.C.
nCEO MSEL1 MSEL0
APEX Device DCLK DATA0 nSTATUS CONF_DONE nCONFIG
N.C.
nCEO MSEL1 MSEL0
Notes Figure 6-3:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active, meaning external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files.
6-10 Configuration Handbook, Volume
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Configuring APEX Devices
Quartus software only allows selection n-bit configuration modes, where must However, these modes configure number devices from When configuring SRAM-based devices using n-bit modes, Table select appropriate configuration mode fastest configuration times.
Table 6-3. Recommended Configuration Using n-Bit Modes Number Devices
Note Table 6-3:
Assume that each DATA line only configuring device, daisy chain devices.
Recommended Configuration Mode
1-bit 2-bit 4-bit 4-bit 8-bit 8-bit 8-bit 8-bit
example, configure three FPGAs, would 4-bit mode. DATA0, DATA1, DATA2 lines, corresponding data transmitted from configuration device FPGA. DATA3, leave corresponding Bit3 line blank Quartus software. printed circuit board (PCB), leave DATA3 line from enhanced configuration device unconnected. Figure shows Quartus Convert Programming Files window (Tools menu) setup this scheme.
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Passive Serial Configuration
Figure 6-4. Software Settings Configuring Devices Using n-Bit Modes
Alternatively, daisy chain FPGAs DATA line while other DATA lines drive device each. example, could 2bit mode drive FPGAs with DATA Bit0 (EP2A15 EP2A25 devices) third device (the EP2A40 device) with DATA Bit1. This 2-bit configuration scheme requires less space configuration flash memory, increase total system configuration time. Figure 6-5.
6-12 Configuration Handbook, Volume
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Configuring APEX Devices
Figure 6-5. Software Settings Daisy Chaining FPGAs DATA Line
your system, have multiple devices that contain same configuration data. support this configuration scheme, device inputs tied GND, while nCEO pins left floating. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. Devices must same density package. devices will start complete configuration same time. Figure shows multi-device configuration when APEX devices receiving same configuration data.
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6-13 Configuration Handbook, Volume
Passive Serial Configuration
Figure 6-6. Multiple-Device Configuration Using Enhanced Configuration Device When FPGAs Receive Same Data
APEX Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Enhanced Configuration Device
DCLK DATA0 nINIT_CONF
N.C.
nCEO MSEL1 MSEL0
APEX Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
N.C.
nCEO MSEL1 MSEL0
APEX Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
N.C.
nCEO MSEL1 MSEL0
Notes Figure 6-6:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active, meaning external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files. nCEO pins devices left unconnected when configuring same configuration data into multiple devices.
6-14 Configuration Handbook, Volume
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Configuring APEX Devices
cascade several EPC2 EPC1 devices configure multiple APEX devices. first configuration device chain master configuration device, while subsequent devices slave devices. master configuration device sends DCLK APEX devices slave configuration devices. first device's connected CONF_DONE pins FPGAs, while nCASC connected next configuration device chain. last device's input comes from previous device, while nCASC left floating. When data from first configuration device sent, drives nCASC low, which turn drives next configuration device. Because configuration device requires less than clock cycle activate subsequent configuration device, data stream uninterrupted. Enhanced configuration devices EPC4, EPC8, EPC16 cannot cascaded.
Since nSTATUS CONF_DONE pins tied together, device detects error, master configuration device stops configuration entire chain entire chain must reconfigured. example, master configuration device does detect CONF_DONE going high configuration, resets entire chain pulling low. This signal drives slave configuration device(s) drives nSTATUS FPGAs, causing them enter reset state. This behavior similar FPGA detecting error configuration data. Figure shows configure multiple devices using cascaded EPC2 EPC1 devices.
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6-15 Configuration Handbook, Volume
Passive Serial Configuration
Figure 6-7. Multi-Device Configuration Using Cascaded EPC2 EPC1 Devices
APEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO
APEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
EPC2/EPC1 Device
DCLK DATA nCASC nINIT_CONF
EPC2/EPC1 Device
DCLK DATA nINIT_CONF
N.C.
nCEO
Notes Figure 6-7:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active, meaning external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files.
When using enhanced configuration devices EPC2 devices, nCONFIG FPGA connected nINIT_CONF, which allows INIT_CONF JTAG instruction initiate FPGA configuration. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. internal pull-up resistor nINIT_CONF always active enhanced configuration devices EPC2 devices, which means external pull-up required nCONFIG tied nINIT_CONF. multiple EPC2 devices used configure APEX device(s), only first EPC2 nINIT_CONF tied device's nCONFIG pin. single configuration chain configure APEX devices with other Altera devices. ensure that devices chain complete configuration same time that error flagged device initiates reconfiguration devices, device CONF_DONE nSTATUS pins must tied together.
6-16 Configuration Handbook, Volume
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Configuring APEX Devices
more information configuring multiple Altera devices same configuration chain, refer Configuring Mixed Altera FPGA Chains chapter volume Configuration Handbook. Figure shows timing waveform configuration scheme using configuration device.
Figure 6-8. APEX Configuration Using Configuration Device Timing Waveform
nINIT_CONF VCC/nCONFIG OE/nSTATUS nCS/CONF_DONE tDSU DCLK DATA User INIT_DONE tOEZX tPOR
Tri-State
Tri-State
User Mode
Note Figure 6-8:
APEX devices enter user-mode clock cycles after CONF_DONE goes high. initialization clock come from APEX internal oscillator CLKUSR pin.
timing information, refer Enhanced Configuration Devices (EPC4, EPC8, EPC16) Data Sheet Configuration Devices SRAM-based Devices Data Sheet Configuration Handbook. Device configuration options create configuration files discussed further Section Software Settings, chapter volume Configuration Handbook.
Configuration Using Microprocessor
configuration scheme, intelligent host (e.g., microprocessor CPLD) transfer configuration data from storage device (e.g., flash memory) target APEX devices. Configuration data stored RBF, HEX, format. Figure shows configuration interface connections between APEX device microprocessor single device configuration.
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6-17 Configuration Handbook, Volume
Passive Serial Configuration
Figure 6-9. Single Device Configuration Using Microprocessor
Memory
ADDR DATA0
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0 N.C.
Microprocessor
DATA0 nCONFIG DCLK
Note Figure 6-9:
Connect pull-up resistor supply that provides acceptable input signal device.
Upon power-up, APEX device goes through approximately During POR, device resets holds nSTATUS low, tri-states user pins. Once FPGA successfully exits POR, user pins tri-stated. APEX devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Operating Conditions table APEX Programmable Logic Device Family Data Sheet. configuration cycle consists three stages: reset, configuration, initialization. While nCONFIG nSTATUS low, device reset. initiate configuration, microprocessor must generate low-to-high transition nCONFIG pin. VCCINT VCCIO pins banks where configuration JTAG pins reside need fully powered appropriate voltage levels order begin configuration process.
When nCONFIG goes high, device comes reset releases open-drain nSTATUS pin, which then pulled high external pull-up resistor. Once nSTATUS released, FPGA ready receive configuration data configuration stage begins. When nSTATUS pulled high, microprocessor should place configuration data time DATA0 pin. least significant (LSB) each data byte must sent first.
6-18 Configuration Handbook, Volume
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Configuring APEX Devices
APEX device receives configuration data DATA0 clock received DCLK pin. Data latched into FPGA rising edge DCLK. Data continuously clocked into target device until CONF_DONE goes high. After FPGA received configuration data successfully, releases open-drain CONF_DONE pin, which pulled high external pull-up resistor. low-tohigh transition CONF_DONE indicates configuration complete initialization device begin. APEX devices, initialization clock source either APEX internal oscillator (typically MHz) optional CLKUSR pin. default, internal oscillator clock source initialization. internal oscillator used, APEX device will take care provide itself with enough clock cycles proper initialization. Therefore, internal oscillator initialization clock source, sending entire configuration file device sufficient configure initialize device. Driving DCLK device after configuration complete does affect device operation. also have flexibility synchronize initialization multiple devices using CLKUSR option. Enable user-supplied start-up clock (CLKUSR) option turned Quartus software from General Device Options dialog box. Supplying clock CLKUSR will affect configuration process. After configuration data been accepted CONF_DONE goes high, APEX devices require clock cycles initialize properly. optional INIT_DONE available, which signals initialization start user-mode with low-to-high transition. Enable INIT_DONE output option available Quartus software from General Device Options dialog box. INIT_DONE used will high external pull-up when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE will low. When initialization complete, INIT_DONE will released pulled high. microprocessor must able detect this low-tohigh transition which signals FPGA entered user mode. usermode, user pins will longer have weak pull-up resistors will function assigned your design. ensure DCLK DATA left floating configuration, microprocessor must drive them either high low, whichever convenient your board.
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6-19 Configuration Handbook, Volume
Passive Serial Configuration
Handshaking signals used configuration mode. Therefore, configuration clock (DCLK) speed must below specified frequency ensure correct configuration. maximum DCLK period exists, which means pause configuration halting DCLK indefinite amount time. error occurs during configuration, FPGA drives nSTATUS low, resetting itself internally. signal nSTATUS also alerts microprocessor that there error. Auto-Restart Configuration After Error option (available Quartus software from General Device Options dialog box) turned APEX device releases nSTATUS after reset time-out period (maximum µs). After nSTATUS released pulled high pull-up resistor, microprocessor reconfigure target device without needing pulse nCONFIG low. this option turned off, microprocessor must generate low-to-high transition (with pulse least nCONFIG restart configuration process. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. CONF_DONE must monitored microprocessor detect errors determine when programming completes. microprocessor sends configuration data CONF_DONE INIT_DONE have gone high, microprocessor must reconfigure target device. optional CLKUSR being used nCONFIG pulled restart configuration during device initialization, need ensure that CLKUSR continues toggling during time nSTATUS (maximum µs).
When FPGA user-mode, initiate reconfiguration transitioning nCONFIG low-to-high. nCONFIG must least When nCONFIG pulled low, FPGA also pulls nSTATUS CONF_DONE pins tri-stated. Once nCONFIG returns logic high state nSTATUS released FPGA, reconfiguration begins. Figure 6-10 shows configure multiple devices using microprocessor. This circuit similar configuration circuit single device, except APEX devices cascaded multi-device configuration.
6-20 Configuration Handbook, Volume
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Configuring APEX Devices
Figure 6-10. Multi-Device Configuration Using Microprocessor
Memory
ADDR DATA0
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO N.C. MSEL0
Microprocessor
DATA0 nCONFIG DCLK DATA0 nCONFIG DCLK
Note Figure 6-10:
pull-up resistor should connected supply that provides acceptable input signal devices chain.
multi-device configuration first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin configuration. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. Since nSTATUS CONF_DONE pins tied together, device detects error, configuration stops entire chain entire chain must reconfigured. example, first FPGA flags error nSTATUS, resets chain pulling nSTATUS low. This behavior similar single FPGA detecting error.
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6-21 Configuration Handbook, Volume
Passive Serial Configuration
Auto-Restart Configuration After Error option turned FPGAs release their nSTATUS pins after reset time-out period (maximum µs). After nSTATUS pins released pulled high, microprocessor reconfigure chain without needing pulse nCONFIG low. this option turned off, microprocessor must generate low-to-high transition (with pulse least nCONFIG restart configuration process. your system, have multiple devices that contain same configuration data. support this configuration scheme, device inputs tied GND, while nCEO pins left floating. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. Devices must same density package. devices will start complete configuration same time. Figure 6-11 shows multi-device configuration when both APEX devices receiving same configuration data. Figure 6-11. Multiple-Device Configuration Using Microprocessor When Both FPGAs Receive Same Data
Memory
ADDR DATA0
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0 N.C. DATA0 nCONFIG DCLK
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO DATA0 nCONFIG DCLK N.C. MSEL0
Microprocessor
Notes Figure 6-11:
pull-up resistor should connected supply that provides acceptable input signal devices chain. nCEO pins both devices left unconnected when configuring same configuration data into multiple devices.
6-22 Configuration Handbook, Volume
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Configuring APEX Devices
single configuration chain configure APEX devices with other Altera devices. ensure that devices chain complete configuration same time that error flagged device initiates reconfiguration devices, device CONF_DONE nSTATUS pins must tied together.
more information configuring multiple Altera devices same configuration chain, refer Configuring Mixed Altera FPGA Chains chapter volume Configuration Handbook. Figure 6-12 shows timing waveform configuration APEX devices using microprocessor.
Figure 6-12. APEX Configuration Using Microprocessor Timing Waveform
tCF2ST1 tCFG nCONFIG tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD tST2CK
CONF_DONE
DCLK DATA tDSU User INIT_DONE High-Z
User Mode
tCD2UM
Notes Figure 6-12:
Upon power-up, APEX device holds nSTATUS more than after reaches minimum requirement. Upon power-up, before during configuration, CONF_DONE low. DATA0 DCLK should left floating after configuration. should driven high low, whichever more convenient.
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6-23 Configuration Handbook, Volume
Passive Serial Configuration
Table defines timing parameters APEX devices configuration.
Table 6-4. Timing Parameters APEX Devices Note Symbol
tCF2CD tCF2ST0 tCFG tSTATUS tCF2ST1 tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG pulse width nSTATUS pulse width nCONFIG high nSTATUS high nCONFIG high first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
Notes Table 6-4:
This information preliminary. This value applicable users delay configuration extending nSTATUS pulse width. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period APEX devices obtain this value.
Device configuration options create configuration files discussed further Software Settings, chapters volume Configuration Handbook.
Configuring Using MicroBlaster Driver
MicroBlastersoftware driver allows configure Altera's FPGAs through ByteBlasterMV cable mode. MicroBlaster software driver supports programming input file targeted embedded passive serial configuration. source code developed Windows operating system, although customize other operating systems. more information MicroBlaster software driver, Altera site http://www.altera.com).
6-24 Configuration Handbook, Volume
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Configuring APEX Devices
Configuration Using Download Cable
this section, generic term "download cable" includes Altera Blaster universal serial (USB) port download cable, MasterBlasterserial/USB communications cable, ByteBlasterII parallel port download cable, ByteBlasterMVparallel port download cable. configuration with download cable, intelligent host (e.g., transfers data from storage device FPGA Blaster, MasterBlaster, ByteBlaster ByteBlasterMV cable. Upon power-up, APEX device goes through approximately During POR, device resets holds nSTATUS low, tri-states user pins. Once FPGA successfully exits POR, user pins tri-stated. APEX devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Operating Conditions table APEX Programmable Logic Device Family Data Sheet. configuration cycle consists stages: reset, configuration initialization. While nCONFIG nSTATUS low, device reset. initiate configuration this scheme, download cable generates low-to-high transition nCONFIG pin. VCCINT VCCIO pins banks where configuration, JTAG pins reside need fully powered appropriate voltage levels order begin configuration process.
When nCONFIG goes high, device comes reset releases open-drain nSTATUS pin, which then pulled high external pull-up resistor. Once nSTATUS released FPGA ready receive configuration data configuration stage begins. programming hardware download cable then places configuration data time device's DATA0 pin. configuration data clocked into target device until CONF_DONE goes high. When using download cable, setting Auto-Restart Configuration After Error option does affect configuration cycle because must manually restart configuration Quartus software when error occurs. Additionally, Enable user-supplied start-up clock (CLKUSR) option affect device initialization since this option disabled when programming FPGA using Quartus programmer download cable. Therefore, turn CLKUSR
Altera Corporation August 2005 6-25 Configuration Handbook, Volume
Passive Serial Configuration
option, need provide clock CLKUSR when configuring FPGA with Quartus programmer download cable. Figure 6-13 shows configuration APEX devices using Blaster, MasterBlaster, ByteBlaster ByteBlasterMV cable. Figure 6-13. Configuration Using Blaster, MasterBlaster, ByteBlaster ByteBlasterMV Cable
APEX Device
MSEL0 MSEL1 CONF_DONE nSTATUS
nCEO
N.C.
DCLK DATA0 nCONFIG
Download Cable 10-Pin Male Header Mode)
Shield
Notes Figure 6-13:
pull-up resistor should connected same supply voltage Blaster, MasterBlaster (VIO pin), ByteBlaster ByteBlasterMV cable. pull-up resistors DATA0 DCLK only needed download cable only configuration scheme used your board. This ensure that DATA0 DCLK left floating after configuration. example, also using configuration device, pull-up resistors DATA0 DCLK needed. header reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlasterMV, this connect. Blaster ByteBlaster this connected when used Active Serial programming, otherwise connect.
download cable configure multiple APEX devices connecting each device's nCEO subsequent device's pin. first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. other configuration pins, nCONFIG, nSTATUS, DCLK, DATA0, CONF_DONE connected every device chain. Because CONF_DONE pins tied together, devices chain initialize enter user mode same time.
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Configuring APEX Devices
addition, because nSTATUS pins tied together, entire chain halts configuration device detects error. Auto-Restart Configuration After Error option does affect configuration cycle because must manually restart configuration Quartus software when error occurs. Figure 6-14 shows configure multiple APEX devices with download cable. Figure 6-14. Multi-Device Configuration using Blaster, MasterBlaster, ByteBlaster ByteBlasterMV Cable
Download Cable 10-Pin Male Header Mode)
APEX Device
MSEL0
MSEL1
CONF_DONE nSTATUS DCLK
nCEO
DATA0 nCONFIG
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
N.C.
DATA0 nCONFIG
APEX Device
Notes Figure 6-14:
pull-up resistor should connected same supply voltage Blaster, MasterBlaster (VIO pin), ByteBlaster ByteBlasterMV cable. pull-up resistors DATA0 DCLK only needed download cable only configuration scheme used your board. This ensure that DATA0 DCLK left floating after configuration. example, also using configuration device, pull-up resistors DATA0 DCLK needed. header reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlasterMV, this connect. Blaster ByteBlaster this connected when used Active Serial programming, otherwise connect.
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6-27 Configuration Handbook, Volume
Passive Serial Configuration
using download cable configure device(s) board that also configuration devices, should electrically isolate configuration device from target device(s) cable. isolate configuration device logic, such multiplexer, that select between configuration device cable. multiplexer chip should allow bidirectional transfers nSTATUS CONF_DONE signals. Another option switches five common signals (nCONFIG, nSTATUS, DCLK, DATA0, CONF_DONE) between cable configuration device. last option remove configuration device from board when configuring FPGA with cable. Figure 6-15 shows combination configuration device download cable configure FPGA.
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Configuring APEX Devices
Figure 6-15. Configuration with Download Cable Configuration Device Circuit
Download Cable 10-Pin Male Header Mode)
APEX Device
MSEL0 MSEL1 DATA0 nCONFIG nCEO N.C. CONF_DONE nSTATUS DCLK
Configuration Device
DCLK DATA nINIT_CONF
Notes Figure 6-15:
pull-up resistor should connected same supply voltage configuration device. header reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlasterMV, this connect. Blaster ByteBlaster this connected when used Active Serial programming, otherwise connect. should attempt configuration with download cable while configuration device connected APEX device. Instead, should either remove configuration device from socket when using download cable place switch five common signals between download cable configuration device. nINIT_CONF (available enhanced configuration devices EPC2 devices only) internal pull-up resistor that always active. This means external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used available (e.g., EPC1 devices), nCONFIG must pulled either directly through resistor. enhanced configuration devices' EPC2 devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-up resistors configuration device option when generating programming files.
more information Blaster, MasterBlaster, ByteBlaster ByteBlasterMV cables, refer following data sheets.
Blaster Port Download Cable Data Sheet MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet
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Fast Passive Parallel Configuration
Fast Passive Parallel Configuration
Fast Passive Parallel (FPP) configuration APEX devices designed meet continuously increasing demand faster configuration times. APEX devices designed with capability receiving bytewide configuration data clock cycle, guarantee configuration time less than with 66-MHz configuration clock. configuration APEX devices performed using Altera enhanced configuration device intelligent host, such microprocessor.
Configuration Using Enhanced Configuration Device
configuration scheme, enhanced configuration device sends byte configuration data every DCLK cycle APEX device. Configuration data stored configuration device. Figure 6-16 shows configuration interface connections between APEX device enhanced configuration device single device configuration. figures this chapter only show configuration-related pins configuration connections between configuration device FPGA.
more information enhanced configuration device flash interface pins, such PGM[2.0], EXCLK, PORSEL, A[20.0], DQ[15.0], refer Enhanced Configuration Devices (EPC4, EPC8, EPC16) Data Sheet Configuration Handbook.
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Configuring APEX Devices
Figure 6-16. Single Device Configuration Using Enhanced Configuration Device
APEX Device
DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0 nCEO
Enhanced Configuration Device
DCLK DATA[7.0] nINIT_CONF
N.C.
Notes Figure 6-16:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF available enhanced configuration devices internal pull-up resistor that always active. This means external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used, nCONFIG must pulled either directly through resistor. enhanced configuration devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files.
value internal pull-up resistors enhanced configuration devices found Operating Conditions table Enhanced Configuration Devices (EPC4, EPC8, EPC16) Data Sheet Configuration Handbook. When using enhanced configuration devices, nCONFIG FPGA connected nINIT_CONF, which allows INIT_CONF JTAG instruction initiate FPGA configuration. nINIT_CONF does need connected functionality used. nINIT_CONF used, nCONFIG must pulled either directly through resistor. internal pull-up nINIT_CONF always active enhanced configuration devices, which means external pull-up required nCONFIG tied nINIT_CONF.
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6-31 Configuration Handbook, Volume
Fast Passive Parallel Configuration
Upon power-up, APEX device goes through Power-On Reset (POR) approximately During POR, device resets holds nSTATUS low, tri-states user pins. configuration device also goes through delay allow power supply stabilize. time enhanced configuration devices either depending PORSEL setting. PORSEL connected GND, delay During this time, configuration device drives low. This signal delays configuration because connected target device's nSTATUS pin. When both devices complete POR, they release their opendrain nSTATUS pin, which then pulled high pull-up resistor. Once FPGA successfully exits POR, user pins tri-stated. APEX devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Operating Conditions table APEX Programmable Logic Device Family Data Sheet. When power supplies have reached appropriate operating voltages, target FPGA senses low-to-high transition nCONFIG initiates configuration cycle. configuration cycle consists stages: reset, configuration, initialization. While nCONFIG nSTATUS low, device reset. beginning configuration delayed holding nCONFIG nSTATUS low. VCCINT VCCIO pins banks where configuration JTAG pins reside need fully powered appropriate voltage levels order begin configuration process.
When nCONFIG goes high, device comes reset releases nSTATUS pin, which pulled high pull-up resistor. Enhanced configuration devices have optional internal pull-up pin. This option available Quartus software from General Device Options dialog box. this internal pull-up used, external pull-up OE/nSTATUS line required. Once nSTATUS released FPGA ready receive configuration data configuration stage begins. When nSTATUS pulled high, configuration device also goes high configuration device clocks data serially FPGA using internal oscillator. APEX device receives configuration data DATA[7.0] pins clock received DCLK pin. byte data latched into FPGA rising edge DCLK.
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Configuring APEX Devices
After FPGA received configuration data successfully releases open-drain CONF_DONE pin, which pulled high pull-up resistor. Since CONF_DONE tied configuration device's pin, configuration device disabled when CONF_DONE goes high. Enhanced configuration devices have optional internal pull-up pin. This option available Quartus software from General Device Options dialog box. this internal pullup used, external pull-up nCS/CONF_DONE line required. high transition CONF_DONE indicates configuration complete initialization device begin. APEX devices, initialization clock source either APEX internal oscillator (typically MHz) optional CLKUSR pin. default, internal oscillator clock source initialization. internal oscillator used, APEX device will take care provide itself with enough clock cycles proper initialization. also have flexibility synchronize initialization multiple devices using CLKUSR option. Enable user-supplied start-up clock (CLKUSR) option turned Quartus software from General Device Options dialog box. Supplying clock CLKUSR will affect configuration process. After configuration data been accepted CONF_DONE goes high, APEX devices require clock cycles initialize properly. optional INIT_DONE available, which signals initialization start user-mode with low-to-high transition. Enable INIT_DONE output option available Quartus software from General Device Options dialog box. INIT_DONE used will high external pullup resistor when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE will low. When initialization complete, INIT_DONE will released pulled high. user-mode, user pins will longer have weak pull-ups will function assigned your design. enhanced configuration device will drive DCLK DATA[7.0] high configuration. error occurs during configuration, FPGA drives nSTATUS low, resetting itself internally. Since nSTATUS tied configuration device will also reset. Auto-Restart Configuration After Error option-available Quartus software from General Device Options dialog box-is turned FPGA will automatically initiate reconfiguration error occurs. APEX device will release nSTATUS after reset time-out period (maximum µs). When nSTATUS released pulled high pull-up resistor, configuration device reconfigures chain.
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6-33 Configuration Handbook, Volume
Fast Passive Parallel Configuration
this option turned off, external system must monitor nSTATUS errors then pulse nCONFIG least restart configuration. external system pulse nCONFIG, nCONFIG under system control rather than tied VCC. addition, configuration device sends data then detects that CONF_DONE gone high, recognizes that FPGA configured successfully. Enhanced configuration devices wait DCLK cycles after last configuration sent CONF_DONE reach high state. this case, configuration device pulls low, which turn drives target device's nSTATUS low. AutoRestart Configuration After Error option software, target device resets then release nSTATUS after reset time-out period (maximum µs). When nSTATUS returns high, configuration device will reconfigure FPGA. When CONF_DONE sensed after configuration, configuration device recognizes that target device configured successfully; therefore, your system should pull CONF_DONE delay initialization. Instead, should CLKUSR option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain will initialize together their CONF_DONE pins tied together. optional CLKUSR being used nCONFIG pulled restart configuration during device initialization, need ensure CLKUSR continues toggling during time nSTATUS (maximum µs). When FPGA user-mode, reconfiguration initiated pulling nCONFIG low. nCONFIG should least When nCONFIG pulled low, FPGA also pulls nSTATUS CONF_DONE pins tri-stated. Since CONF_DONE pulled low, this will activate configuration device since will drive low. Once nCONFIG returns logic high state nSTATUS released FPGA, reconfiguration begins. Figure 6-17 shows configure multiple APEX devices with enhanced configuration device. This circuit similar configuration device circuit single device, except APEX devices cascaded multi-device configuration.
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Configuring APEX Devices
Figure 6-17. Multi-Device Configuration Using Enhanced Configuration Device
APEX Device MSEL1 MSEL0 DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG
APEX Device MSEL1 MSEL0 DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG
Enhanced Configuration Device DCLK DATA[7.0] nINIT_CONF
N.C.
nCEO
nCEO
Notes Figure 6-17:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF available enhanced configuration devices internal pull-up resistor that always active. This means external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used, nCONFIG must pulled either directly through resistor. enhanced configuration devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-up resistors configuration device option when generating programming files.
Enhanced configuration devices (EPC4/8/16) cannot cascaded.
When performing multi-device configuration, must generate configuration device's from each project's SOF. combine multiple SOFs using Quartus software.
more information create configuration files multidevice configuration chains, refer Software Settings, chapter volume Configuration Handbook. multi-device configuration first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin
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Fast Passive Parallel Configuration
configuration. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7.0], CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. When configuring multiple devices, configuration does begin until devices release their nSTATUS pins. Similarly, since device CONF_DONE pins tied together, devices initialize enter user mode same time. Since nSTATUS CONF_DONE pins tied together, device detects error, configuration stops entire chain entire chain must reconfigured. example, first FPGA flags error nSTATUS, resets chain pulling nSTATUS low. This signal drives enhanced configuration device drives nSTATUS FPGAs, which causes them enter reset state. This behavior similar single FPGA detecting error. Auto-Restart Configuration After Error option turned devices will automatically initiate reconfiguration error occurs. FPGAs will release their nSTATUS pins after reset time-out period (maximum µs). When nSTATUS pins released pulled high, configuration device tries reconfigure chain. Auto-Restart Configuration After Error option turned off, external system must monitor nSTATUS errors then pulse nCONFIG least restart configuration. external system pulse nCONFIG nCONFIG under system control rather than tied VCC. your system, have multiple devices that contain same configuration data. support this configuration scheme, device inputs tied GND, while nCEO pins left floating. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7.0], CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. Devices must same density package. devices will start complete configuration same time. Figure 6-18 shows multi-device configuration when both APEX devices receiving same configuration data.
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Configuring APEX Devices
Figure 6-18. Multiple-Device Configuration Using Enhanced Configuration Device When Both FPGAs Receive Same Data
APEX Device MSEL1 MSEL0 DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG
APEX Device MSEL1 MSEL0 DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG
Enhanced Configuration Device DCLK DATA[7.0] nINIT_CONF
N.C.
nCEO
N.C.
nCEO
Notes Figure 6-18:
pull-up resistor should connected same supply voltage configuration device. nINIT_CONF available enhanced configuration devices internal pull-up resistor that always active. This means external pull-up resistor required nINIT_CONF/nCONFIG line. nINIT_CONF does need connected functionality used. nINIT_CONF used, nCONFIG must pulled either directly through resistor. enhanced configuration devices' pins have internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. internal pull-up resistors used default Quartus software. turn internal pull-up resistors, check Disable pull-ups configuration device option when generating programming files. nCEO pins both devices left unconnected when configuring same configuration data into multiple devices.
single enhanced configuration chain configure multiple APEX devices with other Altera devices that support configuration, such Stratix® Stratix devices. ensure that devices chain complete configuration same time that error flagged device initiates reconfiguration devices, device CONF_DONE nSTATUS pins must tied together.
more information configuring multiple Altera devices same configuration chain, refer Configuring Mixed Altera FPGA Chains Configuration Handbook. Figure 6-19 shows timing waveform configuration scheme using enhanced configuration device.
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6-37 Configuration Handbook, Volume
Fast Passive Parallel Configuration
Figure 6-19. APEX Configuration Using Enhanced Configuration Device Timing Waveform
nINIT_CONF VCC/nCONFIG OE/nSTATUS tLOE
nCS/CONF_DONE DCLK DATA User INIT_DONE
Driven High
bit/byte bit/byte
bit/byte
Tri-State
Tri-State
User Mode
Note Figure 6-19:
APEX devices enter user mode clock cycles after CONF_DONE goes high. initialization clock come from APEX internal oscillator CLKUSR pin.
timing information, refer Enhanced Configuration Devices (EPC4, EPC8, EPC16) Data Sheet Configuration Handbook. Device configuration options create configuration files discussed further Software Settings, chapter volume Configuration Handbook.
Configuration Using Microprocessor
configuration scheme, intelligent host, such microprocessor CPLD, transfer configuration data from storage device, such flash memory, target APEX device. Configuration data stored RBF, format. Figure 6-20 shows configuration interface connections between APEX device microprocessor single device configuration.
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Configuring APEX Devices
Figure 6-20. Single Device Configuration Using Microprocessor
Memory
ADDR DATA[7.0]
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
N.C.
Microprocessor
DATA[7.0] nCONFIG DCLK
Note Figure 6-20:
pull-up resistor should connected supply that provides acceptable input signal device.
Upon power-up, APEX device goes through Power-On Reset (POR) approximately During POR, device resets holds nSTATUS low, tri-states user pins. Once FPGA successfully exits POR, user pins tri-stated. APEX devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Operating Conditions table APEX Programmable Logic Device Family Data Sheet. configuration cycle consists three stages: reset, configuration initialization. While nCONFIG nSTATUS low, device reset. initiate configuration, microprocessor must generate low-to-high transition nCONFIG pin. VCCINT VCCIO pins banks where configuration, JTAG pins reside need fully powered appropriate voltage levels order begin configuration process.
When nCONFIG goes high, device comes reset releases open-drain nSTATUS pin, which then pulled high external pull-up resistor. Once nSTATUS released, FPGA ready receive configuration data configuration stage begins. When nSTATUS pulled high, microprocessor should place configuration data byte time DATA[7.0] pins.
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6-39 Configuration Handbook, Volume
Fast Passive Parallel Configuration
APEX device receives configuration data DATA[7.0] pins clock received DCLK pin. Data latched into FPGA rising edge DCLK. Data continuously clocked into target device until CONF_DONE goes high. After FPGA received configuration data successfully, releases open-drain CONF_DONE pin, which pulled high external pull-up resistor. low-tohigh transition CONF_DONE indicates configuration complete initialization device begin. APEX devices, initialization clock source either APEX internal oscillator (typically MHz) optional CLKUSR pin. default, internal oscillator clock source initialization. internal oscillator used, APEX device will take care provide itself with enough clock cycles proper initialization. Therefore, internal oscillator initialization clock source, sending entire configuration file device sufficient configure initialize device. Driving DCLK device after configuration complete does affect device operation. also have flexibility synchronize initialization multiple devices using CLKUSR option. Enable user-supplied start-up clock (CLKUSR) option turned Quartus software from General Device Options dialog box. Supplying clock CLKUSR will affect configuration process. After configuration data been accepted CONF_DONE goes high, APEX devices require clock cycles initialize properly. optional INIT_DONE available, which signals initialization start user-mode with low-to-high transition. This Enable INIT_DONE output option available Quartus software from General Device Options dialog box. INIT_DONE used will high external pullup resistor when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE will low. When initialization complete, INIT_DONE will released pulled high. microprocessor must able detect this low-to-high transition which signals FPGA entered user mode. user-mode, user pins will longer have weak pull-ups will function assigned your design. When initialization complete, FPGA enters user mode.
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Configuring APEX Devices
ensure DCLK DATA0 left floating configuration, microprocessor must take care drive them either high low, whichever convenient your board. DATA[7.1] pins available user pins after configuration. When scheme chosen Quartus software, default these pins tri-stated user mode should driven microprocessor. change this default option Quartus software, select DualPurpose Pins Device Options dialog box. Handshaking signals used configuration mode. Therefore, configuration clock (DCLK) speed must below specified frequency ensure correct configuration. maximum DCLK period exists, which means pause configuration halting DCLK indefinite amount time. error occurs during configuration, FPGA drives nSTATUS low, resetting itself internally. signal nSTATUS also alerts microprocessor that there error. Auto-Restart Configuration After Error option-available Quartus software from General Device Options dialog box-is turned FPGA releases nSTATUS after reset time-out period (maximum µs). After nSTATUS released pulled high pull-up resistor, microprocessor reconfigure target device without needing pulse nCONFIG low. this option turned off, microprocessor must generate low-to-high transition (with pulse least nCONFIG restart configuration process. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. CONF_DONE must monitored microprocessor detect errors determine when programming completes. microprocessor sends configuration data CONF_DONE INIT_DONE have gone high, microprocessor must reconfigure target device. optional CLKUSR being used nCONFIG pulled restart configuration during device initialization, need ensure CLKUSR continues toggling during time nSTATUS (maximum µs).
When FPGA user-mode, reconfiguration initiated transitioning nCONFIG low-to-high. nCONFIG should least When nCONFIG pulled low, FPGA also pulls nSTATUS CONF_DONE pins tri-stated. Once nCONFIG returns logic high state nSTATUS released FPGA, reconfiguration begins.
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Fast Passive Parallel Configuration
Figure 6-21 shows configure multiple devices using microprocessor. This circuit similar configuration circuit single device, except APEX devices cascaded multi-device configuration. Figure 6-21. Multi-Device Configuration Using Microprocessor
Memory
ADDR DATA[7.0]
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX Device
MSEL1 CONF_DONE MSEL0
nSTATUS nCEO
N.C.
Microprocessor
DATA[7.0] nCONFIG DCLK DATA[7.0] nCONFIG DCLK
Note Figure 6-21:
pull-up resistor should connected supply that provides acceptable input signal devices chain.
multi-device configuration first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin configuration. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7.0], CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. Because device CONF_DONE pins tied together, devices initialize enter user mode same time.
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Configuring APEX Devices
Since nSTATUS CONF_DONE pins tied together, device detects error, configuration stops entire chain entire chain must reconfigured. example, first FPGA flags error nSTATUS, resets chain pulling nSTATUS low. This behavior similar single FPGA detecting error. Auto-Restart Configuration After Error option turned FPGAs release their nSTATUS pins after reset time-out period (maximum µs). After nSTATUS pins released pulled high, microprocessor reconfigure chain without needing pulse nCONFIG low. this option turned off, microprocessor must generate low-to-high transition (with pulse least nCONFIG restart configuration process. your system, have multiple devices that contain same configuration data. support this configuration scheme, device inputs tied GND, while nCEO pins left floating. other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7.0], CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DCLK DATA lines buffered every fourth device. Devices must same density package. devices will start complete configuration same time. Figure 6-22 shows multi-device configuration when both APEX devices receiving same configuration data.
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Fast Passive Parallel Configuration
Figure 6-22. Multiple-Device Configuration Using Microprocessor When Both FPGAs Receive Same Data
Memory
ADDR DATA[7.0]
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX Device
MSEL1 CONF_DONE MSEL0
N.C.
nSTATUS nCEO
N.C.
Microprocessor
DATA[7.0] nCONFIG DCLK
DATA[7.0] nCONFIG DCLK
Notes Figure 6-22:
pull-up resistor should connected supply that provides acceptable input signal devices chain. nCEO pins both devices left unconnected when configuring same configuration data into multiple devices.
single configuration chain configure APEX devices with other Altera devices that support configuration, such Stratix. ensure that devices chain complete configuration same time that error flagged device initiates reconfiguration devices, device CONF_DONE nSTATUS pins must tied together.
more information configuring multiple Altera devices same configuration chain, refer Configuring Mixed Altera FPGA Chains Configuration Handbook. Figure 6-23 shows timing waveform configuration scheme using microprocessor.
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Configuring APEX Devices
Figure 6-23. APEX Configuration Using Microprocessor Timing Waveform
tCF2ST1 tCFG nCONFIG tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD tST2CK
CONF_DONE
Byte
DCLK DATA
Byte Byte Byte Byte
User Mode
tDSU User INIT_DONE High-Z User Mode
tCD2UM
Notes Figure 6-23:
Upon power-up, APEX device holds nSTATUS more than after reaches minimum requirement. Upon power-up, before during configuration, CONF_DONE low. DATA0 DCLK should left floating after configuration. should driven high low, whichever more convenient. DATA[7.1] available user pins after configuration state theses pins depends design programmed into device.
Table defines timing parameters APEX devices configuration.
Table 6-5. Timing Parameters APEX Devices (Part Symbol
tCF2CD tCF2ST0 tCFG tSTATUS tCF2ST1 tCF2CK tST2CK tDSU
Note
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG pulse width nSTATUS pulse width nCONFIG high nSTATUS high nCONFIG high first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK
Units
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Passive Parallel Asynchronous Configuration
Table 6-5. Timing Parameters APEX Devices (Part Symbol
tCLK fMAX tCD2UM
Note
Parameter
DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode
Units
Notes Table 6-5:
This information preliminary. This value obtainable users delay configuration extending nCONFIG nSTATUS pulse width. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period obtain this value.
Device configuration options create configuration files discussed further Software Settings, chapter volume Configuration Handbook.
Configuring Using MicroBlaster Driver
MicroBlastersoftware driver supports programming input file targeted embedded fast passive parallel configuration. source code developed Windows operating system, although customize other operating systems. more information MicroBlaster software driver, Altera site (http://www.altera.com).
Passive Parallel Asynchronous Configuration
Passive Parallel Asynchronous (PPA) configuration uses intelligent host, such microprocessor, transfer configuration data from storage device, such flash memory, target APEX device. Configuration data stored TTF, format. host system outputs byte-wide data accompanying strobe signals FPGA. When using PPA, should pull DCLK high through pull-up resistor prevent unused configuration input pins from floating. Figure 6-24 shows configuration interface connections between FPGA microprocessor single device configuration. microprocessor optional address decoder control device's chip select pins, address decoder allows microprocessor select APEX device accessing particular address, which simplifies configuration process. pins must held active during configuration initialization.
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Configuring APEX Devices
Figure 6-24. Single Device Configuration Using Microprocessor Note
Address Decoder ADDR
Memory
ADDR DATA[7.0]
APEX Device CONF_DONE nSTATUS MSEL1 MSEL0
nCEO
N.C.
Microprocessor
DATA[7.0] nCONFIG RDYnBSY
DCLK
Notes Figure 6-24:
used, connected directly. used, connected directly. pull-up resistor should connected supply that provides acceptable input signal device.
During configuration, only required either pin. Therefore, only chip-select input used, other must tied active state. example, tied ground while toggled control configuration. device's pins toggled during configuration design meets specifications tCSSU, tWSP, tCSH listed Table 6-6. Upon power-up, APEX device goes through Power-On Reset (POR) approximately During POR, device resets holds nSTATUS low, tri-states user pins. Once FPGA successfully exits POR, user pins tri-stated. APEX devices have weak pull-up resistors user pins which before during configuration.
value weak pull-up resistors pins that before during configuration found Operating Conditions table APEX Programmable Logic Device Family Data Sheet.
Altera Corporation August 2005
6-47 Configuration Handbook, Volume
Passive Parallel Asynchronous Configuration
configuration cycle consists three stages: reset, configuration initialization. While nCONFIG nSTATUS low, device reset. initiate configuration, microprocessor must generate low-to-high transition nCONFIG pin. VCCINT VCCIO pins banks where configuration JTAG pins reside need fully powered appropriate voltage levels order begin configuration process.
When nCONFIG goes high, device comes reset releases open-drain nSTATUS pin, which then pulled high external pull-up resistor. Once nSTATUS released FPGA ready receive configuration data configuration stage begins. When nSTATUS pulled high, microprocessor should then assert target device's and/or high. Next, microprocessor places 8-bit configuration word (one byte) target device's DATA[7.0] pins pulses low. rising edge nWS, target device latches byte configuration data drives RDYnBSY signal low, which indicates processing byte configuration data. microprocessor then perform other system functions while APEX device processing byte configuration data. During time RDYnBSY low, APEX device internally processes configuration data using internal oscillator (typically MHz). When device ready next byte configuration data, will drive RDYnBSY high. microprocessor senses high signal when polls RDYnBSY, microprocessor sends next byte configuration data FPGA. Alternatively, signal strobed low, causing RDYnBSY signal appear DATA7. Because RDYnBSY does need monitored, this doesn't need connected microprocessor. Data should driven onto data while because will cause contention DATA7 pin. used monitor configuration, should tied high. simplify configuration save port, microprocessor wait total time tBUSY(max) tRDY2WS tW2SB before sending next data byte. this set-up, should tied high RDYnBSY does need connected microprocessor. tBUSY, tRDY2WS tW2SB timing specifications listed Table 6-6.
6-48 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Next, microprocessor checks nSTATUS CONF_DONE. nSTATUS CONF_DONE high, microprocessor sends next data byte. However, nSTATUS configuration data been received, device ready initialization. After FPGA received configuration data successfully, releases open-drain CONF_DONE pin, which pulled high external pull-up resistor. low-to-high transition CONF_DONE indicates configuration complete initialization device begin. APEX devices, initialization clock source either APEX internal oscillator (typically MHz) optional CLKUSR pin. default, internal oscillator clock source initialization. internal oscillator used, APEX device will take care provide itself with enough clock cycles proper initialization. Therefore, internal oscillator initialization clock source, sending entire configuration file device sufficient configure initialize device. also have flexibility synchronize initialization multiple devices using CLKUSR option. Enable user-supplied start-up clock (CLKUSR) option turned Quartus software from General Device Options dialog box. Supplying clock CLKUSR will affect configuration process. After configuration data been accepted CONF_DONE goes high, APEX devices require clock cycles initialize properly. optional INIT_DONE available, which signals initialization start user-mode with low-to-high transition. This Enable INIT_DONE output option available Quartus software from General Device Options dialog box. INIT_DONE used will high external pullup when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE will low. When initialization complete, INIT_DONE will released pulled high. microprocessor must able detect this low-tohigh transition which signals FPGA entered user mode. usermode, user pins will longer have weak pull-ups will function assigned your design. When initialization complete, FPGA enters user mode. ensure DATA0 left floating configuration, microprocessor must take care drive them either high low, whichever convenient your board. After configuration, nCS, nRS, nWS, RDYnBSY, DATA[7.1] pins used user pins. When scheme chosen Quartus software, default
Altera Corporation August 2005
6-49 Configuration Handbook, Volume
Passive Parallel Asynchronous Configuration
these pins tri-stated user mode should driven microprocessor. change this default option Quartus software, select Dual-Purpose Pins Device Options dialog box. error occurs during configuration, FPGA drives nSTATUS low, resetting itself internally. signal nSTATUS also alerts microprocessor that there error. Auto-Restart Configuration After Error option-available Quartus software from General Device Options dialog box-is turned FPGA releases nSTATUS after reset time-out period (maximum µs). After nSTATUS released pulled high pull-up resistor, microprocessor reconfigure target device without needing pulse nCONFIG low. this option turned off, microprocessor must generate low-to-high transition (with pulse least nCONFIG restart configuration process. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. CONF_DONE must monitored microprocessor detect errors determine when programming completes. microprocessor sends configuration data CONF_DONE INIT_DONE gone high, microprocessor must reconfigure target device. optional CLKUSR being used nCONFIG pulled restart configuration during device initialization, need ensure CLKUSR continues toggling during time nSTATUS (maximum µs).
When FPGA user-mode, reconfiguration initiated transitioning nCONFIG low-to-high. nCONFIG should least When nCONFIG pulled low, FPGA also pulls nSTATUS CONF_DONE pins tri-stated. Once nCONFIG returns logic high state nSTATUS released FPGA, reconfiguration begins. Figure 6-25 shows configure multiple APEX devices using microprocessor. This circuit similar configuration circuit single device, except devices cascaded multi-device configuration.
6-50 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Figure 6-25. Multi-Device Configuration Using Microprocessor
Address Decoder ADDR Memory
ADDR DATA[7.0]
APEX Device DATA[7.0] CONF_DONE nSTATUS Microprocessor nCONFIG RDYnBSY
DCLK
APEX Device DATA[7.0] DCLK CONF_DONE nSTATUS nCEO N.C. MSEL1 nCONFIG MSEL0 RDYnBSY
nCEO
MSEL1 MSEL0
Notes Figure 6-25:
used, connected directly. used, connected directly. pull-up resistor should connected supply that provides acceptable input signal devices chain.
multi-device configuration first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin configuration. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. Each device's RDYnBSY have separate input microprocessor. Alternatively, microprocessor limited, RDYnBSY pins feed gate output gate feed microprocessor. example, have devices configuration chain, second device's RDYnBSY will high during time that first device being configured. When first device
Altera Corporation August 2005
6-51 Configuration Handbook, Volume
Passive Parallel Asynchronous Configuration
been successfully configured, will driven nCEO activate next device chain drive RDYnBSY high. Therefore, since RDYnBSY signal driven high before configuration after configuration before entering user-mode, device being configured will govern output gate. signal used multi-device chain since APEX device will tri-state DATA[7.0] pins before configuration after configuration before entering user-mode avoid contention. Therefore, only device that currently being configured will respond strobe asserting DATA7. other configuration pins (nCONFIG, nSTATUS, DATA[7.0], nCS, nWS, CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DATA lines buffered every fourth device. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. Since nSTATUS CONF_DONE pins tied together, device detects error, configuration stops entire chain entire chain must reconfigured. example, first FPGA flags error nSTATUS, resets chain pulling nSTATUS low. This behavior similar single FPGA detecting error. Auto-Restart Configuration After Error option turned FPGAs release their nSTATUS pins after reset time-out period (maximum µs). After nSTATUS pins released pulled high, microprocessor reconfigure chain without needing pulse nCONFIG low. this option turned off, microprocessor must generate low-to-high transition (with pulse least nCONFIG restart configuration process. your system, have multiple devices that contain same configuration data. support this configuration scheme, device inputs tied GND, while nCEO pins left floating. other configuration pins (nCONFIG, nSTATUS, DATA[7.1], nCS, nWS, CONF_DONE) connected every device chain. should special attention configuration signals because they require buffering ensure signal integrity prevent clock skew problems. Specifically, ensure that DATA lines buffered every fourth device. Devices must same density package. devices will start complete configuration same time. Figure 6-26 shows multi-device configuration when both devices receiving same configuration data.
6-52 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Figure 6-26. Multiple-Device Configuration Using Microprocessor When Both FPGAs Receive Same Data
Address Decoder ADDR Memory
ADDR DATA[7.0]
APEX Device DATA[7.0] CONF_DONE nSTATUS Microprocessor nCONFIG RDYnBSY
DCLK
APEX Device DATA[7.0] DCLK CONF_DONE nSTATUS nCEO N.C. MSEL1 nCONFIG MSEL0 RDYnBSY
nCEO
N.C.
MSEL1 MSEL0
Notes Figure 6-26:
used, connected directly. used, connected directly. pull-up resistor should connected supply that provides acceptable input signal devices chain. nCEO pins both devices left unconnected when configuring same configuration data into multiple devices.
single configuration chain configure APEX devices with other Altera devices that support configuration, such Stratix, Mercury, APEX 20K, ACEX FLEX 10KE devices. ensure that devices chain complete configuration same time that error flagged device initiates reconfiguration devices, device CONF_DONE nSTATUS pins must tied together.
more information configuring multiple Altera devices same configuration chain, refer Configuring Mixed Altera FPGA Chains Configuration Handbook. Figure 6-27 shows timing waveform configuration scheme using microprocessor.
Altera Corporation August 2005
6-53 Configuration Handbook, Volume
Passive Parallel Asynchronous Configuration
Figure 6-27. APEX Configuration Timing Waveform
tCFG tCF2ST1
nCONFIG nSTATUS CONF_DONE DATA[7.0] Byte
tDSU
Byte
Byte
Byte
tCSSU tCSH
tCF2WS
tWSP
tRDY2WS
RDYnBSY
tSTATUS tCF2ST0 tCF2CD tWS2B tBUSY
tCD2UM
User I/Os INIT_DONE
High-Z
High-Z
User-Mode
Notes Figure 6-27:
Upon power-up, APEX device holds nSTATUS more than after VCCINT reaches minimum requirement. Upon power-up, before during configuration, CONF_DONE low. user toggle during configuration design meets specification tCSSU, tWSP, tCSH. DATA0 should left floating after configuration. should driven high low, whichever more convenient. DATA[7.1], nCS, nWS, RDYnBSY available user pins after configuration state theses pins depends dual-purpose settings.
Figure 6-28 shows timing waveform configuration scheme when using strobed signal.
6-54 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Figure 6-28. APEX Configuration Timing Waveform Using
tCF2ST1 tCFG
nCONFIG nSTATUS
tCF2SCD tSTATUS
CONF_DONE
tCSSU
tCSH
DATA[7.0]
tWSP tRS2WS
Byte
tDSU
Byte
Byte
INIT_DONE User DATA7/RDYnBSY
tWS2RS tCF2WS tRSD7
tWS2RS tRDY2WS
High-Z tWS2B
User-Mode
tCD2UM tBUSY
Notes Figure 6-28:
Upon power-up, APEX device holds nSTATUS more than after VCCINT reaches minimum requirement. Upon power-up, before during configuration, CONF_DONE low. user toggle during configuration design meets specification tCSSU, tWSP, tCSH. DATA0 should left floating after configuration. should driven high low, whichever more convenient. DATA[7.1], nCS, nWS, nRS, RDYnBSY available user pins after configuration state theses pins depends dual-purpose settings. DATA7 bidirectional pin. input configuration data input, output show status RDYnBSY.
Table defines timing parameters APEX devices configuration.
Table 6-6. Timing Parameters APEX Devices (Part Symbol
tCF2CD tCF2ST0 tCFG tSTATUS
Note
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG pulse width nSTATUS pulse width
Units
Altera Corporation August 2005
6-55 Configuration Handbook, Volume
JTAG Configuration
Table 6-6. Timing Parameters APEX Devices (Part Symbol
tCF2ST1 tCSSU tCSH tCF2WS tDSU tWSP tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRSD7 tCD2UM Notes Table 6-6:
Note
Parameter
nCONFIG high nSTATUS high Chip select setup time before rising edge Chip select hold time after rising edge nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge rising edge rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode
Units
This information preliminary. This value obtainable users delay configuration extending nCONFIG nSTATUS pulse width. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period APEX devices obtain this value.
Device configuration options create configuration files discussed further Software Settings, chapter volume Configuration Handbook. Joint Test Action Group (JTAG) developed specification boundary-scan testing. This boundary-scan test (BST) architecture offers capability efficiently test components PCBs with tight lead spacing. architecture test connections without using physical test probes capture functional data while device operating normally. JTAG circuitry also used shift configuration data into device. more information JTAG boundary-scan testing, refer Application Note IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices.
JTAG Configuration
6-56 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
device operating JTAG mode uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. user pins tri-stated during JTAG configuration. APEX devices designed such that JTAG instructions have precedence over device configuration modes. This means that JTAG configuration take place without waiting other configuration modes complete. example, attempt JTAG configuration APEX FPGAs during configuration, configuration will terminated JTAG configuration will begin. Table explains each JTAG pin's function.
Table 6-7. JTAG Descriptions
Description
Test data input
Function
Serial input instructions well test programming data. Data shifted rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this VCC. Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device. JTAG interface required board, JTAG circuitry disabled leaving this unconnected. Input that provides control signal determine transitions controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this VCC. clock input circuitry. Some operations occur rising edge, while others occur falling edge. JTAG interface required board, JTAG circuitry disabled connecting this GND. Active-low input asynchronously reset boundary-scan circuit. TRST optional according IEEE Std. 1149.1. JTAG interface required board, JTAG circuitry disabled connecting this GND.
Test data output
Test mode select
Test clock input
TRST
Test reset input (optional)
VCCIO bank where JTAG pins reside, tied 3.3-V, both pins JTAG port will drive 3.3-V levels.
Altera Corporation August 2005
6-57 Configuration Handbook, Volume
JTAG Configuration
During JTAG configuration, data downloaded device through Blaster, MasterBlaster, ByteBlaster ByteBlasterMV header. Configuring devices through cable similar programming devices in-system, except TRST should connected VCC. This ensures that controller reset. Figure 6-29. shows JTAG configuration single APEX device. Figure 6-29. JTAG Configuration Single Device Using Download Cable
N.C.
APEX Device
nCE0
nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
TRST
Download Cable 10-Pin Male Header (JTAG Mode) (Top View)
Notes Figure 6-29:
pull-up resistor should connected same supply voltage Blaster, MasterBlaster (VIO pin), ByteBlaster ByteBlasterMV cable. nCONFIG, MSEL0, MSEL1 pins should connected support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. header reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlasterMV, this connect. Blaster ByteBlaster this connected when used Active Serial programming, otherwise connect. must connected driven successful JTAG configuration.
configure single device JTAG chain, programming software places other devices BYPASS mode. BYPASS mode, devices pass programming data from through single bypass register without being affected internally. This scheme enables programming software program verify target device. Configuration data driven into device appears clock cycle later.
6-58 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
APEX devices have dedicated JTAG pins that always function JTAG pins. JTAG testing performed APEX devices both before after configuration, during configuration. chip-wide reset (DEV_CLRn) chip-wide output enable (DEV_OE) pins APEX devices affect JTAG boundary-scan programming operations. Toggling these pins does affect JTAG operations (other than usual boundary-scan operation). When designing board JTAG configuration APEX devices, dedicated configuration pins should considered. Table shows these pins should connected during JTAG configuration.
Table 6-8. Dedicated Configuration Connections During JTAG Configuration Signal
Description
APEX devices chain, should driven connecting ground, pulling resistor, driving some control circuitry. devices that also multi-device FPP, configuration chains, pins should connected during JTAG configuration JTAG configured same order configuration chain. APEX devices chain, nCEO left floating connected next device. description above. These pins must left floating. These pins support whichever non-JTAG configuration used production. only JTAG configuration used, should both pins ground. Driven high connecting VCC, pulling high resistor, driven some control circuitry. Pull resistor. When configuring multiple devices same JTAG chain, each nSTATUS should pulled individually. nSTATUS pulling middle JTAG configuration indicates that error occurred.
nCEO MSEL nCONFIG nSTATUS
CONF_DONE Pull resistor. When configuring multiple devices same JTAG chain, each CONF_DONE should pulled individually. CONF_DONE going high JTAG configuration indicates successful configuration. DCLK DATA0 Should left floating. Drive high, whichever more convenient your board. Should left floating. Drive high, whichever more convenient your board.
When programming JTAG device chain, JTAG-compatible header connected several devices. number devices JTAG chain limited only drive capability download cable. When four more devices connected JTAG chain, Altera recommends buffering TCK, TDI, pins with on-board buffer. JTAG-chain device programming ideal when system contains multiple devices, when testing your system using JTAG circuitry. Figure 6-30 shows multi-device JTAG configuration.
Altera Corporation August 2005
6-59 Configuration Handbook, Volume
JTAG Configuration
Figure 6-30. JTAG Configuration Multiple Devices Using Download Cable
Download Cable 10-Pin Male Header (JTAG Mode)
APEX Device
APEX Device
APEX Device nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1 TRST
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1 TRST
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1 TRST
Notes Figure 6-30:
pull-up resistor should connected same supply voltage Blaster, MasterBlaster (VIO pin), ByteBlaster ByteBlasterMV cable. nCONFIG, MSEL0, MSEL1 pins should connected support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. header reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. ByteBlasterMV, this connect. Blaster ByteBlaster this connected when used Active Serial programming, otherwise connect. must connected driven successful JTAG configuration.
must connected driven during JTAG configuration. multi-device FPP, configuration chains, first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin configuration. Therefore, these devices also JTAG chain, should make sure pins connected during JTAG configuration that devices JTAG configured same order configuration chain. long devices JTAG configured same order multi-device configuration chain, nCEO previous device will drive next device when successfully been JTAG configured. Other Altera devices that have JTAG support placed same JTAG chain device programming configuration.
6-60 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
more information about configuring multiple Altera devices same configuration chain, refer Configuring Mixed Altera FPGA Chains Configuration Handbook. Quartus software verifies successful JTAG configuration upon completion. configuration, software checks state CONF_DONE through JTAG port. CONF_DONE high, Quartus software indicates that configuration failed. CONF_DONE high, software indicates that configuration successful. When Quartus generates file multi-device chain, contains instructions that devices chain will initialized same time. Figure 6-31 shows JTAG configuration APEX FPGA with microprocessor.
Figure 6-31. JTAG Configuration Single Device Using Microprocessor
Memory
ADDR DATA TRST
APEX Device
nCEO N.C. VCC(1)
Microprocessor
nCONFIG MSEL0 MSEL1 nSTATUS CONF_DONE
Notes Figure 6-31:
pull-up resistor should connected supply that provides acceptable input signal devices chain. Connect nCONFIG, MSEL1, MSEL0 pins support non-JTAG configuration scheme. your design only uses JTAG configuration, connect nCONFIG MSEL1 MSEL0 pins ground. must connected driven successful JTAG configuration.
STAPL
STAPL, JEDEC standard JESD-71, standard file format insystem programmability (ISP) purposes. STAPL supports programming configuration programmable devices testing electronic systems, using IEEE 1149.1 JTAG interface. STAPL freely licensed open standard. Player provides interface manipulating IEEE Std. 1149.1 JTAG state machine.
Altera Corporation August 2005
6-61 Configuration Handbook, Volume
Device Configuration Pins
more information JTAG STAPL embedded environments, refer 122: Using STAPL Embedded Processor. download player, visit Altera site: jam-index.jsp
Configuring APEX FPGAs with JRunner
JRunner software driver that allows configure Altera FPGAs, including APEX FPGAs, through ByteBlaster ByteBlasterMV cables JTAG mode. programming input file supported format. JRunner also requires Chain Description File (.cdf) generated Quartus software. JRunner targeted embedded JTAG configuration. source code been developed Windows operating system (OS). customize code make other platforms.
more information JRunner software driver, refer JRunner Software Driver: Embedded Solution JTAG Configuration White Paper source files. following tables describe connections functionality configuration related pins APEX device. Table describes dedicated configuration pins, which required connected properly your board successful configuration. Some these pins required your configuration schemes.
Device Configuration Pins
Table 6-9. Dedicated Configuration Pins APEX Device (Part Name
MSEL0 MSEL1
User Configuration Mode Scheme
Type
Input
Description
Two-bit configuration input that sets APEX device configuration scheme. Table appropriate connections. These pins must remain valid state during power-up, before nCONFIG pulled initiate reconfiguration during configuration. Dedicated input that ensures configuration related banks have powered appropriate 1.8-V 2.5-V/3.3-V voltage levels before starting configuration. logic high (1.5 means logic means 2.5-V/3.3
VCCSEL
Input
6-62 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Table 6-9. Dedicated Configuration Pins APEX Device (Part Name
nCONFIG
User Configuration Mode Scheme
Type
Input
Description
Configuration control input. Pulling this during user-mode will cause FPGA lose configuration data, enter reset state, tri-state pins, returning this logic high level will initiate reconfiguration. your configuration scheme uses enhanced configuration device EPC2 device, nCONFIG tied directly configuration device's nINIT_CONF pin. FPGA drives nSTATUS immediately after powerup releases within (When using configuration device, configuration device holds nSTATUS ms.) Status output. error occurs during configuration, nSTATUS pulled target device. Status input. external source drives nSTATUS during configuration initialization, target device enters error state. Driving nSTATUS after configuration initialization does affect configured device. configuration device used, driving nSTATUS will cause configuration device attempt configure FPGA, since FPGA ignores transitions nSTATUS user-mode, FPGA will reconfigure. initiate reconfiguration, nCONFIG must pulled low. enhanced configuration devices' EPC2 devices' pins have optional internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. Status output. target FPGA drives CONF_DONE before during configuration. Once configuration data received without error initialization cycle starts, target device releases CONF_DONE. Status input. After data received CONF_DONE goes high, target device initializes enters user mode. Driving CONF_DONE after configuration initialization does affect configured device. enhanced configuration devices' EPC2 devices' pins have optional internal programmable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins.
nSTATUS
Bidirectional open-drain
CONF_DON
Bidirectional open-drain
Altera Corporation August 2005
6-63 Configuration Handbook, Volume
Device Configuration Pins
Table 6-9. Dedicated Configuration Pins APEX Device (Part Name
User Configuration Mode Scheme
Type
Input
Description
Active-low chip enable. activates device with signal allow configuration. must held during configuration, initialization, user mode. single device configuration, should tied low. multi-device configuration, first device tied while nCEO connected next device chain. must also held successful JTAG programming FPGA. Output that drives when device configuration complete. single device configuration, this left floating. multi-device configuration, this feeds next device's pin. nCEO last device chain left floating. Clock input used clock data from external source into target device. Data latched into FPGA rising edge DCLK. mode, DCLK should tied high prevent this from floating. After configuration, this tri-stated. schemes that configuration device, DCLK will driven after configuration done. schemes that control host, DCLK should driven either high low, whichever more convenient. Toggling this after configuration does affect configured device. Data input. serial configuration modes, bit-wide configuration data presented target device DATA0 pin. After configuration, EPC1 EPC1441 devices tri-state this pin, while EPC2 devices drive this high. schemes that control host, DATA0 should driven either high low, whichever more convenient. Toggling this after configuration does affect configured device. Data inputs. Byte-wide configuration data presented target device DATA[7.0]. serial configuration schemes, they function user pins during configuration, which means they tristated. After configuration, DATA[7.1] available user pins state these depends Dual-Purpose settings.
nCEO
Output
DCLK
Synchronous configuration schemes FPP)
Input
DATA0
Input
DATA[7.1]
Parallel configuration schemes (FPP PPA)
Inputs
6-64 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Table 6-9. Dedicated Configuration Pins APEX Device (Part Name
DATA7
User Configuration Mode Scheme
Type
Bidirectional
Description
configuration scheme, DATA7 presents RDYnBSY signal after signal been strobed low. serial configuration schemes, functions user during configuration, which means tri-stated. After configuration, DATA7 available user state this depends Dual-Purpose settings. Write strobe input. low-to-high transition causes device latch byte data DATA[7.0] pins. non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, available user state this depends Dual-Purpose settings. Read strobe input. input directs device drive RDYnBSY signal DATA7 pin. used mode, should tied high. non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, available user state this depends Dual-Purpose settings.
Input
Input
Altera Corporation August 2005
6-65 Configuration Handbook, Volume
Device Configuration Pins
Table 6-9. Dedicated Configuration Pins APEX Device (Part Name
RDYnBSY
User Configuration Mode Scheme
Type
Output
Description
Ready output. high output indicates that target device ready accept another data byte. output indicates that target device busy ready receive another data byte. configuration schemes, this will drive high after power-up, before configuration after configuration before entering user-mode. non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, RDYnBSY available user state this depends dual-purpose settings. Chip-select inputs. high select target device configuration. pins must held active during configuration initialization. During configuration mode, only required either pin. Therefore, only chipselect input used, other must tied active state. example, tied ground while toggled control configuration. non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, available user pins state these pins depends dual-purpose settings.
nCS/CS
Input
6-66 Configuration Handbook, Volume
Altera Corporation August 2005
Configuring APEX Devices
Table 6-10 describes optional configuration pins. these optional configuration pins enabled Quartus software, they available general-purpose user pins. Therefore during configuration they function user pins, which means they tristated with weak pull-up resistors.
Table 6-10. Optional Configuration Pins Name
CLKUSR
User Mode
option option off. Input
Type
Description
Optional user-supplied clock input. Synchronizes initialization more devices. This enabled turning Enable user-supplied start-up clock (CLKUSR) option Quartus software Status pin. used indicate when device initialized user mode. When nCONFIG during beginning configuration, INIT_DONE tri-stated pulled high external pull-up resistor. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE will low. When initialization complete, INIT_DONE will released pulled high FPGA enters user mode. Thus, monitoring circuitry must able detect low-to-high transition. This enabled turning Enable INIT_DONE output option Quartus software. Opti
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