Application Note Altera provides building blocks accelerate devel

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Uplink Desubchannelization WiMAX
Application Note
Altera provides building blocks accelerate development worldwide interoperability microwave access (WiMAX) compliant basestations. This application note describes reference design that demonstrates suitability Altera® tools devices implementing uplink desubchannelization function. WiMAX emerging broadband wireless technology that promises high-speed data services. IEEE 802.16e-2005 standard enables mobility. There significant market potential this technology currently being deployed equipment manufacturers. Altera devices ideal platform high throughput designs such those found WiMAX basestation channel card, because dedicated multiplier blocks inherent parallel structure. This structure gives significant cost performance advantage over general purpose processors this type design.
more information IEEE 802.16e-2005, refer IEEE Standard Local Metropolitan Area Networks, Part Interface Fixed Broadband Wireless Access Systems, IEEE P802.16e-2005, February 2006. orthogonal frequency-division multiple access (OFDMA) systems, multiple stations subscriber stations (SSs) transmit same time access point (AP) basestation. uplink bandwidth split into different subchannels, where each subchannel occupies different frequencies available bandwidth. Each allocated more subchannels allocate their data Some subchannels allocated transmit These tend used ranging (timing synchronization) between Hence these subchannels there contention between different SSs. received signal downconverted, cyclic prefix removed converted into frequency domain using operation, signal split into separate subchannels- desubchannelization. uplink desubchannelization reference design uplink (receiver path). accepts frequency domain symbol data extracts different subchannels from then outputs user data output interface ranging data separate output interface.
Altera Corporation AN-450-1.0
Preliminary
Uplink Desubchannelization WiMAX
uplink desubchannelization reference design provides following features:
Desubchannelization functions compliant mandatory parts IEEE802.16e-2005 specifications: Supports UL-PUSC mode support mini-subchannels Suitable WiMAX compliant OFDMA basestations Slot data extracted from input OFDMA symbols output dedicated output interface: slot subchannel over three consecutive OFDMA symbols Both data pilot information output Ranging data extracted from input OFDMA symbols output dedicated output interface Configuration interface: Allows specify number ranging channels next three OFDMA symbols specify which subchannels allocated each ranging channel Allows specify which subchannels allocated user data including contiguous non-contiguous subchannel ranges IDCell specified input port Supports sizes (128, 512, 1,024, 2,048) synthesis time parameter Support multiple antennas
uplink desubchannelization reference design compliant with following WiMAX specification versions:
IEEE P802.16-Revd/D5-2004 "Part Interface Fixed Broadband Wireless Access Systems" IEEE 802.16e-2005 IEEE 802.16-2004/Cor 1-2005 "Part Interface Fixed Mobile Broadband Wireless Access Systems Amendment Physical Medium Access Control Layers Combined Fixed Mobile Operation Licensed Bands Corrigendum
design complies following sections specifications:
8.4.6.2.1 Symbol structure subchannel (PUSC) 8.4.6.2.2 Partitioning subcarriers into subchannels uplink 8.4.6.2.3 Uplink permutation example
WiMAX Physical Layer
Preliminary
Figure shows overview IEEE 802.16e-2005 scalable OFDMA physical layer (PHY) WiMAX basestations.
Altera Corporation
WiMAX Physical Layer
Figure WiMAX Implementation
MAC/PHY Interface
Downlink
Randomization
Derandomization
Uplink
Encoding
Bit-Level Processing
Decoding
Interleaving
Deinterleaving
Symbol Mapping
Symbol Demapping
Channel Estimation Equalization
Subchannelization Pilot Insertion
OFDMA Symbol-Level Processing
Desubchannelization Pilot Extraction
OFDMA Ranging
IFFT
Cyclic Prefix
Remove Cyclic Prefix
Digital Processing
From
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Altera's WiMAX building blocks include level, OFDMA symbol-level, digital intermediate frequency (IF) processing blocks. bit-level processing, Altera provides symbol mapping reference designs support forward error correction (FEC) using Reed-Solomon Viterbi MegaCore® functions. OFDMA symbol-level processing blocks include reference designs that demonstrate subchannelization desubchannelization with cyclic prefix insertion supported fast Fourier transform (FFT) inverse (IFFT) MegaCore functions. Other symbol-level reference designs illustrate ranging, channel estimation, channel equalization. digital processing blocks include single antenna multiantenna digital converter (DUC) digital down converter (DDC) reference designs, advanced crest factor reduction (CFR) digital predistortion (DPD). This application note describes uplink desubchannelization.
more information Altera WiMAX solutions, refer following application notes:
412: Scaleable OFDMA Engine WiMAX 421: Accelerating System Designs WiMAX 430: OFDMA Ranging WiMAX 434: Channel Estimation Equalization WiMAX 439: Constellation Mapper Demapper WiMAX 451: Downlink Subchannelization WiMAX 452: OFDM Kernel WiMAX 457: Integrating Uplink Desubchannelization Ranging Modules WiMAX
Functional Description
Figure shows uplink desubchannelization reference design block diagram.
Preliminary
Altera Corporation
Functional Description
Figure Block Diagram
User Data Extraction Arbitration Ranging Data Extraction User Data Output Interface Ranging Data Output Interface
Configuration Input Interface
Data Input Interface
Strip
Memory
design following four main input output interfaces:
Input interface configuration data Input interface OFDMA symbol data Output interface user slot data Output interface ranging data
design accepts OFDMA symbol data data input interface. first processing stage known strip. This stage removes guard bands that present around frequency bins +N/2 -N/2 each OFDMA symbol. Also carrier (bin removed. remaining frequency bins written internal memory. These remaining frequency bins contain ranging data user data (including pilot information). internal memory double buffered-it store data OFDMA symbols. Thus, while design processes group three symbols extracts ranging user data, reads another group symbols, which undergo strip process design writes them into this internal memory. User data extraction ranging data extraction only start occur after design writes group three consecutive OFDMA symbols into internal memory buffer, because uplink subchannelization occurs over three consecutive symbols. Ranging user data extraction functions effectively occur parallel.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
ranging data extraction block reads configuration data from configuration interface determine following information:
next ranging channel number type ranging this ranging channel (initial, periodic, bandwidth, handover) Starting ending subchannel number this ranging channel starting slot number this ranging channel antenna number
Then determines which subcarriers make this ranging channel send requests arbiter read (extract) this data from internal memory. After sends request last subcarrier current ranging channel, obtains next configuration data word next ranging channel. user slot data extraction block reads configuration data from configuration interface determine following information:
Single contiguous range subchannels extract starting slot number this range subchannels antenna number
Then, each subchannel, determines which subcarriers constitute sends requests arbiter read (extract) this data from internal memory. After sends request last subcarrier last subchannel, obtains next configuration data word next allocation subchannels. arbiter reads requested data from internal memory sends either user slot data output interface request originated from user data extraction block) ranging data output interface. arbiter receives requests simultaneously from both ranging extraction user data extraction blocks, services both requests (one after another).
Multiple Antenna Support
This design timeshared amongst different antennas. number antennas timesharing depends operating clock frequency compared required clock frequency meet throughput. Each block three consecutive OFDMA symbols into desubchannelization design must from same antenna. antenna number must indicated desubchannelization design both range user data input interfaces.
Preliminary
Altera Corporation
Functional Description
Input Interfaces
design following input interfaces:
Data interface Configuration interface: Ranging interface User data interface General purpose input (GPI)
these input interfaces Altera Avalon® Streaming (Avalon-ST) interfaces (with exception signals that form part configuration interface).
more information Avalon-ST interfaces, refer Avalon Streaming Interface Specification.
Input Interface Signals
Table shows input interface signals. Table Input Interface Signals Signal Data Interface
din_valid din_ready din_data
Input Output Input Signifies validity data inputs. Signifies whether uplink desubchannelization design accept more data. output data samples).
transitions synchronous rising clock edge.
Width
Input /Output
Description
Ranging Interface
rmapin_data rmapin_valid rmapin_ready
Input Input Output Ranging information. Signifies validity rmapin_data. Signifies whether uplink desubchannelization design accept more rmapin data.
User Data Interface
dmapin_data dmapin_valid dmapin_ready
Input Input Output User data information. Signifies validity dmapin_data. Signifies whether uplink desubchannelization design accept more dmapin data.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Table Input Interface Signals Signal General Purpose Input
gpin_idcell gpin_idcell2
Input Input
Width
Input /Output
Description
IDCell value. IDCell value (same gpin_idcell).
Data Interface
data interface Avalon-ST compliant (using ready latency Each input sample complex frequency domain data representing single subcarrier. lowest bits data assigned real portion. 16-bit width been assumed real also imaginary parts sample. must feed subcarriers each input OFDMA symbol from frequency (where size). data interface follows simple protocol. accept data samples consecutive clock cycles. upstream agent increase interval between feeding consecutive data samples holding din_valid low. validity data input signals indicated din_valid high. din_valid low, uplink desubchannelization design ignores data inputs. design typically reads data three consecutive symbols time. applies backpressure upstream agent process more data. applies backpressure forcing din_ready low. next cycle, upstream agent must force din_valid apply more valid data until detects din_ready high.
Ranging Interface
ranging interface Avalon-ST compliant (using ready latency protocol exactly same data interface. uplink desubchannelization design apply backpressure deasserting rmapin_ready, forcing upstream agent stop sending more information. Similarly upstream agent delay sending ranging information deasserting rmapin_valid.
Preliminary
Altera Corporation
Functional Description
Table shows 41-bit range configuration bus.
Table Range Configuration Fields rmapin_data[40:0] Bits
[1:0] [4:2] [8:5] [10:9] [17:11] [24:18] [40:25] Header. Antenna number. Ranging channel number. Ranging type. Starting subchannel number. Ending subchannel number. Starting slot number.
Field
Each word range configuration refers ranging channel. antenna number value from There support eight antennas. ranging channel number value from 2,048 size, there maximum ranging channels there subchannels. ranging type provides information type ranging this channel. Table shows valid ranging type values.
Table Valid Ranging Type Values Ranging Type [1:0] Value
Description
Initial/handover ranging over symbols. Initial/handover ranging over four symbols. Periodic/bandwidth ranging over symbols. Periodic/bandwidth ranging over three symbols.
IEEE802.16d/e specifications state that ranging channels occupy either four (for size) (for other sizes) consecutive subchannels. starting ending subchannel number provide range these four subchannels comprising ranging channel. starting slot number slot number lowest numbered subchannel ranging channel.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Each group three OFDMA symbols requires packet range configuration data. Each packet comprise from different words. header field each word signify last range information group three OFDMA symbols question. header equal three, current word last word packet (see Table which shows decoding header word). next word this first word next packet, which refers next group three OFDMA symbols. must ensure that antenna number field does change each word packet. uplink desubchannelization design begin ranging data extraction until first word this configuration packet been read Hence must ensure that this packet available same time before) each group three OFDMA symbols clocked into design.
Table Range Word Header Field Header (rmapin_data[1:0]) Value
00,01,10
Header Field
Last word packet. last word packet.
There special case zero ranging channels. signify that there ranging channels group three OFDMA symbols, packet length must sent range interface, with starting subchannel field (rmapin_data[29:23]) decimal (127 valid subchannel number).
User Data Interface
user data interface Avalon-ST compliant (using ready latency protocol this exactly same data interface ranging interface. Table shows 35-bit user data configuration bus.
Table User Data Configuration Fields (Part dmapin_data[34:0] Bits
[1:0] [4:2] Header. Antenna number.
Field
Preliminary
Altera Corporation
Functional Description
Table User Data Configuration Fields (Part dmapin_data[34:0] Bits
[11:5] [18:12] [34:19]
Field
Starting subchannel number. Ending subchannel number. Starting slot number.
Each word user data configuration data refers range subchannels allocated user data. starting ending subchannel fields list range subchannels (inclusively) that allocated user data. start subchannel number equal subchannel number, only subchannel defined user data. antenna number value from (support antennas). starting slot number slot number lowest numbered subchannel allocated range. packet user data configuration data required each group three OFDMA symbols. Each packet comprise from different words. header field each word signify last user data information group three OFDMA symbols question. header equal three, current word last word packet (see Table which shows decoding header word). next word this first word next packet, which refers next group three OFDMA symbols.
Table User Data Word Header Field Header (rmapin_data[1:0]) Value
00,01,10
Header Field
Last word packet. last word packet.
must ensure that antenna number field does change each word packet. uplink desubchannelization reference design begin user data extraction until first word this configuration packet been read Hence must ensure that this packet available same time before) each group three OFDMA symbols being clocked into design.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
define contiguous non-contiguous subchannel ranges user data allocation. Each word packet defines contiguous subchannel range. ranges defined different words noncontiguous. There special case zero subchannels allocated user data. signify that there subchannels group three OFDMA symbols allocated user data, packet length must sent user data interface, with starting subchannel field (dmapin_data[29:23]) decimal (127 valid subchannel number).
GPIs available specify IDCell value Both these GPIs, should driven same source they should always have same value.
Output Interface Description
output interface consists following sub-interfaces:
User slot data interface Ranging data interface
interfaces Avalon-ST compliant. behavior these interfaces exactly same Avalon-ST input interfaces. output interfaces, uplink desubchannelization design source opposed sink), which drives data valid lines, monitors ready line.
Output Interface Signals
Table shows output interface signals. Table Output Interface Signals Signal User Slot Data Interface
dout_startofpacket dout_endofpacket dout_data[63:0]
Output Output Output Start packet (valid single clock cycle high pulse). packet (valid single clock cycle high pulse). Packet data.
transitions synchronous rising clock edge.
Direction
Description
Preliminary
Altera Corporation
Functional Description
Table Output Interface Signals Signal
dout_valid dout_ready
Direction
Output Input output data valid.
Description
Indicates whether downstream agent accept data.
Ranging Data Interface
drang_startofpacket drang_endofpacket drang_data[63:0] drang_valid drang_ready
Output Output Output Output Input Start packet (single clock cycle high pulse). packet (single clock cycle high pulse). Packet data. output data valid. Indicates whether downstream agent accept data.
configure output data widths synthesis time. This reference design assumes 16-bit wide samples.
User Slot Data Output Interface
This interface Avalon-ST compliant (using ready latency downstream agent apply backpressure uplink desubchannelization design cannot accept data deasserting dout_ready. interface outputs packets data, with each packet marked valid data words output when high detected dout_startofpacket until high detected dout_endofpacket i.e. dout_startofpacket first sample dout_endofpacket last sample packet. Each packet comprises slot (WiMAX terminology) user data. slot comprises subchannel over three consecutive OFDMA symbols. There tiles (where tile four consecutive subcarriers) each symbol allocated subchannel. Over three symbols this equates samples subchannel only samples. remaining samples pilot signals. samples each valid slot output. pilot samples required channel estimation function that follows this block. samples each slot output following order:
lowest numbered tile first symbol tile symbol tile symbol tile symbol
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
tile symbol tile symbol
Each output data word contains complex subcarrier data plus some sideband information, some which required downstream processing blocks (channel estimation, carrier frequency offset estimation, correction). Table shows output user data slot fields.
Table Output User Data Slot Fields dout_data[63:0] Bits
[63:61] [60:53] [52:51] [50:44] [43:35] [34:32] [31:16] [15:0] Antenna number. Lowest eight bits slot number. Symbol offset. Subchannel number (0.69). Physical tile number (0.419). Logical tile index (0.5). Imaginary part complex subcarrier value. Real part complex subcarrier value.
Field
Ranging Data Output Interface
This interface Avalon-ST compliant (using ready latency downstream agent apply backpressure uplink desubchannelization design cannot accept data deasserting drang_ready. interface outputs packets data, with each packet marked valid data words output when high detected drang_startofpacket, until high detected drang_endofpacket (drang_startofpacket first sample drang_endofpacket last sample packet. Each packet comprises slot (WiMAX terminology) user data. ranging channel OFDMA symbol (either samples) constitutes packet this output. ranging extraction begins from first listed ranging channel input configuration read last listed ranging channel. ranging channel comprises either four subchannels (for size) (for other sizes) subchannels. subchannel comprises tiles symbol. subcarriers within tile used ranging data
Preliminary
Altera Corporation
Getting Started
(there pilot signals). Thus ranging channel equates either samples (for size) samples (for other sizes) OFDMA symbol. multiple ranging channels, ranging data ranging channel over three symbols output before moving onto next ranging channel. each ranging channel samples output order from lowest numbered tile first symbol highest numbered tile first symbol, then moving onto symbol then onto symbol same order. With ranging data, sideband information output. complex ranging data along with this sideband information output drang_data. Table shows mapping this word different fields. sideband information remains same entire packet.
Table Ranging Output Word drang_data[63:0] bits
[63:57] [56:55] [54:51] [50:49] [48:35] [34:32] [31:16] [15:0]
Field
First subchannel number (next also comprise ranging channel). Symbol offset (0.2). Ranging channel number. Ranging type. Lowest bits starting slot number ranging channel. Antenna number. Imaginary part ranging data. Real part ranging data.
Getting Started
This section describes system requirements, installation other information about using uplink desubchannelization reference design.
System Requirements
reference design requires following hardware software:
running Windows 2000/XP operating system Quartus® software version 6.0, ModelSim 5.7d (mixed VHDL-Verilog license)
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Install Reference Design
uplink desubchannelization reference design ships with scaleable OFDMA engine.
more information installation instructions scaleable OFDMA engine, refer AN412: Scaleable OFDMA Engine WiMAX. reference design installs default into c:\altera\reference_designs directory, change default. Figure shows directory structure, where <path> top-level directory, wimax_ofdma\source\rtl\ul_rx. Figure Directory
<path> Installation directory. ul_pusc_rx_desubchan Contains uplink desubchannelization reference design. build Contains SignalTap file with embedded signal generator. data Contains vectors testbench. Contains documentation. scripts Contains scripts simulation synthesis. source Contains VHDL source files. Contains testbench files.
After install reference design, follow these steps: Browse <Quartus install Make backup copy existing alt_cusp_package.vhd file. Copy alt_cusp_package.vhd file paste <Quartus install
Preliminary
Altera Corporation
Getting Started
Table lists files associated with test pattern generation hardware debug reference design.
Table Debug Files File Name
ul_desub_debug_tb.vhd ul_desub_debug_toplevel.vhd ul_desub_debug.vhd debug_din_if.vhd debug_config_dmap_if.vhd debug_config_rmap_if.vhd ul_desub_debug_pkg_n2048.vhd ul_desub_debug_pkg_n1024.vhd ul_desub_debug_pkg_n512.vhd ul_desub_debug_pkg_n128.vhd ul_desub_debug_quartus.tcl ul_desub_debug_tb_msim.tcl stp1.stp \scripts \scripts \build test package file. test package file. test package file. test package file. Quartus script build design with embedded test pattern generation. ModelSim script embedded test pattern simulation. SignalTap® file design with embedded test pattern generation.
Directory
Information
testbench test pattern test.
Understand Data Files
Altera provides following data files
Input data: Input range configuration data: Input user data configuration data: Output user slot data:
Altera provide ranging output data from uplink desubchannelization design output ranging data: these data files appropriate testbench.
Input Output Data File Formats
This section describes format input output data files.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Figure shows general structure these files. data arranged into several blocks. Each block three sub-blocks. fields must contain decimal numbers only. Figure General Data Text File Structure
Block Sub-block Sub-block Sub-block
Block Sub-block Sub-block Sub-block
Block Sub-block Sub-block Sub-block
first line contains single number This number indicates number blocks file. number zero, ignore value, number blocks file unknown calculated.
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Altera Corporation
Getting Started
After first line, each block data follows. Each block comprises three sub-blocks. Figure shows structure each block more detail. first line each block contains single number, which indicates number sub-blocks this current block should always Figure Structure Single Block File
Number Sub-blocks this Block. Always
Number Entries Sub-block Always
Value Entry Sub-block Indicates Block Number.
Number Entries Sub-block
Value Entry Sub-block Sideband Signal Configuarion Information. Value Entry Sub-block Sideband Signal Configuarion Information.
Number Entries Sub-block
Value Entry Sub-block Data Signals. Value Entry Sub-block Data Signals.
next line contains single number that indicates number entries sub-block which should always following line contains single number, which value entry sub-block Sub-block only contains block number given this value. next line contains single number that indicates number entries sub-block Sub-block contains sideband signal configuration information. number entries this sub-block varies, depending which file being referred example entries, next lines files contain sideband signal configuration information.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
next line contains single number, that indicates number entries sub-block next lines contain information data signal values.
Sub-Block Sideband Information
following code example possible contents sub-block 117503728
first line contains which means that there entries subblock next lines contain sideband signal configuration information. There numbers each line. first number code that indicates which sideband signal configuration information referred second number gives value this sideband signal configuration information. Table shows sub-block field codes.
Table Sub-Block Field Codes (Part Present Text File Code Signal Input Data Range Input Data
Data Input Data
Output Slot Data
Output Ranging Data
Antenna number Ranging channel number Ranging type Starting slot number Start Range Code Offset Number initial ranging codes Number periodic ranging codes Number bandwidth ranging codes Number handover ranging codes size code
Preliminary
Altera Corporation
Getting Started
Table Sub-Block Field Codes (Part Present Text File Code Signal Input Data Range Input Data
Data Input Data
Output Slot Data
Output Ranging Data
Cyclic prefix length code Positive Timing Offset Negative Timing Offset Margin Positive Timing Offset Margin Negative Timing Offset Code detection threshold Symbol Offset
IDCell basestation
MATLAB initial random generator seed Subchannel Number consecutive symbol counter
Note Table
Extra signals that provide more information about test setup, which useful when integrating with downstream upstream blocks.
Sub-Block Data Values
This section describes sub-block data values. Input Data File input file arranged that each block represents data particular OFDMA symbol. following code shows example start sub-block 1024 9631 8483 12116 -14994 -22526 -3079 -8978 10877 -17961 1604 -2809 -4338 -7953 18214
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
first line contains number data samples OFDMA symbol, which 1,024 (the size equal 1,024 this example). This value equal size (128, 512, 1,024 2,048). Each line contains numbers. first real part sample; second imaginary part. subcarriers each input OFDMA symbol listed, order from frequency (where size). Input Ranging File third sub-block this file represents many ranging channels which subchannels allocated ranging group three consecutive OFDMA symbols. following code shows example sub-block 28644 28650 first line contains number lines this sub-block. This equates number different ranging channels (two this case). Each subsequent line refers ranging channel contains fields. From left right each field represents: Field Header Field Ranging Channel Number Field Ranging Type Field Starting subchannel number allocated this ranging channel Field Last subchannel number allocated this ranging channel Field Starting Slot number lowest numbered subchannel allocated this ranging channel Input User Data File third sub-block this file represents which subchannels allocated User data group three consecutive OFDMA symbols. following code shows example sub-block 3235 3248 3234 3258
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Getting Started
first line indicates that there four different subchannel regions allocated user data. next four lines define each these subchannel regions. Each subsequent line contains four fields. From left right each field represents: Field Header Field Starting Subchannel number allocated user data Field Last Subchannel number allocated user data this region Field Slot number first subchannel number this region Output User Slot Data Sub-block represents user data particular slot (one subchannel over three consecutive OFDMA symbols). following code shows example possible contents subblock 28185 7243 -7939 3651 23976 -11608 -14223 14432 6219 7954 -2072 11659 -14432 -2320 -15028 -18796 -27025 11739 25039 -1896 first line indicates that there subsequent lines this sub-block; this equates number data samples user data slot. Each subsequent line contains information about each slot sample. Each line always contains four fields. Going from left right, different fields represent: Field Real part slot data Field Imaginary part slot data Field OFDMA Symbol offset (0.2) within group three symbols Field Logical tile index that slot data refers (value from 0.5)
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Output Ranging Data Sub-block represents ranging channel data particular OFDMA symbol. following code shows example start sub-block 17388 23877 21709 19399 16389 28867 6923 26390 -14143 -9200 -13723 -17297 13323 17627 12076 17699 first line contains number data samples ranging channel, which this example. This value either (when size 128). next lines contain ranging channel data. Each line contains numbers. first real part sample, second imaginary part. samples ordered from lowest numbered subcarrier lowest numbered subchannel that comprises ranging channel highest numbered subcarrier highest numbered subchannel ranging channel.
Debug Reference Design
understand subcarriers that extracted, feed repeatable test pattern into desubchannelization design, which unique value each different subcarrier. This method also confirm that uplink subchannelization block basing mapping same this desubchannelization block used basestation). following files enable perform this debug:
Test pattern generation logic Top-level design file that instantiates test logic desubchannelization design testbench Modelsim simulation script Script that synthesizes test logic with desubchannelization design Stratix® development board
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Altera Corporation
Getting Started
load test pattern logic into hardware, which allows real hardware debug using either logic analyzers Altera's SignalTap. demonstration purposes, scripts synthesize design Stratix development board allow SignalTap view outputs from uplink desubchannelization design.
Test Pattern
generated test pattern different real imaginary parts data that into design. Real Data Input design processes OFDMA symbols groups three. real data input, (din_real[15:0]), unique value each subcarrier each OFDMA symbol block three OFDMA symbols. Then values repeat each block three OFDMA symbols. real data subdivided into several signals (see Table test pattern generated each these signals.
Table Real Data Test Signals Din_real[15:0] Range
[15:14] [13:0] [13:12] [11:0]
Test Signal Field Name
T_symbol_no T_subcarrier_code T_subcarrier_type T_subcarrier_subcode
Tables through Table show possible values meanings these signals.
Table Encoding T_symbol_no T_symbol_no[1:0] Value
Occurrence
First OFDMA symbol block three. Second OFDMA symbol block three. Third OFDMA symbol block three.
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Preliminary
Uplink Desubchannelization WiMAX
Table Encoding T_subcarrier_type T_subcarrier_type[1:0] Value
Occurrence
Usable Subcarrier. Left guard band subcarrier. Right guard band subcarrier. carrier.
Table Encoding T_subcarrier_subcode T_subcarrier_subcode[11:0] Value
Occurrence
first left guard, first right guard, first usable subcarrier (determined T_subcarrier_type). left guard, right guard, usable subcarrier (determined T_subcarrier_type).
Note Table
usable subcarrier numbering according WiMAX specifications.
Table shows test sequence 1,024K size. Other sizes have similar patterns. only differences number guard usable subcarriers.
Table Example Test Pattern Real Data 1,024 Size (Part Sample Number
Freq
T_symbol_ no[1:0]
T_subcarrier_ type [1:0]
subcarrier Usable subcarrier Usable subcarrier Usable subcarrier Right guard
T_subcarrier_no [11:0]
T_subcarrier_code [13:0]
12,288 (14'h3000) (14'h01A4) (14'h01A5) (14'h0347) 8,192 (14'h2000)
Preliminary
Altera Corporation
Getting Started
Table Example Test Pattern Real Data 1,024 Size (Part Sample Number
1,024
Freq
T_symbol_ no[1:0]
T_subcarrier_ type [1:0]
Right guard
T_subcarrier_no [11:0]
T_subcarrier_code [13:0]
8,193 (14'h2001)
Right guard Left guard Left guard Left guard Usable subcarrier Usable subcarrier Usable subcarrier
8,282 (14'h205A) 4,096 (14'h1000) 4,097 (14'h1001) ,4187 (14'h105B) (14'h0000) (14'h0001). (14'h01A3)
-512 -511
-421 -420 -419
desubchannelization block expects data into order from frequency onwards. Thus, referring size 1,024 (for example) Table test pattern generated order from frequency bins 511, then -512 through Imaginary Data Input imaginary data input output from 16-bit counter, which increments every cycle. This input verifies that output same subcarriers from different groups three OFDMA symbols from different groups three OFDMA symbols same group (hardware processing more than group three OFDMA symbols). real data same value imaginary data different value. Configuration Data same configuration data sent design, whenever design indicates ready accept another configuration data word. configuration packet consists word only. Thus only subchannel range defined. subchannels extracted user data package files (one package file each different size). overwrite default settings here.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Configuration Range same configuration range sent design, whenever design indicates ready accept another configuration range word. configuration packet consists word only; ranging channel defined. subchannels that comprise this channel package files (one package file each different size). overwrite default settings here.
Simulation Desubchannelization with Test Pattern
Altera provides testbench with script (ul_desub_debug_tb_msim.tcl) that from Modelsim simulator. When script, performs following actions:
Compiles uplink desubchannelization reference design Compile test pattern generation logic Loads waveform viewer
testbench feeds clock reset signals into system (desubchannelization plus test pattern generation logic) writes user data ranging outputs from desubchannelization following text files respectively:
sim\desub_op_ddata.txt sim\desub_op_rdata.txt
simulation runs indefinitely, data repeatedly into desubchannelization design. Thus, must stop simulation. simulate desubchannelization design versions different sizes. specify size modify following variables script:
fftsize 1024 proj_topdir c_rx_desubchan"
first variable sets size. 128, 512, 1024, 2048 valid values; second variable path top-level file desubchannelization design.
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Getting Started
After, modifying these variables, script ModelSim simulator.
Hardware Simulation using Stratix Development Board
load uplink desubchannelization reference design test pattern generation logic onto FPGA test hardware. ul_desub_debug_toplevel.vhd file top-level file that instantiates both design test pattern generation logic (the debug system). script ul_desub_debug_quartus.tcl synthesizes debug system Altera's Stratix Development Board enables SignalTap design's outputs. perform hardware simulation, follow these steps: Edit following lines ul_desub_debug_quartus.tcl, reflect size synthesize, location design, version Quartus software.
fftsize proj_topdir x_desubchan" Quartus earlier than Quartus pre_quartus61 Quartus software change directory location ul_desub_debug_quartus.tcl. Quartus console type following command:
source ul_desub_debug_quartus.tcl debug system synthesized Stratix 2S60 device generate following file: Download this .sof file Stratix 2S60 device development board using programming cable. Tools menu click SignalTap Logic Analyzer click Acquire data.
waveform outputs from desubchannelization block displays.
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
Performance
This section shows synthesis results throughput.
Synthesis Results
Table shows synthesis results sizes. results assume 16-bit inputs real imaginary parts input data that into design slot data ranging data output.
Table Uplink Desubchannelization Synthesis Results Memory Device
Cyclone 2C35
Size
1,024 2,048
LEs/ALUTs M512
3,521 (11%) 3,523 (11%) 3,461 (10%) 3,518 (11%) 3,179 (12%) 3,235 (12%) 3,180 (12%) 3,226 (12%) (<1%) (<1%) (<1%) (<1%)
(19%) (42%) (50%) (88%) (13%) (29%) (7%) (7%)
MRAM
(100%) (100%)
Multipliers
(3%) (3%) (3%) (3%) (2%) (2%) (2%) (2%)
FMAX (MHz)
Stratix 2S30
1,024 2,048
Cyclone® synthesis, need VERIFIED_SAFE setting synthesis parameter CYCLONEII_SAFE_WRITE under Default Parameters Analysis Synthesis Settings. Otherwise, twice increase block usage. This workaround silicon issue, when using memory certain configurations. However, this design does memory configurations where silicon issue problem.
more information, refer Cyclone Errata Sheet.
Throughput
OFDMA symbols continuously into uplink desubchannelization reference design data rate appropriate size. design must able output ranging user data group three OFDMA symbols within time taken next three OFDMA symbols into block. meet throughput ,the design must clocked minimum four times data rate sizes.
Preliminary
Altera Corporation
Revision History
Table shows minimum clock frequency throughput.
Table Minimum Clock Frequency Size
1,024 2,048
Data Rate (MHz)
1.25
Minimum Clock Frequency (MHz)
Revision History
Table Revision History Version
Table shows revision history this application note.
Date
February 2007 First release.
Description
Altera Corporation
Preliminary
Uplink Desubchannelization WiMAX
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Preliminary
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