Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 ISP/IAP flas

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Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 ISP/IAP flas

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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 ISP/IAP flash with 10-bit
Rev. September 2006 Product data sheet
LPC2131/32/34/36/38 microcontrollers based 16/32-bit ARM7TDMI-S with real-time emulation embedded trace support, that combine microcontroller with embedded high-speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. their tiny size power consumption, these microcontrollers ideal applications where miniaturization requirement, such access control point-of-sale. With wide range serial communications interfaces on-chip SRAM options they very well suited communication gateways protocol converters, soft modems, voice recognition low-end imaging, providing both large buffer size high processing power. Various 32-bit timers, single dual 10-bit 8-channel ADC(s), 10-bit DAC, channels GPIO lines with nine edge level sensitive external interrupt pins make these microcontrollers particularly suitable industrial control medical systems.
Features
Enhancements brought LPC213x/01 devices
Fast GPIO ports enable port toggling times faster than original LPC213x. They also allow port read time regardless function. Dedicated result registers ADC(s) reduce interrupt overhead. UART0/1 include fractional baud rate generator, auto-bauding capabilities handshake flow-control fully implemented hardware. Additional control enables further reduction power consumption.
features common LPC213x LPC213x/01
16/32-bit ARM7TDMI-S microcontroller tiny LQFP64 HVQFN package. 8/16/32 on-chip static 32/64/128/256/512 on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed operation. In-System Programming/In-Application Programming (ISP/IAP) on-chip bootloader software. Single flash sector full chip erase programming EmbeddedICE Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software high-speed tracing instruction execution.
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
(LPC2131/32) (LPC2134/36/38) 8-channel 10-bit ADCs provide total analog inputs, with conversion times 2.44 channel. Single 10-bit provides variable analog output (LPC2132/34/36/38). 32-bit timers/external event counters (with four capture four compare channels each), unit (six outputs) watchdog. power Real-time clock with independent power dedicated clock input. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s), with buffering variable data length capabilities. Vectored interrupt controller with configurable priorities vector addresses. forty-seven tolerant general purpose pins tiny LQFP64 HVQFN package. nine edge level sensitive external interrupt pins available. maximum clock available from programmable on-chip with settling time On-chip integrated oscillator operates with external crystal range with external oscillator MHz. Power saving modes include Idle Power-down. Individual enable/disable peripheral functions well peripheral clock scaling down additional power optimization. Processor wake-up from Power-down mode external interrupt BOD. Single power supply chip with circuits: operating voltage range (3.3 with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2131FBD64 LPC2131FBD64/01 LPC2132FBD64 LPC2132FBD64/01 LPC2132FHN64 LQFP64 LQFP64 LQFP64 LQFP64 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT314-2 SOT314-2 SOT314-2 SOT314-2 SOT804-2 Type number
HVQFN64 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
LPC2132FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 LPC2134FBD64 LPC2134FBD64/01 LQFP64 LQFP64 plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body
SOT804-2
SOT314-2 SOT314-2
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Ordering information .continued Package Name Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT314-2 SOT314-2 SOT314-2 SOT314-2 SOT804-2 LQFP64 LQFP64 LQFP64 LQFP64
Table
Type number LPC2136FBD64 LPC2136FBD64/01 LPC2138FBD64 LPC2138FBD64/01 LPC2138FHN64
HVQFN64 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
LPC2138FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
SOT804-2
Ordering options
Table Ordering options Flash memory Enhanced UARTs, Temperature ADC, Fast I/Os, range Type number
LPC2131FBD64 LPC2131FBD64/01 LPC2132FBD64 LPC2132FBD64/01 LPC2132FHN64 LPC2132FHN64/01 LPC2134FBD64 LPC2134FBD64/01 LPC2136FBD64 LPC2136FBD64/01 LPC2138FBD64 LPC2138FBD64/01 LPC2138FHN64 LPC2138FHN64/01
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Block diagram
TMS(3) TRST(3) TDI(3)
trace
TCK(3)
TDO(3) signals
XTAL2 RESET XTAL1
EMULATION TRACE MODULE
LPC2131, LPC2131/01 LPC2132, LPC2132/01 LPC2134, LPC2134/01 LPC2136, LPC2136/01 LPC2138, LPC2138/01
P0[31:0] P1[31:16] FAST GENERAL PURPOSE
TEST/DEBUG INTERFACE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
BRIDGE
ARM7 local INTERNAL SRAM CONTROLLER INTERNAL FLASH CONTROLLER
AMBA (Advanced High-performance Bus)
DECODER BRIDGE DIVIDER
8/16/32 SRAM
32/64/128/ 256/512 FLASH
(ARM peripheral bus) EINT[3:0] EXTERNAL INTERRUPTS SERIAL INTERFACES SCL0,1 SDA0,1 SCK0,1 MOSI0,1 MISO0,1 SSEL0,1 TXD0,1 RXD0,1 DSR1(1),CTS1(1) RTS1(1), DTR1(1) DCD1(1), RI1(1) RTCX1 P0[31:0] P1[31:16] REAL TIME CLOCK GENERAL PURPOSE WATCHDOG TIMER PWM[6:1] PWM0 SYSTEM CONTROL RTCX2 VBAT
AD0[7:0] AD1[7:0](1)
CAPTURE/ COMPARE TIMER 0/TIMER
SERIAL INTERFACES
CONVERTERS 1(1) UART0/UART1 CONVERTER(2)
AOUT(2)
002aab067
LPC2134/36/38 only. LPC2132/34/36/38 only. Pins shared with GPIO.
Block diagram
LPC2131_32_34_36_38_3 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Pinning information
Pinning
P0.19/MAT1.2/MOSI1/CAP1.2 P0.18/CAP1.3/MISO1/MAT1.3 P0.20/MAT1.3/SSEL1/EINT3
P1.30/TMS
P1.27/TDO
P1.29/TCK
P1.28/TDI
RESET
XTAL1
XTAL2
VREF
P0.23
P0.21/PWM5/CAP1.3 P0.22/CAP0.0/MAT0.0 RTCX1 P1.19/TRACEPKT3 RTCX2 VDDA P1.18/TRACEPKT2 P0.25/AD0.4
VBAT
VSSA
P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/EINT2 P1.21/PIPESTAT0 P0.14/EINT1/SDA1 P1.22/PIPESTAT1 P0.13/MAT1.1 P0.12/MAT1.0 P0.11/CAP1.1/SCL1 P1.23/PIPESTAT2 P0.10/CAP1.0 P0.9/RXD1/PWM6/EINT3 P0.8/TXD1/PWM4
LPC2131 LPC2131/01
P0.26/AD0.5 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 P1.16/TRACEPKT0
P0.31
P0.0/TXD0/PWM1
P1.31/TRST
P0.1/RXD0/PWM3/EINT0
P0.2/SCL0/CAP0.0
P1.26/RTCK
P0.3/SDA0/MAT0.0/EINT1
P0.4/SCK0/CAP0.1/AD0.6
P1.25/EXTIN0
P0.5/MISO0/MAT0.1/AD0.7
P0.6/MOSI0/CAP0.2
P0.7/SSEL0/PWM2/EINT2
P1.24/TRACECLK
002aab068
LPC2131 LQFP64 pinning
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
P0.19/MAT1.2/MOSI1/CAP1.2
P0.18/CAP1.3/MISO1/MAT1.3
P0.20/MAT1.3/SSEL1/EINT3
P1.30/TMS
P1.27/TDO
P1.29/TCK
P1.28/TDI
RESET
XTAL1
XTAL2
VREF
P0.23
P0.21/PWM5/CAP1.3 P0.22/CAP0.0/MAT0.0 RTCX1 P1.19/TRACEPKT3 RTCX2 VDDA P1.18/TRACEPKT2 P0.25/AD0.4/AOUT
VBAT
VSSA
P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/EINT2 P1.21/PIPESTAT0 P0.14/EINT1/SDA1 P1.22/PIPESTAT1 P0.13/MAT1.1 P0.12/MAT1.0 P0.11/CAP1.1/SCL1 P1.23/PIPESTAT2 P0.10/CAP1.0 P0.9/RXD1/PWM6/EINT3 P0.8/TXD1/PWM4
LPC2132 LPC2132/01
P0.26/AD0.5 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 P1.16/TRACEPKT0
P0.31
P0.0/TXD0/PWM1
P1.31/TRST
P0.1/RXD0/PWM3/EINT0
P0.2/SCL0/CAP0.0
P1.26/RTCK
P0.3/SDA0/MAT0.0/EINT1
P0.4/SCK0/CAP0.1/AD0.6
P1.25/EXTIN0
P0.5/MISO0/MAT0.1/AD0.7
P0.6/MOSI0/CAP0.2
P0.7/SSEL0/PWM2/EINT2
P1.24/TRACECLK
002aab406
LPC2132 LQFP64 configuration
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
P0.19/MAT1.2/MOSI1/CAP1.2
P0.18/CAP1.3/MISO1/MAT1.3
P0.20/MAT1.3/SSEL1/EINT3
P1.30/TMS
P1.27/TDO
P1.29/TCK
P1.28/TDI
RESET
XTAL1
XTAL2
VREF
P0.23
P0.21/PWM5/AD1.6/CAP1.3 P0.22/AD1.7/CAP0.0/MAT0.0 RTCX1 P1.19/TRACEPKT3 RTCX2 VDDA P1.18/TRACEPKT2 P0.25/AD0.4/AOUT
VBAT
VSSA
P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2/AD1.5 P1.21/PIPESTAT0 P0.14/DCD1/EINT1/SDA1 P1.22/PIPESTAT1 P0.13/DTR1/MAT1.1/AD1.4 P0.12/DSR1/MAT1.0/AD1.3 P0.11/CTS1/CAP1.1/SCL1 P1.23/PIPESTAT2 P0.10/RTS1/CAP1.0/AD1.2 P0.9/RXD1/PWM6/EINT3 P0.8/TXD1/PWM4/AD1.1
P0.26/AD0.5 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 P1.16/TRACEPKT0
LPC2134, LPC2134/01 LPC2136, LPC2136/01 LPC2138, LPC2138/01
P0.31
P0.0/TXD0/PWM1
P1.31/TRST
P0.1/RXD0/PWM3/EINT0
P0.2/SCL0/CAP0.0
P1.26/RTCK
P0.3/SDA0/MAT0.0/EINT1
P0.4/SCK0/CAP0.1/AD0.6
P1.25/EXTIN0
P0.5/MISO0/MAT0.1/AD0.7
P0.6/MOSI0/CAP0.2/AD1.0
P0.7/SSEL0/PWM2/EINT2
P1.24/TRACECLK
002aab407
LPC2134/36/38 LQFP64 configuration
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
P0.19/MAT1.2/MOSI1/CAP1.2
P0.18/CAP1.3/MISO1/MAT1.3
P0.20/MAT1.3/SSEL1/EINT3
P1.30/TMS
P1.27/TDO
P1.29/TCK
P1.28/TDI
RESET
XTAL1
XTAL2
VREF
P0.23
terminal index area P0.21/PWM5/AD1.6/CAP1.3 P0.22/AD1.7/CAP0.0/MAT0.0 RTXC1 P1.19/TRACEPKT3 RTXC2 VDDA P1.18/TRACEPKT2 P0.25/AD0.4/AOUT
VBAT P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2/AD1.5 P1.21/PIPESTAT0 P0.14/DCD1/EINT1/SDA1 P1.22/PIPESTAT1 P0.13/DTR1/MAT1.1/AD1.4 P0.12/DSR1/MAT1.0/AD1.3 P0.11/CTS1/CAP1.1/SCL1 P1.23/PIPESTAT2 P0.10/RTS1/CAP1.0/AD1.2 P0.9/RXD1/PWM6/EINT3 P0.8/TXD1/PWM4/AD1.1 P1.24/TRACECLK
002aab943
Koninklijke Philips Electronics N.V. 2006. rights reserved.
VSSA
P0.6/MOSI0/CAP0.2/AD1.0
LPC2132/2138
P0.26/AD0.5 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 P1.16/TRACEPKT0 P0.31 P0.0/TXD0/PWM1 P1.31/TRST P0.1/RXD0/PWM3/EINT0 P0.2/SCL0/CAP0.0 P1.26/RTCK P0.3/SDA0/MAT0.0/EINT1 P0.4/SCK0/CAP0.1/AD0.6 P1.25/EXTIN0 P0.5/MISO0/MAT0.1/AD0.7 P0.7/SSEL0/PWM2/EINT2
Transparent view
LPC2132/38 HVQFN64 configuration
LPC2131_32_34_36_38_3
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit port with individual direction controls each bit. Total pins Port used general purpose bidirectional digital I/Os while P0.31 output only pin. operation port pins depends upon function selected connect block. P0.24 available. P0.0/TXD0/ PWM1 P0.1/RXD0/ PWM3/EINT0 19[1] 21[2] P0.2/SCL0/ CAP0.0 P0.3/SDA0/ MAT0.0/EINT1 22[3] 26[3] P0.4/SCK0/ CAP0.1/AD0.6 27[4] P0.5/MISO0/ MAT0.1/AD0.7 29[4] P0.6/MOSI0/ CAP0.2/AD1.0 30[4] P0.7/SSEL0/ PWM2/EINT2 31[2] P0.8/TXD1/ PWM4/AD1.1 33[4] P0.9/RXD1/ PWM6/EINT3 34[2] P0.10/RTS1/ CAP1.0/AD1.2 35[4] TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input. SCL0 I2C0 clock input/output. Open drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel SDA0 I2C0 data input/output. Open drain output (for I2C-bus compliance). MAT0.0 Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel AD0.6 input This analog input always connected pin. MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer channel AD0.7 input This analog input always connected pin. MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel AD1.0 input This analog input always connected pin. Available LPC2134/36/38 only. SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output AD1.1 input This analog input always connected pin. Available LPC2134/36/38 only. RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. Available LPC2134/36/38. CAP1.0 Capture input Timer channel AD1.2 input This analog input always connected pin. Available LPC2134/36/38 only.
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued 37[3] Type 38[4] Description CTS1 Clear Send input UART1. Available LPC2134/36/38. CAP1.1 Capture input Timer channel SCL1 I2C1 clock input/output. Open drain output (for I2C-bus compliance) DSR1 Data Ready input UART1. Available LPC2134/36/38. MAT1.0 Match output Timer channel AD1.3 input This analog input always connected pin. Available LPC2138 only. DTR1 Data Terminal Ready output UART1. Available LPC2134/36/38. MAT1.1 Match output Timer channel AD1.4 input This analog input always connected pin. Available LPC2134/36/38 only. DCD1 Data Carrier Detect input UART1. Available LPC2134/36/38. EINT1 External interrupt input. SDA1 I2C1 data input/output. Open drain output (for I2C-bus compliance). Ring Indicator input UART1. Available LPC2134/36/38. EINT2 External interrupt input. AD1.5 input This analog input always connected pin. Available LPC2134/36/38 only. EINT0 External interrupt input. MAT0.2 Match output Timer channel CAP0.2 Capture input Timer channel CAP1.2 Capture input Timer channel SCK1 Serial Clock SSP. Clock output from master input slave. MAT1.2 Match output Timer channel CAP1.3 Capture input Timer channel MISO1 Master Slave SSP. Data input master data output from slave. MAT1.3 Match output Timer channel MAT1.2 Match output Timer channel MOSI1 Master Slave SSP. Data output from master data input slave. CAP1.2 Capture input Timer channel MAT1.3 Match output Timer channel SSEL1 Slave Select SSP. Selects interface slave. EINT3 External interrupt input. PWM5 Pulse Width Modulator output AD1.6 input This analog input always connected pin. Available LPC2134/36/38 only. CAP1.3 Capture input Timer channel
P0.11/CTS1/ CAP1.1/SCL1
P0.12/DSR1/ MAT1.0/AD1.3
P0.13/DTR1/ MAT1.1/AD1.4
39[4]
P0.14/DCD1/ EINT1/SDA1
41[3]
P0.15/RI1/ EINT2/AD1.5
45[4]
P0.16/EINT0/ 46[2] MAT0.2/CAP0.2
P0.17/CAP1.2/ SCK1/MAT1.2
47[1]
P0.18/CAP1.3/ MISO1/MAT1.3
53[1]
P0.19/MAT1.2/ MOSI1/CAP1.2
54[1]
P0.20/MAT1.3/ SSEL1/EINT3
55[2]
P0.21/PWM5/ AD1.6/CAP1.3
1[4]
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued Type Description AD1.7 input This analog input always connected pin. Available LPC2134/36/38 only. CAP0.0 Capture input Timer channel MAT0.0 Match output Timer channel General purpose digital input/output pin. AD0.4 input This analog input always connected pin. AOUT output. available LPC2131. AD0.5 input This analog input always connected pin. AD0.0 input This analog input always connected pin. CAP0.1 Capture input Timer channel MAT0.1 Match output Timer channel AD0.1 input This analog input always connected pin. CAP0.2 Capture input Timer channel MAT0.2 Match output Timer channel AD0.2 input This analog input always connected pin. CAP0.3 Capture input Timer channel MAT0.3 Match output Timer channel AD0.3 input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer channel General purpose digital output only pin. Important: This MUST externally pulled when RESET JTAG port will disabled.
P0.22/AD1.7/ 2[4] CAP0.0/MAT0.0
P0.23 P0.25/AD0.4/ AOUT P0.26/AD0.5
58[1] 9[5] 10[4]
P0.27/AD0.0/ 11[4] CAP0.1/MAT0.1
P0.28/AD0.1/ CAP0.2/MAT0.2
13[4]
P0.29/AD0.2/ CAP0.3/MAT0.3
14[4]
P0.30/AD0.3/ EINT3/CAP0.0
15[4]
P0.31
17[6]
P1.0 P1.31
Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through port available. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. TRACESYNC while RESET enables pins P1.25:16 operate Trace port after reset. PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. PIPESTAT2 Pipeline Status, Standard port with internal pull-up.
P1.16/ TRACEPKT0 P1.17/ TRACEPKT1 P1.18/ TRACEPKT2 P1.19/ TRACEPKT3 P1.20/ TRACESYNC P1.21/ PIPESTAT0 P1.22/ PIPESTAT1 P1.23/ PIPESTAT2
16[6] 12[6] 8[6] 4[6] 48[6]
44[6] 40[6] 36[6]
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued 32[6] 28[6] 24[6] Type Description TRACECLK Trace Clock. Standard port with internal pull-up. EXTIN0 External Trigger Input. Standard with internal pull-up. RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. RTCK while RESET enables pins P1.31:26 operate Debug port after reset. Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Input oscillator circuit. Output from oscillator circuit. Ground: reference. Analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. power supply: This power supply voltage core ports. Analog power supply: This should nominally same voltage should isolated minimize noise error. This voltage used power on-chip PLL. reference: This should nominally same voltage should isolated minimize noise error. Level this used reference convertor(s). power supply: this supplies power RTC.
P1.24/ TRACECLK P1.25/EXTIN0 P1.26/RTCK
P1.27/TDO P1.28/TDI P1.29/TCK P1.30/TMS P1.31/TRST RESET
64[6] 60[6] 56[6] 52[6] 20[6] 57[7]
XTAL1 XTAL2 RTXC1 RTXC2 VSSA VDDA
62[8] 61[8] 3[8] 5[8]
VREF
VBAT
tolerant providing digital functions with levels hysteresis slew rate control. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant providing digital (with levels hysteresis slew rate control) analog output function. When configured output, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value ranges from tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip flash program memory
LPC2131/32/34/36/38 incorporate flash memory system respectively. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port. application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When LPC2131/32/34/36/38 on-chip bootloader used, 32/64/128/256/500 flash memory available user code. LPC2131/32/34/36/38 flash memory provides minimum 100000 erase/write cycles years data-retention.
On-chip static
On-chip static used code and/or data storage. SRAM accessed 8-bit, 16-bit, 32-bit. LPC2131, LPC2132/34, LPC2136/38 provide static respectively.
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Memory
LPC2131/32/34/36/38 memory incorporates several distinct regions, shown Figure addition, interrupt vectors re-mapped allow them reside either flash memory (the default) on-chip static RAM. This described Section 6.18 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xE000 0000
RESERVED ADDRESS SPACE
0xC000 0000
0x8000 0000 BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY RESERVED ADDRESS SPACE 0x4001 8000 0x4000 7FFF TOTAL ON-CHIP STATIC (LPC2136/38) TOTAL ON-CHIP STATIC (LPC2132/34) TOTAL ON-CHIP STATIC (LPC2131) 0x4000 4000 0x4000 3FFF 0x4000 2000 0x4000 1FFF 0x4000 0000 RESERVED ADDRESS SPACE TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2138) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2136) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2134) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2132) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2131) 0x0008 0000 0x0007 FFFF 0x0004 0000 0x0003 FFFF 0x0002 0000 0x0001 FFFF 0x0001 0000 0x0000 FFFF 0x0000 8000 0x0000 7FFF 0x0000 0000
002aab069
LPC2131/32/34/36/38 memory
LPC2131_32_34_36_38_3
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes them Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core TIMER0 TIMER1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only EmbeddedICE, DbgCommRX EmbeddedICE, DbgCommTX Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) channel
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Interrupt sources .continued Flag(s) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) (Available LPC2134/36/38 only) channel
Table Block UART1
PWM0 I2C0 SPI0
Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) Capture (CR0, CR1, CR2, CR3) (state change) SPIF, MODF FIFO least half empty (TXRIS) FIFO least half full (RXRIS) Receive Timeout (RTRIS) Receive Overrun (RORRIS)
System Control
Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3)
I2C1
(state change) Brown Detect (Available LPC2134/36/38 only)
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
General purpose parallel Fast
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.7.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset.
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
6.7.2 Fast features available LPC213x/01 only
Fast registers located local fastest possible timing. GPIO registers byte addressable. Entire port value written instruction. Mask registers allow single instruction clear number bits port.
10-bit
LPC2131/32 contain LPC2134/36/38 contain ADCs. These converters single 10-bit successive approximation ADCs with eight multiplexed channels.
6.8.1 Features
Measurement range Each converter capable performing more than 400000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal. Global Start command both converters (LPC2134/36/38 only).
6.8.2 features available LPC213x/01 only
Every analog input dedicated result register reduce interrupt overhead. Every analog input generate interrupt once conversion completed. 10-bit
This peripheral available LPC2132/34/36/38 only. enables LPC2132/34/36/38 generate variable analog output.
6.9.1 Features
10-bit digital analog converter. Buffered output. Power-down mode available. Selectable speed versus power.
6.10 UARTs
LPC2131/32/34/36/38 each contain UARTs. addition standard transmit receive data lines, LPC2134/36/38 UART1 also provides full modem control handshake interface.
6.10.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points
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Product data sheet
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Built-in baud rate generator. Standard modem interface signals included UART1. (LPC2134/36/38 only) LPC2131/32/34/36/38 transmission FIFO control enables implementation
software (XON/XOFF) flow control both UARTs hardware (CTS/RTS) flow control LPC2134/36/38 UART1 only.
6.10.2 UART features available LPC213x/01 only
Fractional baud rate generator enables standard baud rates such 115200
achieved with crystal frequency above MHz.
Auto-bauding. Auto-CTS/RTS flow-control fully implemented hardware (LPC2134/36/38 only). 6.11 I2C-bus serial controller
LPC2131/32/34/36/38 each contain I2C-bus controllers. I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with capability both receive send information (such memory)). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected This I2C-bus implementation supports rates kbit/s (Fast I2C).
6.11.1 Features
Standard compliant interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 6.12 serial controller
LPC2131/32/34/36/38 each contain controller. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
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Product data sheet
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
6.12.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate.
6.13 serial controller
LPC2131/32/34/36/38 each contain Serial Synchronous Port controller (SSP). controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. However, only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. Often only these data flows carries meaningful data.
6.13.1 Features
Compatible with Motorola SPI, 4-wire National Semiconductor Microwire
buses.
Synchronous Serial Communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits bits frame.
6.14 General purpose timers/external event counters
Timer/Counter designed count cycles peripheral clock (PCLK) externally supplied clock, optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them. given time only peripheral's capture inputs selected external event signal source, i.e., timer's clock. rate external events that successfully counted limited PCLK/2. this configuration, unused capture lines selected regular timer capture inputs.
6.14.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. External Event Counter timer operation. Four 32-bit capture channels timer/counter that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match.
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Single-chip 16/32-bit microcontrollers
Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer/counter corresponding match registers, with
following capabilities: match. HIGH match. Toggle match. nothing match.
6.15 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.15.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples Tcy(PCLK)
6.16 Real-time clock
Real-Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.16.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
either dedicated oscillator input clock derived from
external crystal/oscillator input XTAL1. Programmable Reference Clock Divider allows fine adjustment RTC.
Dedicated power supply connected battery main
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
6.17 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2131/32/34/36/38. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.17.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
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Product data sheet
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Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.18 System control
6.18.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal range with external oscillator MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.18.2 "PLL" additional information.
6.18.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.18.3 Reset wake-up timer
Reset sources LPC2131/32/34/36/38: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip reset source starts wake-up timer (see wake-up timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up timer.
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
wake-up timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.18.4 Brownout detector
LPC2131/32/34/36/38 include 2-stage monitoring voltage pins. this voltage falls below asserts interrupt signal Vectored Interrupt Controller. This signal enabled interrupt; not, software monitor signal reading dedicated register. second stage low-voltage detection asserts reset inactivate LPC2131/32/34/36/38 when voltage pins falls below This reset prevents alteration flash operation various elements chip would otherwise become unreliable voltage. circuit maintains this reset down below which point circuitry maintains overall reset. Both thresholds include some hysteresis. normal operation, this hysteresis allows detection reliably interrupt, regularly-executed event loop sense condition. Features available only LPC213x/01 parts include ability power-down mode, turn control when will reset LPC213x/01 microcontroller. This used further reduce power consumption when power mode (such Power Down) invoked.
6.18.5 Code security
This feature LPC2131/32/34/36/38 allow application control whether debugged protected from observation. after reset on-chip bootloader detects valid checksum flash reads 0x8765 4321 from address 0x1FC flash, debugging will disabled thus code flash will protected from observation. Once debugging disabled, enabled only performing full chip erase using ISP.
6.18.6 External interrupt inputs
LPC2131/32/34/36/38 include nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.18.7 Memory Mapping Control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
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Product data sheet
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
6.18.8 Power Control
LPC2131/32/34/36/38 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Selecting external clock instead PCLK clock-source on-chip will enable microcontroller have active during Power-down mode. Power-down current increased with active. However, significantly lower than Idle mode. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.18.9
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.19 Emulation debugging
LPC2131/32/34/36/38 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.19.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core.
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Single-chip 16/32-bit microcontrollers
core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic.
6.19.2 Embedded trace
Since LPC2131/32/34/36/38 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
6.19.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2131/32/34/36/38 contain specific configuration RealMonitor software programmed into on-chip flash memory.
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDDA Vi(VBAT) Vi(VREF) Parameter supply voltage (core external rail) analog supply voltage input voltage VBAT input voltage VREF analog input voltage input voltage related pins tolerant pins; only valid when supply voltage present other pins Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based package heat transfer, device power consumption human body model pins
Conditions
-0.5 -0.5
+3.6 +4.6 +4.6 +4.6 +5.1 +6.0
Unit
-0.5 -0.5 -0.5 -0.5
-0.5
0.5[3] 100[4] 100[4] +125
supply ground
Vesd
electrostatic discharge voltage
-4000
+4000
following applies Limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. exceed peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
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Product data sheet
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDDA Vi(VBAT) Vi(VREF) Ilatch Vhys IOHS IOLS IDD(act) Parameter supply voltage (core external rail) analog supply voltage input voltage VBAT input voltage VREF LOW-level input current HIGH-level input current OFF-state output current latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit current LOW-level short-circuit current pull-down current pull-up current active mode supply current VDDA Tamb code
Conditions
2.0[2]
Typ[1]
Unit
Standard port pins, RESET, RTCK pull-up VDD; no-pull-down VDD; pull-up/down -(0.5VDD) (1.5VDD); configured provide digital function output active
[3][4][5]
while(1){}
executed from flash, active peripherals CCLK CCLK IDD(pd) Power-down mode supply Tamb current Tamb
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Product data sheet
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Single-chip 16/32-bit microcontrollers
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol IBATpd Parameter Conditions Typ[1] Unit Power-down mode battery clock supply current[10] (from RTXC pins); Tamb Vi(VBAT) Vi(VBAT) Vi(VBAT) Vi(VBAT) IBATact active mode battery supply current[10] CCLK MHz; PCLK MHz; PCLK enabled RTCK; clock (from RTXC pins); Tamb Vi(VBAT) Vi(VBAT) Vi(VBAT) IBATact(opt) optimized active mode battery supply current[10][11] PCLK disabled RTCK PCONP register; clock (from RTXC pins); Tamb Vi(VBAT) CCLK CCLK CCLK CCLK I2C-bus Vhys pins HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTXC1) Vo(RTXC2) input voltage XTAL1 output voltage XTAL2 input voltage RTXC1 output voltage RTXC2
[13] [13] [12] [12]
0.7VDD
0.5VDD
0.3VDD
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode.
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Product data sheet
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LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
supply voltages must present. 3-state outputs into 3-state mode when grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition Applies P1.16 P1.25.
[10] VBAT. [11] Optimized battery consumption. [12] input threshold voltage I2C-bus pins meets I2C-bus specification, input voltage below will recognized logic while input voltage above will recognized logic [13] VSS.
Table static characteristics VDDA Tamb unless otherwise specified; frequency MHz. Symbol EL(adj)
Parameter analog input voltage analog input capacitance
Conditions
[1][2]
VDDA ±0.5
Unit
differential linearity error VSSA VDDA integral non-linearity offset error gain error absolute error VSSA VDDA VSSA VDDA VSSA VDDA VSSA VDDA
monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral no-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDDA VSSA 1024
002aac046
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Dynamic characteristics
Table Dynamic characteristics Tamb commercial applications, over specified ranges.[1] Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL tr(o) tf(o) tf(o)
Parameter oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time output rise time output fall time output fall time
Conditions
Tcy(clk) Tcy(clk)
Typ[2]
Unit
Port pins (except P0.2 P0.3)
I2C-bus pins (P0.2 P0.3) Cb[3]
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Timing
0.45
0.2VDD 0.2VDD tCHCL tCLCX Tcy(clk)
002aaa907
tCHCX tCLCH
External clock timing
LPC2138 power consumption measurements
(mA)
002aab404
frequency (MHz)
Test conditions: code executed from flash; peripherals enabled PCONP register; PCLK CCLK/4. (max) (typical) (typical)
IDD(act) measured different frequencies (CCLK) temperatures
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
(mA)
002aab403
frequency (MHz)
Test conditions: Idle mode entered executing code from flash; peripherals enabled PCONP register; PCLK CCLK/4. (max) (typical) (typical)
idle measured different frequencies (CCLK) temperatures
(µA)
002aab405
temp °(C)
Test conditions: Power-down mode entered executing code from flash; peripherals enabled PCONP register. (max) (typical)
IDD(pd) measured different temperatures
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Package outline
LQFP64: plastic profile quad flat package; leads; body SOT314-2
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 10.1 0.75 0.45 0.12 1.45 1.05 1.45 1.05
12.15 12.15 11.85 11.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT314-2 REFERENCES 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT314-2 (LQFP64)
LPC2131_32_34_36_38_3 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
HVQFN64: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
SOT804-2
terminal index area
detail
terminal index area DIMENSIONS original dimensions) UNIT max. 0.05 0.00 0.80 0.65 0.30 0.18 9.05 8.95 8.95 8.55 7.25 6.95
scale 9.05 8.95 8.95 8.55 7.25 6.95 0.05 0.05
OUTLINE VERSION SOT804-2
REFERENCES -JEDEC MO-220 JEITA
EUROPEAN PROJECTION
ISSUE DATE 04-03-25
Package outline SOT804-2 (HVQFN64)
LPC2131_32_34_36_38_3 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Abbreviations
Table Acronym FIFO GPIO JTAG SRAM UART Acronym list Description Analog-to-Digital Converter BrownOut Detection Central Processing Unit Digital-to-Analog Converter Debug Communications Channel First First General Purpose Input/Output Joint Test Action Group Phase-Locked Loop Power-On Reset Pulse Width Modulator Random Access Memory Serial Peripheral Interface Static Random Access Memory Synchronous Serial Port Universal Asynchronous Receiver/Transmitter VLSI Peripheral
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Revision history
Table Revision history Release date 20060921 Data sheet status Product data sheet Change notice Supersedes LPC2131_32_34_36_38_2 Document LPC2131_32_34_36_38_3 Modifications:
Changed data sheet status Product Section "Features"; updated with list enhancements introduced LPC213x/01 Section "Ordering information"; updated with parts Table "Pin description"; updated (AD1.x availability) Table "Limiting values"; added electrostatic discharge voltage information Section "Pin connect block"; details about PINSEL registers removed Section "General purpose parallel Fast I/O"; updated with LPC213x/01 details Section "10-bit ADC"; updated with LPC213x/01 details Section 6.10 "UARTs"; updated with LPC213x/01 details Section 6.18.4 "Brownout detector"; updated with LPC213x/01 details. Preliminary data sheet Preliminary data sheet LPC2131_2132_2138_1
LPC2131_32_34_36_38_2 LPC2131_2132_2138_1
20050318 20041118
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet
13.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Philips Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Philips Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Philips Semiconductors accepts liability inclusion and/or Philips Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Philips Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Philips Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Philips Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
13.3 Disclaimers
General Information this document believed accurate reliable. However, Philips Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Philips Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Philips Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Philips Semiconductors product reasonably expected
13.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark Koninklijke Philips Electronics N.V.
Contact information
additional information, please visit: sales office addresses, send email
LPC2131_32_34_36_38_3
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Product data sheet
Rev. September 2006
Philips Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
Contents
6.5.1 6.7.1 6.7.2 6.8.1 6.8.2 6.9.1 6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 General description Features Enhancements brought LPC213x/01 devices features common LPC213x LPC213x/01 Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash program memory On-chip static RAM. Memory map. Interrupt controller Interrupt sources. connect block General purpose parallel Fast Features Fast features available LPC213x/01 only 10-bit Features features available LPC213x/01 only 10-bit Features UARTs Features UART features available LPC213x/01 only I2C-bus serial controller Features serial controller. Features serial controller Features General purpose timers/external event counters Features Watchdog timer. Features Real-time clock Features Pulse width modulator Features 6.18 6.18.1 6.18.2 6.18.3 6.18.4 6.18.5 6.18.6 6.18.7 6.18.8 6.18.9 6.19 6.19.1 6.19.2 6.19.3 13.1 13.2 13.3 13.4 System control Crystal oscillator. PLL. Reset wake-up timer Brownout detector Code security External interrupt inputs Memory Mapping Control. Power Control. Emulation debugging. EmbeddedICE Embedded trace. RealMonitor Limiting values Static characteristics Dynamic characteristics Timing LPC2138 power consumption measurements Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers. Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
Koninklijke Philips Electronics N.V. 2006.
rights reserved.
more information, please visit: sales office addresses, email Date release: September 2006 Document identifier: LPC2131_32_34_36_38_3

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