Application Note Altera® Express-to-DDR2 SDRAM reference design p

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Express-to-DDR2 SDRAM Reference Design
Application Note
Altera® Express-to-DDR2 SDRAM reference design provides sample interface between Altera Express MegaCore® function 64-bit, 256-MByte DDR2 SDRAM memory. Altera offers this reference design potential users demonstrate operation Altera's Express MegaCore function. reference design enables users evaluate Express MegaCore function integration into Altera FPGA. reference design following features:
Supports Express (PCIe) root complex PCIe point memory read write transactions Supports PCIe point PCIe root complex read write transactions Uses dual-port FIFO buffer function from library parameterized modules (LPM) Uses Express MegaCore function Uses DDR2 SDRAM Controller MegaCore function Uses Stratix® field-programmable gate array (FPGA) with internal transceivers
This document contains following topics:
General Description Reference Design Overview Functional Description Interface Signal Descriptions Registers Using Reference Design Appendix Design Limitations References
General Description
reference design sample application that connects Altera Express MegaCore function DDR2 SDRAM memory through reference design interface circuitry. Altera provides Stratix Express Development Kit, which includes Express form-factored printed circuit board, which reference design uses hardware platform. Altera also provides software that includes driver, programming information, graphic user interface (GUI) conduct sample operations.
Altera Corporation AN-431-1.0
Preliminary
Express-to-DDR2 SDRAM Reference Design
Altera Express-to-DDR2 SDRAM reference design represents example typical user application that interfaces system side Altera Express MegaCore function; line, external, side Express MegaCore function connects PCIe connector. Specifically, this reference design provides interface logic between Altera Express MegaCore function DDR2 SDRAM controller that enables accesses external DDR2 SDRAM memory through PCIe bus. Express MegaCore function operate PCIe slave master DDR2 SDRAM access. When Express MegaCore function operates PCIe master initiator), engine reference design initiates transaction, monitors status, manages progress data transfers. When Express MegaCore function operates PCIe slave target), PCIe root complex host system initiates memory read/write transactions Express MegaCore function FPGA Express MegaCore function transfers data DDR2 SDRAM.
Reference Design Overview
Figure shows high-level block diagram reference design. reference design comprises Express MegaCore function, DDR2 SDRAM controller, reference design application logic between two. This sample application logic includes application logic block (labeled Top), application logic block (labeled Top). application logic functions connect PCIe through Express MegaCore function memory through DDR2 SDRAM controller block. This section provides overview following reference design components:
Application Logic Application Logic Engine Express MegaCore Function DDR2 SDRAM Controller
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Altera Corporation
Reference Design Overview
Figure Block Diagram
Clock Domain Boundary
Command FIFO Tx_dma_rd 128x32 Read Bypass FIFO 128x32
Data FIFO
Tx_pcie
64x128
Tx_ddr_resp
DDR2 Memory DDR2 Controller
32x32
Read PCIe MegaCore Function
PCIe Link
50x32 Pending Read FIFO Rx_ddr 72x32 Command FIFO 72x128 Data FIFO Rx_pcie
Clock Domain Boundary
Application Logic
application logic block controls DDR2 SDRAM controller interface, receiving data from DDR2 SDRAM, generating packets send Express MegaCore function. master mode, also interacts with registers generate reads send Express MegaCore function. Data flows through application block from DDR2 SDRAM memory PCIe bus.
Root-Complex-Initiated Read Request
During root-complex-initiated read request, application logic performs following functions:
Receives data from DDR2 SDRAM Forms PCIe packet when enough data accumulates Generates PCIe READ COMPLETION packet Sends PCIe READ COMPLETION packet with data Express MegaCore function
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Express-to-DDR2 SDRAM Reference Design
End-Point-Initiated Write Request
During end-point-initiated write request, application logic performs following functions:
Receives data from DDR2 SDRAM Forms PCIe packet when enough data accumulates Generates PCIe WRITE packet Sends PCIe WRITE packet with data Express MegaCore function
End-Point-Initiated Read Request
During end-point-initiated read request, control logic performs following functions:
Generates PCIe READ packet Sends PCIe READ packet Express MegaCore function
Application Logic Components
application logic comprises following components:
Read Requests Generation Block (Tx_dma_rd) DDR2 Read Response State Machine (Tx_ddr_resp) PCIe Packet Generation Block (Tx_pcie) Read Command FIFO Buffer (128 Data FIFO Buffer 128) Read Bypass FIFO Buffer (128
data path FIFOs buffer data transferred between DDR2 SDRAM memory PCIe bus. FIFO buffers synchronize data crossing PCIe DDR2 clock domains. Read Requests Generation Block (Tx_dma_rd) read requests generation block (Tx_dma_rd) monitors register. When directed dma_start signal when ready start transaction, Tx_dma_rd uses information from registers generate more read requests them command FIFO.
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Reference Design Overview
DDR2 Read Response State Machine (Tx_ddr_resp) DDR2 read response state machine (Tx_ddr_resp) monitors DDR2 SDRAM controller system-side data data valid signal. also checks Pending Read FIFO buffer pending read requests. there pending read request, uses information from Pending Read FIFO determine much data expect from DDR2 SDRAM controller. also determines when where send DDR2 data when available. PCIe Packet Generation Block (Tx_pcie) PCIe packet generation block draws commands from command FIFO read bypass FIFO. Based command information, generates Express MegaCore function system-side signals that initiate requests read completions send descriptors data Express MegaCore function. Read Read stores read requests information. Based stored information, works with Rx_ddr block determine where send read completion data when ready written DDR2 SDRAM. Command FIFO Buffer (128 command FIFO buffer stores PCIe commands generated Tx_dma_rd block Tx_ddr_resp block. Tx_pcie block receives PCIe commands after they cross from DDR2 clock domain PCIe clock domain. Data FIFO Buffer 128) data FIFO buffer provides buffer space data transferred from DDR2 SDRAM controller Express MegaCore function. During read completion during write transactions, DDR2 SDRAM controller returns requested data, which enters into this FIFO buffer. DDR2 response control module, Tx_ddr_resp, controls write operations this buffer PCIe control module, Tx_pcie, controls read operations from this buffer. data FIFO buffer size bits ensure that store whole PCIe packet, needed, before sending packet PCIe controller, Tx_pcie. Unlike data FIFO buffer, this FIFO buffer always operates 64-bit wide buffer. read write from this FIFO buffer always occurs bits time.
Altera Corporation
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Express-to-DDR2 SDRAM Reference Design
Read Bypass FIFO Buffer (128 read bypass FIFO buffer provides buffer space read requests when lack transmit credits prevent Tx_pcie block from sending read requests Express MegaCore function. When Express MegaCore function ready accept read requests, read bypass FIFO buffer temporarily store read requests enable Tx_pcie block send other requests meantime.
Application Logic
application logic block receives PCIe packets from Express MegaCore function transfers data DDR2 SDRAM controller. application logic controls data flow from PCIe DDR2 SDRAM memory.
Root Complex Initiated Memory Write
During root complex initiated memory write, PCIe-DDR2 control logic performs following functions:
Receives decodes PCIe write packet Writes data into data FIFO buffer Interacts with DDR2 SDRAM controller read data from data FIFO buffer then write into DDR2 SDRAM memory
Root Complex Initiated Memory Read
During root complex initiated memory read, application logic performs following functions:
Receives decodes PCIe read packet Interacts with DDR2 SDRAM controller fetch data from DDR2 SDRAM memory
Point Initiated Write
During point initiated write, application logic performs following functions:
Reads registers creates internal PCIe read request Interacts with DDR2 SDRAM controller fetch data from DDR2 SDRAM memory
Point Initiated Read
During point initiated read, application logic performs following functions:
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Reference Design Overview
Receives decodes PCIe read completion packet Writes data into data FIFO buffer Interacts with DDR2 SDRAM controller read data from data FIFO buffer then write into DDR2 SDRAM memory
Application Logic Components
application logic comprises following components:
PCIe Receiver Block (Rx_pcie) DDR2 Interface Logic (Rx_ddr) Command FIFO Buffer Data FIFO Buffer 128) Pending Read FIFO Buffer
data path FIFOs buffer data transferred between DDR2 SDRAM memory PCIe bus. FIFO buffers synchronize data crossing PCIe DDR2 clock domains. PCIe Receiver Block (Rx_pcie) PCIe receiver block performs three main functions:
Interface with Express MegaCore functionRx_pcie receives requests data from Express MegaCore function. decodes system-side signals from Express MegaCore function. extracts information from descriptor PCIe packet, which puts into command FIFO buffer pending read FIFO buffer. Manage access registersRx_pcie decodes descriptors PCIe packets. transaction targets registers, Rx_pcie terminates packet accesses registers. Initiate write transactionsRx_pcie monitors registers. When directed dma_start signal when ready start transaction, Rx_pcie uses information from registers generate more read requests, which loads into command FIFO pending read FIFO.
DDR2 Interface Logic (Rx_ddr) DDR2 interface logic draws commands from command FIFO. Based command FIFO information, Rx_ddr generates DDR2 controller system-side signals request DDR2 read write requests. DDR2 write requests, works with Read determine where write data DDR2 SDRAM memory.
Altera Corporation
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Express-to-DDR2 SDRAM Reference Design
Command FIFO Buffer command FIFO receives reformatted command from Rx_pcie block. converts commands from PCIe clock domain DDR2 clock domain transfers commands Rx_ddr block. Data FIFO Buffer 128) data FIFO buffer stores data transferred from PCIe DDR2 SDRAM memory. During write during read completion transactions, PCIe block, Rx_pcie, helps control data going into data FIFO buffer. DDR2 block, Rx_ddr, reads data from data FIFO buffer. upper bits from FIFO buffer byte-enables 64-bit data bus. read operations from data FIFO buffer always occur trunks bits with only bits stored into DDR2 SDRAM memory. Pending Read FIFO Buffer When receiving read request from Express MegaCore function, application logic also receives details about much completion data expect from DDR2 SDRAM memory where send read completion data when ready. application logic stores request details received command FIFO buffer pending read FIFO buffer. Tx_ddr_resp block reads from pending read FIFO buffer uses information state machine track read completion data coming back from DDR2 SDRAM controller.
Engine
engine interfaces with application logic, data path FIFO buffers, DDR2 SDRAM controller coordinate transfers from DDR2 SDRAM memory. engine consists following elements:
Control Logic Registers
Control Logic
control logic, distributed through application logic indicated dotted dash line Figure page performs following functions:
Initiates transaction DDR2 SDRAM memory Express MegaCore function
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Functional Description
Interacts with application logic state machines track operation status Monitors data path FIFO buffers current DDR2 SDRAM memory access Monitors registers instructions initiate transaction
Registers
Setting registers engine initiates transactions. These registers memory-mapped base address register BAR2 Express MegaCore function. Target transactions access registers through their memory-mapped addresses. registers require another master PCIe supply their contents. registers consist following elements:
PCIe lower address register (0x0) PCIe upper address register (0x4) Byte counter register (0x8) control status register (0xC) local address register (0x10)
Express MegaCore Function
Express MegaCore function connects system application logic side. other side, connects that connects PCIe link. Express MegaCore function performs PCIe functions physical layer, data link layer, transaction layer specified Express Specification.
DDR2 SDRAM Controller
DDR2 SDRAM controller interfaces with application logic system side off-chip DDR2 SDRAM memory other side. translates PCIe cycles DDR2 SDRAM access cycles, vice versa, based control signals from application logic.
Functional Description
This section describes operations various modules Express-to-DDR2 SDRAM reference design provides details following topics:
Transactions Targeting Reference Design Register Access Memory Mapping Transactions Initiated from Reference Design
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Express-to-DDR2 SDRAM Reference Design
Transactions Targeting Reference Design
Express MegaCore function receives requests completions from PCIe link embedded Interface Express (PIPE) implementation. Express MegaCore function PCIe application logic circuit, Rx_top Figure page together manage these requests. Express MegaCore function performs PCIe related functions, such parsing packet errors, multilane deskewing, checking Cyclic Redundancy Check (CRC), Link (LCRC), End-to-End (ECRC) errors, generating flow control packets, forth. After Express MegaCore function receives packet successfully, without errors, sends packet PCIe control logic, Rx_pcie. Rx_pcie logic decodes PCIe packet, receives associated data, any, then forwards request into command FIFO buffer data into data FIFO buffer. control logic DDR2 side, Rx_ddr Figure receives request data from FIFO buffers DDR2 clock domain, splits request into multiple DDR2 requests, sends requests DDR2 SDRAM controller. This section describes details following topics:
Packet Processing PCIe Target Memory Read PCIe Target Memory Write
Packet Processing
This section describes processing packet progresses from PIPE DDR2 SDRAM controller provides brief overview PCIe functions. further details, refer Express Compiler User Guide. Express MegaCore function implements Media Access Control (MAC) function with eight separate PIPE interfaces that connect eight Physical Coding Submodule (PCS) blocks implementing Express link. Each lane operates independently symbols arriving each lane appear skewed with respect other lanes. deskews lanes aligning characters each lane during link initialization. PCIe tolerate skew eight symbols between different lanes link. After lane deskewing completes, Physical Layer parses incoming packets passes them Data Link Layer (DLL) further processing.
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Functional Description
perform CRC, must first determine packet type examining framing symbol. Start-DLLP-Packet (SDP) framing symbol indicates Data Link Layer Packet (DLLP). Start-TLP-Packet (STP) framing symbol indicates Transaction Layer Packet (TLP). DLLPs require 16-bit TLPs require 32-bit LCRC. error detected LCRC indicates corrupted packet requests retry from remote device scheduling negative acknowledgement (NAK) transmission transmit side link. succeeds, then examines sequence number packet correct match what expected. match indicates valid packet accepts further processing. detects sequence number discontinuity, requests retry from remote device scheduling transmission. LCRC sequence number correct, then passes packet Transaction Layer further processing. packet DLLP, terminates packet takes appropriate action. Transaction Layer accepts from into receive buffer partitioned into sections, that stores non-posted requests another that stores posted requests completions. checking enabled, Transaction Layer first performs ECRC received TLP. ECRC succeeds, Transaction Layer stores appropriate section receive buffer signals Application Layer that available. ECRC fails, Transaction Layer drops logs error information configuration space. Advanced Error Reporting enabled, Transaction Layer invokes appropriate error reporting mechanisms. that passed ECRC contains Memory Read Memory Write request, Transaction Layer compares address contained addresses enabled base address registers (BARs). BIOS configures addresses. address received non-posted does match address enabled BARs, Transaction Layer generates completion with completion status "Unsupported Request" Express link. drops unmatched posted TLPs. address does match addresses, Transaction Layer accepts valid request signals application logic that valid available receive buffer. After Express MegaCore function claims target transaction, asserts request signal, rx_req, appropriate descriptor signal, rx_desc, system side indicate target transaction request application logic.
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Express-to-DDR2 SDRAM Reference Design
Upon detecting target transaction, application logic accepts asserting acknowledge signal, rx_ack. application logic decodes command information from descriptor rx_desc determine type destination current target access, DDR2 SDRAM memory internal registers.
PCIe Target Memory Read
When target memory read request reaches application logic, following sequence actions occurs:
Express MegaCore function asserts rx_req. same clock cycle, rx_desc becomes available, only most significant (MSB) half bits. least significant (LSB) half rx_desc becomes available next clock cycle. application logic ready accept memory read request, asserts rx_ack. application logic ready accept memory read request, options: assert signals until application logic ready accept request. rx_req rx_desc states remain unchanged. Assert rx_retry signal Express MegaCore function that application logic ready accept read request. Express MegaCore function then sends non-read request instead, outstanding. example, Express MegaCore function write requests, sends them application logic. After application logic accepts memory read request, decodes rx_desc. extracts necessary information, reformats request, puts request into command FIFO. DDR2 clock domain, Rx_ddr logic accepts read request from command FIFO translates into more DDR2 read requests. Rx_ddr logic sends read requests DDR2 SDRAM controller sequentially. DDR2 SDRAM controller reformats read requests sends them DDR2 SDRAM memory. After some time, DDR2 SDRAM memory returns read request data. application logic data FIFO accumulates data. same time, application logic state machine monitors this action determines when return read completion packet Express MegaCore function. When enough data accumulates application logic data FIFO, application logic state machine generates PCIe read completion packet puts application logic command FIFO.
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Functional Description
Through application logic data FIFO packet crosses clock domain Tx_pcie logic reads PCIe packet. same clock cycle, Tx_pcie logic asserts tx_req tx_desc signal Express MegaCore function that packet available. Express MegaCore function ready accept read completion packet, asserts tx_ack. same time, data starts transfer Express MegaCore function tx_data tx_dv asserts until data transfer completes. During data transfer, Express MegaCore function ready accept data clock cycle, asserts tx_ws signal. application logic keeps data unchanged until tx_ws deasserts.
PCIe Target Memory Write
When target memory write request reaches application logic, following sequence actions occurs:
Express MegaCore function asserts rx_req. same clock cycle, rx_desc becomes available, only half bits. half rx_desc becomes available next clock cycle. application logic ready accept memory write request, asserts rx_ack. application logic ready accept memory write request, does assert signals until ready accept request. rx_req rx_desc state remains unchanged. After application logic accepts memory write request, decodes rx_desc. extracts necessary information, reformats request, puts request into command FIFO. DDR2 clock domain, Rx_ddr logic accepts write request from command FIFO translates into more DDR2 write requests. Rx_ddr logic sends write requests DDR2 SDRAM controller sequentially. When DDR2 SDRAM controller ready accept write data, asserts local_wdata_req signal. application logic responds providing write data local_wdata bus. DDR2 SDRAM controller reformats write requests sends them DDR2 SDRAM memory.
Register Access
Target transactions access register with appropriate memory-mapped address. PCIe target transactions registers single-cycle transactions.
Altera Corporation
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Express-to-DDR2 SDRAM Reference Design
Memory Mapping
this reference design, Express MegaCore function reserves MBytes system address space (Table accessed through base address registers BAR0 BAR1, KBytes system address space registers through BAR2.
Table Memory Address Space Memory Region
BAR0 BAR1 BAR2
Block Size
MByte KBytes
Memory Type
bit, prefetchable bit, non-prefetchable
Description
MByte DDR2 memory range capable supporting bits address Internal reference design configuration registers
Although PCIe address width, application logic only presents bits DDR2 SDRAM controller.
BAR0 BAR1 specify PCIe address range. PCIe function claims target transaction there match with BAR0 and/or BAR1 based 32-bit 64-bit addressing specified request descriptor. BAR2 maps registers (Table
Table Internal Registers Memory Mapped Addresses Range Reserved
0x00000-0x00003 0x00004-0x00007 0x00008-0x0000B 0x0000C-0x0000F 0x00010-0x00013
Read/Write
Write Write Write Read/Write Write
Mnemonic
HPAR[31:0] LPAR[31:0] BCR[31:0] CSR[31:0] LAR[31:0]
Register Name
PCIe Upper Address Register PCIe Lower Address Register Byte Counter Register Control/Status Register Local Address Register
Transactions Initiated from Reference Design
engine interfaces with registers initiate transaction. Then, process transactions, engine works with various blocks Rx/Tx application logic provide following functions:
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Functional Description
Generate requests Provide status signals ongoing transaction registers Interact with data path FIFO buffer transfer data from DDR2 SDRAM memory Express MegaCore function vice versa
reference design initiate three types transactions:
PCIe read completion read write
Refer "Transactions Targeting Reference Design" page section description PCIe read completion transaction. This section describes following topics:
PCIe Read PCIe Write
PCIe Read
initiate read request, root port first programs registers sequentially. After control register written decoded, dma_start signal asserts clock cycle initiate read. processing PCIe read request, following sequence actions occurs:
After dma_start signal asserts, Tx_dma_rd block application logic starts read transaction. generates read request(s) based information obtained from registers loads them into command FIFO buffers. After PCIe packets cross clock domain boundary command FIFO buffers, Tx_pcie block reads them Tx_pcie block decodes PCIe packet, asserts tx_req generates tx_desc. Express MegaCore function ready accept read request form memory reads, asserts tx_ack. Express MegaCore function ready accept memory read request there transmit credits available read requests, read request detours into read bypass FIFO. This Tx_pcie block then send subsequent non-read request instead. After Express MegaCore function accepts read request, reformats sends onto PCIe link.
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Express-to-DDR2 SDRAM Reference Design
After some time, PCIe link returns with read completion request. Rx_pcie block recognizes read completion request from asserted rx_req corresponding rx_desc signals. Rx_pcie block accepts packet asserting rx_ack. data enters accumulates data FIFO. During data transfer, application logic ready accept data clock cycle, asserts rx_ws. Express MegaCore function keeps data unchanged until rx_ws deasserts. Rx_pcie block also loads read completion request into command FIFO. After crossing clock domain boundary, Rx_ddr block reads read completion request. When enough data present, Rx_ddr block generates read commands sends data DDR2 SDRAM controller. DDR2 SDRAM controller forwards data with write command DDR2 SDRAM memory store data.
PCIe Write
initiate write request, root port first programs registers sequentially. After control register written decoded, dma_start signal asserts clock cycle initiate write. processing PCIe write request, following sequence actions occurs:
When application logic block, Rx_pcie, detects dma_start signal, generates PCIe packet(s) based information registers. Rx_pcie block writes PCIe packet(s) into command FIFO. DDR2 clock domain, Rx_ddr accepts read request from command FIFO translates into more DDR2 read requests. Rx_ddr sends read requests DDR2 SDRAM controller sequentially. DDR2 SDRAM controller reformats read requests sends them DDR2 SDRAM memory. After some time, DDR2 SDRAM memory returns read request data. data accumulates data FIFO. same time, Tx_ddr_resp state machine application logic monitors this action determines when send read data Express MegaCore function. When enough data accumulates data FIFO, Tx_ddr_resp block application logic generates PCIe write packet puts command FIFO.
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Interface Signal Descriptions
After PCIe packet crosses clock domain boundary, Tx_pcie reads asserts tx_req tx_desc same clock cycle signal Express MegaCore function that write packet available. Express MegaCore function ready accept write packet, asserts tx_ack. same time, data starts transfer Express MegaCore function tx_data tx_dv asserts until data transfer completes. During data transfer, Express MegaCore function ready accept data clock cycle, asserts tx_ws. application logic keeps data unchanged until tx_ws deasserts. After Express MegaCore function receives data, sends write packet onto link complete write.
Interface Signal Descriptions
This section describes signals reference design application logic categories:
Interface Signals with Express MegaCore Function Interface Signals with DDR2 SDRAM Controller
Interface Signals with Express MegaCore Function
following signals interface with Express MegaCore function, grouped follows:
Descriptor Signals Data Signals Descriptor Signals Data Signals
information local signals Express MegaCore function, refer Express Compiler User Guide.
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Express-to-DDR2 SDRAM Reference Design
Descriptor Signals
Table describes descriptor signals that interface with Express MegaCore function.
Table Descriptor Signals Signal
tx_ack
Description
Transmit acknowledge. Through this signal, asserted clock cycle, Express MegaCore function acknowledges descriptor phase request made application when application asserts tx_req. following clock cycle with tx_req remaining asserted, application request descriptor transmission with tx_desc. Transmit request. Assert this signal with each request. Always assert with
tx_req
tx_desc[127:0] keep asserted until Express MegaCore function asserts tx_ack. This signal need deassert between back-to-back descriptor
packets.
tx_desc[127:0]
Transmit descriptor bus, bits 127:0 transaction. include double-word (DWORD) Express transaction header. Bits have same meaning standard transaction layer packet header defined Express Base Specification Revision 1.0a. Byte header occupies bits 127:120 tx_desc bus, byte header occupies bits 119:112, through byte which occupies bits 7:0. bits tx_desc[2] tx_desc[34] indicate alignment data tx_data follows:
tx_desc[2] (64-bit address) First DWORD located tx_data[31:0] tx_desc[34] (32-bit address) First DWORD located bits tx_data[31:0] tx_desc[2] (64-bit address) First DWORD located bits tx_data[63:32] tx_desc[34] (32-bit address) First DWORD located bits tx_data[63:32]
descriptor indicates type transaction layer packet transit:
tx_desc[126] transaction layer packet without data tx_desc[126] transaction layer packet with data
following examples show placement this bus:
tx_desc[105:96]: length[9:0] tx_desc[126:125]: fmt[1:0] tx_desc[126:120]: command type[6:0]
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Interface Signal Descriptions
Data Signals
Table describes data signals that interface with Express MegaCore function.
Table Data Signals (Part Signal
tx_cred[65:0]
Description
Transmit credit. This optional signal informs application layer whether transmit transaction layer packet particular type based available flow control credits. This signal optional because Express MegaCore function always checks sufficient credits before acknowledging request. However, checking available credits with this signal, application improve system performance follows:
dividing large transaction layer packet into smaller transaction layer packets based available credits, arbitrating among different types transaction layer packets sending particular transaction layer packet across virtual channel that advertises available credits.
acknowledging transaction layer packet, Express MegaCore function consumes corresponding flow control credits updates this signal clock cycle after asserting tx_ack. component that received infinite credits initialization, each field this signal highest potential value. Express MegaCore function, this signal bits wide provides exact number available credits each flow control type. Refer Table Express MegaCore function tx_cred[65:0]bit decoding.
tx_ws
Transmit wait states. With this signal, Express MegaCore function insert wait states prevent data loss following circumstances:
give DLLP transmission priority give high-priority virtual channel retry buffer transmission priority when link initializes with fewer lanes than permitted link.
Express MegaCore function ready assert tx_ack acknowledge descriptor phase, asserts tx_ws throttle transmission.
tx_dfr
Transmit data phase framing. This signal asserts same clock cycle tx_req request data phase (assuming data phase needed). Continue asserting this signal until clock cycle preceding last data phase.
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Express-to-DDR2 SDRAM Reference Design
Table Data Signals (Part Signal
tx_dv
Description
Transmit data valid. application interface asserts this signal indicate that
tx_data[63:0] valid. Assert this signal clock cycle following assertion tx_dfr until last data phase transmission. Express MegaCore function only accepts data while this signal asserts long tx_ws remains
deasserted. application interface rely fact that first data phase never occurs before asserted tx_ack acknowledges descriptor phase. However, first data phase coincide with assertion tx_ack transaction layer packet header comprises only DWORDs.
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Interface Signal Descriptions
Table Data Signals (Part Signal
tx_data[63:0]
Description
Transmit data bus. This signal transfers data from application interface link includes DWORD transaction layer packet header tx_desc. DWORDs wide, tx_data[63:0] naturally aligns with address ways transaction layer packet address. Depending DWORD packet header, this appears tx_desc[2] tx_desc[34]. bits tx_desc[2] tx_desc[34] indicate alignment data tx_data follows:
tx_desc[2] (64-bit address) First DWORD located tx_data[31:0] tx_desc[34] (32-bit address) First DWORD located bits tx_data[31:0] tx_desc[2] (64-bit address) First DWORD located bits tx_data[63:32] tx_desc[34] (32-bit address) First DWORD located bits tx_data[63:32]
This natural alignment allows tx_data[63:0] connect directly 64-bit data path aligned quad-word (QWORD) address little endian convention). DWORD transaction) shown:
Clock Cycles tx_data[63:32] tx_data[31:0]
DWORD transaction) shown:
Clock Cycles tx_data[63:32] tx_data[31:0]
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Express-to-DDR2 SDRAM Reference Design
Table Data Signals (Part Signal
tx_err
Description
Transmit error. This signal, used discard nullify transaction layer packet, asserts clock cycle during data phase. Express MegaCore function records event memory waits data phase. Ensure that upon assertion tx_err, application interface stops transaction layer packet transmission deasserting tx_dfr tx_dv. This signal only applies transaction layer packets sent link opposed transaction layer packets sent configuration space). This signal available Express MegaCore function; used, this signal zero.
Table describes tx_cred[65:0]bits Express MegaCore function.
Table Transmit Credit: Decoding tx_cred[65:0] Express MegaCore function (Part tx_cred
[7:0]
Value
credits available Sufficient credit available least credits available 1-256: number credits available 257-511: reserved
Description
Posted header. Ignore this field value Posted Header credits, tx_cred[60], Posted Data. bits permit advertisement credits, which corresponds Maximum Payload Size. Ignore this field value Posted Data credits, tx_cred[61], Non-Posted Header. Ignore this field value Non-Posted Header credits, tx_cred[62], Non-Posted Data. Ignore this field value Non-Posted Data credits, tx_cred[63], Completion Header
[19:8]
[27:20] credits available
Sufficient credit available least
[39:28] credits available
Sufficient credit available least
[47:40] credits available
Sufficient credit available least
[59:48] credits available
1-256: number credits available 257-511: reserved
Completion Data, Posted Data. bits permit advertisement credits, which corresponds Maximum Payload Size. Posted Header Credits. Infinite when Posted Data Credits. Infinite when
[60] [61] [62]
Posted Header Credits infinite Posted Header Credits infinite Posted Data Credits infinite Posted Data Credits infinite
Non-Posted Header Credits infinite Non-Posted Header Credits. Infinite when Non-Posted Header Credits infinite
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Interface Signal Descriptions
Table Transmit Credit: Decoding tx_cred[65:0] Express MegaCore function (Part tx_cred
[63] [64] [65]
Value
Non-Posted Data Credits infinite Non-Posted Data Credits infinite Completion Credits infinite Completion Credits infinite Completion Data Credits infinite Completion Data Credits infinite
Description
Non-Posted Data Credits. Infinite when Completion Header Credits. Infinite when Completion Data Credits. Infinite when
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Express-to-DDR2 SDRAM Reference Design
Descriptor Signals
Table describes descriptor signals that interface with Express MegaCore function.
Table Descriptor Signals (Part Signal
rx_req
Description
Receive request. Express MegaCore function asserts this signal request packet transfer application interface. rx_req asserts minimum clock cycles when first DWORDs transaction layer packet header become valid. assert rx_abort, rx_retry, rx_ack same time rx_req. complete descriptor becomes valid second clock cycle which rx_req asserts. Receive descriptor bus. Bits (125:0) have same meaning standard transaction layer packet header defined Express Base Specification Revision 1.0a. Byte header occupies bits 127:120 rx_desc bus, byte header occupies bits 119:112, with byte bits 7:0. Bits 135:128 contain descriptor decoding (Table Completion transactions received endpoint have bits asserted require routing master block application layer.
rx_desc[135:0]
rx_desc[127:64] begins transmission same clock cycle that rx_req asserts, allowing precoding arbitrating begin shortest time possible. other bits rx_desc become valid until following clock cycle shown following diagram.
Clock Cycles rx_req rx_ack rx_desc[135:128] rx_desc[127:64] rx_desc[63:0]
Valid
Valid
Valid
descriptor indicates type transaction layer packet transit:
rx_desc[126] transaction layer packet without data rx_desc[126] transaction layer packet with data
rx_ack
Receive acknowledge. This signal asserts clock cycle when application interface acknowledges descriptor phase starts data phase, any. When rx_req deasserts following clock cycle, rx_desc becomes ready next transmission.
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Interface Signal Descriptions
Table Descriptor Signals (Part Signal
rx_abort
Description
Receive abort. application interface asserts this signal application accept requested descriptor. this case, descriptor removed from receive buffer space, flow control credits updated, and, necessary, application layer generates completion transaction with unsupported request (UR) status transmit side. Receive retry. application interface asserts this signal accept non-posted request. This condition requires that application layer assert rx_mask along with rx_retry that while rx_mask asserts, only posted completion transactions appear receive interface. Receive mask non-posted requests). This signal masks non-posted request transactions made application interface present only posted completion transactions. Assert this signal together with rx_retry; deassert when Express MegaCore function accept non-posted requests again.
rx_retry
rx_mask
Express MegaCore function generates eight MSBs rx_desc[135:0] with decoding information (Table
Table Descriptor Decoding, rx_desc[135:128]
Type Component
decoded decoded decoded decoded decoded decoded Expansion decoded Reserved
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Express-to-DDR2 SDRAM Reference Design
Data Signals
Table describes data signals that interface with Express MegaCore function.
Table Data Signals (Part Signal
rx_be[7:0]
Description
Receive byte enable. These signals qualify data rx_data[63:0]. Each rx_be[7:0] indicates whether corresponding byte data rx_data[63:0] valid. These signals available Express MegaCore function. Receive data phase framing. This signal asserts same subsequent clock cycle rx_req request data phase (assuming data phase needed). deasserts clock cycle preceding last data phase signal data phase application layer. Thus, application layer does require data phase counter. Receive data valid. Express MegaCore function asserts this signal indicate that rx_data[63:0] contains data.
rx_dfr
rx_dv
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Interface Signal Descriptions
Table Data Signals (Part Signal
rx_data[63:0]
Description
Receive data bus. This transfers data from link application layer. DWORDs wide, naturally aligns with address ways, rx_desc:
rx_desc[2] (64-bit address) First DWORD located rx_data[31:0] rx_desc[34] (32-bit address) First DWORD located bits rx_data[31:0] rx_desc[2] (64-bit address) First DWORD located bits rx_data[63:32]. rx_desc[34] (32-bit address) First DWORD located bits rx_data[63:32].
This natural alignment allows rx_data[63:0] connect directly 64-bit data path aligned QWORD address little endian convention). DWORD transaction) shown:
Clock Cycles rx_data[63:32] rx_data[31:0]
DWORD transaction) shown:
Clock Cycles rx_data[63:32] rx_data[31:0]
rx_ws
Receive wait states. With this signal, application layer insert wait states throttle data transfer.
Interface Signals with DDR2 SDRAM Controller
following signals interface with DDR2 SDRAM controller, grouped follows:
Signals Signals
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Express-to-DDR2 SDRAM Reference Design
signal directions reflect perspective from Express MegaCore function.
Signals
Table describes data signals that interface with DDR2 SDRAM controller.
Table Signals Signal
local_rdata[] local_rdata_valid
Description
Read data bus. width local_rdata twice that memory data bus. Read data valid signal. local_rdata_valid signal indicates that valid data present read data bus. timing local_rdata_valid automatically adjusts accommodate choice resynchronization pipelining options.
Signals
Table describes data signals that interface with DDR2 SDRAM controller.
Table Signals (Part Signal
local_ready
Description
local_ready signal indicates that DDR2 SDRAM controller ready accept request signals. local_ready asserts clock cycle that read write request asserts, that indicates request been accepted. local_ready signal deasserts indicate that DDR2 SDRAM controller cannot accept more requests. Write data request signal, which indicates local interface that should present valid write data next clock edge. Memory address which burst should start. width this sized using following equation: chip select: width bank bits bits column bits column address memory side ignored, because local data width twice that memory data width.
local_wdata_req local_addr[]
local_be[]
Byte enable signal, which masks individual bytes during writes.
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Registers
Table Signals (Part Signal
local_read_req local_size[] local_wdata[] local_write_req
Read request signal
Description
burst size requested access, encoded binary number. Write data bus. local_wdata width twice that memory data bus. Write request signal
Registers
This section describes registers engine. This reference design implements following registers:
PCIe Address Register (PAR) Byte Counter Register (BCR) Control Status Register (CSR) Local Address Register (LAR)
These registers, memory-mapped BAR2 PCIe function, require another PCIe host PCIe configure their content prior initiating transfer. activate requires writing registers following sequence: Write with PCIe starting address current transaction. Write with number bytes transfer. Write with DDR2 SDRAM memory starting address transaction. Write with appropriate value.
Writing logical into triggers state machine. next clock cycle sets dma_busy register indicate that transfer progress. engine sends requests corresponding block initiate transfer. receiver block transfers data between DDR2 SDRAM memory system memory. engine deasserts dma_busy signal when transfer completes transaction start then.
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PCIe Address Register (PAR)
PCIe address bits long 32-bit register. Therefore, PCIe address register comprises 32-bit registers, PCIe upper address register (HPAR) PCIe lower address register (LPAR). Combining upper HPAR lower LPAR forms PCIe address. 32-bit PCIe request addressing, only lower LPAR bits valid. 64-bit PCIe request addressing, combined 64-bit address valid. contains PCIe address current transfer stays unchanged until reprogrammed. PCIe transfer initiated engine must begin QWORD boundary. Only master program PAR. Table shows format.
Table Address Register Format Data
31.0
Name
Read/Write
Write
Definition
32-bit address
Byte Counter Register (BCR)
byte counter register 13-bit register. 13-bit counter implements BCR. holds byte count current memory transfer. PCIe transfer initiated engine requires QWORD transfer. Only root port write into BCR. Table shows format.
Table Byte Counter Register Format Data
12.0 31.13
Name
Read/Write
Write
Definition
13-bit counter Reserved
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Registers
Control Status Register (CSR)
32-bit configures engine. directs operation provides status current transfer. Only PCIe root port write into read from CSR. Table describes format.
Table Control Status Register Format Data
Mnemonic
Read/Write
Read/Write
Write Reserved
Definition
read/write. asserted HIGH, signals write. deasserted, signals read. Start. When asserted HIGH, indicates that registers programmed transaction ready begin. Reserved Busy. When asserted HIGH, indicates that current still progress registers ready programming.
Start
Write
30.8
Busy
Read
Local Address Register (LAR)
32-bit holds SDRAM address from which data transfers to/from SDRAM. Implemented with 23-bit counter, write-only register. Table shows format LAR.
Table Local Address Register Format Data
22.0 31.23
Name
Read/Write
Write
Definition
23-bit address Reserved
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Express-to-DDR2 SDRAM Reference Design
Using Reference Design
following sections describe reference design:
Hardware Requirements Software Requirements Reference Design Installation Running Application Appendix
Hardware Requirements
reference design application requires following hardware:
Stratix Express Development Board (Figure Computer with PCIe slot Stratix Express Development Board. Computer with Quartus® software downloading applications Stratix Express development board. Altera USB-Blastercable
Figure Stratix Express Development Board
High-Speed Mezzanine Card Interfaces User Push-Button Switches HSMC Interface (J2) Transmit/Receive Yellow LEDs
External Clock Input Connector (J4) Configuration Done (D8) User Switch Bank (S5) Ethernet RJ-45 Single Port (RJ1)
User LEDs through D16) HSMC Interface (J1)
Power Supply Input (J3) Device (U4) Power Switch (SW1)
JTAG Header (J5)
Temperature Sensor With Alarm (U7)
Ports (J6,
QDRII SRAM (U6) Flash Device (U3) Stratix Device (U10) Express Edge Connector
100-MHz Crystal (X1) 155.25-MHz Crystal (X4)
DDR2 Mbytes SDRAM (U2)
DDR2 Mbytes SDRAM (U5, U11, U13)
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Using Reference Design
some computer systems, PCIe slot support PCIe application because hardware software limitations. Ensure that selected computer supports PCIe before starting. Some computer configurations require graphics card keep PCIe slot available development board.
Software Requirements
reference design application requires installation following software:
Express Development Kit, Stratix Edition reference design package, available downloadable compressed file www.altera.com. package includes following items: Reference design Quartus project archive Demo application drivers, installation computer SRAM Object File (SOF) reference design Programmer Object File (POF) reference design Quartus Software, Development Edition, including MegaCore functions from MegaCore Library CD-ROM, installation computer
Reference Design Installation
reference design application requires computers (Figure Specify computer development board computer, computer Quartus programming computer. Figure Hardware Configuration
Development Board USB-Blaster Cable Computer Quartus
Computer Application Demo
prerequisite, installation reference design requires that computer already have Quartus software installed. information about installing Quartus software, refer Quartus Development Software Handbook.
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installation procedure includes following activities:
Installing Drivers Reference Design Application Demo Installing Development Board Downloading Programming Files Development Board
Installing Drivers Reference Design Application Demo
Installation drivers requires administrator privileges computer install drivers reference design application demo, following steps: Download Express Development Kit, Stratix Edition reference design package Quartus programming computer, computer extract compressed files. Copy Drivers directory development board computer, computer Open Drivers directory, double-click install.bat file. After install.bat file finished copying files installing drivers application demo, shut down computer
Installing Development Board
Insert Express development board PCIe slot. Start computer Windows Found Hardware Wizard appears (Figure
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Using Reference Design
Figure Found Hardware Wizard Window
Click Next. Hardware Installation window appear (Figure
Figure Hardware Installation Window
StratixII
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Express-to-DDR2 SDRAM Reference Design
Hardware Installation window appears, click Continue Anyway Click Finish Completing Found Hardware Wizard window (Figure finish installing drivers.
Figure Installation Complete Window
Downloading Programming Files Development Board
Altera delivers Stratix Express development board preprogrammed with Express design example. reference design will replace this default example through procedures described this section. these procedures also when developing other designs. Programming development board effected through Quartus software computer hence requires Altera USB-Blaster cable connection between computer development board computer This connection allows direct configuration development board downloading SOF, filetype .sof, POF, filetype .pof. reference design package downloaded computer includes files.
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Using Reference Design
used programming FPGA, this temporary configuration, because FPGA loses this programmed content after board powers down. contrast, used programming non-volatile MAX® flash memory, which then loads programmed content into FPGA when board powers programming provides more persistent configuration. following procedures describe programming development board:
Connecting USB-Blaster Cable Programming with Programming with
Connecting USB-Blaster Cable connect USB-Blaster cable, following steps: Connect USB-Blaster cable, the10-pin female plug, JTAG header (J5) Stratix EP2SGX90 Express development board. Connect marker line cable header (J5). numbered board. Connect other cable port computer running Quartus software, computer Ensure that USB-Blaster download cable driver installed before using USB-Blaster cable downloading. information about installing USB-Blaster download cable driver included with Quartus software, refer USB-Blaster Download Cable User Guide. driver files installed <quartus-install-dir> \drivers\usb-blaster.
Programming with program on-board FPGA with design file view state machine status Quartus software's SignalTap® logic analyzer, following steps: Start Quartus software computer Tools menu, click SignalTap Logic Analyzer. Open PCIe SignalTap file reference design alternate design).
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SignalTap Logic Analyzer window, click Setup button enable USB-Blaster hardware. Click Scan Chain button identify device add-in card. Select Stratix device drop-down box. From same directory SignalTap file, select PCIe SOF. This alternate design reference design SOF. Press Program button next file name program FPGA. Reboot computer that BIOS configure system card setup system memory space.
example system status display Figure SignalTap logic analyzer displays status ltssm state machine, 0x0F, which indicates that Express MegaCore function state. lane-active-led waveform shows number active lanes, 0x7h, which indicates that eight PCIe lanes display uses 0x7h, invert 0x8h, because corresponding board LEDs active LOW.
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Using Reference Design
Figure Quartus Software SignalTap Window
more information about SignalTap Logic Analyzer included with Quartus software, refer Design Debugging Using SignalTap Logic Analyzer chapter volume Quartus Handbook. Programming with reference design package includes POF. However, needed, generated from configure flash development board. Ensure that been verified before converting POF. This requires loading into FPGA running tests confirm that loaded configuration operates properly.
Programming flash memory with involves following activities:
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Generate converting Program flash memory
following steps generate POF: Start Quartus software. From Quartus menu, choose File, then select Convert Programming files. Enter following parameters (Figure Programming File Type "pof" Configuration device "CFI_512MB" Options button "0x1FF0000" (512MB 64K) File name: <output file name>.pof
Click File select file add. Click Generate.
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Figure Convert Programming Files Window
following steps program flash memory: Ensure that JTAG (the USB-Blaster cable) connected development board enabled. Identify device programmer window. Program flash memory with compliant design POF, "Pfl.pof" found Express-to-DDR2 SDRAM Reference Design directory (Figure Right-click this line select Attach POF.
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Select newly generated flash image supplied found Express-to-DDR2 SDRAM Reference Design directory. Select Program/Configure checkboxes "page_0" image "Option bits" image.
Figure Programming Flash Window
Click Program button wait flash programmed Note: messages appear that "Device silicon ready" (Figure 10), press "Config_Done" button (S1) development board start programming. This issue appears with boards that have already their flash programmed.
Figure Device Ready Messages
Reboot computer
Running Application
bring application demo GUI, initiate application executing siigxpcie.exe file found Express-to-DDR2 SDRAM reference design Drivers directory computer application window appears shown Figure
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Appendix
Figure Altera Express Demo Application Window
From GUI, application demo perform tests that include memory read write transactions board loop read write transactions; also read various configuration registers.
Appendix
appendix lists some limitations reference design. also lists additional sources related information.
Design Limitations
This reference design following limitations:
designed transfer data with size less than bytes non-multiples bytes. designed transfer data with non-QWORD-aligned address. registers mostly write-only registers programmed demonstration software. attempt read registers demonstration software will result "0".
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References
more information refer following documents:
Altera Compiler User Guide Altera DDR2 SDRAM Controller Compiler User Guide Micron Technology DDR2 SDRAM data sheet
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: literature@altera.com
Copyright 2006 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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