June 2005, ver. Application Note co-ordinate rotation digita

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CORDIC Reference Design
June 2005, ver.
Application Note
co-ordinate rotation digital computer (CORDIC) reference design implements CORDIC algorithm, which converts cartesian polar coordinates vice versa also allows vectors rotated through given angle. CORDIC iterative process, using series shifts adds. Hence often hardware efficient solution over using multiplications, division square roots. reference design comprises MATLAB accurate model CORDIC algorithm implemented hardware test environment. test environment allows configure CORDIC reference design test conditions compare results with theoretical results. Altera provides separately encrypted Verilog source code, precompiled simulation files ModelSim simulator, testbench hardware implementation CORDIC.
Background
CORDIC provides iterative solution performing vector rotations arbitrary angles using only shifts adds. CORDIC algorithm operate either vectoring rotation mode. Vectoring mode performs cartesian polar conversion. input vector rotated until axis; final value equal magnitude input vector. While rotating vector, total angle traversed also recorded, which provides phase input vector. Rotation mode performs polar cartesian conversion. input vector value equals magnitude value equals zero) rotated specified angle. final vector cartesian equivalent input polar values. Vector rotation mode rotates input vector specified angle. output gives cartesian coordinates rotated vector. final values rotation, vector rotation, vectoring modes arescaled CORDIC processing gain. This processing gain varies with number iterations performed. approaches 1.6476 number iterations goes infinity.
Altera Corporation AN-263-1.4
263: CORDIC Reference Design
some point system this gain have compensated for. vectoring mode, resultant magnitude value) needs divided processing gain multiplied reciprocal processing gain); rotation mode either input polar magnitude (input value) output values divided processing gain.
Functional Description
Figure shows top-level block diagram CORDIC reference design. inputs outputs twos complement signed numbers. widths number iterations parameterizable. range given where -2(z_bits Figure Block Diagram
x_in y_in z_in mode CORDIC Reference Design x_out y_out z_out
Cartesian Polar Conversion
cartesian polar conversion following attributes: x_in y_in input cartesian values z_in must zero mode enforce vectoring mode x_out polar magnitude (scaled processing gain) z_out polar phase
Polar Cartesian Conversion
polar cartesian conversion following attributes: x_in input polar magnitude. y_in must zero. z_in input polar phase. mode enforce rotation mode x_out, y_out cartesian values (scaled processing gain)
Altera Corporation
263: CORDIC Reference Design
Vector Rotation
vector rotation following attributes: x_in y_in input cartesian values z_in angle rotate input vector mode enforce rotation mode x_out y_out cartesian values
Vector Width
vector width should increased over required width, because processing gain CORDIC block. example, bits represent magnitude, should select bits vector width inputs outputs. required sign extension inputs must performed, prior presenting inputs CORDIC reference design. select input output vector widths bits
Iterations
accuracy CORDIC algorithm improves with each iteration, until number iterations equals width inputs. CORDIC reference design pipelined every iteration. number clock cycles required perform conversion equal number iterations plus (this extra number required additional registering). number iterations from must exceed number bits input values.
Processing Gain Compensation
CORDIC reference design does compensate processing gain. However, Altera supply source code gain compensation block with encrypted source code CORDIC reference design,. This block synthesizable provided sample code necessarily optimized). gain compensation block implementations, which selectable parameters.
Altera Corporation
263: CORDIC Reference Design
first implementation gain compensation series shifts adds. latency clock cycles. vector lengths this achieves performance over uses approximately LEs. second implementation uses Stratix block latency clock cycles. vector lengths this achieves performance over using block.
Testbench
Verilog testbench optionally connects processing gain compensation block either before testing rotational mode removing gain) and/or after CORDIC reference design testing vectoring mode removing gain). Input data read from text files, output from system read compared expected data which also stored text files. error messages logged screen also logged output file. MATLAB environment auto-generates input data expected output data text files generate them manually. Altera provides scripts simulation with ModelSim simulators.
Design Flow
MATLAB environment configures CORDIC reference design (i.e., vector widths, number iterations, gain compensation) test conditions (i.e., rotation vectoring modes, number input samples, random sequential input data, restrictions input values). plot graphs compare performance MATLAB accurate model CORDIC with theoretical results. Once satisfied with behavior CORDIC (i.e. accuracy), allows input output data written text files Verilog parameters configure hardware CORDIC, gain compensation blocks, testbench. Verilog testbench confirms that Verilog behaves identically your MATLAB CORDIC model that required. Verilog testbench shipped with CORDIC reference design encrypted source code.
Altera Corporation
263: CORDIC Reference Design
Getting Started
This section involves following steps: Software Requirements Install Design Design Walkthrough
Software Requirements
design requires following software: Altera® Quartus® software version Mathworks MATLAB version ModelSim version 5.7a
Install Design
install reference design, .exe. follow installation instructions. Figure shows directory structure.
Altera Corporation
263: CORDIC Reference Design
Figure Directory Structure
cordic-<version> build Contains project file files Quartus synthesis fitting. Contains encrypted source files. altera_sim_lib Contains simulation models Altera device structures (i.e., blocks that gain compensation block). gate_sim Contains simulation models gate-level simulation. source Contains encrypted source files. mlab Contains MATLAB files accurate model. verilog Contains Verilog source files CORDIC gain compression blocks. test Contains common files that used both projects. dat_files Contains text files inputs their expected outputs from CORDIC reference design, which Verilog testbench requires. MATLAB auto-generate these text files. mlab Contains MATLAB files. Contains MATLAB testbench. verilog Contains Verilog files. cordic_compiled_lib Contains precompiled simulation files. scripts Contains ModelSim simulation scripts. Contains Verilog testbench.
Tables describe files each directory. Table sourcebuild Directory Files File Name
cordic.psf cordic.quartus
Description
Quartus project settings file. Quartus project file.
Altera Corporation
263: CORDIC Reference Design
Table Directory Files File Name
altera_sim_lib/altera_mf.v
Description
Verilog functional simulation models structures Altera devices (e.g., blocks).
Verilog simulation models required gate-level simulation.
Table source/mlab Directory Files File Name
cordic.m neg2pos.m
Description
accurate MATLAB model CORDIC gain compensation blocks. MATLAB function calculates absolute number that represents negative numbers twos complement.
Table source/verilog Directory Files File Name
cordic.v cordic_core.v ip_quad_info.v ip_quad_adj.v op_quad_adj.v cordic_inc.v cordic_inc_p2.v
Description
level CORDIC module. module containing algorithm. Determines quadrant information CORDIC inputs. Adjusts inputs algorithm. Adjusts outputs from algorithm. Contains static parameters. Contains parameters that change according CORDIC configuration; auto-generated MATLAB. Gain compensation block.
cordic_gain_corr.v
Altera Corporation
263: CORDIC Reference Design
Table test/dat_files Directory Files (required Verilog testbench) File Name
ip_mode.txt ip_xy.txt ip_z.txt op_exp_xy.txt op_exp_z.txt op_err.txt Note:
MATLAB auto-generate files except op_err.txt.
Description
CORDIC mode each input (rotation vectoring); auto-generated MATLAB. inputs CORDIC system. inputs CORDIC system. Expected outputs from CORDIC system. Expected output from CORDIC system. Output error from simulation run.
Table test/mlab/tb Directory Files File Name
cordic_gui.fig cordic_gui.m cordic_test.m comb_mlab_files MATLAB file GUI. MATLAB file GUI. MATLAB script that runs CORDIC test. Pearl script that combines data results from different sets files containing input expected output data.
Description
Table test/verilog/scripts Directory Files File Name
encrypt_msim_com.bat encrypt_msim_gui.bat
Description
batch file using ModelSim simulate design command mode. batch file using ModelSim mode simulate design.
Altera Corporation
263: CORDIC Reference Design
Table test/verilog/tb Directory Files File Name
cordic_tb.v modelsim_wave.do
Description
Verilog testbench. Waveform file ModelSim.
Design Walkthrough
walkthrough involves following steps: Start MATLAB Parameterize Design Auto-generate Verilog Simulation Files from MATLAB Simulation
Start MATLAB
start MATLAB GUI, perform following steps: Start MATLAB. Change working directory cordic-<version>/test/mlab/tb. Type following command: cordic_gui Output messages still output MATLAB command window.
CORDIC test control window opens (see Figure
Altera Corporation
263: CORDIC Reference Design
Figure CORDIC Test Control Window
Parameterize Design
parameterize your design, perform following steps: CORDIC Configuration part CORDIC test control panel, perform following steps: Choose vector widths: bits, bits extend. Where number bits specifies number bits going into CORDIC. Bits extends specifies number extra bits CORDIC works with, increase accuracy.
Altera Corporation
263: CORDIC Reference Design
Choose number iterations. want gain compensation, select Gain Compensation, choose gain compensation logic. choose logic shifts adds, enter value Bits Extend, increase accuracy.
Test Set-up part CORDIC test control panel, perform following steps: Choose rotational, vectoring, vector rotation mode. require fixed point test, select Fixed Point. Selecting Fixed Point overrides settings your widths. Choose either Sequential Random input data. rotational mode, enter number input data values magnitude phase. vectoring mode, enter number input data values values. vector rotation mode, enter different number rotation angles Phase box, enter different number input vectors Magnitude (each different input magnitude different starting phase, resulting different input vector; starting phases distributed evenly throughout degree space). Each different input vector rotated through different rotation angles. rotational mode, enter Input Data Constraints: minimum magnitude, maximum magnitude, minimum phase, maximum phase. vectoring mode, enter Input Data Constraints: minimum maximum minimum maximum
Click Run.
Altera Corporation
263: CORDIC Reference Design
Select type graph that want MATLAB plot. Figure Figure show various graphs that select, various CORDIC test control panel settings.
Figure Input Values Graph
Altera Corporation
263: CORDIC Reference Design
Figure Output Polar Errors Graph
Altera Corporation
263: CORDIC Reference Design
Figure Output Cartesian Plane Graph
When have viewed graph, click Close Plots.
Auto-generate Verilog Simulation Files from MATLAB
Once MATLAB testing reaches conclusion with configuration suitable CORDIC reference design auto-generate Verilog simulation files from MATLAB, perform following steps: Click Write Data Files write input expected output data Click Write Verilog Parameters, write required Verilog parameters These files contain parameters configure CORDIC reference design, gain compensation block, testbench.
Altera Corporation
263: CORDIC Reference Design
Simulation
ModelSim simulation files, perform following steps: Open ModelSim simulator. Change working directory Ensure that required data files cordic<version>/test/dat_files directory. want batch file otherwise batch file. output file, which generated from simulation run, subsquently change parameter values data used test still have ModelSim simulator open from previous run, type ModelSim window, which recompiles testbench reruns simulation.
Performance
Table shows Quartus push-button performance CORDIC reference design Stratixdevices.
Table Example Performance Stratix Devices Widths Number Iterations Logic Elements (LEs) Device Note fMAX (MHz)
Note:
EP1S10F484C5 device.
2,021 3,462 5,287
Altera Corporation
263: CORDIC Reference Design
Table shows Quartus push-button performance CORDIC reference design Cyclonedevices. Table Example Performance Cyclone Devices Widths Number Iterations Logic Elements (LEs)
Note:
EP1C 3T144C6 device. EP1C 4F324C6 device. EP1C 12F324C6 device.
Device
fMAX (MHz)
2,022 3,463 5,287
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: literature@altera.com
Copyright 2005 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
Altera Corporation

June 2005, ver. Application Note co-ordinate rotation digita

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