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Stratix Filtering Reference Design
Application Note
filtering reference designs provided Development Kit, Stratix Edition, Development Kit, Stratix Professional Edition, show Altera® Builder system design, simulation, board-level verification. Builder digital signal processing (DSP) development tool that interfaces MathWorks industry leading system-level modeling tool Simulink with Altera Quartus® development software. Builder provides seamless design flow which perform algorithmic design system integration MATLAB Simulink software then port design hardware description language (HDL) files Quartus software. Using Builder, automatically generate register transfer level (RTL) design testbench from Simulink. These files pre-verified output files optimized Altera Quartus software rapid prototyping. built-in Builder SignalTap® Analysis block allows capture signal activity from internal Stratix device nodes, while system under test runs system speed hardware. import SignalTap data into MATLAB workspace further analysis. This development flow easy intuitive even your experience designing with programmable logic design software extensive. Stratix Filtering uses following items:
Quartus software Builder with SignalTap logic analyzer read-back feature Altera finite impulse response (FIR) Compiler MegaCore® function Altera numerically controlled oscillators (NCO) Compiler MegaCore function MathWorks MATLAB MathWorks Simulink Mentor Graphics® ModelSim®-Altera, ModelSim ModelSim simulation software Stratix EP1S25 development board Stratix EP1S80 development board
Figure shows top-level schematic filtering reference design. NCOs generate 1-MHz sinusoidal signal 10-MHz sinusoidal signal respectively. signals added together on-chip before they pass through digital-to-analog (D/A) converter Stratix
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Stratix Filtering Reference Design
development board. resulting analog signal looped back analog-to-digital (A/D) converter board then passed on-chip, low-pass filter with cut-off frequency MHz. low-pass filter removes 10-MHz sinusoidal signal allows 1-MHz sinusoidal signal through fir_result output. When install software from Development Kit, Stratix Stratix Professional Edition CD-ROM, design files installed directory structure, shown Figure Figure Filtering Reference Design Directory Structure
stratix_dsp_kit-v<version> directory contains files Stratix EP1S25 development board. stratix_dsp_pro_kit-v<version> directory contains files Stratix EP1S80 development board. Docs Contains schematics, data sheet, readme file Development Kit, Stratix Edition Development Kit, Stratix Professional Edition. Reference_Design Contains reference design Development Kit, Stratix Edition Development Kit, Stratix Professional Edition. Filtering Contains filtering reference design file documentation. Contains filtering Application Note. Exercises1and2and3 Contains exercises Exercise4 Contains exercise
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This application note provides following exercises:
"Exercise Review Filtering Design" page 5-Review filtering design using Builder. "Exercise Simulate Model Simulink" page 15-Analyze Builder-generated models simulate filtering design Simulink. "Exercise Perform Simulation" page 19-Perform simulation using ModelSim software simulation tool. "Exercise Analyze Results Hardware" page 23-Program Stratix device with filtering design SignalTap read-back feature Builder capture data from internal Stratix device nodes while design runs system speed. then compare results from SignalTap analysis with simulation results from Exercise verify that design functioning correctly hardware.
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Stratix Filtering Reference Design
Before Begin
instructions this application note assume that have already installed software provided with Development Kit, Stratix Edition, Development Kit, Stratix Professional Edition your more information installation instructions, Development Kit, Stratix Stratix Professional Edition Getting Started User Guide. must have following software installed your
Quartus software starting with version Builder version 2.2.1 Compiler MegaCore function starting with version 3.2.0 Compiler MegaCore function starting with version 2.2.1 MathWorks MATLAB version 7.0.1 MathWorks Simulink version ModelSim-Altera software, ModelSim ModelSim software version 5.8d This application note assumes that have installed software into default locations.
must Builder setup script once, following installation MegaCores. script updates Builder other newly installed upgraded MegaCores.
more information Using MegaCore Functions chapter Builder User Guide. setup script, follow these steps: MATLAB software. Current Directory browser, browse directory where Builder installed: script typing setup_dspbuilder MATLAB prompt workspace.
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Exercise Review Filtering Design
Exercise Review Filtering Design
review filtering design, follow these steps: MATLAB software. Current Directory browser, browse following directories:
Stratix EP1S25 development board:
Stratix EP1S80 development board:
Choose Open (File menu) select file filter_design.mdl (.mdl Simulink Model File). Review Simulink design (see Figure filtering design contains combination OpenCore® Plus MegaCore functions Builder blocks. OpenCore Plus feature lets test-drive Altera MegaCore functions free. verify functionality MegaCore function quickly easily, well evaluate size speed before making purchase decision. hardware evaluation feature allows generate time-limited programming files designs that include Altera MegaCore function. perform board-level design verification before deciding purchase licenses each used MegaCore functions. only need purchase license when completely satisfied with MegaCore's functionality performance, would like take your design production.
more information OpenCore Plus hardware evaluation, AN320: OpenCore Plus Evaluation Megafunctions.
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Stratix Filtering Reference Design
Figure Simulink Design Exercises (filter_design.mdl File)
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Exercise Review Filtering Design
Review NCO_1MHz MegaCore Function
launch Toolbench 1MHz Compiler MegaCore function, follow these steps: Double-click NCO_1MHz block launch Toolbench Compiler MegaCore function (see Figure
Figure Toolbench Compiler MegaCore Function
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Stratix Filtering Reference Design
Click Step Parameterize review parameters NCO_1MHz block. NCO_1MHz block generates 1-MHz sinusoidal signal (see Figure
Figure 1-MHz Sinusoidal Signal
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Exercise Review Filtering Design
block implemented using multiplier-based architecture, which reduces memory usage using hardware multipliers Stratix device. Table shows parameters that Toolbench Parameters tab.
Table Compiler Parameters NCO_1MHz Parameter
Parameters Accumulator Precision Angular Precision Magnitude Precision Generation Algorithm Implement Phase Dithering Dither Level Clock Rate Desired Output Frequency Implementation Architecture Outputs Device Family Number Channels Dedicated Multiplier(s) Single Output Stratix bits bits bits Multiplier-Based
Value
Click Cancel exit Toolbench when finished reviewing parameter settings.
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Stratix Filtering Reference Design
Review NCO_10MHz MegaCore Function
launch Toolbench 10MHz Compiler MegaCore function, follow these steps: Double-click NCO_10MHz block (see Figure page launch Toolbench Compiler MegaCore function. Click Step Parameterize review parameters NCO_10MHz block. NCO_10MHz block generates 10-MHz sinusoidal signal, shown Figure
Figure 10-MHz Sinusoidal Signal
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Exercise Review Filtering Design
Table shows parameters that Toolbench Parameters tab.
Table Compiler Parameters NCO_10MHz Parameter
Parameters Accumulator Precision Angular Precision Magnitude Precision Generation Algorithm Implement Phase Dithering Dither Level Clock Rate Desired Output Frequency Implementation Architecture Outputs Device Family Number Channels Dedicated Multiplier(s) Single Output Stratix bits bits bits Multiplier-Based
Value
NCO_10MHz block contains same parameter values NCO_1MHz block, except constant value that into phase increment input desired output frequency. This constant value determines frequency sinusoidal output. MegaWizard® Plug-In calculates constant value when enter clock period desired output frequency wizard. Figure page shows calculated result 1-MHz sine wave 53,687,091. chosen clock frequency corresponds 80-MHz oscillator Stratix EP1S25 development board Stratix EP1S80 development board. Similarly, desired output frequency yields phase increment value 536,870,912 (see Figure Click Cancel exit Toolbench when finished reviewing parameter settings.
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Stratix Filtering Reference Design
Review fir_compiler MegaCore Function
launch Toolbench Compiler MegaCore function, follow these steps: Double-click fir_compiler block launch Toolbench Compiler MegaCore function (see Figure
Figure Toolbench Compiler MegaCore Function
Click Step Parameterize review parameters fir_compiler block (see Figure filter block 35-tap, low-pass filter with cut-off frequency MHz. designed filter 10-MHz sinusoidal signal.
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Exercise Review Filtering Design
Figure Filter Parameters
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Stratix Filtering Reference Design
Table shows parameters that that Toolbench Parameters tab.
Table Compiler Parameters Parameter
Filter Type Window Type Sample Rate Number Coefficients Cutoff Frequency Rate Specification (Multi-rate Filter Settings) Width (Coefficients) Input Number System Input Width Output Number System Bits Keep Least Significant (LSB) (Round) Most Significant (MSB) (Truncate) Structure Device Family Pipeline Level Data Storage Coefficient Storage
Value
Pass Blackman Single Rate Signed Decimal (A/D width) Custom Resolution bits bits Distributed Arithmetic Fully Parallel Filter Stratix Logic Cells Logic Cells
Click Cancel exit Toolbench after have finished reviewing parameter settings. Close filter_design.mdl file.
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Exercise Simulate Model Simulink
Exercise Simulate Model Simulink
simulate model Simulink software, follow these steps: Choose Configuration Parameters (Simulation menu). settings Simulink simulation parameters should same shown Figure not, change them match Figure
Figure Simulink Simulation Parameters
Click Start simulation choosing Start (Simulation menu).
Ignore MATLAB warnings about unconnected input output pins.
Double-click Scope block view filtered unfiltered signals time domain.
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Stratix Filtering Reference Design
Click binocular icon auto-scale waveforms. Figure Figure show scaled waveforms time domain.
Figure Time Domain Plot adder_result_sim-Unfiltered Data
Figure Time Domain Plot fir_result_sim-Filtered Data
Switch MATLAB window.
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Exercise Simulate Model Simulink
view frequency response filtered unfiltered signals, plot_fft.m file, which included with lab. view unfiltered data, type following command MATLAB command window:
Response Unfiltered Data',8e7)r where: adder_result_sim name signal output adder Frequency Response Unfiltered Data title plot sampling frequency MHz), which well above Nyquist frequency
MATLAB plot displays frequency response unfiltered data (see Figure 11). Figure Response adder_result_sim Unfiltered Data
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Stratix Filtering Reference Design
view frequency response filtered data, type following command MATLAB command window:
Response Filtered Data',8e7)r where: fir_result_sim name signal output filter Frequency Response Filtered Data title plot sampling frequency MHz), which well above Nyquist frequency
MATLAB plot displays frequency response filtered data (see Figure 12). Figure Response fir_result_sim Filtered Data
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Exercise Perform Simulation
Exercise Perform Simulation
generate simulation files filtering design example, follow these steps: Double-click SignalCompiler block your model display SignalCompiler Analyze feature (see Figure 13).
Figure SignalCompiler Block, Analyze Feature
Click Analyze.
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Stratix Filtering Reference Design
Click Testbench shown Figure
Figure Signal Compiler Block, Hardware Compilation Feature
Turn Generate Stimuli VHDL Testbench option. Under Hardware Compilation section Figure click 1-Convert VHDL. Signal Compiler generates simulation script, tb_filter_design.tcl (.tcl tool command language file), VHDL testbench that imports Simulink input stimuli, tb_filter_design.vhd. Click simulation Simulink generate input stimulus files choosing Start (Simulation menu). Close filtering design file when finished generating input stimulus files.
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Exercise Perform Simulation
perform simulation with ModelSim software, follow these steps: shorter simulation times, ModelSim software. Start ModelSim software. Choose Change Directory (File menu). Browse your working directory click Open. Choose Execute Macro (Tools menu). Browse tb_filter_design.tcl script click Open. simulation results displayed waveform. ModelSim waveform editor displays signals decimal notation (see Figure analog waveform (see Figure 16).
Figure ModelSim Waveform Editor
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Stratix Filtering Reference Design
display analog waveform, right-click signal (shown Figure select Format Analog. This opens Wave Analog window. Turn Analog Step click Figure ModelSim Analog Waveform
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Exercise Analyze Results Hardware
Exercise Analyze Results Hardware
Exercise includes following actions:
Stratix EP1S25 development board Stratix EP1S80 development board hardware analysis. Review changes made filtering reference design. Program Stratix EP1S25 device Stratix EP1S80 device with filtering reference design. must select correct device development board SignalTap analysis Builder examine filtered unfiltered data.
Stratix EP1S25 Development Board Hardware Analysis
Before performing hardware analysis, must connect cables board: cable ByteBlasterMVcable. includes both cables. connect cables, follow these steps: Connect SLP-50 anti-aliasing filter D/A2 board. Connect cable SLP-50 anti-aliasing filter A/D1 board. Connect ByteBlasterMV cable your board's 10-pin Joint Test Action Group (JTAG) header Stratix configuration.
Align ByteBlasterMV connector that stripe oriented towards Altera logo board.
After connect cables, connect jumper across jumper pins JP23 board (see Figure 17). jumper settings connect onboard 80-MHz oscillator A/D1.
detailed instructions connect cables board, Stratix EP1S25 Development Board Data Sheet. details installing ByteBlasterMV driver (Windows 2000, ByteBlasterMV Download Cable User Guide.
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Stratix Filtering Reference Design
Figure Stratix EP1S25 Development Board Jumper Connections JP23
JP23
Stratix EP1S80 Development Board Hardware Analysis
Before performing hardware analysis, must connect cables board: cable ByteBlasterMV cable. includes both cables. connect cables, follow these steps: Connect SLP-50 anti-aliasing filter D/A2 board. Connect cable SLP-50 anti-aliasing filter A/D1 board. Connect ByteBlasterMV cable your board's 10-pin JTAG header Stratix configuration.
After connect cables, connect jumper across jumper pins JP23 board (see Figure 18). jumper settings connect onboard 80-MHz oscillator A/D1. Connect jumper across pins JP26 connect PLL-generated clock from Stratix EP1S80 device D/A2 (see Figure 18).
detailed instructions connect cables board, Stratix EP1S80 Development Board Data Sheet. details installing ByteBlasterMV driver (Windows 2000, ByteBlasterMV Download Cable User Guide. Figure Stratix EP1S80 Development Board Jumper Connections JP23 JP26
JP23 JP26
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Exercise Analyze Results Hardware
Review Changes Made Filtering Reference Design
review changes made filtering reference design, follow these steps: MATLAB software. Current Directory browser, browse following directories:
Stratix EP1S25 development board:
Stratix EP1S80 development board:
Choose Open (File menu) select file filter_design.mdl. Review schematic design (see Figure page 26). figure shows filtering reference design Stratix EP1S25 development board. design Stratix EP1S80 development board same, except Stratix Board 1S25 Configuration block replaced with Stratix Board 1S80 Configuration block. filtering reference design Exercise same used Exercises (see Figure page except:
output adder directly connected input filter. adder output connected converter filter input connected converter. combined NCO-generated sinusoids converted from onboard converters. signal exits board connector, loops back into board through connector, converted digital onboard converters before re-entering Stratix device. cable securely connected between ADC, signal output filter during SignalTap analysis.
output adder bitwise function. function converts output from two's complement format unsigned integer format inverting most significant
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Stratix Filtering Reference Design
(MSB) offset 213. This conversion needed because onboard converters assume input samples unsigned integers.
register placed after bitwise function reduce (clock output delay) transmit circuitry. counter circuit been added generate pulse every 4,096 clock cycles after reset asserted.
Figure Simulink Design Exercise (filter_design.mdl File)
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Exercise Analyze Results Hardware
Program Stratix EP1S25 EP1S80 Device
program Stratix EP1S25 EP1S80 device, follow these steps: Double-click SignalCompiler block shown Figure Click Analyze shown Figure page Signal Compiler window opens shown Figure page Under Hardware Compilation section Signal Compiler window, Click Convert VHDL. Signal Compiler generates script that SignalTap analysis "Perform SignalTap Analysis". design been precompiled. design, skip synthesis fitting steps. step choose recompile design, must: Turn SignalTap option Signal Compiler Project Setting Options section Signal Compiler window.
Perform Hardware Compilation: Click Convert VHDL Click Synthesis Click Quartus Filter
Click Program Device. Click
Perform SignalTap Analysis
filter_design.mdl, specify falling edge trigger condition count_reached_tap, follow these steps: Double-click SignalTap Analysis block. SignalTap Analyzer displays nodes connected SignalTap blocks signals analyzed. Click count_reached_tap under Signal Name. Choose Falling Edge Trigger Condition list. Click Change. condition updated.
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Stratix Filtering Reference Design
Right click adder_result_tap select Unsigned Decimal radix (see Figure 20).
Figure Specify Radix Unsigned adder_result_tap
Figure shows switch locations EP1S25 development board. Figure Stratix EP1S25 Development Board
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Exercise Analyze Results Hardware
Figure shows switch locations EP1S80 development board. Figure Stratix EP1S80 Development Board
analyzer display results MATLAB plot, follow these steps: using Stratix EP1S25 development board, turn board enable counter circuit shown Figure counter circuit count_reached falling edge used trigger condition each 4,096 clock cycles. using Stratix EP1S80 development board, turn board enable counter circuit shown Figure counter circuit count_reached falling edge used trigger condition each 4,096 clock cycles. Click Start Analysis. Builder runs script instruct SignalTap embedded logic analyzer begin analyzing data wait trigger conditions occur. Click SignalTap Analysis block when SignalTap logic analyzer finishes acquiring data. SignalTap Analysis block indicates that finished acquiring data displaying message "SignalTap Analysis complete." MATLAB plots display captured data: binary format, radix specified. MATLAB plots display captured data time domain.
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Stratix Filtering Reference Design
Close MATLAB plot data displayed binary format. Examine MATLAB plot data displayed radix specified. Zoom fir_result_tap signal (see Figure 23). fir_result_tap signal scaled version 1-MHz sinusoid.
Figure SignalTap Signals Time Domain
Return MATLAB window. MATLAB window, type following command: filter_design_tap_variables This command runs Builder-generated script that reads SignalTap data into MATLAB workspace.
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Exercise Analyze Results Hardware
view filtered unfiltered signals, type following command MATLAB command window:
Response Unfiltered Data',8e7) where:
adder_result_tap name signal represented adder_result_tap SignalTap block Simulink model Frequency Response Unfiltered Data title plot sampling frequency MHz)
previously described, onboard converters assume unsigned integer inputs, output adder converted from signed integer unsigned integer (see Figure page 26). conversion adds component plot that removed nplot_fft script (normalized plot_fft script). difference data type format (signed integer unsigned integer) simulation emulation tools (Simulink SignalTap result different background noise representation between Figure page Figure page basics similar-two peaks background noise about lower.
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Stratix Filtering Reference Design
MATLAB plot displays frequency response unfiltered data (see Figure 24). Figure Response adder_result_tap-Unfiltered Data
view frequency response filtered data, type following command MATLAB command window:
Response Filtered Data',8e7) where:
fir_result_tap name signal represented fir_result_tap SignalTap block Simulink model Filtered Response Filtered Data title plot sampling frequency MHz)
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Exercise Analyze Results Hardware
MATLAB plot displays frequency response filtered data (see Figure 25). Figure Response fir_result_tap-Filtered Data
Compare filtered data plots SignalTap board results (Figure with Simulink simulation results (Figure page 18). Both results show sine wave pass filtered sine wave.
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Stratix Filtering Reference Design
Troubleshooting
This section provides troubleshooting information.
Errors When Load Simulink filter_design.mdl Design?
order load filter_design.mdl successfully, must have correct versions Builder, MATLAB/Simulink, cores. "Before Begin" page details.
SignalTap Filtered Signal Different From Figure shows?
cable securely connected between D/A2 A/D1, signal output filter during SignalTap analysis. Figure page
Conclusion
Stratix Stratix Professional filtering reference designs provide basic design example using onboard converters converters. demonstrates SignalTap real-time FPGA signal acquisition feature Builder environment Simulink.
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com
Copyright 2004 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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