AGX52010-1.1 ArriaGX devices have dedicated digital signal proces

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AGX52010-1.1 ArriaGX devices have dedicated digital signal proces

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Blocks Arria Devices
AGX52010-1.1
ArriaGX devices have dedicated digital signal processing (DSP) blocks optimized applications requiring high data throughput. These blocks combined with flexibility programmable logic devices (PLDs), provide with ability implement various high performance functions easily. Complex systems such CDMA2000, voice over Internet protocol (VoIP), high-definition television (HDTV) require high performance blocks process data. These system designs typically blocks finite impulse response (FIR) filters, complex filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions, correlators. Arria blocks consist combination dedicated blocks that perform multiplication, addition, subtraction, accumulation, summation operations. configure these blocks implement arithmetic functions like multipliers, multiply-adders multiplyaccumulators which necessary most functions. Along with blocks, TriMatrixmemory structures Arria devices also support various soft multiplier implementations. combination soft multipliers dedicated blocks increases number multipliers available Arria devices provides with wide variety implementation options flexibility when designing your systems.
more information about Arria devices respectively, Arria Device Family Data Sheet volume Arria Device Handbook. Each Arria device four columns blocks that efficiently implement multiplication, multiply-accumulate (MAC) multiply-add functions. Figure 10-1 shows arrangement block columns with surrounding LABs. Each block configured support:
Block Overview
Eight 9-bit multipliers Four 18-bit multipliers 36-bit multiplier
Altera Corporation August 2007
10-1 Preliminary
Blocks Arria Devices
Figure 10-1. Blocks Arranged Columns with Adjacent LABs
Block Column
Rows
Block
multipliers then feed adder accumulator block within block. Arria device multipliers support rounding saturation Q1.15 input formats. block also input registers that configured operate shift register chain efficient implementation functions such filters. accumulator within block initialized value supports rounding saturation Q1.15 input formats multiplier. single block broken down operate different configuration modes simultaneously. more information Q1.15 formatting, section "Saturation Rounding" page 10-11.
10-2 Arria Device Handbook, Volume
Altera Corporation August 2007
Block Overview
number blocks column number columns available increases with device density. Table 10-1 shows number blocks each Arria device multipliers that implement.
Table 10-1. Number Blocks Arria Devices Note Device
EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E EP1AGX90E Note Table 10-1:
Each device either number 18-, 36-bit multipliers shown. total number multipliers each device multipliers.
Blocks
Multipliers
Multipliers
Multipliers
addition block multipliers, Arria device's TriMatrix memory blocks soft multipliers. availability soft multipliers increases number multipliers available within device. Table 10-2 shows total number multipliers available Arria devices using blocks soft multipliers.
Table 10-2. Number Multipliers Arria Devices Device
EP1AGX20C EP1AGX35C/D EP1AGX50C/D EP1AGX60C/D/E
Blocks
Soft Multipliers (1),
Total Multipliers (3),
(3.55) (3.18) (2.94) (2.65)
Altera Corporation August 2007
10-3 Arria Device Handbook, Volume
Blocks Arria Devices
Table 10-2. Number Multipliers Arria Devices Device
EP1AGX90E Notes Table 10-2:
Soft multipliers implemented multiplication mode. blocks configured with 18-bit data widths coefficients 18-bits. Soft multipliers only implemented M512 TriMatrix memory blocks, M-RAM blocks. number parentheses represents increase factor, which total number multipliers with soft multipliers divided number multipliers supported blocks only. total number multipliers vary according multiplier mode used.
Blocks
Soft Multipliers (1),
Total Multipliers (3),
(2.84)
Refer Arria Architecture chapter volume Arria Device Handbook more information about Arria TriMatrix memory blocks. Refer 306: Implementing Multipliers FPGA Devices more information soft multipliers.
10-4 Arria Device Handbook, Volume
Altera Corporation August 2007
Block Overview
Figure 10-2 shows block configured multiplier mode. Figure 10-2. Block Mode
Optional Serial Shift Register Inputs from Previous Block
Adder Output Block
Multiplier Block
Q1.15 Round/ Saturate
Output Selection Multiplexer
CLRN
From interface block
CLRN
CLRN
Optional Stage Configurable Accumulator Dynamic Adder/Subtractor
Adder/ Subtractor/ Accumulator
Q1.15 Round/ Saturate
Q1.15 Round/ Saturate
CLRN
CLRN Summation Block
Adder
CLRN
CLRN
Q1.15 Round/ Saturate
CLRN
CLRN
CLRN
Summation Stage Adding Four Multipliers Together
Adder/ Subtractor/ Accumulator
Q1.15 Round/ Saturate
Q1.15 Round/ Saturate
CLRN
Optional Serial Shift Register Outputs Next Block Column
CLRN
Optional Pipline Register Stage
CLRN
Optional Input Register Stage with Parallel Input Shift Register Configuration
MultiTrack Interconnect
Altera Corporation August 2007
10-5 Arria Device Handbook, Volume
Blocks Arria Devices
Figure 10-3 shows multiplier configuration block. Figure 10-3. Block Mode
CLRN CLRN
CLRN
Adder/ Subtractor/
CLRN CLRN
CLRN
Summation
CLRN CLRN
CLRN
Adder/ Subtractor/
CLRN CLRN
CLRN
Output Selection Multiplexer
CLRN
CLRN CLRN
CLRN
Adder/ Subtractor/
CLRN CLRN
CLRN
Summation
CLRN CLRN
CLRN
Adder/ Subtractor/
CLRN CLRN
CLRN
MultiTrack Interconnect
10-6 Arria Device Handbook, Volume
Altera Corporation August 2007
Architecture
Architecture
block consists following elements:
multiplier block adder/subtractor/accumulator block summation block Input output interfaces Input output registers
Multiplier Block
Each multiplier block following elements:
Input registers multiplier block rounding and/or saturation stage Q1.15 input formats pipeline output register
Figure 10-4 shows multiplier block architecture. Figure 10-4. Multiplier Block Architecture
mult_round mult_saturate signa signb aclr[3.0] shiftinb clock[3.0] shiftina ena[3.0] sourcea
Data
Q1.15 Round/ Saturate
Data
CLRN
CLRN
sourceb Data
CLRN
Pipeline Register
Output Register
mult_is_saturated
CLRN
Multiplier Block
Block
shiftoutb shiftouta
Notes Figure 10-4:
These signals registered registered once match data path pipeline. send these signals through either pipeline registers. rounding and/or saturation only supported 18-bit signed multiplication Q1.15 inputs.
Altera Corporation August 2007
10-7 Arria Device Handbook, Volume
Blocks Arria Devices
Input Registers
Each multiplier operand feed input register directly multiplier. following block signals control each input register within block:
clock[3.0] ena[3.0] aclr[3.0]
input registers feed multiplier drive dedicated shift output lines, shiftouta shiftoutb. dedicated shift outputs from multiplier block directly feed input registers adjacent multiplier below within same block first multiplier next block form shift register chain, shown Figure 10-5. dedicated shift register chain spans single column longer shift register chains requiring multiple columns implemented using regular FPGA routing resources. Therefore, this shift register chain length registers largest member Arria device family. Shift registers useful functions such filters. When implementing multipliers, need external logic create shift register chain because input shift registers internal block. This implementation significantly reduces resources required, avoids routing congestion, results predictable timing. Arria blocks allow dynamically select whether particular multiplier operand regular data input dedicated shift register input using sourcea sourceb signals. logic value sourcea signal indicates that data dedicated scan-chain; logic value indicates that regular data input. This feature allows implementation dynamically loadable shift register where shift register operates normally using scan-chains also loaded dynamically parallel using data input value. Figure 10-5 shows shift register chain.
10-8 Arria Device Handbook, Volume
Altera Corporation August 2007
Architecture
Figure 10-5. Shift Register Chain Note
Block Data CLRN
Q1.15 Round/ Saturate
A[n] B[n] CLRN
Data
CLRN
shiftoutb
shiftouta
Q1.15 Round/ Saturate
CLRN
CLRN
CLRN
shiftoutb
shiftouta Block CLRN
Q1.15 Round/ Saturate
CLRN
CLRN
shiftoutb
shiftouta
Note Figure 10-5:
Either Data Data input parallel input constant coefficient multiplication.
Altera Corporation August 2007
10-9 Arria Device Handbook, Volume
Blocks Arria Devices
Table 10-3 shows summary input register modes block.
Table 10-3. Input Register Modes Register Input Mode
Parallel input Shift register input
Multiplier Stage
multiplier stage supports multipliers well other smaller multipliers between these configurations. "Operational Modes" page 10-19 details. Depending data width multiplier, single block perform many multiplications parallel. Each multiplier operand unique signed unsigned number. signals, signa signb, control representation each operand respectively. logic value signa signal indicates that data signed number while logic value indicates unsigned number. Table 10-4 shows sign multiplication result various operand sign representations. result multiplication signed operands signed value.
Table 10-4. Multiplier Sign Representation Data (signa Value)
Unsigned (logic Unsigned (logic Signed (logic Signed (logic
Data (signb Value)
Unsigned (logic Signed (logic Unsigned (logic Signed (logic
Result
Unsigned Signed Signed Signed
There only signa signb signal each block. Therefore, data inputs feeding same block must have same sign representation. Similarly, data inputs feeding same block must have same sign representation. multiplier offers full precision regardless sign representation. When signa signb signals unused, Quartus® software sets multiplier perform unsigned multiplication default.
10-10 Arria Device Handbook, Volume
Altera Corporation August 2007
Architecture
Saturation Rounding
blocks have hardware support perform optional saturation rounding after each multiplier Q1.15 input formats. Designs must multipliers saturation rounding options because Q1.15 input format requires 16-bit input widths. Q1.15 input format multiplication requires signed multipliers. most significant (MSB) Q1.15 input format represents value's sign bit. signed multipliers ensure proper sign extension during multiplication.
Q1.15 format uses bits represent each fixed point input. sign bit, remaining 15-bits used represent value after decimal place fractional value). This Q1.15 value equivalent integer number representation 16-bits divided 215, shown following equations.
0000 0000 0000 0x4000 0x1000
0000 0000 0000
Q1.15 numbers between When performing multiplication, even though Q1.15 input only uses multiplier inputs, entire 18-bit input transmitted multiplier. This similar 1.17 input, where least significant bits (LSBs) always multiplier output will 2.34 value bits total) before performing rounding saturation. MSBs sign bits. Since output only requires sign bit, ignore MSBs, resulting Q1.34 value before rounding saturation. When design performs saturation, multiplier output gets saturated 0x7FFFFFFF 1.31 format. This uses bits [34.3] overall 36-bit multiplier output. three LSBs block obtains mult_is_saturated accum_is_saturated overflow signal value from multiplier accumulator output. Therefore, whenever saturation occurs, multiplier accumulator output sends
Altera Corporation August 2007
10-11 Arria Device Handbook, Volume
Blocks Arria Devices
mult_is_saturated accum_is_saturated overflow signal. other times, this overflow signal when saturation enabled reflects value multiplier accumulator output. When design performs rounding, adds 0x00008000 1.31 format multiplier output, only uses bits [34.15] overall 36-bit multiplier output. Adding 0x00008000 1.31 format 36-bit multiplier result equivalent adding 0004 0000 2.34 format. LSBs Figure 10-6 shows which bits used when design performs rounding saturation multiplication.
10-12 Arria Device Handbook, Volume
Altera Corporation August 2007
Architecture
Figure 10-6. Rounding Saturation Bits
Multiplication
Sign
Bits
LSBs
Sign Bits
Bits
LSBs
Sign
Bits
LSBs
Saturated Output Result
Sign Bits
Bits
LSBs
111000
Rounded Output Result
Sign Bits
Bits
LSBs
Sign Bits
Bits
Bits
0000 0000 000001 0000 0000 000000
LSBs Ignored
0000 0000 00000
Note Figure 10-6:
Both sign bits same. design only uses sign bit, other ignored.
design performs multiply_accumulate multiply_add operation, multiplier output input adder/subtractor/accumulator blocks 2.31 value, three LSBs
Altera Corporation August 2007
10-13 Arria Device Handbook, Volume
Blocks Arria Devices
Pipeline Registers
output from multiplier feed pipeline register this register bypassed. Pipeline registers implemented multiplier size increase block's maximum performance, especially when using subsequent block adder stages. Pipeline registers split long signal path between adder/subtractor/accumulator block adder/output block, creating shorter paths.
Adder/Output Block
adder/output block following elements:
adder/subtractor/accumulator block summation block output select multiplexer Output registers
adder/output block configured
output interface accumulator which optionally loaded one-level adder two-level adder with dynamic addition/subtraction control first-level adder final stage 36-bit multiplier, complex multiplier, complex multiplier
output select multiplexer sets output configuration block. output registers used register output adder/output block. adder/output block cannot used independently from multiplier.
10-14 Arria Device Handbook, Volume
Altera Corporation August 2007
Architecture
Figure 10-7 shows adder/output block architecture. Figure 10-7. Adder/Output Block Architecture
adder1_round Accumulator Feedback
Output Select Multiplexer
Result accum_sload_upper_data accum_sload0 Adder/ Subtractor/ Accumulator overflow0
Output Registers
addnsub1
Q1.15 Rounding
Result signa
Summation signb Result accum_sload_upper_data accum_sload1
Q1.15 Rounding
Output Register Block
addnsub3
Adder/ Subtractor/ Accumulator
overflow1
Result adder3_round
Accumulator Feedback
Notes Figure 10-7:
adder/output block mode. mode, there four adder/subtractor blocks summation blocks. send these signals through pipeline register. pipeline length Q1.15 inputs available modes.
Adder/Subtractor/Accumulator Block
adder/subtractor/accumulator block first level adder stage adder/output block. This block configured accumulator adder/subtractor.
Altera Corporation August 2007
10-15 Arria Device Handbook, Volume
Accumulator
Accumulator
When adder/subtractor/accumulator configured accumulator, output adder/output block feeds back accumulator shown Figure 10-7. accumulator perform addition only, subtraction only addnsub signal used dynamically control accumulation direction. logic value addnsub signal indicates that accumulator performing addition while logic value indicates subtraction. Each accumulator cleared either clearing block output register using accum_sload signal. accumulator clear using accum_sload signal independent from resetting output registers accumulation cleared begin without losing clock cycles. accum_sload signal controls feedback multiplexer that specifies that output multiplier should summed with zero instead accumulator feedback path. accumulator also initialized/preloaded with non-zero value using accum_sload signal accum_sload_upper_data with clock cycle latency. Preloading accumulator done adding result multiplier with value specified accum_sload_upper_data bus. case accumulator clearing, accum_sload signal specifies feedback multiplexer that accum_sload_upper_data signal should feed accumulator instead accumulator feedback signal. accum_sload_upper_data signal only loads upper 36-bits accumulator. load entire accumulator, value lower 16-bits must sent through multiplier feeding that accumulator with multiplier perform multiplication one. overflow signal will high positive edge clock when accumulator detects overflow underflow. overflow signal will stay high only clock cycle after overflow underflow detected even overflow underflow condition still present. latch external block used preserve overflow signal indefinitely until latch cleared. blocks support Q1.15 input format saturation rounding each accumulator. following signals available that control saturation rounding both performed output accumulator:
accum_round accum_saturation accum_is_saturated output
Altera Corporation August 2007
10-16 Arria Device Handbook, Volume
Accumulator
Each block sets accum_round accum_saturation signals which control rounding saturation performed accumulator output respectively (one signals each accumulator). Rounding saturation accumulator output only available when implementing multiplier-accumulator conform widths required Q1.15 input format computation. logic value accum_round accum_saturation signal indicates that rounding saturation performed while logic indicates that rounding saturation performed. logic value accum_is_saturated output signal tells that saturation occurred result accumulator. Figure 10-10 shows block configured perform multiplieraccumulator operations. Adder/Subtractor addnsub1 addnsub3 signals specify whether performing addition subtraction. logic value addnsub1 addnsub3 signals indicates that adder/subtractor performing addition while logic value indicates subtraction. These signals dynamically controlled using logic external block. first stage configured subtractor, output adder/subtractor block share same signa signb signals multiplier block. signa signb signals pipelined with latency clock cycles not. blocks support Q1.15 input format rounding (not saturation) after each adder/subtractor. addnsub1_round addnsub3_round signals determine rounding performed output adder/subtractor. addnsub1_round signal controls rounding adder/subtractor addnsub3_round signal controls rounding bottom adder/subtractor. Rounding adder output only available when implementing multiplier-adder conform widths required Q1.15 input format computation. logic value addnsub_round signal indicates that rounding performed while logic indicates that rounding performed.
Summation Block
output adder/subtractor block feeds optional summation block, which adder block that sums outputs both adder/subtractor blocks. summation block used when more than multiplier results summed. This useful applications such filtering.
Altera Corporation August 2007
10-17 Arria Device Handbook, Volume
Accumulator
Output Select Multiplexer
outputs different elements adder/output block routed through output select multiplexer. Depending operational mode block, output multiplexer selects whether outputs blocks comes from outputs multiplier block, outputs adder/subtractor/accumulator, output summation block. output select multiplier configuration automatically software, based block operational mode specify.
Output Registers
output registers register block output. following signals control each output register within block:
clock[3.0] ena[3.0] aclr[3.0]
output registers used block operational mode. output registers form part accumulator multiply-accumulate mode.
Refer Arria Architecture chapter volume Arria Device Handbook more information block routing interface.
Altera Corporation August 2007
10-18 Arria Device Handbook, Volume
Operational Modes
Operational Modes
block used four basic operational modes, combination modes, depending application needs. Table 10-5 shows four basic operational modes number multipliers that implemented within single block depending mode.
Table 10-5. Block Operational Modes Mode Number Multipliers
Simple multiplier Eight multipliers with eight product outputs
Four multipliers with four product outputs 52-bit multiplyaccumulate blocks
multiplier
Multiply accumulate Two-multiplier adder Four-multiplier adder
Four two-multiplier two-multiplier adder (one adder (two complex multiply) complex multiply) four-multiplier adder four-multiplier adder
Quartus software includes megafunctions used control mode operation multipliers. After make appropriate parameter settings using megafunction's MegaWizard® Plug-In Manager, Quartus software automatically configures block. Arria blocks operate different modes simultaneously. example, single block broken down operate multiplier well multiplier-adder where both multiplier's input input have same sign representations. This increases block resource efficiency allows implement more multipliers within Arria device. Quartus software automatically places multipliers that share same block resources within same block. Additionally, each Arria block dynamically switch between following three modes:
four 18-bit independent multipliers 18-bit multiplier-accumulators 36-bit multiplier
Altera Corporation August 2007
10-19 Arria Device Handbook, Volume
Operational Modes
Each half Arria block separate mode control signals, which allows implement multiple 18-bit multipliers multiplieraccumulators within same block dynamically switch them independently they separate block halves). design requires 36-bit multiplier, must switch entire block accommodate since multiplier requires entire block. smallest input width that supports dynamic mode switching bits.
Simple Multiplier Mode
simple multiplier mode, block performs individual multiplication operations general-purpose multipliers applications such computing equalizer coefficient updates which require many individual multiplication operations.
18-Bit Multipliers
Each block multiplier configured 18-bit multiplication. single block support eight individual multipliers four individual multipliers. operand widths 9-bits, multiplier will implemented operand widths from 18-bits, multiplier will implemented. Figure 10-8 shows block simple multiplier operation mode.
Altera Corporation August 2007
10-20 Arria Device Handbook, Volume
Operational Modes
Figure 10-8. Simple Multiplier Mode
mult_round mult_saturate signa signb aclr[3.0] shiftinb clock[3.0] shiftina ena[3.0] sourcea
Output Register
CLRN sourceb Data CLRN CLRN Multiplier Block Block shiftoutb shiftouta CLRN
Q1.15 Round/ Saturate
Data CLRN mult_is_saturated
Data
Notes Figure 10-8:
These signals registered registered once match data path pipeline. This signal same latency data path. rounding saturation only supported 18-bit signed multiplication Q1.15 inputs.
multiplier operands accept signed integers, unsigned integers combination both. signa signb signals changed dynamically registered block. Additionally, multiplier inputs result registered independently. pipeline registers within block used pipeline multiplier result, increasing performance block.
36-Bit Multiplier
36-bit multiplier also simple multiplier mode uses entire block, including adder/output block implement 36-bit multiplication operation. device inputs 18-bit sections 36-bit input into four 18-bit multipliers. adder/output block adds partial products obtained from multipliers using summation block. Pipeline registers used between multiplier stage summation block speed multiplication. 36-bit multiplier supports signed, unsigned well mixed sign multiplication. Figure 10-9 shows block configured implement 36-bit multiplier.
Altera Corporation August 2007
10-21 Arria Device Handbook, Volume
Operational Modes
Figure 10-9. 36-Bit Multiplier
signa signb aclr clock
A[17.0]
CLRN
CLRN CLRN
B[17.0]
A[35.18]
Data
CLRN
B[35.18]
CLRN
CLRN
Multiplier Adder signa signb
CLRN
A[35.18]
CLRN
CLRN CLRN
B[17.0]
A[17.0]
CLRN
CLRN CLRN
B[35.18]
Notes Figure 10-9:
These signals either registered registered once match pipeline. These signals either registered, registered once, registered twice match data path pipeline.
Altera Corporation August 2007
10-22 Arria Device Handbook, Volume
Operational Modes
36-bit multiplier useful applications requiring more than 18-bit precision, example, mantissa multiplication precision floating-point arithmetic applications.
Multiply Accumulate Mode
multiply accumulate mode, output multiplier stage feeds adder/output block which configured accumulator subtractor. Figure 10-10 shows block configured operate multiply accumulate mode. Figure 10-10. Multiply Accumulate Mode
aclr[3.0] clock[3.0] ena[3.0] shiftinb shiftina accum_sload_upper_data accum_sload
Data
Q1.15 Round/ Saturate
Accumulator CLRN
Q1.15 Round/ Saturate
Data
CLRN
CLRN
accum_is_saturated Data CLRN
overflow
mult_is_saturated
shiftoutb
shiftouta
signb (1), signa (1), mult_round mult_saturate
addnsub signb (1), signa (1), accum_round accum_saturate
Notes Figure 10-10:
signa signb signals same multiplier stage adder/output block. These signals registered registered once match data path pipeline. send these signals through either pipeline registers. These signals match latency data path.
single block implement independent 18-bit multiplier accumulators. Quartus software implements smaller multiplier accumulators tying unused lower-order bits 18-bit multiplier ground. multiplier accumulator output 52-bits wide account 36-bit multiplier result with 16-bits accumulation. this mode, block uses output registers accum_sload overflow
Altera Corporation August 2007
10-23 Arria Device Handbook, Volume
Blocks Arria Devices
signals. accum_sload signal used clear accumulator that accumulation operation begin without losing clock cycles. This signal unregistered registered once twice. accum_sload signal also used preload accumulator with value specified accum_sload_upper_data signal with clock cycle penalty. accum_sload_upper_data signal only loads upper 36-bits (bits [51.16] accumulator). load entire accumulator, value lower 16-bits (bits [15.0]) must sent through multiplier feeding that accumulator with multiplier perform multiplication one. Bits [17.16] overlapped both accum_sload_upper_data signal multiplier output. Either these signals used load bits [17.16]. overflow signal indicates overflow underflow accumulator. This signal gets updated every clock cycle accumulation operation every cycle. preserve signal, external latch used. addnsub signal used specify accumulation subtraction performed dynamically. block implement just accumulator (without multiplication) specifying multiply multiplier stage followed accumulator force Quartus software implement function within block.
Multiply Mode
multiply mode, output multiplier stage feeds adder/output block which configured adder subtractor subtract outputs more multipliers. block configured implement either two-multiply (where outputs multipliers added/subtracted together) four-multiply function (where outputs four multipliers added subtracted together). adder block within block only used follows multiplication operations.
Two-Multiplier Adder
two-multiplier adder configuration, block implement four 9-bit smaller multiplier adders 18-bit multiplier adders. adders configured take both multiplier outputs difference both multiplier outputs. have option vary summation/subtraction operation dynamically. These multiply functions useful applications such FFTs complex filters. Figure 10-11 shows block configured two-multiplier adder mode.
10-24 Arria Device Handbook, Volume
Altera Corporation August 2007
Complex Multiply
Figure 10-11. Two-Multiplier Adder Mode
mult_round mult_saturate signa signb aclr[3.0] clock[3.0] ena[3.0] signb signa addnsub_round addnsub1
shiftina shiftinb
mult0_is_saturated
Data
Q1.15 Round/ Saturate
CLRN
CLRN
Data
Adder/ Subtractor/ Accumulator Q1.15 Rounding
CLRN
CLRN
Data
Data
Q1.15 Round/ Saturate
CLRN
CLRN mult1_is_saturated
Data
shiftoutb
shiftouta
Notes Figure 10-11:
These signals registered registered once match data path pipeline. send these signals through pipeline register. pipeline length These signals match latency data path.
Complex Multiply
block configured implement complex multipliers using two-multiplier adder mode. single block implement 18-bit complex multiplier 9-bit complex multipliers. complex multiplication written ((ac) (bd)) ((ad) (bc)) implement this complex multiplication within block, real part ((ac) (bd)) implemented using multipliers feeding subtractor block while imaginary part ((ad) (bc)) implemented using another multipliers feeding adder block, data
Altera Corporation August 2007
10-25 Arria Device Handbook, Volume
Blocks Arria Devices
18-bits. Figure 10-12 shows 18-bit complex multiplication. data widths 9-bits, block perform separate complex multiplication operations using eight 9-bit multipliers feeding four adder/subtractor/accumulator blocks. Resources external block must used route correct real imaginary input components appropriate multiplier inputs perform correct computation complex multiplication operation. Figure 10-12. Complex Multiplier Using Two-Multiplier Adder Mode
Block Adder (Imaginary Part) Subtractor (Real Part)
Four-Multiplier Adder
four-multiplier adder configuration, block implement individual multiplier adders. These modes useful implementing one-dimensional two-dimensional filtering applications. four-multiplier adder performed addition stages. outputs four multipliers initially summed first-stage adder/subtractor/accumulator blocks. results these adder/subtractor/accumulator blocks then summed final stage summation block produce final four-multiplier adder result. Figure 10-13 shows block configured fourmultiplier adder mode.
10-26 Arria Device Handbook, Volume
Altera Corporation August 2007
Complex Multiply
Figure 10-13. Four-Multiplier Adder Mode
mult_round mult_saturate signa signb aclr[3.0] clock[3.0] ena[3.0]
shiftina shiftinb
mult0_is_saturated
CLRN CLRN
Q1.15 Round/ Saturate
CLRN
Data
Data CLRN
CLRN
Adder/ Subtractor/ Accumulator
Q1.15 Rounding
Data
Q1.15 Round/ Saturate
mult1_is_saturated
CLRN
Data
CLRN
CLRN
CLRN
addnsub1 addnsub1/3_round signa signb addnsub3
Adder
CLRN
Data
mult0_is_saturated
CLRN CLRN
Q1.15 Round/ Saturate
Data
CLRN
Data CLRN
CLRN
Adder/ Subtractor/ Accumulator
Q1.15 Rounding
Data
Q1.15 Round/ Saturate
CLRN
Data
CLRN
mult1_is_saturated
CLRN
CLRN
shiftoutb
shiftouta
Notes Figure 10-13:
These signals registered registered once match data path pipeline. should send these signals through pipeline register match latency data path. These signals match latency data path. rounding saturation only supported 18-bit signed multiplication Q1.15 inputs.
Altera Corporation August 2007
10-27 Arria Device Handbook, Volume
Blocks Arria Devices
Filter
four-multiplier adder mode used implement filter complex filter applications. this, block four-multiplier adder mode with input registers configured shift registers using dedicated shift register chain. input registers configured shift registers will contain input data while inputs configured regular inputs will hold filter coefficients. Figure 10-14 shows block configured four-multiplier adder mode using input shift registers.
10-28 Arria Device Handbook, Volume
Altera Corporation August 2007
Filter
Figure 10-14. Filter Implemented Using Four-Multiplier Adder Mode with Input Shift Registers
Data
CLRN
A[n] Coefficient Adder)
Coefficient
CLRN
CLRN
CLRN
Coefficient Adder)
Coefficient
CLRN
CLRN
CLRN
Coefficient Adder)
Coefficient
CLRN
CLRN
Altera Corporation August 2007
10-29 Arria Device Handbook, Volume
Blocks Arria Devices
built-in input shift register chain within block eliminates need shift registers externally block logic elements (LEs). This architecture feature simplifies filter design improves filter performance because filter circuitry localized within block. Input shift registers 36-bit simple multiplier mode have implemented using external registers block.
single block implement four 18-bit filter. filters larger than four taps, blocks cascaded with additional adder stages implemented using LEs.
Software Support
Altera provides distinct methods implementing various modes block your design: instantiation inference. Both methods following three Quartus megafunctions:
lpm_mult altmult_add altmult_accum
instantiate megafunctions Quartus software block. Alternatively, with inference, create design synthesize using third-party synthesis tool like LeonardoSpectrumor Synplify Quartus Native Synthesis that infers appropriate megafunction recognizing multipliers, multiplier adders, multiplier accumulators. Using either method, Quartus software maps functionality blocks during compilation.
Quartus On-Line Help instructions using megafunctions MegaWizard Plug-In Manager. more information, Design Synthesis section volume Quartus Development Software Handbook. Arria device blocks optimized support applications requiring high data throughput such filters, functions encoders. These blocks flexible configured implement several operational modes suit particular application. built-in shift register chain, adder/subtractor/accumulator block summation block minimizes amount external logic required implement these functions, resulting efficient resource utilization improved performance data throughput applications. Quartus
Conclusion
10-30 Arria Device Handbook, Volume
Altera Corporation August 2007
Referenced Documents
software, together with LeonardoSpectrumand Synplify software provide complete easy-to-use flow implementing these multiplier functions blocks.
Referenced Documents
This chapter references following documents:
306: Implementing Multipliers FPGA Devices Arria Architecture chapter volume Arria Device Handbook Arria Device Family Data Sheet volume Arria Device Handbook Design Synthesis section volume Quartus Development Software Handbook
Document Revision History
Table 10-6 shows revision history this chapter.
Table 10-6. Document Revision History Date Document Version
Minor text edits. 2007, v1.0 Initial Release
Changes Made
Summary Changes
August 2007, v1.1 Added "Referenced Documents" section.
Altera Corporation August 2007
10-31 Arria Device Handbook, Volume
Blocks Arria Devices
10-32 Arria Device Handbook, Volume
Altera Corporation August 2007

AGX52010-1.1 ArriaGX devices have dedicated digital signal proces

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