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Macronix NBit Memory Family 64M-BIT CMOS SERIAL eLiteFlashMEMORY


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MX25L6405
Macronix NBit Memory Family
64M-BIT CMOS SERIAL eLiteFlashMEMORY
Auto Erase Auto Program Algorithm Automatically erases verifies data selected sector Automatically programs verifies data selected page internal algorithm that automatically times program pulse widths (Any page programed should have page erased state first) Status Register Feature Electronic Identification
GENERAL Serial Peripheral Interface (SPI) compatible Mode Mode 67,108,864 structure Equal Sectors with byte each sector erased Single Power Supply Operation volt read, erase, program operations Latch-up protected 100mA from write inhibit from 1.5V 2.5V PERFORMANCE High Performance Fast access time: 50MHz serial clock (30pF 1TTL Load) Fast program time: 3ms/page (typical, 256-byte page) Fast erase time: 1s/sector (typical, 64K-byte sector) 128s/chip (typical) Acceleration mode: Program time: 2.4ms/page (typical) Erase time: 0.8s/sector (typical) 102s/chip (typical) Power Consumption active read current: 30mA (max.) 50MHz active programming current: 30mA (max.) active erase current: 38mA (max.) standby current: 50uA (max.) Deep power-down mode (typical) Minimum erase/program cycle array Minimum 100K erase/program cycle additional SOFTWARE FEATURES Input Data Format 1-byte Command code
JEDEC 2-byte Device
command, 1-byte Device REMS command, ADD=00H will output manufacturer's first ADD=01H will output device first Additional sector independent from main memory parameter storage eliminate EEPROM from system HARDWARE FEATURES SCLK Input Serial clock input Input Serial Data Input SO/PO7 Serial Data Output Parallel mode Data output/input WP#/ACC Hardware write protection Program/erase acceleration HOLD# pause chip without diselecting chip (not paralled mode, please connect HOLD# during parallel mode) PO0~PO6 parallel mode data output/input PACKAGE 16-pin (300mil) Pb-free devices RoHS Compliant
P/N: PM1107
REV. 1.3, NOV. 2006
MX25L6405
GENERAL DESCRIPTION
MX25L6405 CMOS 67,108,864 serial eLiteFlashMemory, which configured 8,388,608 internally. MX25L6405 features serial peripheral interface software protocol allowing operation simple wire bus. three signals clock input (SCLK), serial data input (SI), serial data output (SO). access device enabled input. MX25L6405 provide sequential read operation whole chip. User start read from byte array. While array reached, device will wrap around beginning array continuously outputs data until goes high. After program/erase command issued, auto program/ erase algorithms which program/erase verify specified page locations will executed. Program command executed page (256 bytes) basis, erase command executed both chip sector (64K bytes) basis. provide user with ease interface, status register included indicate status chip. status read command issued detect completion error flag status program erase operation. increase user's factory throughputs, parallel mode provided. performance read/program dramatically improved than serial mode programmer machine. When device operation high, standby mode draws less than 50uA current. additional sector with 100K erase/program endurance cycles suitable parameter storage replaces EEPROM system. MX25L6405 utilizes MXIC's proprietary memory cell which reliably stores memory contents even after program erase cycles.
CONFIGURATIONS
16-PIN (300 mil)
HOLD# SO/PO7 SCLK WP#/ACC
DESCRIPTION
SYMBOL SO/PO7(1) SCLK HOLD#(2) WP#/ACC DESCRIPTION Chip Select Serial Data Input Serial Data Output Parallel Data output/input Clock Input Hold, pause serial communication (HOLD# parallel mode) Write Protection: connect GND; program/erase acceleration: connect 3.3V Power Supply Ground Parallel data output/input (PO0~PO6 connected serial mode) Internal Connection
PO0~PO6
Note: PO0~PO7 provided 8-LAND package. HOLD# recommended connect during parallel mode.
P/N: PM1107 REV.1.3, NOV. 2006
MX25L6405
BLOCK DIAGRAM
additional
Address Generator
X-Decoder
Memory Array
Data Register Y-Decoder SRAM Buffer Sense Amplifier Generator Output Buffer
CS#, ACC, WP#,HOLD#
Mode Logic
State Machine
SCLK
Clock Generator
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
DATA PROTECTION
MX25L6405 designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transition. During power device automatically resets state machine Read mode. addition, with control register architecture, alteration memory contents only occurs after successful completion specific command sequences. device also incorporates several features prevent inadvertent write cycles resulting from power-up power-down transition system noise. Power-on reset tPUW: avoid sudden power switch system power supply transition, poweron reset tPUW (internal timer) protect Flash. other command change data. will return reset stage under following situation: Power-up Write Disable (WRDI) command completion Write Status Register (WRSR) command completion Page Program (PP) command completion Sector Erase (SE) command completion Block Erase (BE) command completion Chip Erase (CE) command completion Software Protection Mode (SPM): using BP0-BP2 bits part Flash protected from data change. Hardware Protection Mode (HPM): using going protect BP0-BP2 bits SRWD from data change. Deep Power Down Mode: entering deep power down mode, flash device also under protected from writing commands except Release from deep power down mode command (RDP) Read Electronic Signature command (RES).
Valid command length checking: command length will checked whether byte base completed byte boundary. Write Enable (WREN) command: WREN command required Write Enable Latch (WEL) before
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Table Protected Area Sizes
(note2) Status Protection Area None Upper 128th (Sector 127) Upper 64th (two sectors: 127) Upper 32nd (four sectors: 127) Upper sixteenth (eight sectors: 127) Upper eigthth (sixteen sectors: 127) Upper quarter (thirty-two sectors: 127) Upper half (thirty-two sectors: 127)
Note device ready accept Chip Erase instruction only Block Protect (BP3, BP2, BP1, BP0)
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
HOLD FEATURE
HOLD# signal goes hold serial communications with device. HOLD feature will stop operation write status register, programming, erasing progress. operation HOLD requires Chip Select(CS#) keeping starts falling edge HOLD# signal while Serial Clock (SCLK) signal being Serial Clock signal being low, HOLD operation will start until Serial Clock signal being low). HOLD condition ends rising edge HOLD# signal while Serial Clock(SCLK) signal being low( Serial Clock signal being low, HOLD operation will until Serial Clock being low), Figure
Figure Hold Condition Operation
SCLK
HOLD#
Hold Condition (standard)
Hold Condition (non-standard)
Serial Data Output (SO) high impedance, both Serial Data Input (SI) Serial Clock (SCLK) don't care during HOLD operation. Chip Select (CS#) drives high during HOLD operation, will reset internal logic device. re-start communication with chip, HOLD# must high must low.
PROGRAM/ERASE ACCELERATION
activate program/erase acceleration function requires connecting voltage (see Figure then followed normal program/erase process. utilizing program/erase acceleration operation, performances improved shown table "ERASE PROGRAM PERFORMACE".
Figure ACCELERATED PROGRAM TIMING DIAGRAM
tVHH tVHH
Note: tVHH (VHH Rise Fall Time) min. 250ns
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Table COMMAND DEFINITION
COMMAND WREN (byte) (write Enable) Action sets (WEL) write enable latch WRDI (write disable) RDID (read identification) RDSR (read status register) WRSR READ (write status (read data) register) write bytes values read status register until goes high Fast Read Parallel (fast read Mode data) Enter stay Parallel Mode until power REMS (Read Electronic Manufacturer Device Output manufacturer device
reset (WEL) write enable latch
output read manufacturer status 2-byte register device
COMMAND (byte) (Sector (Chip Erase) Erase) Action
(Page (Deep Program) Power Down)
EN4K (Enter sector)
EX4K (Exit sector)
RES(Read (Release Electronic from Deep Power-down)
Enter additional sector
Exit additional sector
ADD=00H will output manufacturer's first ADD=01H will output device first. recommended adopt other code which above command definition table.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Table Memory Organization
Sector Address Range 7F0000h 7FFFFFh 7E0000h 7EFFFFh 7D0000h 7DFFFFh 7C0000h 7CFFFFh 7B0000h 7BFFFFh 7A0000h 7AFFFFh 790000h 79FFFFh 780000h 78FFFFh 770000h 760000h 750000h 740000h 730000h 720000h 710000h 700000h 6F0000h 6E0000h 6D0000h 6C0000h 6B0000h 6A0000h 690000h 680000h 670000h 660000h 650000h 640000h 630000h 620000h 610000h 600000h 5F0000h 5E0000h 5D0000h 5C0000h 5B0000h 5A0000h 590000h 580000h 77FFFFh 76FFFFh 75FFFFh 74FFFFh 73FFFFh 72FFFFh 71FFFFh 70FFFFh 6FFFFFh 6EFFFFh 6DFFFFh 6CFFFFh 6BFFFFh 6AFFFFh 69FFFFh 68FFFFh 67FFFFh 66FFFFh 65FFFFh 64FFFFh 63FFFFh 62FFFFh 61FFFFh 60FFFFh 5FFFFFh 5EFFFFh 5DFFFFh 5CFFFFh 5BFFFFh 5AFFFFh 59FFFFh 58FFFFh Sector Address Range 570000h 57FFFFh 560000h 56FFFFh 550000h 55FFFFh 540000h 54FFFFh 530000h 53FFFFh 520000h 52FFFFh 510000h 51FFFFh 500000h 50FFFFh 4F0000h 4FFFFFh 4E0000h 4EFFFFh 4D0000h 4DFFFFh 4C0000h 4CFFFFh 4B0000h 4BFFFFh 4A0000h 4AFFFFh 490000h 49FFFFh 480000h 48FFFFh 470000h 47FFFFh 460000h 46FFFFh 450000h 45FFFFh 440000h 44FFFFh 430000h 43FFFFh 420000h 42FFFFh 410000h 41FFFFh 400000h 40FFFFh 3F0000h 3FFFFFh 3E0000h 3EFFFFh 3D0000h 3DFFFFh 3C0000h 3CFFFFh 3B0000h 3BFFFFh 3A0000h 3AFFFFh 390000h 39FFFFh 380000h 38FFFFh 370000h 37FFFFh 360000h 36FFFFh 350000h 35FFFFh 340000h 34FFFFh 330000h 33FFFFh 320000h 32FFFFh 310000h 31FFFFh 300000h 30FFFFh
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Sector Address Range 2F0000h 2FFFFFh 2E0000h 2EFFFFh 2D0000h 2DFFFFh 2C0000h 2CFFFFh 2B0000h 2BFFFFh 2A0000h 2AFFFFh 290000h 29FFFFh 280000h 28FFFFh 270000h 27FFFFh 260000h 26FFFFh 250000h 25FFFFh 240000h 24FFFFh 230000h 23FFFFh 220000h 22FFFFh 210000h 21FFFFh 200000h 20FFFFh 1F0000h 1FFFFFh 1E0000h 1EFFFFh 1D0000h 1DFFFFh 1C0000h 1CFFFFh 1B0000h 1BFFFFh 1A0000h 1AFFFFh 190000h 19FFFFh 180000h 18FFFFh 170000h 17FFFFh 160000h 16FFFFh 150000h 15FFFFh 140000h 14FFFFh 130000h 13FFFFh 120000h 12FFFFh 110000h 11FFFFh 100000h 10FFFFh 0F0000h 0FFFFFh 0E0000h 0EFFFFh 0D0000h 0DFFFFh 0C0000h 0CFFFFh 0B0000h 0BFFFFh 0A0000h 0AFFFFh 090000h 09FFFFh 080000h 08FFFFh 070000h 07FFFFh Sector Address Range 060000h 06FFFFh 050000h 05FFFFh 040000h 04FFFFh 030000h 03FFFFh 020000h 02FFFFh 010000h 01FFFFh 000000h 00FFFFh
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
DEVICE OPERATION
Before command issued, status register should checked ensure device ready intended operation. When incorrect command inputted this LSI, this becomes standby mode keeps standby mode until next falling edge. standby mode, this should High-Z. When correct command inputted this LSI, this becomes active mode keeps active mode until next rising edge. Input data latched rising edge Serial Clock(SCLK) data shifts falling edge SCLK. difference mode mode shown Figure following instructions: RDID, RDSR, READ, FAST_READ, RES, REMS-the shifted-in instruction sequence followed data-out sequence. After data being shifted out, high. following instructions: WREN, WRDI, WRSR, Parallel Mode, EN4K, EX4K, must high exactly byte boundary; otherwise, instruction will rejected executed. During progress Write Status Register, Program, Erase operation, access memory array neglected affect current operation Write Status Register, Program, Erase.
Figure Modes Supported
CPOL CPHA SCLK shift shift
(SPI mode
(SPI mode
SCLK
Note: CPOL indicates clock polarity master, CPOL=1 SCLK high while idle, CPOL=0 SCLK while transmitting. CPHA indicates clock phase. combination CPOL CPHA decides which mode supported.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
COMMAND DESCRIPTION Write Enable (WREN)
Write Enable (WREN) instruction setting Write Enable Latch (WEL) bit. those instructions like WRSR, which intended change device content, should every time after WREN instruction setting bit. sequence issuing WREN instruction goes low-> sending WREN instruction code-> goes high. (see Figure
Write Disable (WRDI)
Write Disable (WRDI) instruction re-setting Write Enable Latch (WEL) bit. sequence issuing WRDI instruction goes low-> sending WRDI instruction code-> goes high. (see Figure reset following situations: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Chip Erase (CE) instruction completion
Read Identification (RDID)
RDID instruction reading manufacturer 1-byte followed Device 2-byte. MXIC Manufacturer C2(hex), memory type 20(hex) first-byte device individual device second-byte followings: 17(hex) MX25L6405. sequence issuing RDID instruction goes low-> sending RDID instruction code 24-bits data RDID operation high time during data out. (see Figure. While Program/Erase operation progress, will decode RDID instruction, there's effect cycle program/erase operation which currently progress. When goes high, device standby stage.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Read Status Register (RDSR)
RDSR instruction reading Status Register Bits. Read Status Register read time (even program/erase/write status register condition) continuously. recommended check Write Progress (WIP) before sending instruction when program, erase, write status register operation progress. sequence issuing RDSR instruction goes low-> sending RDSR instruction code-> Status Register data (see Figure. definition status register bits below: bit. Write Progress (WIP) bit, volatile bit, indicates whether device busy program/erase/write status register progress. When sets which means device busy program/erase/write status register progress. When sets which means device progress program/erase/write status register cycle. bit. Write Enable Latch (WEL) bit, volatile bit, indicates whether device internal write enable latch. When sets which means internal write enable latch set, device accept program/erase/write status register instruction. When sets which means internal write enable latch; device will accept program/erase/write status register instruction. BP3, BP2, BP1, bits. Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate protected area(as defined table device against program/erase instruction without hardware protection mode being set. write Block Protect (BP3, BP2, BP1, BP0) bits requires Write Status Register (WRSR) instruction executed. Those bits define protected area memory against Page Program (PP), Sector Erase (SE), Chip Erase(CE) instructions (only Block Protect bits instruction executed) Program/erase error bit. When program/erase there error occurred last program/erase operation. Flash accept program/erase command re-do program/erase operation. SRWD bit. Status Register Write Disable (SRWD) bit, non-volatile bit, operated together with Write Protection (WP#) providing hardware protection mode. hardware protection mode requires SRWD sets signal stage. hardware protection mode, Write Status Register (WRSR) instruction longer accepted execution SRWD Block Protect bits (BP3, BP2, BP1, BP0) read only. SRWD Status Register Write Protect status register write disable Program/ erase error 1=error level level level level protected protected protected protected block block block block (note (note (note (note (write enable latch) (write progress bit)
1=write enable 1=write operation 0=not write 0=not write enable operation
Note: table "Protected Area Sizes"
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Write Status Register (WRSR)
WRSR instruction changing values Status Register Bits. Before sending WRSR instruction, Write Enable (WREN) instruction must decoded executed Write Enable Latch (WEL) advance. WRSR instruction change value Block Protect (BP3, BP2, BP1, BP0) bits define protected area memory shown table WRSR also reset Status Register Write Disable (SRWD) accordance with Write Protection (WP#) signal. WRSR instruction cannot executed once Hardware Protected Mode (HPM) entered. sequence issuing WRSR instruction goes low-> sending WRSR instruction code-> Status Register data SI-> goes high. (see Figure WRSR instruction effect status register 64Mb device. must high exactly byte boundary; otherwise, instruction will rejected executed. selftimed Write Status Register cycle time (tW) initiated soon Chip Select (CS#) goes high. Write Progress (WIP) still check during Write Status Register cycle progress. sets during timing, sets when Write Status Register Cycle completed, Write Enable Latch (WEL) reset.
Table Protection Modes
Mode Software protection mode(SPM) Status register condition Status register written (WEL "1") SRWD, BP0-BP2 bits changed SRWD status WP#=1 SRWD bit=0, WP#=0 SRWD bit=0, WP#=1 SRWD=1 Memory protected area cannot program erase.
Hardware protection mode (HPM)
SRWD, BP0-BP2 status register bits cannot changed
WP#=0, SRWD bit=1
protected area cannot program erase.
Note: defined values Block Protect (BP3, BP2, BP1, BP0) bits Status Register, shown Table
above table showing, summary Software Protected Mode (SPM) Hardware Protected Mode (HPM). Software Protected Mode (SPM): When SRWD bit=0, matter high, WREN instruction change values SRWD, BP3, BP2, BP1, BP0. protected area, which defined BP3, BP2, BP1, BP0, software protected mode (SPM). When SRWD bit=1 high, WREN instruction change values SRWD, BP3, BP2, BP1, BP0. protected area, which defined BP3, BP2, BP1, BP0, software protected mode (SPM)
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Note: SRWD bit=1 low, impossible write Status Register even previously been set. rejected write Status Register executed. Hardware Protected Mode (HPM): When SRWD bit=1, then before SRWD bit=1), enters hardware protected mode (HPM). data protected area protected software protected mode BP3, BP2, BP1, hardware protected mode against data modification. Note: exit hardware protected mode requires driving high once hardware protected mode entered. permanently connected high, hardware protected mode never entered; only software protected mode BP3, BP2, BP1, BP0.
Read Data Bytes (READ)
read instruction reading data out. address latched rising edge SCLK, data shifts falling edge SCLK maximum frequency first address byte location. address automatically increased next higher address after each byte data shifted out, whole memory read single READ instruction. address counter rolls over when highest address been reached. sequence issuing READ instruction goes low-> sending READ instruction code-> 3-byte address data SO-> READ operation high time during data out. (see Figure.
Read Data Bytes Higher Speed (FAST_READ)
FAST_READ instruction quickly reading data out. address latched rising edge SCLK, data each shifts falling edge SCLK maximum frequency first address byte location. address automatically increased next higher address after each byte data shifted out, whole memory read single FAST_READ instruction. address counter rolls over when highest address been reached. sequence issuing FAST_READ instruction goes low-> sending FAST_READ instruction code-> 3-byte address SI-> 1-dummy byte address SI->data SO-> FAST_READ operation high time during data out. (see Figure. While Program/Erase/Write Status Register cycle progress, FAST_READ instruction rejected without impact Program/Erase/Write Status Register current cycle.
Parallel Mode (Highly recommended production throughputs increasing)
parallel mode provides inputs/outputs increasing throughputs factory production purpose. parallel mode requires command code, after writing parallel mode command then going high, after that, eLiteFlashMemory available accept read/program/read status/read ID/RES/REMS command normal writing command procedure. eLiteFlashMemory will parallel mode until power-off. Only effective Read Array normal read(not FAST_READ), Read Status, Read Page Program, REMS write data period. (refer Figure 29~34) normal write command SI), effect Under parallel mode, fastest access clock freq. will changed 1.5MHz(SCLK clock freq.) parallel mode, will change 50ns.
P/N: PM1107 REV.1.3, NOV. 2006
MX25L6405
Sector Erase (SE)
Sector Erase (SE) instruction erasing data chosen sector "1". Write Enable (WREN) instruction must execute Write Enable Latch (WEL) before sending Sector Erase (SE). address sector (see table valid address Sector Erase (SE) instruction. must high exactly byte boundary (the latest eighth address byte been latched-in); otherwise, instruction will rejected executed. sequence issuing instruction goes sending instruction code-> 3-byte address goes high. (see Figure self-timed Sector Erase Cycle time (tSE) initiated soon Chip Select (CS#) goes high. Write Progress (WIP) still check during Sector Erase cycle progress. sets during timing, sets when Sector Erase Cycle completed, Write Enable Latch (WEL) reset. page protected BP3, BP2, BP1, bits, Sector Erase (SE) instruction will executed page.
(10) Chip Erase (CE)
Chip Erase (CE) instruction erasing data whole chip "1". Write Enable (WREN) instruction must execute Write Enable Latch (WEL) before sending Chip Erase (CE). address sector (see table valid address Chip Erase (CE) instruction. must high exactly byte boundary( latest eighth address byte been latched-in); otherwise, instruction will rejected executed. sequence issuing instruction goes low-> sending instruction code-> goes high. (see Figure self-timed Chip Erase Cycle time (tCE) initiated soon Chip Select (CS#) goes high. Write Progress (WIP) still check during Chip Erase cycle progress. sets during timing, sets when Chip Erase Cycle completed, Write Enable Latch (WEL) reset. chip protected BP3, BP2, BP1, bits, Chip Erase (CE) instruction will executed. will only executed when BP3, BP2, BP1, "0".
(11) Page Program (PP)
Page Program (PP) instruction programming memory "0". Write Enable (WREN) instruction must execute Write Enable Latch (WEL) before sending Page Program (PP). eight least significant address bits (A7-A0) transmitted data which goes beyond current page programmed from start address same page (from address whose least significant address bits (A7-A0) must keep during whole Page Program cycle. must high exactly byte boundary( latest eighth address byte been latched-in); otherwise, instruction will rejected executed. more than bytes sent device, data last 256-byte programmed request page previous data will disregarded. less than bytes sent device, data programmed request address page without effect other address same page. sequence issuing instruction goes low-> sending instruction code-> 3-byte address SI-> least 1-byte data SI-> goes high. (see Figure self-timed Page Program Cycle time (tPP) initiated soon Chip Select (CS#) goes high. Write Progress (WIP) still check during Page Program cycle progress. sets during timing, sets when Page Program Cycle completed, Write Enable Latch (WEL) reset. page protected BP3, BP2, BP1, bits, Page Program (PP) instruction will executed.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
(12) Enter 4Kbit Mode (EN4K) Exit 4Kbit Mode (EX4K)
Enter Exit 4kbit mode (EN4K EX4K) (see Figure EN4K EX4K will executed when chip busy state. Enter 4kbit mode then read write command will executed this 4kbit. read write command sequence same normal array. address this bits A22~A9=0 (for 64Mb) A8~A0 customer defined. Note Chip erase WRSR will executed 4kbit mode. During Enter 4Kbit Mode, following instructions accepted: WREN, WRDI, RDID, RDSR, FAST_READ, READ, RDP, RES, REMS. Note Chip erase can't erase this 4kbit About fail status: Bit6 status register used state fail status, bit6=1 means program erase have been failed. write command will clear this bit.
(13) Deep Power-down (DP)
Deep Power-down (DP) instruction setting device minimizing power consumption entering Deep Power-down mode), standby current reduced from ISB1 ISB2). Deep Power-down mode requires Deep Power-down (DP) instruction enter, during Deep Power-down mode, device active Write/ Program/Erase instruction ignored. When goes high, it's only standby mode deep power-down mode. It's different from Standby mode. sequence issuing instruction goes low-> sending instruction code-> goes high. (see Figure Once instruction set, instruction will ignored except Release from Deep Power-down mode (RDP) Read Electronic Signature (RES) instruction. (RES instruction allow been read out). When Power-down, deep power-down mode automatically stops, when power-up, device automatically standby mode. instruction must high exactly byte boundary (the latest eighth instruction code been latched-in); otherwise, instruction will executed. soon Chip Select (CS#) goes high, delay required before entering Deep Power-down mode reducing current ISB2.
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
Release from Deep Power-down (RDP) instruction terminated driving Chip Select (CS#) High. When Chip Select (CS#) driven High, device Stand-by Power mode. device previously Deep Powerdown mode, transition Stand-by Power mode immediate. device previously Deep Power-down mode, though, transition Stand-by Power mode delayed tRES2, Chip Se-lect (CS#) must remain High least tRES2(max), specified Table Once Stand-by Power mode, device waits selected, that receive, decode execute instructions. instruction reading style 8-bit Electronic Signature, whose values shown table Definitions. This same RDID instruction. recommended design. deisng, please RDID instruction. Even Deep power-down mode, RDP, RES, REMS also allowed executed, only except device progress program/erase/write cycle; there's effect current program/erase/write cycle progress. sequence shown Figure 23,24,25. instruction ended goes high after been read least once. outputs repeatedly
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
continuously send additional clock cycles SCLK while low. device previously Deep Powerdown mode, device transition standby mode immediate. device previously Deep Power-down mode, there's delay tRES2 transit standby mode, must remain high least tRES2(max). Once standby mode, device waits selected, receive, decode, execute instruction. instruction releasing from Deep Power Down Mode.
(15) Read Electronic Manufacturer Device (REMS)
REMS instruction alternative Release from Power-down/Device instruction that provides both JEDEC assigned manufacturer specific device REMS instruction very similar Release from Power-down/Device instruction. instruction initiated driving shift instruction code "90h" followed dummy bytes bytes address (A7~A0). After which, Manufacturer MXIC (C2h) Device shifted falling edge SCLK with most significant (MSB) first shown figure Device values listed Table Definitions page one-byte address initially 01h, then device will read first then followed Manufacturer Manufacturer Device read continuously, alternating from other. instruction completed driving high.
Table Definitions: RDID: manufacturer MX25L6405 RES: device MX25L6405 REMS: manufacturer MX25L6405 device memory type memory density
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
POWER-ON STATE
device below states when power-up: Standby mode please note deep power-down mode) Write Enable Latch (WEL) reset device must selected during power-up power-down stage unless achieves below correct level: minimum power-up stage then after delay tVSL power-down Please note that pull-up resistor ensure safe proper power-up/down level. internal power-on reset (POR) circuit protect device from data corruption inadvertent data change during power state. When lower than (POR threshold voltage value), internal logic reset flash device response command. further protection device, after reaching level, tPUW time delay required before device fully accessible commands like write enable(WREN), page program (PP), sector erase(SE), chip erase(CE) write status register(WRSR). does reach minimum level, correct operation guaranteed. write, erase, program command should sent after below time delay: tPUW after reached level tVSL after reached minimum level device accept read command after reached minimum time delay tVSL, even time tPUW passed. Please refer figure "power-up timing". Note: stabilize level, rail decoupled suitable capacitor close package pins recommended.(generally around 0.1uF) power-down stage, drops below level, operations disable device response command. data corruption might occur during stage while write, program, erase cycle progress.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
RATING VALUE Industrial grade 70°C Commercial grade Storage Temperature Applied Input Voltage Applied Output Voltage Ground Potential -55°C 125°C -0.5V 4.6V -0.5V 4.6V -0.5V 4.6V Ambient Operating Temperature -40°C 85°C Notes Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operational sections this specification implied. Exposure absolute maximum rating conditions extended period affect reliability. Specifications contained within following tables subject change. During voltage transitions, pins overshoot 4.6V -0.5V period 20ns. input output pins overshoot VCC+0.5V while VCC+0.5V smaller than equal 4.6V.
Figure 4.Maximum Negative Overshoot Waveform
Figure Maximum Positive Overshoot Waveform
20ns
-0.5V
4.6V 3.6V
20ns
CAPACITANCE 25°C,
SYMBOL COUT PARAMETER Input Capacitance Output Capacitance MIN. MAX. UNIT CONDITIONS VOUT
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure INPUT TEST WAVEFORMS MEASUREMENT LEVEL
Input timing referance level 0.8VCC 0.7VCC 0.3VCC 0.2VCC Measurement Level Output timing referance level
0.5VCC
Note: Input pulse rise fall time <5ns
Figure OUTPUT LOADING
DEVICE UNDER TEST
2.7K +3.3V
6.2K
DIODES=IN3064 EQUIVALENT
CL=30pF Including capacitance
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Table CHARACTERISTICS (Temperature -40°C 85°C Industrial grade, Temperature 70°C Commercial grade, 2.7V 3.6V)
SYMBOL PARAMETER ISB1 ISB2 ICC1 Input Load Current Output Leakage Current Standby Current Deep Power-down Current Read ICC2 ICC3 Program Current (PP) Write Status Register (WRSR) Current ICC4 ICC5 Sector Erase Current (SE) Chip Erase Current (CE) Voltage Program Acceleration Input Voltage Input High Voltage Output Voltage Output High Voltage VCC-0.2 -0.5 0.7VCC 0.3VCC VCC+0.4 1.6mA -100uA 11.5 12.5 Erase Progress CS#=VCC Erase Progress CS#=VCC VCC=2.7V~3.6V NOTES MIN. MAX. UNITS TEST CONDITIONS f=50MHz (serial) f=1.5MHz (parallel) f=20MHz (serial) f=1.2MHz (parallel) Program Progress Program status register progress CS#=VCC
Notes Typical values 3.3V, 25°C. These currents valid product versions (package speeds). Typical value calculated simulation.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Table CHARACTERISTICS (Temperature -40°C 85°C Industrial grade, Temperature 70°C Commercial grade, 2.7V 3.6V)
Symbol fSCLK Parameter Clock Frequency following instructions: Serial FAST_READ, RES,REMS, WREN, WRDI, RDID, RDSR, WRSR, EN4K, EX4K Parallel Clock Frequency READ instructions Serial Parallel tCLH Clock High Time Serial Parallel tCLL Clock Time Serial Parallel Clock Rise Time (peak peak) Serial Parallel Clock Fall Time (peak peak) Serial Parallel tCSS Active Setup Time (relative Active Hold Time (relative tDSU Data Setup Time Data Hold Time Active Hold Time (relative Active Setup Time (relative tCSH Deselect Time tDIS Output Disable Time Clock Output Valid Output Hold Time HOLD# Setup Time (relative HOLD# Hold Time (relative HOLD Setup Time (relative HOLD Hold Time (relative HOLD Output Low-Z HOLD# Output High-Z Write Protect Setup Time Write Protect Hold Time High Deep Power-down Mode High Standby Mode without Electronic Signature Read High Standby Mode with Electronic Signature Read Write Status SRWD, BP3, BP2, BP1, Register Cycle Time WIP, Page Program Cycle Time Sector Erase Cycle Time Chip Erase Cycle Time Alt. Min. D.C. Typ. Max. Unit V/ns V/ns V/ns V/ns
fRSCLK tCH(1) tCL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL(4) tDP(2) tRES1(2) tRES2(2)
D.C.
Notes must greater than equal Value guaranteed characterization, 100% tested production. Expressed slew-rate. Only applicable constraint WRSR instruction when SRWD Test condition shown Figure
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Table Power-Up Timing Threshold
Symbol tVSL(1) tPUW(1) VWI(1) Parameter VCC(min) Time delay Write instruction Write Inhibit Voltage Min. Max. Unit
Note: These parameters characterized only.
INITIAL DELIVERY STATE
device delivered with memory array erased: bits (each byte contains FFh). Status Register contains (all Status Register bits
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Serial Input Timing
tSHSL tCHSL SCLK tDVCH tCHDX tCLCH tCHCL tSLCH tCHSH tSHCH
High-Z
Figure Output Timing
SCLK tCLQV tCLQX tQLQH tQHQL
ADDR.LSB
tCLQV tCLQX
tSHQZ
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Hold Timing
tHLCH tCHHL SCLK tCHHH tHLQZ tHHQX tHHCH
HOLD#
"don't care" during HOLD operation.
Figure Disable Setup Hold Timing during WRSR when SRWD=1
tWHSL tSHWL
SCLK
High-Z
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Write Enable (WREN) Sequence (Command
SCLK Command
High-Z
Figure Write Disable (WRDI) Sequence (Command
SCLK Command
High-Z
Figure Read Identification (RDID) Sequence (Command
SCLK Command Manufacturer Identification High-Z
Device Identification
Notes: serial RDID RDSR mode, output will enabled clock's rising edge. That means, MXIC's drip will enable output half cycle advance compare with other compatible vendor's spec.
P/N: PM1107 REV.1.3, NOV. 2006
MX25L6405
Figure Read Status Register (RDSR) Sequence (Command
SCLK command Status Register High-Z
Status Register
Notes: serial RDID RDSR mode, output will enabled clock's rising edge. That means, MXIC's drip will enable output half cycle advance compare with other compatible vendor's spec.
Figure Write Status Register (WRSR) Sequence (Command
SCLK command Status Register
High-Z
Figure Read Data Bytes (READ) Sequence (Command
SCLK command 24-Bit Address
High-Z
Data
Data
Notes: READ mode, FAST_READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec. Detail condition please reference waveform.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Read Data Bytes Higher Speed (FAST_READ) Sequence (Command
SCLK Command ADDRESS
High-Z
SCLK Dummy Byte
DATA DATA
Notes: READ mode, FAST_READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec. Detail condition please reference waveform.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Page Program (PP) Instruction Sequence
SCLK Command 24-Bit Address Data Byte
2072
2073
2074
2075
2076
2077
2078
SCLK Data Byte Data Byte
Data Byte
Figure Sector Erase (SE) Instruction Sequence
SCLK Command Address
Note: command 20(hex) D8(hex).
P/N: PM1107
2079
REV.1.3, NOV. 2006
MX25L6405
Figure Chip Erase (CE) Sequence (Command
SCLK Command
Note: command 60(hex) C7(hex).
Figure Deep Power-down (DP) Sequence (Command
SCLK Command
Stand-by Mode
Deep Power-down Mode
Figure Release from Deep Power-down Read Electronic Signature (RES) (Command
Sequence
SCLK Command tRES2
Dummy Bytes
High-Z
Electronic Signature
Deep Power-down Mode
Stand-by Mode
Notes: READ mode, FAST_READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec. Detail condition please reference waveform.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Release from Deep Power-down (RDP) Sequence (Command
SCLK Command tRES1
High-Z
Deep Power-down Mode
Stand-by Mode
Figure Read Electronic Manufacturer Device (REMS) Sequence (Command
SCLK Command Dummy Bytes
High-Z
SCLK
Manufacturer Device
Notes: ADD=00H will output manufacturer's first ADD=01H will output device first READ mode, FAST_READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec. Detail condition please reference waveform.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Power-up Timing
VCC(max) Program, Erase Write Commands Ignored Chip Selection Allowed VCC(min) Reset State Flash tPUW tVSL Read Command allowed Device fully accessible
time
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Enter 4Kbit Mode (EN4K) Sequence (Command
SCLK Command High-Z
Figure Exit 4Kbit Mode (EX4K) Sequence (Command
SCLK Command High-Z
Note: Enter Exit 4kbit mode (EN4K EX4K) EN4K EX4K will executed when chip busy state. Enter 4kbit mode then read write command will executed this 4kbit. read write command sequence same normal array. address this bits A22~A9=0 (for 64Mb), A8~A0 customer defined. Note Chip erase WRSR will executed 4kbit mode Note Chip erase can't erase this 4kbit About fail status: Bit6 status register used state fail status, bit6=1 means program erase have been failed. write command will clear this bit.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure READ ARRAY SEQUENCE (Parallel)
SCLK PO7,PO6, .PO0 SCLK PO7,PO6, .PO0 SCLK PO7,PO6, .PO0
Byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Hi-Z byte (03h) byte (AD1)
Bit1
Bit0
Byte
Byte
byte (AD3)
Hi-Z
Notes Byte='03h' Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,.AD16=BIT0. Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,.AD8=BIT0. Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, .AD0=BIT0. From Byte Would Output Array Data. Under parallel mode, fastest access clock freq. will changed 1.2MHz(SCLK clock freq.). read array parallel mode requires parallel mode command (55H) before read command. Once parallel mode, eLiteFlashMemory will exit parallel mode until power-off. READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel)
SCLK PO7,PO6, .PO0 SCLK PO7,PO6, .PO0 SCLK PO7,PO6, .PO0
Byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Hi-Z byte (02h) byte (AD1)
Bit1
Bit0
Byte
Byte
byte (BA)
Hi-Z
Notes Byte='02h' Byte=Address 1(AD1), AD23=BIT7, AD22=BIT6, AD21=BIT5, AD20=BIT4,.AD16=BIT0. Byte=Address 2(AD2), AD15=BIT7, AD14=BIT6, AD13=BIT5, AD12=BIT4,.AD8=BIT0. Byte=Address 3(AD3), AD7=BIT7, AD6=BIT6, .AD0=BIT0. byte: write data byte. Under parallel mode, fastest access clock freq. will changed 1.2MHz(SCLK clock freq.). program parallel mode requires parallel mode command (55H) before program command. Once parallel mode, eLiteFlashMemory will exit parallel mode until power-off.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Read Identification (RDID) Sequence (Parallel)
SCLK Command Manufacturer Identification PO7~0 High-Z
High-Z Byte output Device Identification
Notes Under parallel mode, fastest access clock freg. will changed 1.2MHz(SCLK clock freg.) read identification parallel mode, which requires parallel mode command (55H) before read identification command. Once parallel mode, eLiteFlashMemory will exit parallel mode until power-off. Only bytes would output manufacturer Device It's same serial RDID mode. serial RDID RDSR mode, output will enabled clock's rising edge. That means, MXIC's drip will enable output half cycle advance compare with other compatible vendor's spec.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Release from Deep Power-down Read Electronic Signature (RES) Sequence (Parallel)
SCLK Command Dummy Bytes tRES2
Electronic Signature
High-Z PO7~0
Byte Output Deep Power-down Mode Stand-by Mode
Notes Under parallel mode, fastest access clock freg. will changed 1.2MHz(SCLK clock freg.) release from deep power-down mode read parallel mode, which requires parallel mode command (55H) before read status register command. Once parallel mode, eLiteFlashMemory will exit parallel mode until power-off. READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure READ STATUS REGISTER TIMING SEQUENCE (Parallel)
SCLK PO7,PO6, .PO0 SCLK PO7,PO6, .PO0
Byte
Bit7
Bit6
Bit0
Hi-Z
Byte Byte
byte (05h)
Hi-Z
Notes Byte='05h' BIT7 status register write disable signal. BIT7=1, means write disable. BIT6=0 Program/erase correct. BIT5, defines level protected block. BIT1 write enable latch BIT0=0 Device ready state Under parallel mode, fastest access clock freq. will changed 1.2MHz(SCLK clock freq.). read status register parallel mode requires parallel mode command (55H) before read status register command. Once parallel mode, eLiteFlashMemory will exit parallel mode until power-off. serial RDID RDSR mode, output will enabled clock's rising edge. That means, MXIC's drip will enable output half cycle advance compare with other compatible vendor's spec.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
Figure Read Electronic Manufacturer Device (REMS) Sequence (Parallel)
SCLK Command Dummy Bytes
High-Z
PO7~0
SCLK
Manufacturer
PO7~0
Device
Notes ADD=00H will output manufacturer's first ADD=01H will output device first Under parallel mode, fastest access clock freg. will changed 1.2MHz(SCLK clock freg.) read parallel mode, which requires parallel mode command (55H) before read command. Once parallel mode, eLiteFlashMemory will exit parallel mode until power-off. READ mode, mode REMS mode, MXIC will enable output entire cycle advance compare with other compatible vendor's spec.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
RECOMMENDED OPERATING CONDITIONS
Device Power-Up timing illustrated Figure recommended supply voltages control signals device power-up. timing figure ignored, device operate correctly.
VCC(min)
tSHSL
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHDX tCLCH tCHCL
High Impedance
Figure Timing Device Power-Up
Symbol
Parameter Rise Time
Notes
Min.
Max. 500000
Unit us/V
Notes Sampled, 100% tested. spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH figure, please refer CHARACTERISTICS" table.
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
ERASE PROGRAMMING PERFORMANCE
PARAMETER Chip Erase Time Chip Erase Time (with ACC=12V) Sector erase Time Sector erase Time (with ACC=12V) Additional Erase Time Page Programming Time Page Programming Time (with ACC=12V) Erase/Program Cycle Main Array Additional 100K cycles cycles Note Excludes system level overhead(3) Note Note Min. TYP. Max. UNIT Comments Note Note
Notes Typical program erase time assumes following conditions: 25°C, 3.0V, bits programmed checkerboard pattern. Under worst conditions 70°C 3.0V. Maximum values including program/erase cycles. System-level overhead time required execute command sequences page program command. Excludes programming prior erasure. pre-programming step embedded erase algorithm, bits programmed before erasure)
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect Input Voltage with respect power pins, Input Voltage with respect Current Includes pins except VCC. Test conditions: 3.0V, time. -1.0V -1.0V -1.0V -100mA MAX. 12.5V VCCmax 1.0V +100mA
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
ORDERING INFORMATION
PART MX25L6405MC-20 MX25L6405MC-20G MX25L6405MI-20 MX25L6405MI-20G ACCESS TIME(ns) OPERATING CURRENT(mA) STANDBY CURRENT(uA) 0~70°C 0~70°C -40~85°C -40~85°C 16-SOP 16-SOP 16-SOP 16-SOP Pb-free Pb-free Temperature PACKAGE Remark
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
PART NAME DESCRIPTION
6405
OPTION: Pb-free blank: normal SPEED: 50MHz, TEMPERATURE RANGE: Commercial (0°C 70°C) Industrial (-40°C 85°C)
PACKAGE: 300mil 16-SOP
DENSITY MODE: 6405: 64Mb
TYPE:
DEVICE: Serial Flash
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
PACKAGE INFORMATION
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
REVISION HISTORY
Revision Description Removed "Preliminary" title Added "Recommended Operating Conditions" Added "additional erase time" "cycle time" Added "Part Name Description" separated from MX25L1605, MX25L3205, MX25L6405 MX25L6405 Improved chip erase time: without ACC=12V with ACC=12V Added description about Pb-free device RoHS compliant Format change Added statement Page P1,22,41 Date JUL/15/2005
AUG/03/2005
JUN/08/2006 NOV/06/2006
P/N: PM1107
REV.1.3, NOV. 2006
MX25L6405
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