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Data Sheet April 2007 FN3365.9 Halfband Filter HSP43216 Half


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HSP43216
Data Sheet April 2007 FN3365.9
Halfband Filter
HSP43216 Halfband Filter addresses wide variety applications combining fS/4 sample frequency) quadrature up/down convert circuitry with fixed coefficient halfband filter processor shown block diagram. These elements configured operate four following modes: decimate filtering real input signal; interpolate filtering real input signal; fS/4 quadrature down conversion real input signal followed decimate-by-2 filtering produce complex analytic signal; interpolate-by-2 filtering complex analytic signal followed fS/4 quadrature conversion produce real valued output. frequency response HSP43216's halfband filter shape factor, (passband+transition band)/passband, 1.24:1 with 90dB stopband attenuation. passband less than 0.0003dB ripple from 0.2fS with stopband attenuation greater than 90dB from 0.3fS Nyquist. 0.25fS filter provides attenuation. HSP43216 processes data streams with word widths 16-bits data rates 52MSPS. processing throughput part easily doubled rates 104MSPS using part together with external multiplexer demultiplexer. Programmable rounding provided support output precisions from 8-bits 16-bits.
Features
Sample Rates 52MSPS Architected Support Sample Rates 104MSPS Using External Multiplexer Four Modes Operation: Interpolate Filtering Decimate Filtering Quadrature Real Signal Conversion fS/4 Quadrature Down Conversion Followed Decimate Filtering 16-Bit Inputs Outputs 67-Tap Halfband Filter with 20-Bit Coefficients Two's Complement Offset Binary Outputs Programmable Rounding Outputs 1.24:1 Filter Shape Factor >90dB Stopband Attenuation <0.0003dB Passband Ripple Saturation Logic Output
Applications
Digital Down Conversion pre/post Filtering Tuning Bandwidth Expansion HSP45116 HSP45106
Ordering Information
PART NUMBER HSP43216JC-52 HSP43216VC-52 HSP43216VC-52Z (Note) PART MARKING 43216JC-52 43216VC-52 43216VC-52Z TEMP. RANGE (°C) PACKAGE PLCC MQFP MQFP (Pb-free) PKG. DWG. N84.1.15 Q100.14x20 Q100.14x20
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2007. Rights Reserved other trademarks mentioned property their respective owners.
HSP43216 Block Diagram
AIN0-15 INPUT DATA FLOW BIN0-15 CONTROLLER fS/4 QUADRATURE DOWN CONVERT PROCESSOR 67-TAP HALFBAND FILTER PROCESSOR fS/4 QUADRATURE CONVERT PROCESSOR OUTPUT DATA FLOW CONTROLLER/ FORMATTER BOUT0-15 AOUT0-15
SYNC USB/LSB MODE0-1 INT/EXT RND0-2
Pinouts
HSP43216JC (100 MQFP) VIEW
MODE1 MODE0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 RND2 BOUT0 BOUT1 BOUT2 BOUT3 BOUT4 BOUT5 BOUT6 BOUT7 BOUT8 BOUT9 BOUT10 BOUT11 BOUT12 BOUT13 BOUT14 AOUT15 AOUT14 AOUT13 AOUT12 AOUT11 AOUT10 AOUT9 AOUT8 AOUT7 AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AOUT0 BOUT15
FN3365.9 April 2007
HSP43216 Pinouts (Continued)
HSP43216 PLCC) VIEW
MODE1 MODE0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1
AOUT15 AOUT14 AOUT13 AOUT12 AOUT11 AOUT10 AOUT9 AOUT8 AOUT7 AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AOUT0
Description
NAME AIN0-15 BIN0-15 MODE0-1 INT/EXT SYNC TYPE Power. Ground. Clock Input. (CMOS LEVEL). frequency Input Data AIN0 LSB. Input data format 16-bit Two's Complement. Input Data BIN0 LSB. Input data format 16-bit Two's Complement. Mode Select Inputs four operational modes highlighted Table Internal\External multiplexer select inputs whether data multiplex/demultiplex function required various operational modes performed internally (High State) externally chip (Low State). This input used synchronize input sample stream with zero degree phase down convert Local Oscillators. straight decimate modes, this input synchronize input sample stream with particular phase halfband filter. (See Operational Modes Section additional information). Upper Lower Sideband select line used specify direction frequency translation imparted data stream Down Convert Decimate Mode Quadrature Real Convert Mode. (See Operational Modes Section additional information). Round Select inputs number output bits from eight (RND 000) sixteen (RND 110). Least significant output bits zeroed. Table Three-State Control Output OUTA0-15. Active Low. Three-State Control Output OUTB0-15. Active Low. Format select input used convert two's complement output offset binary (unsigned). When asserted high, AOUT15 BOUT15-bits inverted from normal two's complement representation. Output AOUT0 LSB. Output BOUT0 LSB. DESCRIPTION
USB/LSB
RND0-2 AOUT0-15 BOUT0-15
RND2 BOUT0 BOUT1 BOUT2 BOUT3 BOUT4 BOUT5 BOUT6 BOUT7 BOUT8 BOUT9 BOUT10 BOUT11 BOUT12 BOUT13 BOUT14 BOUT15
FN3365.9 April 2007
HSP43216
QUADRATURE DOWN CONVERT PROCESSOR 67-TAP HALFBAND FILTER PROCESSOR QUADRATURE CONVERT PROCESSOR
INPUT DATA FLOW CONTROLLER
OUTPUT DATA FLOW CONTROLLER
AIN0-15
DELAY
EVEN FILTER SYNC USB/LSB
PIPELINE
AOUT0-15
1,-1,1,. -1,1,-1,.
.,2,-2,2 .,-2,2,-2
fS/4 L.O.
BIN0-15
DELAY
FILTER
PIPELINE
BOUT0-15
MODE0-1 SYNC INT/EXT RND0-2 USB/LSB
Indicates elements which operate CLK/2 when INT/EXT control input high.
FIGURE HALFBAND BLOCK DIAGRAM
Functional Description
operation HSP43216 centers around fixed coefficient, 67-Tap, Halfband Filter Processor shown Figure Halfband Filter Processor operates stand alone provide fundamental modes operation: interpolate decimate filtering real signal. other modes, Quadrature Up/Down Convert circuitry operates together with Filter Processor block provide fS/4 Down Conversion with decimate filtering Quadrature Real Conversion. Down Convert Decimate mode, real input sample stream spectrally shifted fS/4. Each component resulting complex signal then halfband filtered decimated produce real imaginary output samples half input data rate. Quadrature Real Conversion mode, real imaginary components quadrature input interpolated halfband filtered. filtered result then spectrally shifted fS/4 real component this operation output twice input sample rate.The HSP43216 configured different operational modes setting state mode control pins, MODE1-0 shown Table
TABLE MODE SELECT TABLE MODE1-0 Decimate Interpolate Down Convert Decimate Quadrature Real Conversion MODE
Input Data Flow Controller
Input Data Flow Controller routes data samples from AIN0-15 BIN0-15 inputs internal processing elements Halfband. data routing paths based mode operation more fully discussed Operational Modes section.
Quadrature Down Convert Processor
Quadrature Down Convert Processor operates Quadrature which provides negative spectral shift required center upper sideband real input signal This operation equivalent multiplying real sample stream, x(n), quadrature components complex exponential e-j(/2)n given below:
(EQ.
FN3365.9 April 2007
HSP43216
added flexibility, spectrally reversed version above process realized configuring Down Convert processor impart positive spectral shift input signal. This effect centering lower sideband input signal achieved reversing sign sine term quadrature shown below:
(EQ.
direction spectral shift imparted Down Convert Processor Upper Sideband/ Lower Sideband control input, USB/LSB. When this input high, spectral shift used center input signal's upper sideband When asserted low, spectral shift used center lower sideband SYNC control input used synchronize incoming data stream with zero degree phase complex exponential described Operational Modes section. real imaginary sample streams generated down convert operation passed Halfband Filter block upper lower processing legs respectively. Down Convert Processor only active Down Convert Decimate Mode, MODE1-0 other modes, data upper lower processing legs pass unaltered.
polyphase implementation halfband filter provides flexibility realize variety filter configurations. Decimate Mode, outputs each polyphase branch summed yield filter output. Interpolate mode, polyphase filters produce independent outputs which multiplexed into single sample stream interpolated data rate. Convert Down Convert Modes, polyphase branches filter real imaginary components complex sample stream with equivalent identical 67Tap Halfband Filters. these modes, real component processed Even filter imaginary component processed filter. Operational Modes Section provides further details regarding data flow operation Filter Processor various modes.
MAGNITUDE (DB)
67-Tap Halfband Filter Processor
processing required implement 67-Tap Halfband filter distributed across polyphase branches comprised even filters shown Figure Even Filter performs filtering operation using even indexed coefficients (even phase) halfband filter. Filter uses indexed coefficients (odd phase) halfband filter. NOTE: filter's processing reduces delay scale operation since center only non-zero halfband filter. Together polyphase filters perform of-products required implement 67-tap halfband filter architecture capable supporting variety operational modes. frequency response halfband filter given graphically Figure tabular form Table Table shows different modes related frequency with which spectra Figure normalized.
TABLE NORMALIZED FREQUENCY MODE MODE Decimate Interpolate Down Convert Decimate Quadrature Real CLK/2 CLK/2
-100
-120 fS/8 fS/4 3fS/8 FS/2 NORMALIZED FREQUENCY
FIGURE FREQUENCY RESPONSE 67-TAP HALFBAND FILTER
standard term, group delay defined time takes obtain valid filtered data given certain input pattern. Both Even filters have identical group delay clocks relative operating mode halfband. group delay been specified data flow diagrams following this section. delay clocks equal when INT/EXT CLK/2 when INT/EXT
NOTE: Pipeline delay specifies time takes bits toggle output given certain input pattern. filter pipeline delay CLKs with respect operating mode because consists only center 67-tap halfband. Even filter pipeline delay 2-35 CLKs with respect operating mode.
FN3365.9 April 2007
TABLE FREQUENCY RESPONSE 67-TAP HALFBAND FILTER NORMALIZED MODE SPECIFIC SAMPLE RATE FREQUENCY (NORMALIZED) 0.000000 0.003906 0.007812 0.011719 0.015625 0.019531 0.023438 0.027344 0.031250 0.035156 0.039062 0.042969 0.046875 0.050781 0.054688 0.058594 0.062500 0.066406 0.070312 0.074219 0.078125 0.082031 0.085938 0.089844 0.093750 0.097656 0.101562 0.105469 0.109375 0.113281 MAGNITUDE (dB) -0.000256 -0.000143 -0.000071 -0.000013 -0.000004 -0.000001 0.000032 -0.000000 -0.000026 0.000002 0.000036 0.000050 0.000021 0.000008 -0.000012 -0.000140 -0.000226 -0.000138 0.000010 0.000036 0.000179 0.000190 0.000064 0.000011 -0.000064 -0.000018 -0.000000 0.000020 0.000053 0.000012 FREQUENCY (NORMALIZED) 0.125000 0.128906 0.132812 0.136719 0.140625 0.144531 0.148438 0.152344 0.156250 0.160156 0.164062 0.167969 0.171875 0.175781 0.179688 0.183594 0.187500 0.191406 0.195312 0.199219 0.203125 0.207031 0.210938 0.214844 0.218750 0.222656 0.226562 0.230469 0.234375 0.238281 MAGNITUDE (dB) -0.000278 -0.000098 0.000001 0.000077 0.000166 0.000106 0.000015 -0.000022 -0.000048 -0.000074 -0.000022 0.000005 0.000009 0.000041 0.000095 0.000090 -0.000012 -0.000037 -0.000145 -0.000208 -0.000927 -0.005089 -0.018871 -0.053894 -0.128250 -0.266964 -0.501238 -0.866791 -1.401949 -2.145948 FREQUENCY (NORMALIZED) 0.250000 0.253906 0.257812 0.261719 0.265625 0.269531 0.273438 0.277344 0.281250 0.285156 0.289062 0.292969 0.296875 0.300781 0.304688 0.308594 0.312500 0.316406 0.320312 0.324219 0.328125 0.332031 0.335938 0.339844 0.343750 0.347656 0.351562 0.355469 0.359375 0.363281 MAGNITUDE (dB) -6.020594 -7.989334 -10.364986 -13.194719 -16.533196 -20.447622 -25.024382 -30.379687 -36.679477 -44.169450 -53.259353 -64.619008 -79.291213 -90.247748 -91.540418 -96.987389 -97.990997 -94.450644 -94.268681 -97.250387 -103.660592 -105.940671 -98.212931 -94.313447 -95.354251 -98.447393 -103.249457 -93.387604 -91.390894 -94.404415 FREQUENCY (NORMALIZED) 0.375000 0.378906 0.382812 0.386719 0.390625 0.394531 0.398438 0.402344 0.406250 0.410156 0.414062 0.417969 0.421875 0.425781 0.429688 0.433594 0.437500 0.441406 0.445312 0.449219 0.453125 0.457031 0.460938 0.464844 0.468750 0.472656 0.476562 0.480469 0.484375 0.488281 MAGNITUDE (dB) -90.469534 -91.528735 -98.960202 -105.235066 -97.073218 -101.790858 -103.660592 -96.903272 -97.160860 -106.804655 -96.213761 -91.368358 -91.202963
FN3365.9 April 2007
HSP43216
-96.903271 -103.058722 -92.156508 -90.247741 -91.623161 -98.760392 -103.883238 -96.861830 -96.987388 -100.046559 -106.804655 -104.119091 -105.235066 -104.637666 -105.940673 -107.323099 -102.375213
0.117188 0.121094
-0.000022 -0.000149
0.242188 0.246094
-3.137997 -4.416657
0.367188 0.371094
-103.883234 -93.245384
0.492188 0.496094
-94.009640 -91.312516
HSP43216 Quadrature Convert Processor
fS/4 Quadrature Convert Processor provides fS/4 spectral shift used construct real signal from complex sample stream. operation performed equivalent multiplying quadrature data stream, i(n)+jq(n), samples complex exponential, e-j(/2)n, outputting real part that mathematical operation given below: Real jq(n) (n/2) Real (n/2) q(n) (n/2)] (n/2) q(n) (n/2)]} (n/2) q(n) (n/2) (n/2) q(n) (-n/2)
(EQ.
Convert with particular input sample described Operational Modes Section. Convert Processor also scales data streams output from Filter Processor required operational mode. modes which employ interpolation, Convert Processor scales Filter Processor's output compensate attenuation half caused interpolation process. down convert decimate mode, filter processor output also scaled compensate attenuation introduced down covert process. scaling operations performed summarized Table
TABLE SCALE FACTORS APPLIED CONVERT PROCESSOR MODE MODE Decimate (MODE1-0 Interpolate (MODE1-0 Down Convert Decimate (MODE1-0 Quadrature Real (MODE1-0 SCALE FACTOR
above operation, positive fS/4 spectral shift imparted quadrature input which causes upper sideband resulting real output defined spectral content input signal shown Figure added flexibility, Convert processor configured impart negative fS/4 shift quadrature input which generates real output whose lower sideband defined spectrum quadrature input shown Figure state USB/LSB control input determines direction spectral shift. this input "High", positive fS/4 shift introduced Convert Processor. USB/LSB asserted "Low", negative fS/4 spectral shift introduced.
Output Data Flow Controller
Output Flow Controller routes data AOUT0-15 BOUT0-15 output depending mode operation. decimate mode (MODE1-0 00), output from filter processor's polyphase branches summed output through AOUT0-15. Down Convert Decimate mode (MODE1-0 10), real imaginary data streams produced down convert process pass output directly AOUT0-15 BOUT0-15 respectively. modes using interpolation, MODE1-0 with internal multiplexing enabled, INT/EXT high, data ples output from polyphase branches internally multiplexed into single stream output AOUT0-15. mode using interpolation specified together with external multiplexing, INT/EXT low, data stream multiplexing performed chip data upper lower processing legs output through AOUT0-15 BOUT0-15. Output Data Flow Controller also sets binary format precision 16-bit outputs. data format specified either two's complement (FMT input low) offset binary (FMT input high). precision output data from 8-bits 16-bits round control inputs, RND2-0. RND2-0 inputs round output data precision ranging from 8-bits 16-bits specified Table Saturation logic incorporated output flow controller insure that numerical growth associated with worst case signal input rounding condition saturates 16-bit value.
-fS/2
-fS/4
fS/4
fS/2
-fS/2
-fS/4
fS/4
fS/2
FIGURE fS/4 POSITIVE SHIFT: CONVERSION
-fS/2
-fS/4
fS/4
fS/2
-fS/2
-fS/4
fS/4
fS/2
FIGURE fS/4 NEGATIVE SHIFT: DOWN CONVERSION
Convert Processor implements convert operation multiplying in-phase quadrature samples upper lower processing legs nonzero sine cosine terms above expression. resulting data then multiplexed together Output Flow Controller yield real output sample stream. SYNC control input used align zero degree phase
FN3365.9 April 2007
HSP43216
TABLE OUTPUT ROUNDING CONTROL ROUND FUNCTION Round output 8-bits, AOUT15-8 BOUT15-8, zero lower bits. Round output 9-bits, AOUT15-7 BOUT15-7, zero lower bits. Round output 10-bits, AOUT15-6 BOUT15-6, zero lower bits. Round output 11-bits, AOUT15-5 BOUT15-5, zero lower bits. Round output 12-bits, AOUT15-4 BOUT15-4, zero lower bits. Round output 14-bits, AOUT15-2 BOUT15-2, zero lower bits. Round output 16-bits, AOUT15-0 BOUT15-0. Zero outputs.
polyphase implementation, input data broken into even sample streams which processed polyphase filters running half input data rate. These filters designated even filters depending upon whether coefficients were derived from even indexed coefficients original transversal filter. This architecture only produces outputs which discarded decimation process. NOTE: Since only non-zero halfband filter center tap, Filter reduces delay multiply operation. operation HSP43216 Decimate mode analogous polyphase implementation Figure this mode, internal data paths routed shown Figure Figure different data flows depend whether internal external multiplexing been selected using INT/EXT control input. either case, input data stream decomposed into even sample streams which then routed even polyphase filters. output each polyphase filter summed output AOUT0-15.
EVEN FILTER .,X4,X2,X0 FILTER .,X5,X3,X1
Operational Modes
Decimate Filter Mode (Mode1-0
concept operation Decimate Filter mode most easily understood comparing transversal filter implementation equivalent polyphase implementation. transversal implementation shown Figure
.,Y2,Y1,Y0
X3,X2,X1,X0
.,Y1,Y0
.,Y4,Y2,Y0
Y(0) Y(1)
Y(0)
Y(1)
Y(2)
Y(3)
FIGURE POLYPHASE IMPLEMENTATION DECIMATE HALFBAND FILTER
Indicates samples discarded decimation process
FIGURE TRANSVERSAL IMPLEMENTATION DECIMATE HALFBAND FILTER
inspecting sum-of-products decimated output Figure seen that even indexed input samples always multiplied even filter coefficients samples always multiplied coefficients. This computational partitioning realized polyphase implementation shown Figure
FN3365.9 April 2007
HSP43216
PIPELINE DELAY 2-35 GROUP DELAY
EVEN FILTER
AIN0-15
AOUT0-15
PIPELINE DELAY GROUP DELAY
FILTER
Clocked CLK/2
FIGURE DATA FLOW DIAGRAM DECIMATE FILTER MODE (INT/EXT
PIPELINE DELAY 2-35 GROUP DELAY AIN0-15 BIN0-15 PIPELINE DELAY GROUP DELAY FILTER EVEN FILTER AOUT0-15
FIGURE DATA FLOW DIAGRAM DECIMATE FILTER MODE (INT/EXT
internal multiplexing selected (INT/EXT input data stream decomposed into even samples internally processing elements operating half input (see elements marked Figure 7A). this mode, Data Flow Controller routes data samples input through AIN015 upper lower processing legs with sample relative delay. Since data sample clocked into either processing legs CLK/2, each processes data stream comprised every other input sample, sample relative delay each leg's input forces even samples clocked into while samples clocked into other. user choose which sample gets routed upper (even) processing asserting SYNC. Specifically, sample input following assertion SYNC will routed upper processing shown Figure With internal multiplexing, minimum pipeline delay upper processing CLK's pipeline delay bottom CLK's. filtered decimated data stream held AOUT0-15 CLK's. external multiplexing selected (INT/EXT demultiplex function required chip break input data into even sample streams input through AIN0-15 BIN0-15. this mode, Data Flow Controller routes even sample streams directly following processing elements which running input rate. This allows device perform decimate filtering signals sampled twice maximum rate device (104 MSPS). With external multiplexing, minimum pipeline delay through upper processing CLK's pipeline delay through lower processing CLK's shown Figure
this mode, SYNC effect part operation. NOTE: proper operation, samples demultiplexed AIN0-15 input must precede those input BIN0-15 input sample order. example, given data sequence demultiplex function would route AIN0-15 BIN0-15.
SYNC
AIN0-15
EVEN
EVEN
INPUTS DESIGNATED EVEN PROCESSED UPPER LEG, INPUTS DESIGNATED PROCESSED LOWER LEG.
FIGURE DATA SYNCHRONIZATION WITH PROCESSING LEGS (INT/EXT
Interpolate Filter Mode (Mode1-0
with Decimate mode concept operation Interpolate Filter mode more easily understood comparing transversal filter implementation equivalent polyphase implementation. transversal implementation shown Figure inspecting filter outputs Figure seen that even indexed outputs result sum-of-products coefficients, indexed outputs result sum-of-products even coefficients. This computational partitioning evident polyphase implementation shown Figure
FN3365.9 April 2007
HSP43216
HALFBAND FILTER .,X2,X1,X0 Y(0) Y(1) Y(2) Y(3) .X1,0,X0,0 .,Y1,Y0
polyphase implementation, input data stream feeds even filters running input sample rate. interpolated sample stream derived multiplexing output each polyphase branch into single data stream twice input sample rate. Decimate example, even filters comprised even indexed coefficients from original transversal filter. operation HSP43216 Interpolate mode analogous polyphase example above. this mode internal data flow routed shown Figure Figure 11B. different data flows depend selection internal external multiplexing INT/EXT. this mode, data input through AIN0-15 even polyphase branches filter processor. output each branch multiplexed together generate output data stream interpolated rate. NOTE: output each polyphase branch scaled compensate attenuation half caused interpolation.
FIGURE TRANSVERSAL IMPLEMENTATION INTERPOLATE HALFBAND FILTER
EVEN FILTER .,X2,X1,X0 .,Y5,Y3,Y1
FILTER
.,Y2,Y1,Y0
.,Y4,Y2,Y0
X0(C1)+X1(C3)+X2(C5) X0(C0)+X1(C2)+X2(C4)+X3(C6) X1(C1)+X2(C3)+X3(C5)
FIGURE POLYPHASE IMPLEMENTATION INTERPOLATE HALFBAND FILTER
AIN0-15
PIPELINE DELAY 2-35 GROUP DELAY
EVEN FILTER
AOUT0-15
Clocked CLK/2
PIPELINE DELAY GROUP DELAY
FILTER
FIGURE 11A. DATA FLOW DIAGRAM INTERPOLATE FILTER MODE (INT/EXT
PIPELINE DELAY 2-35 GROUP DELAY AIN0-15 PIPELINE DELAY GROUP DELAY FILTER EVEN FILTER
AOUT0-15
BOUT0-15
FIGURE 11B. DATA FLOW DIAGRAM INTERPOLATE FILTER MODE (INT/EXT
FN3365.9 April 2007
HSP43216
internal multiplexing selected (INT/EXT data stream input through AIN0-15 both upper lower processing legs shown Figure 11A. output each processing then multiplexed together produce interpolated sample stream twice input sample rate. this mode device clocked interpolated data rate support multiplexing each processing leg's output into single data stream. upper lower processing legs each input data rate CLK/2 indicated marking various registers processing elements Figure 11A. this mode, data samples clocked into part every other rising edge CLK. SYNC signal used specify which cycles used register data part's input. Specifically, every other rising edge starting after assertion SYNC will used clock data into part. With internal multiplexing minimum pipeline delay through upper processing CLK's pipeline delay through lower processing CLK's, (2[19+3]+4). external multiplexing selected (INT/EXT upper lower processing legs output through AOUT0-15 BOUT0-15 multiplexing into single data stream chip.This allows processing legs maximum clock rate which coincides with interpolated output data rate MSPS. NOTE: samples output BOUT0-15 precede those AOUT0-15 sample order. This requires multiplexing scenario which BOUT0-15 selected before AOUT0-15. With external multiplexing, minimum pipeline delay through upper processing CLK's pipeline delay through lower processing CLK's shown Figure 11B. this mode SYNC effect part operation. examining combination down conversion, filtering decimation, seen that real outputs only dependent sum-of-products even indexed samples filter coefficients, imaginary outputs only function sum-of-products indexed samples filter coefficients. This computational partitioning allows quadrature filters required after down conversion realized using same poly-phase processing elements used previous modes. functional block diagram polyphase implementation shown Figure this implementation, input data stream broken into even sample streams processed independently even filters. decomposing sample stream into even samples, zero terms produced down convert drop data streams, output each filters represent decimated data streams both real imaginary outputs.
INPUT SIGNAL SPECTRUM
-fS/2
fS/2
DOWN CONVERTED SIGNAL
-fS/2
fS/2
FILTERED SIGNAL FILTER PASSBAND
Down Convert Decimate Mode (MODE1-0
Down Convert Decimate Mode real input signal spectrally shifted -fS/4 which centers upper sideband This operation produces real imaginary components which each filtered decimated identical 67-tap halfband filters. added flexibility, positive fS/4 spectral shift selected which centers lower sideband direction spectral shift selected USB/LSB described Quadrature Down Convert section. spectral representation down convert decimate operation shown Figure (USB/LSB NOTE: Each complex terms output Filter Processor scaled compensate attenuation half introduced down conversion process. Down Convert Decimate mode most easily understood first considering transversal implementation using filter shown Figure
-fS/2 fS/2
DECIMATED OUTPUT SIGNAL SPECTRUM
-f'S
2f'S
INPUT SAMPLE RATE DECIMATED SAMPLE RATE, fS/2
FIGURE DOWN CONVERT DECIMATE OPERATION
FN3365.9 April 2007
HSP43216
HALFBAND FILTER .X2,X1,X0 0,-1, COS(n/2) HALFBAND FILTER .,I2,I0 0,-1,0,1. SIN(-n/2) REAL OUTPUTS .,R2,R0
HSP43216's implementation Down Convert Decimate mode analogous polyphase solution shown Figure part's data flow diagram this mode shown Figure Figure 15B. seen figures, input sample data broken into even sample streams which feed upper lower processing legs described Decimate Mode section. data each processing then modulated with nonzero quadrature components complex exponent (see Quadrature Down Convert Section). Following this operation, upper becomes processing chain real (In-phase) component quadrature down conversion lower processes complex (Quadrature) component down conversion. filter processing block implements equivalent decimate Halfband filter each quadrature legs. internal multiplexing specified (INT/EXT upper lower processing legs with even sample streams which derived from data input through AIN0-15. input sample stream synchronized with zero degree phase term down converter using SYNC control input. example, input data sample will into real (upper) processing mixed with zero degree cosine term quadrature input following assertion SYNC shown Figure pipeline delay through real processing (upper leg) CLK's delay through imaginary processing (lower leg) CLK's. complex samples output through AOUT0-15 BOUT0-15 present CLK's since quadrature streams have been decimated filter processor.
IMAGINARY OUTPUTS
Indicates samples discarded decimation process
FIGURE DOWN CONVERT DECIMATE FUNCTION USING TRANSVERSAL FILTERS
EVEN FILTER .,X4,X2,X0 .,R1,R0 1,-1,1,-1,.
FILTER .,I1,I0
.,X5,X3,X1
-1,1,-1,1.
REAL OUTPUTS X0(C0)-X2(C2)+X4(C4)-X6(C6) -X2(C0)+X4(C2)-X6(C4)+X8(C6) X4(C0)-X6(C2)+X8(C4)-X10(C6)
IMAGINARY OUTPUTS -X1(C1)+X3(C3)-X5(C5) X3(C1)-X5(C3)+X7(C5) -X5(C1)+X7(C3)-X9(C5)
FIGURE DOWN CONVERT DECIMATE FUNCTION USING POLYPHASE FILTERS
FN3365.9 April 2007
HSP43216
PIPELINE DELAY 2-35 GROUP DELAY
EVEN FILTER
AIN0-15
1,-1,1,-1,. -1,1,-1,1,.
AOUT0-15
PIPELINE DELAY GROUP DELAY
FILTER
BOUT0-15
Clocked CLK/2
FIGURE 15A. DATA FLOW DIAGRAM DOWN CONVERT DECIMATE MODE (INT/EXT
PIPELINE DELAY 2-35 GROUP DELAY AIN0-15 1,-1,1,-1,. -1,1,-1,1,. BIN0-15 EVEN FILTER AOUT0-15
PIPELINE DELAY GROUP DELAY FILTER
BOUT0-15
FIGURE 15B. DATA FLOW DIAGRAM DOWN CONVERT DECIMATE MODE (INT/EXT
SYNC
demultiplex function would route AIN015 BIN0-15.
AIN0-15
180o
270o
SYNC
SAMPLE DESIGNATED 180o LABELS MIXED WITH RESPECTIVE COSINE TERMS UPPER PROCESSING LEG, OTHER SAMPLES, THOSE LABELED 270o, MIXED WITH RESPECTIVE SINE TERMS LOWER LEG.
AIN0-15
180o
180o
FIGURE DATA SYNCHRONIZATION PHASE QUADRATURE
180o LABELS INDICATE PHASE ALIGNMENT SAMPLES INPUT THROUGH AIN0-15 WITH COSINE TERM QUADRATURE DOWN CONVERT
external multiplexing selected (INT/EXT demultiplex function required chip break input data stream into even samples input through AIN0-15 BIN0-15. this mode, real imaginary processing legs input clock rate which allows device perform down convert decimate function real signals sampled twice maximum speed grade device (104 MSPS). With external multiplexing, minimum pipeline delay through upper processing CLK's pipeline delay through lower processing CLK's shown Figure 15B. synchronize even samples input through AIN0-15 with zero degree cosine term quadrature SYNC should asserted same clock that target sample present input part shown Figure NOTE: proper operation, samples demultiplexed AIN0-15 input must precede those input BIN0-15 input sample order. example, given data sequence
FIGURE DATA SYNCHRONIZATION WITH PHASE DOWN CONVERT
Quadrature Real Conversion Mode (MODE1-0 Quadrature Real Conversion mode used construct real output from quadrature input. accomplish this, Halfband Filter Processor interpolates quadrature components complex input signal factor two. Next, Quadrature Up-Convert Processor spectrally shifts signal fS/4 derives real output described fS/4 Quadrature Up-Convert Processor Section. direction spectral shift controlled USB/LSB input used designate frequency content complex input either upper lower sideband resulting real output signal. spectral representation quadrature real conversion shown Figure USB/LSB NOTE: fS/4 Up-Convert Processor uses quadrature factors
FN3365.9 April 2007
HSP43216
scaled compensate attenuation introduced interpolation process.
INPUT SIGNAL SPECTRUM .R1,R0 .R1,0,R0,0 .,Y2,Y1,Y0 HALFBAND FILTER .I1,I0 INTERPOLATED SIGNAL FILTER PASSBAND .I1,0,I0,0 -1,0,1,0. SIN(-(n+1)/2) HALFBAND FILTER COS((n+1)/2) 0,1,0,-1.
-f'S/2
f'S/2
Y(0) Y(1) Y(2)
UPCONVERTED SIGNAL
-f'S/2
f'S/2
Y(3)
REAL OUTPUT
FIGURE QUADRATURE REAL CONVERTER USING TRANSVERSAL FILTERS
-f'S/2 f'S/2 EVEN FILTER .R1,R0
INPUT SAMPLE RATE INTERPOLATED SAMPLE RATE,
FIGURE QUADRATURE REAL CONVERSION
1,-1,1,-1,. .,Y2,Y1,Y0
Quadrature Real Conversion mode most easily understood first considering implementation using transversal filter shown Figure examining combination interpolation, filtering, conversion seen that particular output only dependent sum-of-products even indexed samples coefficients sum-of-products indexed samples coefficients. This computational partitioning allows dual interpolation filters required this mode realized using same polyphase filter structure used other modes. functional block diagram polyphase implementation Quadrature Real Conversion mode shown Figure this implementation, real imaginary components complex input stream drive even filters. output each filter then modulated non-zero factors multiplexed into single real output stream.
FILTER
.I1,I0
-1,1,-1,1.
Y(0) -1(I0(C1)+I1(C3))+I2(C5)) Y(1) 1(R0(C0)+R1(C2)+R2(C4))+R3(C6)) Y(2) 1(I1(C1)+I2(C3)+I3(C5)) Y(3) -1(R1(C0)+R2(C2)+R3(C4)+R4(C6))
FIGURE POLYPHASE IMPLEMENTATION QUADRATURE REAL CONVERTER
FN3365.9 April 2007
HSP43216
PIPELINE DELAY 2-35 GROUP DELAY
EVEN FILTER
AIN0-15
2,-2,2,-2,.
BIN0-15
PIPELINE DELAY GROUP DELAY
FILTER
-2,2,-2,2,.
AOUT0-15
Clock Input data rate, CLK/2
FIGURE 21A. DATA FLOW DIAGRAM QUADRATURE REAL CONVERSION MODE (INT/EXT
PIPELINE DELAY 2-32 GROUP DELAY AIN0-15 BIN0-15 PIPELINE DELAY GROUP DELAY FILTER EVEN FILTER 2,-2,2,-2,. -2,2,-2,2,. BOUT0-15 AOUT0-15
FIGURE 21B. DATA FLOW DIAGRAM QUADRATURE REAL CONVERSION MODE (INT/EXT
other modes, operation HSP43216 Quadrature real Conversion mode analogous that polyphase solution described above. data flow diagrams this particular mode shown Figures 21B. Internal Multiplexing specified (INT/EXT real imaginary components quadrature input through AIN0-15 BIN0-15 processed upper lower legs respectively (see Figure 21A). Each component complex input interpolated, mixed with non-zero sine cosine terms quadrature multiplexed together into real output sample stream through AOUT0-15. Prior output multiplexer, upper lower processing legs each input data rate CLK/2 indicated marking various registers processing elements Figure 21A. complex input sample stream synchronized with zero degree phase converters quadrature asserting SYNC control input cycle prior targeted data sample shown Figure This ensures that real sample input upper processing will mixed with zero degree cosine term. minimum pipeline delay through real processing (upper leg) CLK's delay through imaginary processing (lower leg) CLK's.
CLK/2 SYNC
AIN0-15 BIN0-15
FIGURE DATA SYNCHRONIZATION WITH PROCESSING LEGS (INT/EXT
external multiplexing selected (INT/EXT output from upper lower processing legs exit through AOUT0-15 BOUT0-15 multiplexing into single data stream chip (see Figure 21B).This allows processing legs maximum rate which coincides with interpolated output data rate MSPS. NOTE: output BOUT0-15 precedes that AOUT0-15 sample order. This requires multiplexing scenario which selects BOUT0-15 then AOUT0-15 each HSP43216. With external multiplexing, minimum pipeline delay through upper processing CLK's pipeline delay through lower processing CLK's shown Figure 21B. SYNC control input used described preceding paragraph.
FN3365.9 April 2007
HSP43216
Absolute Maximum Ratings
Supply Voltage +7.0V Input, Output Voltage -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (°C/W) (°C/W) PLCC Package. 23.0 MQFP Package 35.0 Maximum Junction Temperature PLCC MQFP Packages +150°C Maximum Storage Temperature Range .-65°C +150°C Maximum Lead Temperature (Soldering 10s) +300°C
Operating Conditions
Voltage Range +4.75V +5.25V Temperature Range +70°C
Characteristics
Gate Count .35469 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current
5.0V +70°C SYMBOL ICCOP TEST CONDITIONS Max, Frequency 52MHz INT/EXT `1', Notes Max, Frequency 52MHz INT/EXT `0', Notes UNITS
Standby Power Supply Current Input Leakage Current Output Leakage Current Clock Input High Clock Input Logical Input Voltage Logical Zero Input Voltage Logical Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance NOTES:
ICCSB VIHC VILC COUT
Max, Outputs Loaded Max, Input Max, Input -3mA, 5mA, Frequency 1MHz, measurements referenced GND. +25°C, Note
Power supply current proportional frequency. Typical rating 9mA/MHz when Internal Multiplexing selected, INT/EXT Power supply current proportional frequency. Typical rating 11mA/MHz when External Multiplexing selected, INT/EXT Output load test circuit 40pF. tested, characterized initial design major process/design changes. Maximum junction temperature must considered when operating part high clock frequencies.
FN3365.9 April 2007
HSP43216
Electrical Specifications
(Note 52MHz PARAMETER Period High Setup Time AIN0-15, BIN0-15 Hold Time AIN0-15, BIN0-15 from MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB Setup Time MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB Hold Time AOUT0-15, BOUT0-15 Delay Output Enable Time Output Disable Time Output Rise, Output Fall Times NOTES: tests performed with 40pF, 5mA, -3mA. Input reference level 2.0V, other inputs 1.5V. Test 3.0V, VIHC 4.0V, Controlled design process parameters directly tested. Characterized upon initial design after major process and/or changes. SYMBOL Note Note NOTES UNITS
Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP 1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
FN3365.9 April 2007
HSP43216 Waveforms
AIN0-15, BIN-15
MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB
AOUT0-15, BOUT0-15
FIGURE TIMING RELATIVE
2.0V 0.8V
FIGURE OUTPUT RISE FALL TIMES
FN3365.9 April 2007
HSP43216 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27)
N84.1.15 (JEDEC MS-018AF ISSUE
0.004 (0.10)
LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 1.185 1.150 0.541 1.185 1.150 0.541 0.180 0.120 1.195 1.158 0.569 1.195 1.158 0.569 MILLIMETERS 4.20 2.29 30.10 29.21 13.75 30.10 29.21 13.75 4.57 3.04 30.35 29.41 14.45 30.35 29.41 14.45 NOTES Rev. 11/97
0.025 (0.64) 0.045 (1.14)
D2/E2 D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51) SEATING PLANE
0.026 (0.66) 0.032 (0.81)
0.013 (0.33) 0.021 (0.53)
0.045 (1.14)
0.025 (0.64) VIEW TYP.
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. Dimensions include mold mismatch measured extreme material condition body parting line. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
FN3365.9 April 2007
HSP43216 Metric Plastic Quad Flatpack Packages (MQFP)
Q100.14x20 (JEDEC MS-022GC-1 ISSUE
LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL
SEATING PLANE 0.076 0.003
MILLIMETERS 0.25 2.57 0.22 0.22 23.08 19.88 17.10 13.90 0.73 0.65 3.40 2.87 0.38 0.33 23.32 20.12 17.30 14.10 1.03 NOTES Rev. 4/99
0.010 0.101 0.009 0.009 0.908 0.782 0.673 0.547 0.029
0.134 0.113 0.015 0.013 0.918 0.792 0.681 0.555 0.040
0.026
NOTES:
0.40 0.016 0o-7o
12o-16o 0.20 0.008
0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 0.13/0.23 0.005/0.009
Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. dimensions tolerances ANSI Y14.5M-1982. Dimensions determined seating plane Dimensions determined datum plane Dimensions include mold protrusion. Allowable protrusion 0.25mm (0.010 inch) side. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm (0.003 inch) total. number terminal positions.
12o-16o
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN3365.9 April 2007

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