FN3177.3 Dual Filter HSP43168/883 Dual Filter consists indep
|
|
|
Top Searches for this datasheet
HSP43168/883
FN3177.3
Dual Filter
HSP43168/883 Dual Filter consists independent 8-tap filters. Each filter supports decimation from provides on-board storage sets coefficients. Block Diagram shows cells each separate coefficient bank separate inputs. outputs cells either summed multiplexed MUX/Adder. compute power Cells configured provide quadrature filtering, complex filtering, convolution, 1D/2-D correlations, interpolating/decimating filters. cells take advantage symmetry coefficients pre-adding data samples prior multiplication. This allows 8-tap implemented using only multipliers filter cell. These cells configured either single 16-tap filter dual 8-tap filters. Asymmetric filtering also supported. Decimation provided boost effective number filter taps from times. Further, Decimation Registers provide delay necessary fractional data conversion filtering with kernels flexibility dual further enhanced sets user programmable coefficients. Coefficient selection changed asynchronously from clock clock. ability toggle between coefficient sets further simplifies applications such polyphase adaptive filtering. HSP43168 power fully static design implemented advanced CMOS process. configuration device controlled through standard microprocessor interface.
Features
This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph 1.2.1. Independent 8-Tap Filters Configurable Single 16-Tap 10-Bit Data Coefficients On-Board Storage Programmable Coefficient Sets Taps, Kernels, 20-Bit Data Coefficients Programmable Decimation Programmable Rounding Output Standard Microprocessor Interface 33MHz, 25.6MHz Versions
Applications
Quadrature, Complex Filtering Correlation Image Processing PolyPhase Filtering Adaptive Filtering
Ordering Information
PART NUMBER HSP43168GM-25/883 HSP43168GM-33/883 TEMP. RANGE PACKAGE PKG. G84.A G84.A
Block Diagram
CIN0 CSEL0 CONTROL CONFIGURATION
COEFFICIENT BANK INA0 CELL
COEFFICIENT BANK
CELL
INB0 OUT0
ADDER OUT9
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
HSP43168/883 Pinouts
VIEW
OUT18 INB1 INB4 INB5 INB6 INB9
OUT15 OUT14 OUT12 OUT10 OUT11 OUT16 OUT13
OUT9
INB0
INB2
INB7
INB8
INA1
OUT19 OUT17
INB3
INA0
INA2
OUT21 OUT20
INA3
INA4
OUT24 OUT23 OUT25 OUT27 OUT22 OUT26
INA7 INA8
INA5 INA9
INA6 CIN0
CIN2
CIN1
TXFR SHFT RVRS
ACCEN
CIN3
FWRD MUX0 MUX1
CSEL0 CSEL2 CIN9
CIN6 CIN7
CIN4 CIN5
'A1'
CSEL1 CSEL3 CSEL4 CIN8
BOTTOM VIEW
RVRS SHFT 'A1'
CSEL1 CSEL3 CSEL4 CIN8
MUX0 MUX1
CSEL0
CSEL2 CIN9
CIN7
CIN5
TXFR FWRD
CIN6
CIN4
ACCEN CIN2
CIN1
CIN3 CIN0
OUT27 OUT22 OUT26
INA8 INA7
INA9 INA5
INA6
OUT24 OUT23 OUT25
OUT21 OUT20 OUT19 OUT17 OUT9 INB3
INA3 INA0
INA4 INA2
OUT18
OUT16 OUT13
INB0
INB2
INB7
INB8
INA1
OUT15 OUT14 OUT12 OUT10 OUT11
INB1
INB4
INB5
INB6
INB9
HSP43168/883 Description
NAME CIN0-9 A0-8 CSEL0-4 INA0-9 INB0-9 OUT9-27 NUMBER D11, K10, E10, L11, E1-3, C1-2, B1-3, A5-8, B6-8, C6-7 A2-4, J1-2, H1-2, G1-3, F2-3 L1-5, K2-3, K5-6, F9-11, G9-11, H10-11, J10-11, K11, K8-9, L6-10 B9-10 TYPE VCC: power supply pin. Ground. Control/Coefficient Data Bus. Processor interface loading control data coefficients. CIN0 LSB. Control/Coefficient Address Bus. Processor interface addressing control Coefficient Registers. LSB. Control/Coefficient Write Clock. Data latched into Control Coefficient Registers rising edge Coefficient Select. This input determines which coefficient sets used This input registered CSEL0 LSB. Input INA0 LSB. Bidirectional Input INB0 input only. When used output, INB1-9 LSB's output bus. MSB's Output Bus. Data format either unsigned two's complement depending configuration. OUT27 MSB. Shift Enable. This active input enables shifting data through Decimation Registers. Forward Input Enable. When active low, data from forward decimation path input ALU's through input. When high, inputs ALUs zeroed. Reverse Input Enable. When active low, data from reverse decimation path input ALU's through input. When high, inputs ALUs zeroed. Data Transfer Control. This active input switches LIFO being read into reverse decimation path with LIFO being written from forward decimation path (see Figure Adder/Mux Control. This input controls data flow through output Adder/Mux. Table lists various configurations. Clock. inputs except those associated with processor interface (CIN0-9, A0-8, output enables (OEL, OEH) registered rising edge CLK. Output Enable Low. This tristate control enables LSB's output INB1-9 when low. Output Enable High. This tristate control enables OUT9-27 when low. Accumulate Enable. This active high input allows accumulation Cell Accumulator. this input latches Accumulator contents into Output Holding Registers while zeroing feedback path accumulator. DESCRIPTION
SHFTEN FWRD RVRS TXFR MUX0-1 ACCEN
HSP43168/883
Absolute Maximum Ratings 25oC
Supply Voltage. +8.0V Input, Output Voltage -0.5V +0.5V Lead Temperature (Soldering 10s) .300oC Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) JC(oC/W) Ceramic Package 33.5 Maximum Package Power Dissipation 125oC Ceramic Package .1.49 Maximum Junction Temperature 175oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Operating Voltage Range +4.5V +5.5V Operating Temperature Range -55oC 125oC
Characteristics
Gate Count 32529 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS GROUP SUB-GROUPS LIMITS TEMPERATURE (oC) UNITS
PARAMETER Logical Input Voltage Logical Zero Input Voltage Logical Input Voltage Clock Logical Zero Input Voltage Clock Output HIGH Voltage Output Voltage Input Leakage Current Output Leakage Current Standby Power Supply Current Operating Power Supply Current Functional Test NOTES:
SYMBOL VIHC VILC ICCSB
CONDITIONS 5.5V 4.5V 5.5V 4.5V -400µA VCC= 4.5V (Note +2.0mA VCC= 4.5V (Note 5.5V 5.5V 5.5V, Outputs Open 25.6MHz, GND, 5.5V (Note (Note
ICCOP
281.6
Interchanging force sense conditions permitted. Operating Supply Current proportional frequency, typical rating 11mA/MHz. Tested follows: 1MHz, (clock inputs) 3.4V, (all other inputs) 2.6V, 0.4V, 1.5V, 1.5V.
HSP43168/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested (NOTE CONDITIONS GROUP SUBGROUPS Note Note (-33MHz) TEMPERATURE (oC) (-25MHz) UNITS
PARAMETER Period High Period High Set-up Time; A0-8 Hold Time; A0-8 High Set-up Time; CIN0-9 High Hold Time; CIN0-9 High Set-up Time; Set-up Time; CIN0-9 Set-up Time; CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, MUX0-1 High Hold Time; CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, MUX0-1 High Output Delay OUT0-27 Output Enable Time NOTES:
SYMBOL TAWS TAWH TCWS TCWH TWLCL TCVCL TECS
TECH
Note
testing performed follows: Input levels (CLK Input) 4.0V input levels (all other inputs) 3.0V timing reference levels (CLK) 2.0V; others 1.5V. 4.5V 5.5V. Output load test load circuit with Output transition measured 1.5V 1.5V. Transition measured ±200mV from steady state voltage, Output loading test load circuit, 40pF. Set-up time requirements loading data CIN0-9 guarantee recognition following clock.
HSP43168/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS (-33MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL COUT CONDITIONS Open, MHz, measurements referenced device GND. NOTES TEMPERATURE (oC) (-25MHz) UNITS
Output Disable Time Output Rise Time Output Fall Time NOTES:
From 0.8V 2.0V From 2.0V 0.8V
parameters Table controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Loading specified test load circuit with 40pF. TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS
Test Load Circuit
INCLUDES STRAY CAPACITANCE
1.5V
EQUIVALENT CIRCUIT SWITCH OPEN ICCSB ICCOP TEST
HSP43168/883 Waveforms
tECS CSEL0-4, MUX0-1 SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9 OUT0-27
tECH
tWLCL
tAWS A0-8
tAWH
tCWS CIN0-15
tCWH
tCVCL 1.5V 1.5V
OEL,
1.7V OUT0-27 HIGH IMPEDANCE 1.3V
HIGH IMPEDANCE
OUTPUT ENABLE, DISABLE TIMING
2.0V 0.8V
2.0V 0.8V
OUTPUT RISE FALL TIMES
HSP43168/883 Burn-In Circuit
BOTTOM VIEW
RVRS CSEL0 'A1'
CSEL1 CSEL3 CSEL4 CIN8 CSEL2 CIN9 CIN7 CIN6 CIN5 CIN4 CIN3 CIN0
SHFT MUX0 MUX1 TXFR FWRD ACCEN
CIN2
CIN1
OUT27 OUT22 OUT26 OUT24 OUT23 OUT25
INA8 INA7
INA9 INA5
INA6
OUT21 OUT20 OUT19 OUT17 OUT18 OUT9 OUT16 OUT13 INB0 INB3 INB2 INB7
INA3 INA0 INB8
INA4 INA2 INA1
OUT15 OUT14 OUT12 OUT10 OUT11 INB1
INB4
INB5
INB6
INB9
NOTES: VCC/2 (2.7V ±10%) used outputs only. (±20%) resistor connected pins except GND. ±0.5V. 0.1µf (Min) capacitor between position. 100KHz ±10%, F0/2, F1/2. F15/2, duty cycle. Input voltage limits: 0.8V Max, ±10%.
HSP43168/883
NAME CIN8 CSEL4 CSEL3 CSEL1 RVRS CIN5 CIN7 CIN9 CSEL2 MUX1 MUX0 SHFTEN CIN4 CIN6 CSEL0 FWRD TXFR CIN3 ACCEN CIN0 CIN1 CIN2 OEHB INA9 INA8 BURN-IN SIGNAL
NAME SUM26 SUM22 SUM27 INA6 INA5 INA7 SUM25 SUM23 SUM24 INA4 INA3 SUM20 SUM21 INA2 INA0 INB3 OELB SUM9 SUM17 SUM19 INA1 INB8 INB7 INB2 INB0 SUM13 SUM16 SUM18 INB9 INB6 INB5 INB4 INB1 SUM11 SUM10 SUM12 SUM14 SUM15
BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
HSP43168/883 Characteristics
DIMENSIONS: 1mils METALLIZATION: Type: Si-Al Si-Al-Cu Thickness: GLASSIVATION: Type: Nitrox Thickness: WORST CASE CURRENT DENSITY: 1.93 A/cm2
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite Irvine, 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Palm Bay, 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. William Graisse, 1006 Lausanne Switzerland TEL: 6140560 FAX: 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433
Other recent searches
SYM-30DLHW - SYM-30DLHW SYM-30DLHW Datasheet
Si4412ADY - Si4412ADY Si4412ADY Datasheet
QCC12B - QCC12B QCC12B Datasheet
P3055LS - P3055LS P3055LS Datasheet
FMI16N60E - FMI16N60E FMI16N60E Datasheet
CB120 - CB120 CB120 Datasheet
CB200 - CB200 CB200 Datasheet
AD7228A - AD7228A AD7228A Datasheet
1N4247 - 1N4247 1N4247 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
