Data Sheet March 2006 FN2921.11 110MHz, High Slew Rate, High Outp
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HA-5002
Data Sheet March 2006 FN2921.11
110MHz, High Slew Rate, High Output Current Buffer
HA-5002 monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing advantages Intersil D.I. technologies, HA-5002 current buffer offers 1300V/µs slew rate with 110MHz bandwidth. ±200mA output current capability enhanced output impedance. monolithic HA-5002 will replace hybrid LH0002 with corresponding performance increases. These characteristics range from 3000k input impedance increased output voltage swing. Monolithic design technologies have allowed more precise buffer developed with more than order magnitude smaller gain error. HA-5002 will provide many present hybrid users with higher degree reliability same time increase overall circuit performance. military grade product, refer HA-5002/883 datasheet.
Features
Voltage Gain. 0.995 High Input Impedance .3000k Output Impedance Very High Slew Rate 1300V/µs Very Wide Bandwidth 110MHz High Output Current. ±200mA Pulsed Output Current 400mA Monolithic Construction Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Line Driver Data Acquistion 110MHz Buffer Radara Cable Driver High Power Current Booster High Power Current Source Sample Holds Video Products
Ordering Information
PART NUMBER HA2-5002-2 HA2-5002-5 HA3-5002-5 HA3-5002-5Z (Note) HA4P5002-5 HA4P5002-5Z (Note) HA9P5002-5 HA9P5002-5Z (Note) HA9P5002-9 HA9P5002-9Z (Note) PART MARKING HA2-5002-2 HA2-5002-5 HA3-5002-5 HA3-5002-5Z HA4P5002-5 HA4P5002-5Z 50025 50025Z 50029 50029Z TEMP. RANGE (°C) PACKAGE Metal Metal PDIP PDIP* (Pb-free) PLCC PLCC (Pb-free) SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) PKG. DWG. T8.C T8.C E8.3 E8.3 N20.35 N20.35 M8.15 M8.15 M8.15 M8.15
*Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2006. Rights Reserved. other trademarks mentioned property their respective owners.
HA-5002 Pinouts
HA-5002 (PDIP, SOIC) VIEW HA-5002 (PLCC) VIEW
HA-5002 (METAL CAN) VIEW
V2NC
V1V2-
V113
NOTE: Case Voltage Floating
FN2921.11 March 2006
HA-5002
Absolute Maximum Ratings
Voltage Between Terminals. Input Voltage V1Output Current (Continuous) ±200mA Output Current (50ms Off) ±400mA
Thermal Information
Thermal Resistance (Typical, Note (°C/W) (°C/W) PDIP Package*. Metal Package PLCC Package. SOIC Package Junction Temperature (Hermetic Packages, Note 175°C Junction Temperature (Plastic Packages, Note 150°C Storage Temperature Range -65°C 150°C Lead Temperature (Soldering 10s) 300°C (PLCC SOIC Lead Tips Only) *Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications.
Operating Conditions
Temperature Range HA-5002-2 -55°C 125°C HA-5002-5 75°C HA-5002-9 -40°C 85°C
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: Maximum power dissipation, including load conditions, must designed maintain maximum junction temperature below 175°C packages, below 150°C plastic packages. measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Bias Current Input Resistance Input Noise Voltage TRANSFER CHARACTERISTICS Voltage Gain (VOUT ±10V)
VSUPPLY ±12V ±15V, 10pF, Unless Otherwise Specified TEST CONDITIONS TEMP (°C) Full Full Full Full 10Hz-1MHz Full ±15V ±12V Full Full Full 1VRMS, 10kHz 0.1% HA-5002-2 0.980 0.900 0.971 0.995 ±10.7 ±13.5 ±10.5 <0.005 20.7 0.980 HA-5002-5, 0.900 0.971 0.995 ±11.2 ±13.9 ±10.5 <0.005 20.7 UNITS µV/°C µVP-P A/mA V/ns
-3dB Bandwidth Current Gain OUTPUT CHARACTERISTICS Output Voltage Swing
1VP-P
Output Current Output Resistance Harmonic Distortion TRANSIENT RESPONSE Full Power Bandwidth (Note Rise Time Propagation Delay Overshoot Slew Rate Settling Time
±10V,
FN2921.11 March 2006
HA-5002
Electrical Specifications
PARAMETER Differential Gain Differential Phase POWER REQUIREMENTS Supply Current Power Supply Rejection Ratio NOTE: Slew Rate FPBW Full Full VSUPPLY ±12V ±15V, 10pF, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (°C) HA-5002-2 0.06 0.22 HA-5002-5, 0.06 0.22 UNITS Degrees
Test Circuit Waveforms
+15V V1-15V V2OUT
FIGURE LARGE SMALL SIGNAL RESPONSE
VOUT
VOUT
SMALL SIGNAL WAVEFORMS
SMALL SIGNAL WAVEFORMS
FN2921.11 March 2006
HA-5002 Test Circuit Waveforms (Continued)
VOUT
VOUT
LARGE SIGNAL WAVEFORMS
LARGE SIGNAL WAVEFORMS
Schematic Diagram
V1IN V2Q2
Application Information
Layout Considerations
wide bandwidth HA-5002 necessitates that high frequency circuit layout procedures followed. Failure follow these guidelines result marginal performance. Probably most crucial RF/video layout rules ground plane. ground plane provides isolation minimizes distributed circuit capacitance inductance which will degrade high frequency performance.
Other considerations proper power supply bypassing keeping input output connections short possible which minimizes distributed capacitance reduces board space.
Power Supply Decoupling
optimal device performance, recommended that positive negative power supplies bypassed with capacitors ground. Ceramic capacitors ranging value from 0.01 0.1µF will minimize high frequency variations supply voltage, while frequency bypassing requires
FN2921.11 March 2006
HA-5002
larger valued capacitors since impedance capacitor dependent frequency. also recommended that bypass capacitors connected close HA-5002 (preferably directly supply pins).
Capacitive Loading
HA-5002 will drive large capacitive loads without oscillation peak current limits should exceeded. Following formula Cdv/dt implies that slew rate capacitive load must controlled keep peak current below maximum current limiting approach shown. HA-5002 become unstable with small capacitive loads (50pF) certain precautions taken. Stability enhanced following: source resistance series with input increasing capacitive load 150pF greater; decreasing CLOAD 20pF less; adding output resistor adding feedback capacitance 50pF greater. Adding source resistance generally yields best results.
Operation Reduced Supply Levels
HA-5002 operate supply voltage levels lower. Output swing directly affected well slight reductions slew rate bandwidth.
Short Circuit Protection
output current limited using following circuit:
OUTMAX OUTMAX
IOUTMAX 200mA (CONTINUOUS) RLIM V1V2RLIM
V1.8 MAXIMUM POWER DISSIPATION PDIP TEMPERATURE (°C) QUIESCENT POWER DISSIPATION ±15V SUPPLIES SOIC
PLCC
JMAX DMAX Where: TJMAX Maximum Junction Temperature Device Ambient Junction Case Thermal Resistance Case Heat Sink Thermal Resistance Heat Sink Ambient Thermal Resistance Graph based JMAX DMAX
FIGURE MAXIMUM POWER DISSIPATION TEMPERATURE
FN2921.11 March 2006
HA-5002 Typical Application
+12V V1-12V VOUT V2V2+ VOUT
FIGURE COAXIAL CABLE DRIVER SYSTEM
Typical Performance Curves
VOLTAGE GAIN (dB) GAIN PHASE FREQUENCY (MHz) PHASE SHIFT 135° 180° ±15V, VOLTAGE GAIN (dB) PHASE FREQUENCY (MHz) 135° 180° PHASE SHIFT GAIN ±15V,
FIGURE GAIN/PHASE FREQUENCY
FIGURE GAIN/PHASE FREQUENCY
0.994 0.992 0.990 VOLTAGE GAIN (V/V) VOLTAGE GAIN (V/V) 0.988 0.986 0.984 0.982 0.980 0.978 0.976 0.974 TEMPERATURE (°C) VOUT -10V +10V ±15V
0.998 ±15V 0.997 0.996 0.995 0.994 0.993 0.992 0.991 VOUT -10V VOUT +10V
TEMPERATURE (°C)
FIGURE VOLTAGE GAIN TEMPERATURE 100)
FIGURE VOLTAGE GAIN TEMPERATURE
FN2921.11 March 2006
HA-5002 Typical Performance Curves
±15V BIAS CURRENT (µA) TEMPERATURE (°C) TEMPERATURE (°C)
(Continued)
±15V
OFFSET VOLTAGE (mV)
FIGURE OFFSET VOLTAGE TEMPERATURE
FIGURE BIAS CURRENT TEMPERATURE
±15V, RLOAD SUPPLY CURRENT (mA)
±15V, IOUT
OUTPUT VOLTAGE
+VOUT
-VOUT
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE MAXIMUM OUTPUT VOLTAGE TEMPERATURE
FIGURE SUPPLY CURRENT TEMPERATURE
IOUT 125°C, 25°C SUPPLY CURRENT (mA) IMPEDANCE -55°C 100K
±15V
1000
SUPPLY VOLTAGE (±V) ZOUT
100K
100M
FREQUENCY (Hz)
FIGURE SUPPLY CURRENT SUPPLY VOLTAGE
FIGURE INPUT/OUTPUT IMPEDANCE FREQUENCY
FN2921.11 March 2006
HA-5002 Typical Performance Curves
(Continued)
RLOAD PSRR (dB)
VOUT MAX, VP-P 100kHz
25°C 125°C, -55°C
SUPPLY VOLTAGE (±V)
100K
FREQUENCY (Hz)
100M
FIGURE VOUT MAXIMUM VSUPPLY
FIGURE PSRR FREQUENCY
1500 1400 SLEW RATE (V/µs) 1300 1200 1100 1000 SUPPLY VOLTAGE (±V) VOUT (mV)
±15V 25°C
-100 -150
INPUT VOLTAGE (VOLTS)
FIGURE SLEW RATE SUPPLY VOLTAGE
FIGURE GAIN ERROR INPUT VOLTAGE
Characteristics
SUBSTRATE POTENTIAL (POWERED UP): V1TRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation
FN2921.11 March 2006
HA-5002 Metallization Mask Layout
HA-5002
V1IN
(ALT) (ALT)
FN2921.11 March 2006
HA-5002 Dual-In-Line Plastic Packages (PDIP)
INDEX AREA
E8.3 (JEDEC MS-001-BA ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES Rev. 12/93
0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
BASE PLANE SEATING PLANE 0.010 (0.25)
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.300 0.115 0.430 0.150
2.54 7.62 10.92 3.81
2.93
FN2921.11 March 2006
HA-5002 Metal Packages (Can)
REFERENCE PLANE BASE SEATING PLANE BASE METAL LEAD FINISH
T8.C MIL-STD-1835 MACY1-X8 (A1)
LEAD METAL PACKAGE INCHES SYMBOL 0.165 0.016 0.016 0.016 0.335 0.305 0.110 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS 4.19 0.41 0.41 0.41 8.51 7.75 2.79 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES Rev. 5/18/94
0.200 0.100 0.027 0.027 0.500 0.250 0.010 0.040 0.034 0.045 0.750 0.050 0.045
5.08 2.54 1.02 0.86 1.14 19.05 1.27 1.14
0.69 0.69 12.70 6.35 0.25
SECTION
NOTES: (All leads) applies between applies between 0.500 from reference plane. Diameter uncontrolled beyond 0.500 from reference plane. Measured from maximum diameter product. basic spacing from centerline terminal basic spacing each lead lead position places) from looking bottom package. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
FN2921.11 March 2006
HA-5002 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27)
N20.35 (JEDEC MS-018AA ISSUE
0.004 (0.10)
LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 0.385 0.350 0.141 0.385 0.350 0.141 0.180 0.120 0.395 0.356 0.169 0.395 0.356 0.169 MILLIMETERS 4.20 2.29 9.78 8.89 3.59 9.78 8.89 3.59 4.57 3.04 10.03 9.04 4.29 10.03 9.04 4.29 NOTES Rev. 11/97
0.025 (0.64) 0.045 (1.14)
D2/E2 D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51)
SEATING PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) VIEW TYP.
0.025 (0.64)
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. Dimensions include mold mismatch measured extreme material condition body parting line. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
FN2921.11 March 2006
HA-5002 Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M8.15 (JEDEC MS-012-AA ISSUE
LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 1.35 0.10 0.33 0.19 4.80 3.80 1.75 0.25 0.51 0.25 5.00 4.00 NOTES Rev. 6/05
0.0532 0.0040 0.013 0.0075 0.1890 0.1497
0.0688 0.0098 0.020 0.0098 0.1968 0.1574
0.10(0.004)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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FN2921.11 March 2006
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