Data Sheet PD60303 IRS20955(S)PbF PROTECTED DIGITAL AUDIO DR
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IRS20955(S)PbF
Data Sheet PD60303
IRS20955(S)PbF
PROTECTED DIGITAL AUDIO DRIVER
Features
Floating input enables easy half-bridge implementation Programmable bidirectional over-current protection with self-reset function Programmable preset deadtime improved performances High noise immunity ±100 ratings deliver output power logic compatible input Operates RoHS compliant
Product Summary
VOFFSET (max) Gate driver Selectable deadtime Propagation delay protection delay Shutdown propagation delay 45ns (max) (max)
Description
IRS20955 high voltage, high speed MOSFET driver with floating input designed Class audio amplifier applications. Bi-directional current sensing detects over-current conditions during positive negative load currents without external shunt resistors. built-in protection control block provides secure protection sequence against overcurrent conditions programmable reset timer. internal deadtime generation block enables accurate gate switching optimum deadtime setting better audio performance, such lower lower audio noise floor.
Package
Typical Connection
IRS20955
VREF OCSET
Speaker
(Please refer Lead Assignments correct configuration. This diagram shows electrical connections only)
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IRS20955(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced COM; currents defined positive into lead. thermal resistance power dissipation ratings measured under board mounted still conditions.
Symbol
VCSH VCSD VOCSET VREF IDDZ ICCZ IBSZ IOREF Rth,JA
Definition
High-side floating supply voltage High-side floating supply voltage (Note1) High-side floating output voltage input voltage Low-side fixed supply voltage (Note1) Low-side output voltage Floating input supply voltage Floating input supply voltage (Note1) input voltage input voltage input voltage OCSET input voltage VREF voltage Floating input supply Zener clamp current (Note1) side supply Zener clamp current (Note1) Floating supply Zener clamp current (Note1) Reference output current Allowable voltage slew rate Allowable voltage slew rate (Note2) Allowable voltage slew rate upon power-up (Note3) Maximum power dissipation Thermal resistance, junction ambient Junction temperature Storage temperature Lead temperature (soldering, seconds)
Min.
-0.3 VB-20 Vs-0.3 Vs-0.3 -0.3 -0.3 -0.3 (See IDDZ) -0.3 -0.3 -0.3 -0.3 -0.3
Max.
VB+0.3 VB+0.3 VB+0.3 +0.3 VDD+0.3 VDD+0.3 VDD+0.3 +0.3 +0.3 +0.3
Units
V/ns V/ms °C/W
Note1: VSS, -COM contain internal shunt Zener diodes. Please note that voltage ratings these limited clamping current. Note2: rising falling edges step signal Vss=15 Note3: ramps from
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IRS20955(S)PbF
Recommended Operating Conditions
proper operation, device should used within recommended conditions below. voltage parameters absolute voltages referenced COM. offset ratings tested with supplies biased IDD=5 VCC=12 VB-VS=12
Symbol
IDDZ VCSD IOREF VOCSET
Definition
High-side floating supply absolute voltage High-side floating supply offset voltage Floating input supply zener clamp current Floating input supply absolute voltage High-side floating output voltage Low-side fixed supply voltage Low-side output voltage input voltage input voltage input voltage Reference output current (Note OCSET input voltage Ambient temperature Input pulse width
Min.
VS+10 Note (note
Max.
VS+18
Units
Note Logic operational equal +200 Logic state held equal -VBS. Note Nominal voltage VREF IOREF dictates total external resistor value VREF 16.7 Note Output logic status respond correctly input pulse width smaller than minimum pulse width
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IRS20955(S)PbF
Electrical Characteristics
,VBS= IDD=5 VSS=20 VS=0 V,CL=1 TA=25 unless otherwise specified.
Symbol Low-Side Supply
UVCC+ UVCCIQCC VCLAMPL UVBS+ UVBSIQBS ILKH VCLAMPH UVDD+ UVDDIQDD VCLAMPM ILKM IIN+ IIN-
Definition
19.6 19.6
20.4 20.4 10.2
21.6
Units
Test Conditions
supply UVLO positive threshold supply UVLO negative threshold Low-side quiescent current Low-side Zener diode clamp voltage High-side well UVLO positive threshold High-side well UVLO negative threshold High-side quiescent current High-side low-side leakage current High-side Zener diode clamp voltage VDD, floating supply UVLO positive threshold VDD, floating supply UVLO negative threshold Floating input quiescent current Floating input Zener diode clamp voltage Floating input side low-side leakage current Logic high input threshold voltage Logic input threshold voltage Logic input bias current Logic input bias current
ICC=5
High-Side Floating Supply
21.6 10.8 VB=VS =200 IBS=5 VDD=9.5 +VSS IDD=5 VDD=VSS =200
Floating Input Supply
Floating Input
=3.3
Protection
VREF Vth,OCL Vth,OCH Vth,1 Vth,2 ICSD+ ICSDtSD tOCH tOCL Reference output voltage Low-side threshold High-side threshold VCSH shutdown release threshold self reset threshold discharge current charge current Shutdown propagation delay from VCSD Vth,OCH shutdown Propagation delay time from VCSH Vth,OCH shutdown Propagation delay time from Vth,OCL shutdown Output high short circuit current (source) Output short circuit current (sink) level output voltage COM, 1.1+ 0.62 0.26 1.2+ 0.70 0.30 1.3+ 0.78 0.34 IOREF =0.5 OCSET=1.2 Fig. VS=200 Fig. Fig. Fig. Fig.
Gate Driver
IoVOL PW<10 PW<10
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IRS20955(S)PbF
Electrical Characteristics (cont.)
,VBS= IDD=5 VSS=20 VS=0 V,CL=1 TA=25 unless otherwise specified. ton,1 toff,1 ton,2 toff,2 VDT1 VDT2 VDT3 High level output voltage Turn-on rise time Turn-off fall time High-side low-side turn-on propagation delay, floating inputs High-side low-side turn-off propagation delay, floating inputs High-side low-side turn-on propagation delay, non-floating inputs High-side low-side turn-off propagation delay, non-floating inputs Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO) Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO) Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO) Deadtime: turn-off turn-on (DTLO-HO) turn-off turn-on (DTHO-LO)VDT= VDT4 mode select threshold mode select threshold mode select threshold 0.51(V 0.32(V 0.21(V 0.57(V 0.36(V 0.23(V 0.63(V 0.40(V 0.25(V VCC, VCC, 100V, VDT>VDT1, VDT1>VDT> VDT2, VDT2>VDT> VDT3, VDT3>VDT, IO=0
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IRS20955(S)PbF
Lead Definitions
Symbol
VREF OCSET
Description
Floating input positive supply Shutdown timing capacitor, referenced non-inverting input, phase with Floating input supply return reference output setting OCSET Low-side over-current threshold setting, referenced Input programmable deadtime, referenced Low-side supply return Low-side output Low-side logic supply High-side floating supply return High-side output High-side floating supply High-side over-current sensing input, referenced
VREF OCSET
IRS20955(S)
IRS20955(S) 16-Lead SOIC (narrow body)
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IRS20955(S)PbF
Block Diagram
FLOATING INPUT
DETECT HIGH SIDE
DETECT
10.2V
INPUT LOGIC
20.4V
LEVEL SHIFT
LEVEL SHIFT
FLOATING HIGH SIDE
LEVEL SHIFT
CHARGE/ DISCHARGE
DETECT
DEAD-TIME
LEVEL SHIFT PROTECTION CONTROL LEVEL SHIFT SIDE
20.4V
OCSET
5.1V REFERENCE
VREF
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IRS20955(S)PbF
ff(H
ff(L
VthOCL
tOCL
Figure VTH,OCL Shutdown Waveform Figure Switching Time Waveform Definitions
Vth1
VthOCH
HO/LO
tOCH
Figure Shutdown Waveform Definitions
Figure VCSH Vth, Shutdown Waveform
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IRS20955(S)PbF
Functional Description
Floating Input IRS20955S accepts floating inputs, enabling easy half-bridge implementation. VDD, refer VSS. result, input signal directly feed into while referencing VSS, which typically midpoint between positive negative voltages half-bridge configuration. IRS20955S also accepts non-floating input when tied COM.
Over-Current Protection (OCP) IRS20955S features over-current protection protect power MOSFETs during abnormal load conditions. IRS20955S engages sequence events when detects over-current condition during high-side low-side turn soon either high-side low-side current sensing block detects over-current: Latch (OCL) flips logic states shutdowns outputs starts discharging external capacitor When VCSD, voltage across falls below lower threshold Vth2, output signal from COMP2 resets OCL. starts charging external capacitor When VCSD goes above upper threshold Vth1, logic COMP1 flips resumes operation. long over-current condition exists, will repeat over-current protection sequence.
10.2V
LEVEL SHIFT
PROTECTION
Floating Bias 200V
Floating Input Isolation
IRS20955
Figure Floating Input Structure
Figure Over-Current Protection Timing Chart
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IRS20955(S)PbF
Vth1
COMP1
UVLO(VB)
COMP2 Vth2
LEVEL SHIFT
FLOATING INPUT
LEVEL SHIFT
LEVEL SHIFT
FLOATING HIGH SIDE
SIDE
UVLO(VCC) DEAD TIME
Figure Shutdown Functional Block Diagram Designing timing capacitor, used program tRESET tSU. tRESET, amount time that elapses from when enters shutdown mode time when resumes operation. tRESET should long enough avoid over heating MOSFET from repetitive sequence shutting down resuming operation during over-current conditions. most applications, minimum recommended time tRESET 0.1. amount time between powering shutdown mode moment releases shutdown begin normal operation. values chosen tRESET will determine capacitance using given equations:
Protection Control internal protection control block dictates operational mode-normal, shutdown, using input pin. functions expected normal mode. shutdown mode, forces output with respect turn power MOSFETs. provides five functions. Power delay timer Self-reset timer Shutdown input Latched protection configuration Shutdown status output (host I/F) Self Reset Protection putting capacitor between VSS, IRS20955S reset itself after entering shutdown mode.
VREF OCSET
RESET
Figure Self Reset Protection Configuration www.irf.com
where ICSD charge/discharge current supply voltage with respect VSS.
IRS20955(S)PbF
Shutdown Input When VCSD falls below Vth2, IRS20955S begins charge attempt resume operation. Once voltage rises above upper threshold, Vth1, begins operate normally again.
SHUTDOWN
Interfacing with System Controller IRS20955S communicate with external system controller through simple interfacing circuit such shown Figure generic transistor, shown detect sink current during event output shutdown signal external system controller. Another generic transistor, shown then reset internal protection logic pulling voltage below Vth2 minimum Note that configured operate latched OCP. After power sequence, reset signal required release from shutdown mode.
VREF OCSET
Figure Shutdown Input Latched Protection Connecting through less resistor configures over-current protection latch. latch locks shutdown mode after overcurrent detected. external reset switch used bring below lower threshold Vth2 minimum properly reset latch. After power sequence, reset signal required release from shutdown mode.
<10k
RESET
Figure Interfacing with System Controller Programming Trip Level Class audio amplifier, direction load current alternates with audio input signal. over-current condition therefore occur during either positive current cycle negative current cycle. IRS20955 uses RDS(ON) output MOSFETs current sensing resistors. structural constraints high voltage ICs, current sensing implemented differently high side side. measured current exceeds predetermined threshold, block outputs signal protection block shutdown MOSFET protect switching devices.
VREF OCSET
Figure Latched Protection Configuration
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IRS20955(S)PbF
DETECT
HIGH SIDE
LEVEL SHIFT
FLOATING HIGH SIDE
DETECT
LEVEL SHIFT
DEAD TIME
SIDE
OCSET
VREF
Figure Bi-Directional Over-Current Protection Low-side Over-Current Sensing negative load currents, low-side over-current sensing monitors load condition shuts down switching operation load current exceeds preset trip level. Low-side current sensing based measurement across side MOFET during low-side turn order avoid triggering from overshoot, blanking interval inserted after turn disables over-current detection OCSET used program threshold low-side over-current sensing. When measured across low-side MOSFET exceeds voltage OCSET with respect COM, IRS20955S begins sequence described earlier. Since voltage from compared voltage OCSET pin, voltage OCSET determines trip level over-current detection. selecting trip level over-current, voltage OCSET calculated using equation below. VOCSET VDS(LOW SIDE) ITRIP+ RDS(ON) order minimize effect input bias current OCSET pin, select resistor values such that current through voltage divider more. Note: Using VREF generate input OCSET through resistive divider provides improved immunity from fluctuations VCC.
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IRS20955(S)PbF
OCREF 5.1V
0.5mA OCSET
Comparator
IRS20955
Figure Low-Side Over-Current Sensing High-side current sensing based measurement across high-side MOFET during high-side turn through pins order avoid triggering from overshoot, blanking interval inserted after turn disables over-current detection contrast low-side current sensing, threshold which engages protection internally fixed external resistive divider used program higher threshold. external reverse blocking diode, required block high voltages from feeding into while high-side off. forward voltage drop across minimum threshold required high-side over-current protection
VCSH HIGHSIDE
Low-Side Over-Current Setting low-side MOSFET have RDS(ON) current trip level VOCSET given VOCSET ITRIP+ RDS(ON) Choose R4+R5=10 properly load VREF pin.
VOCSET VREF
where VREF Based E-12 series resistor values, choose complete design. general, RDS(ON) positive temperature coefficient that needs considered when setting threshold level. Variations RDS(ON) will affect selection external internal component values. High-Side Over-Current Sensing positive load currents, high-side over-current sensing also monitors load condition shuts down switching operation load current exceeds preset trip level.
where VDS(HIGH SIDE) drain source voltage high-side MOSFET during high-side turn VF(D1) forward drop voltage Since VDS(HIGH SIDE) determined product drain current RDS(ON) high-side MOSFET. VCSH rewritten
VCSH (RDS
Note: reverse blocking diode forward biased resistor when high-side MOSFET
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IRS20955(S)PbF
Comparator
1.2V
IRS20955
Figure Programming High-Side Over-Current Threshold High-Side Over-Current Setting Figure demonstrates typical circuitry used high-side current sensing. following example, over-current protection level trip using MOSFET with RDS(ON) component values calculated using following formula: R3=10
VthOCH
high speed switching diode, more than sufficient. Deadtime Generator Deadtime blanking period inserted between high-side turn low-side turn prevent shoot through. IRS20955S, internal deadtime generation block allows user select optimum deadtime from range preset values. Selecting preset deadtime through DT/SD voltage easily done through external voltage divider. This setting deadtime prevents outside noise from modulating switching timing, which critical audio performances. Determine Optimal Deadtime effective deadtime actual application differs from deadtime specified this datasheet switching fall time, deadtime value this datasheet defined time period between beginning turn-off side switching stage beginning turn-on other side shown Figure fall time MOSFET gate voltage must subtracted from deadtime value datasheet determine effective deadtime Class audio amplifier. (Effective deadtime) (Deadtime datasheet)
where Vth,OCL forward voltage reverse blocking diode VDS@ID=30A voltage drop across high-side MOSFET when MOSFET current Therefore, VDS@ID=30A RDS(ON) Based formulas above,
Choosing Right Reverse Blocking Diode selection appropriate reverse blocking diode used place depends voltage rating speed. effectively block voltages, reverse voltage must higher than voltage difference between reverse recovery time must fast boot strap charging diode. diode such Philips BAV21 www.irf.com
IRS20955(S)PbF
Programming Deadtime
Effective dead time
Dead-time datasheet
Figure Effective Deadtime longer deadtime period required MOSFET with larger gate charge value because longer Although shorter effective deadtime setting beneficial achieving better linearity Class amplifiers, likelihood shoot-through current increases with narrower deadtime settings. Negative values effective deadtime cause excessive heat dissipation MOSFETs, leading potentially serious damage. calculate optimal deadtime given application, fall time both actual circuit need taken into account. addition, variations temperature device parameters could also affect effective deadtime actual circuit. Therefore, minimum effective deadtime recommended avoid shootthrough current over range operating temperatures supply voltages.
IRS20955S selects deadtime from range preset deadtime values based voltage applied pin. internal comparator translates input predetermined deadtime comparing input with internal reference voltages. These internal reference voltages through resistive voltage divider using VCC. relationship between operation mode voltage illustrated Figure16 below.
Dead- time
15nS 25nS 35nS 45nS
0.23 xVcc
0.36 xVcc
0.57 xVcc
Figure Deadtime Table suggests pairs resistor values used voltage divider selecting deadtime. Resistors with tolerance acceptable when using these values.
IRS20955
>0.5mA
Figure External Voltage Divider
Table Recommended Resistor Values Deadtime Selection Deadtime Mode DT/SD Voltage Open 0.46(VCC) 0.29(VCC) Open
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IRS20955(S)PbF
Supplying designed supplied with internal Zener diode clamp. IDD, supply current VDD, estimated 10-9 switching frequency (Dynamic power consumption) (Static) (Zener bias) value used supply should meet following requirement:
10.2
value this charging resistor subject several constraints: minimum value RCHARGE limited leakage current bootstrap voltage supply through RCHARGE, which would limit maximum modulation index system. maximum value RCHARGE limited current charge capability resistor during startup: CHARGE where ICHARGE current through RCHARGE IQBS high side quiescent current.
Furthermore, make sure below maximum zener diode bias current, IDDZ, during static state conditions.
10.2
Figure Boot Strap Supply Pre-charging Start-up Sequence (UVLO) protection control block IRS20955S monitors status ensure that both voltage supplies above UVLO (undervoltage lockout) threshold before beginning normal operation. either below under voltage threshold, disabled shutdown mode until both rise above voltage threshold. Power-down Sequence soon falls below UVLO threshold, protection logic IRS20955S turns shutting power MOSFETs.
IRS20955S
VREF OCSET 10.2V
Figure Supplying Charging Prior Start high-side bootstrap capacitor charged through resistor from positive supply utilizing internal 20.4 Zener diode between This scheme eliminates need charge boot strap capacitor through lowside turn during start-up. www.irf.com
Figure IRS20955 UVLO Timing Chart
20.4V
Example: case where average switching frequency kHz, required 1.18 Based this calculation, power supply voltage would require less.
IQBC
IQBS
20.4V
IRS20955(S)PbF
PMID PZDD PLDD
Power Supply Decoupling IRS20955S contains analog circuitry, careful attention must given decoupling power supplies proper operation. Ceramic capacitors more should placed close power supply pins board. Please refer application note AN-978 general design considerations high voltage gate driver Negative Bias Clamping below when negative supply missing dual supply configuration. this case, excessive negative voltage with respect could damage IRS20955S. Having diode clamp potential negative biases recommended protect standard recovery diode with current rating such 1N4002 sufficient this purpose.
VREF Negative Clamping Diode OCSET
where PZDD power dissipation from internal Zener diode clamping PLDD power dissipation from internal logic circuitry V+BUS positive voltage feeding resistor feeding from V+BUS *For obtaining value RDD, refer section "Supplying VDD." PLSM: Power Dissipation Input Level Shifter PLSM VSS,BIAS where switching frequency VSS,BIAS bias voltage with respect
PLOW: Power Dissipation Low-Side
-Vbus
Figure Negative Clamping Junction Temperature Estimation power dissipation IRS20955S dominated following items: PMID: Power dissipation floating input logic protection circuitry PLSM: Power dissipation input level shifter PLOW: Power dissipation low-side PLSH: Power dissipation high-side level shifter PHIGH: Power dissipation high-side PMID: Power Dissipation Floating Input Logic Protection Circuitry power dissipation floating input section given
power dissipation low-side comes from losses logic circuitry losses driving
PLOW PLDD (int) where PLDD power dissipation from internal logic circuitry
power dissipation from gate drive stage output impedance typically IRS20955S Rg(int) internal gate resistance side MOSFET driver, typically IRS20955S external gate resistance side MOSFET total gate charge side MOSFET
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IRS20955(S)PbF
PLSH: Power Dissipation High-Side Level Shifter PLSH VBUS where switching frequency VBUS difference between positive voltage negative voltage Total power dissipation, given
PMID PLSM PLOW PHSM PHIGH
Given Rth,JA, thermal resistance between ambient junction temperature, junction temperature, calculated from formula provided below.
PHIGH: Power Dissipation High-side power dissipation high-side comes from losses logic circuitry losses driving
PHIGH PLDD (int) where
PLDD power dissipation from internal logic circuitry power dissipation from gate drive stage equivalent output impedance typically IRS20955S Rg(int) internal gate resistance highside MOSFET driver, typically IRS20955S external gate resistance high-side MOSFET total gate charge high- side MOSFET
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IRS20955(S)PbF
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5W-1982 CONTROLLING DIMENSION. MILLIMETER DIMENSIONS SHOWN MILLIMETER [INCHES] OUTLINE CONFORMS JEDEC OUTLINE MS-012AC DIMENSION LENGTH LEAD SOLDERING SUBSTRATE DIMENSION DOES INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL EXCEED 0.15 [.006]
16-Lead SOIC (narrow body)
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IRS20955(S)PbF
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 7.90 8.10 3.90 4.10 15.70 16.30 7.40 7.60 6.40 6.60 10.20 10.40 1.50 1.50 1.60
16SOICN Imperial 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 0.059 0.062
REEL DIMENSIONS 16SOICN Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 22.40 0.881 18.50 21.10 0.728 0.830 16.40 18.40 0.645 0.724
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IRS20955(S)PbF
ORDER INFORMATION
16-Lead SOIC IRS20955SPbF 16-Lead SOIC Tape Reel IRS20955STRPbF
SO-16 package MSL3 qualified. This product been designed qualified industrial level. Qualification standards found IR's Site http://www.irf.com/
WORLD HEADQUARTERS: Kansas St., Segundo, California 90245 Tel: (310) 252-7105 Data specifications subject change without notice 08/02/2007
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