IDT70V5388/78 True four-ported memory cells which allow simultane

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3.3V 64/32K SYNCHRONOUS FOURPORTSTATIC
IDT70V5388/78
True four-ported memory cells which allow simultaneous access same memory location Synchronous Pipelined device 64/32K organization Pipelined output mode allows fast 200MHz operation High Bandwidth Gbps (200MHz bits wide ports) LVTTL interface High-speed clock data access 3.0ns (max.) 3.3V operating power Interrupt flags message passing Width depth expansion capabilities Counter readback address lines
R/WP1
UBP1 CE0P1 CE1P1 LBP1 OEP1
Counter wrap-around control Internal mask register controls counter wrap-around Counter-Interrupt flags indicate wrap-around Mask register readback address lines Global Master reset ports Dual Chip Enables ports easy depth expansion Separate upper-word lower-word controls ports 272-BGA package (27mm 27mm 1.27mm ball pitch) 256-BGA package (17mm 17mm 1.0mm ball pitch) Commercial Industrial temperature ranges JTAG boundary scan MBIST (Memory Built-In Self Test) controller Green parts available, ordering information
Port Logic Block Diagram(2)
I/O9P1 I/O17P1 I/O0P1 I/O8P1
Port Control
TRST
CLKMBIST JTAG Controller MBIST
Addr. Read Back
Port Readback Register
MRST
A0P1 A15P1(1)
CNTRDP1 MKRDP1 MKLDP1 CNTINCP1 CNTLDP1 CNTRSTP1 CLKP1 MRST CNTINT
Port Mask Register Priority Decision Logic Port Counter/ Address Register Port Address Decode
64KX18 Memory Array
R/WP1 CE0P1 CE1P1
Port Interrupt Logic
INTP1
MRST NOTE: A15x IDT70V5378. Port Port Port Logic Blocks similar Port Logic Blocks.
5649
JANUARY 2006
DSC-5649/4
©2006 Integrated Device Technology, Inc.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Description
IDT70V5388/78 high-speed 64/32Kx18 synchronous FourPort RAM. memory array utilizes FourPort memory cells allow simultaneous access address from four ports. Registers control, data, address inputs provide minimal setup hold times. timing latitude provided this approach allows systems designed with very short cycle times. With input data register integrated burst counters, 70V5388/78 been optimized applications having unidirectional bi-directional data flow bursts. automatic power down feature, controlled CE1, permits on-chip circuitry each port enter very standby power mode. IDT70V5388/78 provides wide range functions specially designed facilitate system operations. These include full-boundary, maskable address counters with associated interrupts each port, mailbox interrupt flags each port facilitate inter-port communications, Memory Built-In Self-Test (MBIST), JTAG support asynchronous Master Reset simplify device initialization. addition, address lines have been pins, permit support CNTRD (the ability output current value internal address counter address lines) MKRD (the ability output current value counter mask register). specific details device operation, please refer Functional Description subsequent explanatory sections, beginning page
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Configuration(4)
70V5388/78BG BG-272(2) 272-Pin View(3)
09/25/02
I/O17 A15(1) A15(1) I/O8
I/O15 I/O16
I/O13 I/O14
I/O11 I/O12
I/O9 I/O10 I/O15
I/O16 I/O17
I/O14 I/O13
I/O12 I/O11 I/O9
I/O10 I/O10 I/O12 I/O11 I/O9
I/O14 I/O13 I/O16 I/O17 I/O9 I/O10 I/O15 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 A15(1)
MKRD CNTRD
CNTINT CNTINC
CNTRD MKRD
CNTINT CNTINC
MKLD CNTLD
CNTRST
CNTLD MKLD
GND(5)
GND(5) GND(5) GND(5)
CNTRST
CNTRST
CNTRST
A15(1) I/O8
MKLD CNTLD
CNTINC CNTINT
CNTLD MKLD
CNTINC CNTINT
MKRD CNTRD I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O6 I/O1 I/O0 I/O0 I/O2 I/O3 I/O0 I/O2 I/O3 I/O6 I/O1 I/O0 I/O3 I/O2
CNTRD MKRD I/O5 I/O4 I/O7 I/O6
I/O8 I/O7
TRST
I/O4 I/O5
I/O8 I/O7
I/O4 I/O5
MRST
CLKMBIST
I/O1
I/O1
5649
NOTES: IDT70V5378. This package code used reference package diagram. This text does indicate orientation actual part marking. Package body approximately 27mm 27mm 2.33mm, with 1.27mm ball-pitch. Central balls thermal dissipation only. They connected device VSS.
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Configuration(2)
70V5388/78BC BC-256(3) 256-Pin BGA(4) View
09/25/02
I/O16
I/O13
I/O9
I/O14
I/O10
I/O9
I/O12
I/O16
I/O11
I/O15
I/O17
A15(1)
I/O17
I/O14 I/O10
I/O15
I/O11
I/O13 I/O17 I/O12
I/O16
I/O15
I/O12
I/O17 I/O12
I/O9
I/O11
I/O15 I/O10
I/O14
A15(1)
I/O11
I/O16 I/O13
I/O10
I/O14
I/O9
I/O13
CNTRD CNTINC
CNTLD CNTINC CNTRD
CNTLD CNTRST CNTINT
MKLD
CNTRST MKRD
CNTINT MKLD
CNTRST
CNTINT MKRD
I/O6
CNTRST
CNTINT MKLD
CNTRD MKRD CNTINC CNTLD MKLD
CNTLD CNTINC MKRD
CNTRD
I/O2
I/O7
I/O2
TRST MRST
CLKMBIST
I/O5
I/O1
I/O3
I/O7
I/O2
I/O7
I/O3
I/O0
I/O4
I/O8
I/O3
I/O6
A15(1)
I/O8
I/O4
I/O0
I/O5
I/O1
I/O2
I/O6
I/O1
I/O5
I/O7
A15(1)
I/O6
I/O3
I/O8
I/O4
I/O0
I/O1
I/O5
I/O0
I/O4
I/O8
5649
NOTES: A15x IDT70V5378. Package body approximately 17mm 17mm 1.4mm, with 1.0mm ball-pitch. This package code used reference package diagram. This text does indicate orientation actual part-marking.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Definitions
Port A0P1 A15P1(1) I/O0P1 I/O17P1 CLKP1 Port A0P2 A15P2(1) I/O0P2 I/O17P2 CLKP2 Port A0P3 A15P3(1) I/O0P3 I/017P3 CLKP3 Port A0P4 A15P4(1) I/O0P4 I/O17P4 CLKP4 Description Address Inputs. CNTRD MKRD operations, these pins serve outputs internal address counter internal counter mask register respectively. Data Input/Output. Clock Input. maximum clock input rate fMAX. clock signal free running strobed depending system requirements. Master Reset Input. MRST asycnchronous input, affects ports. must asserted (MRST VIL) initial power-up. Master Reset sets internal value address counters zero, sets counter mask registers each port 'unmasked'. also resets output flags mailboxes counter interrupts (INT CNTINT VIH) deselects registered control signals. CE0P2, CE1P2 CE0P3, CE1P3 CE0P4, CE1P4 Chip Enable Inputs. activate port, both signals must asserted their active states (CE0 VIL, VIH). given port disabled either chip enable deasserted (CE0 and/or VIL). Read/Write Enable Input. This signal asserted VIL) order write FourPort memory array, asserted HIGH (R/W VIH) order read from array. Lower Byte Select Input (I/O0 I/O8). Asserting this signal VIL) enables read/write operations lower byte. read operations, this signal used conjunction with order drive output data lower byte data bus. Upper Byte Select Input (I/O9 I/O17). Asserting this signal VIL) enables read/write operations upper byte. read operations, this signal used conjunction with order drive output data upper byte data bus. Output Enable Input. Asserting this signal VIL) enables device drive data pins during read operation. asychronous input. Counter Load Input. Asserting this signal (CNTLD VIL) loads address address lines A15(1)) into internal address counter that port. Counter Increment Input. Asserting this signal (CNTINC VIL) increments internal address counter that port each rising edge clock signal. counter will increment defined counter mask register that port (default mode advance address each clock cycle). Counter Readback Input. When asserted (CNTRD VIL) causes that port output value internal address counter address lines that port. Counter readback independent chip enables that port. port activated (CE0 VIH), during counter readback operation, then data will output data associated with that readback address FourPort memory array (assuming that byte enables output enables also asserted). Truth Table indicates required states other counter controls during this operation. specific operation timing this funcion described detail text. Counter Reset Input. Asserting this signal (CNTRST VIL) resets address counter that port zero. Counter Interrupt Flag Output. This signal asserted (CNTINT VIL) when internal address counter that port 'wraps around' from address [(the counter will increment defined counter mask register that port (default mode advance address each clock cycle)] address min. result counter increment (CNTINT IL). signal goes clock cycle, then automatically resets.
5649
MRST
CE0P1, CE1P1
R/WPI
R/WP2
R/WP3
R/WP4
LBP1
LBP2
LBP3
LBP4
UBP1
UBP2
UBP3
UBP4
OEP1
OEP2
OEP3
OEP4
CNTLDP1
CNTLDP2
CNTLDP3
CNTLDP4
CNTINCP1
CNTINCP2
CNTINCP3
CNTINCP4
CNTRDP1
CNTRDP2
CNTRDP3
CNTRDP4
CNTRSTP1
CNTRSTP2
CNTRSTP3
CNTRSTP4
CNTINTP1
CNTINTP2
CNTINTP3
CNTINTP4
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Definitions (con't.)
Port MKLDP1 Port MKLDP2 Port MKLDP3 Port MKLDP4 Description Counter Mask Register Load Input. Asserting this signal (MKLD VIL) loads address address lines A15(1)) into counter mask register that port. Counter mask register operations described detail text. Counter Mask Register Readback Input. Asserting this signal (MKRD VIL) causes that port output value internal counter mask register address lines A15(1)) that port. Address Counter Counter-Mask Operational Table indicates required states other counter controls during this operation. Counter mask register readback independent chip enables that port. port activated (CE0 VIH) during counter mask register readback operation, then data will output data associated with that address FourPort memory array assuming that byte enables output enables also asserted). specific operation timing this function described detail text. Interrupt Flag Output. FourPort equipped with mailbox functions: each port specific address wthin memory array which, when written other ports, will generate interrupt flag that port. port clears interrupt reading that address. memory location valid address data storage: full 18-bit word stored recall target port other port. mailbox functions associated interrupts described detail text. JTAG Input: Test Mode Select JTAG Input: Test Mode Reset (Intialize Controller reset MBIST Controller) JTAG Input: Test Clock JTAG Input: Test Data Input (serial) JTAG Output: Test Data Output (serial) MBIST Input: MBIST Clock Thermal Grounds (should treated like Core Power Supply (3.3V) Electrical Grounds (0V)
5649
MKRDP1
MKRDP2
MKRDP3
MKRDP4
INTP1
INTP2
INTP3
INTP4
TRST CLKMBIST
NOTE: A15x IDT70V5378.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Truth Table I-Read/Write Enable Control(1,2,3)
Upper Byte I/O9-17 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z Lower Byte I/O0-8 High-Z High-Z High-Z High-Z DOUT High-Z DOUT High-Z MODE Deselected-Power Down Deselected-Power Down Bytes Deselected Write Lower Byte Only Write Upper Byte Only Write Both Bytes Read Lower Byte Only Read Upper Byte Only Read Both Bytes Outputs Disabled
5649
NOTES: VIL, Don't Care. CNTLD, CNTINC, CNTRST VIH. asynchronous input signal.
Truth Table II-Address Counter Mask Control(1,2)
External Address Previous Internal Address Internal Address Used 1(5) CNTLD CNTINC
CNTRST L(3)
MKLD
DI/O(0) DI/O(p) DI/O DI/O(p) Counter Reset Address Counter disabled reused) External Address Used
MODE
L(4)
External Address Blocked-Counter disabled reused)
DI/O(p+1)(5) Counter Enabled-Internal Address generation
5649
NOTES: VIH, VIL, Don't Care. Read write operations controlled appropriate setting R/W, CE0, CNTLD CNTRST independent other memory control signals including address counter advances CNTINC rising edge CLK, regardless other memory control signals including CE0, CE1, counter will increment defined counter mask register that port (default mode advance address each clock cycle).
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Address Counter Counter-Mask Control Operational Table (Any Port)(1,2)
MRST CNTRST MKLD H(3) CNTLD CNTINC CNTRD MKRD Mode MasterReset Reset Load Load Operation Counter/Address Register Reset Mask Register (resets chip reset state definition) Counter/Address Register Reset Load Address Lines into Mask Register Load Address Lines into Counter/Address Register
Increment Counter Increment Readback Readback Hold Readback Counter Address Lines
Readback Mask Register Address Lines Counter Hold
5649
NOTES: "don't care", VIH, VIL. Counter operation mask register operation independent Chip Enable. MKLD will also hold counter. Please refer Truth Table
Recommended Operating Temperature Supply Voltage(1)
Grade Commercial Industrial Ambient Temperature +70OC -40OC +85OC 3.3V 150mV 3.3V 150mV
5649
Recommended Operating Conditions
Symbol Parameter Supply Voltage Ground Input High Voltage (Address, Control Inputs) Input Voltage Min. 3.15 -0.3(1) Typ.
Max. 3.45 150mV
Unit
5649
NOTES: This parameter This "instant case temperature.
NOTES: Undershoot -1.5V pulse width less than 10ns allowed. VTERM must exceed 150mV.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) TBIAS(3) TSTG IOUT Rating Terminal Voltage with Respect Temperature Under Bias Storage Temperature Junction Temperature Output Current Commercial Industrial -0.5 +4.6 +125 +150 +150 Unit
Capacitance(1)
Symbol COUT(3)
+25°C, 1.0MHZ)
Parameter Input Capacitance Output Capacitance Conditions(2) VOUT Max. 10.5 Unit
5623
NOTES: These parameters determined device characterization, production tested. references interpolated capacitance when input output switch from from COUT also references CI/O.
5649
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. VTERM must exceed 150mV more than cycle time maximum, limited 20mA period VTERM 150mV. Ambient Temperature under Bias. conditions. Chip Deselected.
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VDD 3.3V 150mV)
70V5388/78S Symbol |ILI| |ILI| |ILO Parameter Input Leakage Current
(1,2)
Test Conditions Max., Max., VOUT Outputs tri-state mode +4mA, Min. -4mA, Min.
Min.
Max.
Unit
5649
JTAG Input Leakage Current Output Leakage Current Output Voltage Output High Voltage
NOTE: 2.0V leakages undefined. Applicable only TMS, TRST inputs.
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(3) (VDD 3.3V 150mV)
70V5388/78S200 70V5388/78S166 70V5388/78S133 70V5388/78S100 Com'l Only Com'l Com'l Com'l Symbol Parameter Dynamic Operating Current (All Ports Active) Standby Current (All Ports Level Inputs) Standby Current (One Port Level Inputs) Test Condition CE4(5) VIL, Outputs Disabled, fMAX(1) CE4(5) VIH, Outputs Disabled, fMAX(1) VIH(5) Active Port, Outputs Disabled, f=fMAX(1) Version COM'L COM'L COM'L COM'L COM'L Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
5649
ISB1
ISB2
ISB3
Full Standby Current (All Ports Outputs Disabled, Ports CMOS CE(5) 0.2V, 0.2V Level Inputs) 0.2V, 0(2) Full Standby Current (One Port CMOS Level Inputs) 0.2V 0.2V(5) 0.2V 0.2V Active Port, Outputs Disabled, fMAX(1)
ISB4
NOTES: fMAX, address control lines (except Output Enable) cycling maximum frequency clock cycle 1/tCYC, using TEST CONDITIONS" input levels means address, clock, control lines change. Applies only input CMOS level standby. Parameters identical ports. 3.3V, 25°C Typ, production tested. (f=0) 120mA (Typ). means CE0X CE1X means CE0X CE1X 0.2V means CE0X 0.2V CE1X 0.2V 0.2V means CE0X 0.2V CE1X 0.2V represents indicator appropriate port.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Test Conditions (VDDQ 3.3V)
Input Pulse Levels (Address Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V 3.0V 1.5V 1.5V Figure
5649
DATAOUT
1.5V 10pF (Tester)
5649
Figure Output Test Load *(For tHZ, tWZ, tOW)
(Typical,
Capacitance (pF) from Test Load
5649
Figure Typical Output Derating (Lumped Capacitive Load).
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Range (Read Write Cycle Timing) (VDD 3.3V 150mV, +70°C)
70V5388/78S200 Com'l Only Symbol fMAX2 tCYC2 tCH2 tCL2 tSCLD tHCLD tSCINC tHCINC tSCRST tHCRST tSCRD tHCRD tSMLD tHMLD tSMRD tHMRD tOLZ (1,5) tOHZ (1,5) tCD2 tCA2 tCM2 tCKHZ tCKLZ
(1,2,5)
70V5388/78S166 Com'l Min.
70V5388/78S133 Com'l Min.
70V5388/78S100 Com'l Min.
Parameter Maximum Frequency Clock Cycle Time Clock HIGH Time Clock Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Setup Time Hold Time Input Data Setup Time Input Data Hold Time Byte Setup Time Byte Hold Time CNTLD Setup Time CNTLD Hold Time CNTINC Setup Time CNTINC Hold Time CNTRST Setup Time CNTRST Hold Time CNTRD Setup Time CNTRD Hold Time MKLD Setup Time MKLD Hold Time MKRD Setup Time MKRD Hold Time Output Enable Data Valid LOW-Z HIGH-Z Clock Data Valid Clock Counter Address Readback Valid Clock Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH Output HIGH-Z Clock HIGH Output LOW-Z
Min.
Max.
Max.
Max.
Max.
Unit
(1,2,5)
5649
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Range (Read Write Cycle Timing) (VDD 3.3V 150mV, +70°C)
70V5388/78S200 Com'l Only Symbol Interrupt Timing tSINT tRINT tSCINT tRCINT Clock Time Clock Reset Time Clock CNTINT Time Clock CNTINT Reset Time
70V5388/78S166 Com'l Min. Max.
70V5388/78S133 Com'l Min. Max.
70V5388/78S100 Com'l Min. Max. Unit
Parameter
Min.
Max.
Master Reset Timing tRSR tROF Master Reset Pulse Width Master Reset Recovery Time Master Reset Output Flags Reset Time
Port Port Delays tCCS JTAG Timing(4) fJTAG tTCYC tJCD tJDC fBIST tJRST tJRSR Maximum JTAG Controller Frequency Clock Cycle Time Clock High Time Clock Time JTAG Setup JTAG Hold Clock Valid (JTAG Data Output) Clock Invalid (JTAG Data Output Hold) Maximum CLKMBIST Frequency CLKMBIST High Time CLKMBIST Time JTAG Reset JTAG Reset Recovery
Clock-to-Clock Setup Time
5649
NOTES: Guaranteed design (not production tested). Valid both data address outputs. This parameter defines time necessary port complete write have valid data available that address access from other port(s). Attempting read data before elapsed will result output indeterminate data. JTAG operations occur speed (10MHz). base device speed specified this datasheet. Transition measured from High-impedance voltage with Output Test Load (Figure
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Switching Waveforms Timing Waveform Read Cycle(2)
tCYC2 tCH2
tCL2
Latency) tCD2 tCKLZ
ADDRESS
DATAOUT
tOLZ
tOHZ
NOTES: asynchronously controlled; other inputs synchronous rising clock edge. 5649 CNTLD VIL, CNTINC CNTRST VIH. output disabled (High-Impedance state) VIH, following next rising edge clock. Refer Truth Table Addresses have accessed sequentially since CNTLD constantly loads address rising edge CLK; numbers reference only. HIGH, then appropriate Byte DATAOUT would disabled (High-Impedance state).
Timing Waveform Multi-Device Read(1,2)
tCH2 ADDRESS(B1)
CE0(B1)
tCYC2 tCL2
tCD2 tCD2 tCKLZ tCKHZ tCD2 tCKHZ
DATAOUT(B1) ADDRESS(B2)
CE0(B2)
tCD2 tCKHZ tCKLZ tCKLZ
5649
tCD2
DATAOUT(B2)
NOTES: Represents Device Represents Device Each Device consists IDT70V5388/78 this waveform, setup depth expansion this example. ADDRESS(B1) ADDRESS(B2) this situation. CNTLD VIL; 1(B1), CE1(B2) R/W, CNTINC, CNTRST VIH.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Timing Waveform Port Write Port Read(1,2,4)
CLK"A" R/W"A" ADDRESS"A"
MATCH
MATCH
DATAIN"A"
VALID
tCCS(3) CLK"B" tCD2 R/W"B" ADDRESS"B"
MATCH
MATCH
DATAOUT"B"
VALID
5649 NOTES: CNTLD VIL; CE1, CNTINC, CNTRST, MRST, MKLD, MKRD CNTRD VIH. Port "B", which being read from. Port "A", which being written minimum specified, then data from Port read valid until following Port clock cycle (ie, time from write valid read opposite port will tCCS tCYC2 tCD2). tCCS minimum, then data from Port read available first Port clock cycle (ie, time from write valid read opposite port will tCYC2 tCD2). timing same ports. Port port. Port other port device.
Timing Waveform Read-to-Write-to-Read VIL)(2)
tCYC2 tCH2 tCL2
ADDRESS
DATAIN
tCD2
tCKHZ tCKLZ
tCD2 READ
5649
DATAOUT READ
WRITE
NOTES: Output state (High, Low, High-impedance) determined previous cycle control signals. CNTLD VIL; CNTINC, CNTRST, MRST, MKLD, MKRD CNTRD VIH. "NOP" Operation". Addresses have accessed sequentially since CNTLD constantly loads address rising edge CLK; numbers reference only. "NOP" Operation." Data memory selected address corrupted should re-written guarantee data integrity.
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Timing Waveform Read-to-Write-to-Read Controlled)(2)
tCH2
tCYC2 tCL2
ADDRESS
DATAIN
tCD2 tOHZ
tCD2 tCKLZ
DATAOUT
READ
WRITE
READ
5649
NOTES: Output state (High, Low, High-impedance) determined previous cycle control signals. CNTLD VIL; CNTINC, CNTRST, MRST, MKLD, MKRD CNTRD VIH. Addresses have accessed sequentially since CNTLD constantly loads address rising edge CLK; numbers reference only. This timing does meet requirements fastest speed grade. This waveform indicates logically could done timing allows.
Timing Waveform Read with Address Counter Advance(1)
tCH2 ADDRESS tCYC2 tCL2
tSCLD tHCLD
CNTLD
tSCLD tHCLD
CNTINC
tCD2 DATAOUT 1(2) READ EXTERNAL ADDRESS READ WITH COUNTER
tSCLD tHCLD 2(2)
COUNTER HOLD
READ WITH COUNTER
5649 NOTES: CE0, VIL; CE1, CNTRST, MRST, MKLD, MKRD CNTRD VIH. there address change CNTLD (loading address) CNTINC (advancing address), i.e. CNTLD CNTINC then data output remains constant subsequent clocks.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Timing Waveform Write with Address Counter Advance(1)
tCH2 ADDRESS tCYC2 tCL2
INTERNAL(3) ADDRESS tSCLD tHCLD
CNTLD
An(7)
tSCINC tHCINC
CNTINC
DATAIN WRITE EXTERNAL ADDRESS
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5649
Timing Waveform Counter Reset(2)
tCH2
tCYC2 tCL2
ADDRESS INTERNAL(3) ADDRESS
CNTLD
tSCLD tHCLD
CNTINC
tSCRST tHCRST
CNTRST
tSCINC tHCINC
DATAIN
DATAOUT EXECUTE CNTRST
WRITE READ READ READ ADDRESS
READ ADDRESS
5649
NOTES: VIL; CNTRST, MRST, MKLD, MKRD, CNTRD vIH. VIL; VIH. "Internal Address" equal "External Address" when CNTLD equals counter value when CNTLD VIH. Addresses have accessed sequentially since CNTLD constantly loads address rising edge CLK; numbers reference only. Output state (High, Low, High-impedance) determined previous cycle control signals. dead cycle exists during CNTRST operation. READ WRITE cycle coincidental with counter CNTRST cycle: Address 0000h will accessed. Extra cycles shown here simply clarification. more information CNTRST function refer Truth Table CNTINC advances Internal Address from `An' +1'. transition shown indicates time required counter advance. +1'Address written during this cycle.
6.42
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Timing Waveform Master Reset(1)
tCYC2 tCH2 tCL2
MRST tROF ADDRESS/ DATA LINES
tRSR tS(2)
OTHER INPUTS
INACTIVE
ACTIVE
CNTINT
5649
NOTES: Master Reset will reset device. JTAG MBIST reset please refer JTAG Timing specification. set-up time required input control signals.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Timing Waveform Load Read Address Counter(1,2,3)
tCYC2 tCH2 tCL2 tSCLD CNTLD CNTINC tSCINC CNTRD INTERNAL ADDRESS tHCINC tSCRD tHCRD tHCLD tCKLZ tCA2 An+2(4) tCKHZ
tCD2
An+1
An+2
An+2
An+2
DATAOUT
Qx-1
LOAD EXTERNAL ADDRESS
Qn+1
Qn+2
READ INTERNAL ADDRESS
Qn+2
Qn+2
READ DATA WITH COUNTER
5649
NOTES: CE0, VIL; CE1, R/W, CNTRST, MRST, MKLD MKRD VIH. Address output mode. Host must driving address after time tCKLZ next clock cycle. Address input mode. Host drive address after tCKHZ. This value address counter being read address lines.
Timing Waveform Load Read Mask Register(1,2,3,4)
tCYC2 tCH2 tCL2 tSMLD MKLD tSMRD MKRD MASK INTERNAL VALUE
LOAD MASK REGISTER VALUE
tHMLD
tCKLZ
tCA2 An(4)
tCKHZ
tHMLD
READ MASK-REGISTER VALUE
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NOTES: Address output mode. Host must driving address after time tCKLZ next clock cycle. Address input mode. Host drive address after tCKHZ. CE0, VIL; CE1, R/W, CNTRST, MRST, CNTLD, CNTRD CNTINC This value mask register being read address lines.
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IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
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Timing Waveform Counter Interrupt(1,3)
tCYC2 tCH2 tCL2 EXTERNAL ADDRESS MKLD tSCLD CNTLD tSCINC CNTINC COUNTER INTERNAL ADDRESS
007Fh
xx7Dh
tSMLD
tHMLD tHCLD tHCINC
xx7Dh
xx7Eh
xx7Fh
xx00h
xx00h
tSCINT
tRCINT
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CNTINT
Timing Waveform Mailbox Interrupt Timing(4,6)
tCYC2 tCH2 tCL2
CLKP1
PORT-1 ADDRESS INTP2
FFFE
tSINT
An+1 tRINT
An+2
An+3
tCYC2 tCH2 tCL2
CLKP2
PORT-2 ADDRESS
Am+1
FFFE
Am+3
Am+4
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NOTES: CE0, VIL; CE1, R/W, CNTRST, MRST, CNTRD MKRD VIH. CNTINT always driven. CNTINT goes counter address increments (via CNTINC VIL) past maximum value programmed into mask register 'wraps around' xx00h CNTINT stays cycle, then resets. this example, mask register programmed xx7Fh ('x' indicates "Don't Care"). Counter Mask Register operations detailed page CNTRST, MRST, CNTRD CNTINC MKRD MKLD mailbox interrupt circuitry relies state chip enables, read/write signal, address location generate clear interrupts appropriate other control signals such "Don't Care". Please refer Truth Table (page further explanation. Address FFFEh mailbox location Port IDT70V5388. Refer Truth Table mailbox location other Ports (page 22). Port configured write operation (setting interrupt) this example, Port configured read operation (clearing interrupt). Ports used example: port interrupt other port operations Truth Table (page 22). interrupt flag always with respect rising edge writing port's clock, cleared with respect rising edge reading port's clock.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
Functional Description
IDT70V5388/78 provides true synchronous FourPort Static interface. Registered inputs provide minimal set-up hold times address, data, critical control inputs. internal registers clocked rising edge clock signal, however, self-timed internal write pulse independent HIGH transition clock signal duration input signal. This done order offer fastest possible cycle times highest data throughput. MHz, device supports cycle time provides pipelined data output from clock edge data valid. Four ports operating MHz, each with width bits, results data throughput rate nearly Gbps. true synchronous device, IDT70V5388/78 provides flexibility clock each port independently: ports different frequencies and/or synchronization with each other. true FourPort device, IDT70V5388/78 capable performing simultaneous reads from ports same address location. Care should taken when attempting write read address locations simultaneously: timing diagrams depict critical parameter tCCS, which determines amount time needed ensure that write successfully been completed valid data available output. Violation tCCS produce indeterminate data read. more ports attempting write same address location simultaneously will result indeterminate data recorded that address. Each port equipped with dual chip enables, CE1. HIGH clock cycle port will power down internal circuitry that port order reduce static power consumption. multiple chip enables also allow easier banking multiple IDT70V5388/78s depth expansion configurations. cycle required with chip enables reasserted reactivate outputs.
Depth Width Expansion
IDT70V5388/78 features dual chip enables (refer Truth Table order facilitate rapid simple depth expansion with requirements external logic. Figure illustrates control various chip enables order expand devices depth. IDT70V5388/78 also used applications requiring expanded width, indicated Figure Through combining control signals, devices grouped necessary accommodate applications requiring 36-bits wider.
A16/A15(1)
IDT70V5388/78
IDT70V5388/78
Control Inputs
Control Inputs
IDT70V5388/78
IDT70V5388/78
R/W, CLK, CNTLD, CNTRST, CNTINC
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Control Inputs
Control Inputs
Figure Depth Width Expansion with IDT70V5388/78 NOTE: IDT70V5388, IDT70V5378.
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IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
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Mailbox Interrupts
IDT70V5388/78 supports mailbox interrupts, facilitating communication among devices attached each port. user chooses interrupt function, then each upper four address locations memory array assigned mailbox ports: FFFFh (7FFFh IDT70V5378) mailbox Port FFFEh (7FFEh IDT70V5378) mailbox Port FFFDh (7FFDh IDT70V5378) mailbox Port FFFCh (7FFCh IDT70V5378) mailbox Port Truth Table details operation mailbox interrupt functions. given port's interrupt (i.e., goes LOW) whenever other port device writes given port's address. example, Port will Port Port Port write FFFFh (7FFFh IDT70V5378). will relation clock writing port (see also Mailbox Interrupt Timing waveform page 20). port writes mailbox, interrupt generated. mailbox location valid memory address: user store 18-bit data word that location retrieval target port. event that more ports attempt interrupt same port same time, interrupt signal will LOW, data actually stored that location will indeterminate. actual interrupt generated result evaluating state address pins, chip enables, pin: user wishes interrupt specific port without changing data stored that port's mailbox, possible disabling byte enables during that write cycle. Once gone specific port, that port reset reading assigned mailbox. case Port would clear signal reading FFFFh (7FFFh IDT70V5378). stated previously, interrupt operation executes based state address pins, chip enables, pin: possible clear interrupt asserting read appropriate location while keeping output enable (OE) byte enables deasserted, avoid having drive data bus. reset, goes HIGH again, relation reading port's clock signal.
Master Reset
IDT70V5388/78 equipped with asynchronous Master Reset input, which asserted independently clock inputs will take effect Master Reset timing waveform page Master Reset sets internal value address counters zero, sets counter mask register each port ones (i.e., completely unmasked). also resets mailbox interrupts counter interrupts HIGH (i.e., non-asserted) sets registered control signals deselected state. Master Reset operation must performed after power-up, order initialize various registers device known state. Master Reset will reset device. JTAG MBIST reset please refer JTAG Section page
Truth Table III-Mailbox Interrupt Flag Operations
Port 1(1,2)
A15-A 0(4) FFFF FFFE FFFD FFFC
Port 2(1,2)
A15-A 0(4) FFFF FFFE FFFD FFFC
Port 3(1,2)
A15-A 0(4) FFFF FFFE FFFD FFFC
Port 4(1,2)
A15-A 0(4) FFFF FFFE FFFD FFFC Function Port Flag(3) Reset Port Flag Port Flag(3) Reset Port Flag Port Flag(3) Reset Port Flag Port Flag(3) Reset Port Flag
5649 NOTES: status "Don't Care" interrupt logic circuitry. desirable reset interrupt flag given port while keeping tri-state condition, then this accomplished setting while read access asserted appropriate address location. status controls "Don't Care" interrupt circuitry. desirable interrupt flag specific port without overwriting data value already stored mailbox location, then this accomplished setting during write access that specific mailbox. Similarly, desirable reset interrupt flag given port while keeping tri-state condition, then this accomplished setting while read access asserted appropriate address location. interrupt specific port other three ports. appropriate control states other three ports depicted above. event that more ports attempt same interrupt flag simultaneously valid data write, data stored mailbox location will indeterminate. IDT70V5378, therefore Mailbox Interrupt Addresses 7FFF, 7FFE, 7FFD 7FFC. Address comparison will
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
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Address Counter Control Operations
Each port IDT70V5388/78 equipped with internal address counter, ease process bursting data into device. Truth Table depicts specific operation counter functions, include order priority among signals. counter controls independent chip enables. device supports ability load address value each access, load address value given clock cycle CNTLD control then allow counter increase that value preset increments each successive clock CNTINC control (see also Counter Mask Operations section that follows). counter suspended clock cycle disabling CNTINC, reset zero clock cycle asserting CNTRST control. CNTRST only affects address value stored counter: effect counter mask register. When counter reaches maximum value array (i.e., address FFFFh IDT70V5388 address 7FFFh IDT70V5378) reaches highest value permitted Counter Mask Register, then `wraps around' beginning array. When Address reached counter increment (i.e., result external address load), then CNTINT signal that port driven clock cycle, automatically resetting next cycle. When CNTRD control asserted, IDT70V5388/78 will output current address stored internal counter that port noted Load Read Address Counter timing waveform page address will output address lines. During this output, data I/Os will driven accordance with settings chip enables, byte enables, output enable that port: device does automatically tri-state these pins during address readback operation.
CNTRD MKRD
Read Back Register
Addr. Read Back
MKLD
Address (I/O)
Mask Register
Memory Array
CNTLD CNTINC CNTRST
Counter/ Address Register
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Figure Logic Block Diagram Read Back Operations
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Counter-Mask Register
CNTINT
STEP Load Counter-Mask Register
A15(2)A14
Counter Address
Masked Address STEP Load Address Counter
A15(2)
STEP
Address Register
A15(2)A14
STEP
Address Register
A15(2)A14
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Figure Programmable Counter-Mask Register Operation
NOTE: "X's" this diagram represent upper bits counter. IDT70V5378.
internal address counter each port associated Counter Mask Register that allows configuration internal address counter that port. Truth Table groups operations address counter with those counter mask register, include Master Reset applicable readback operations. Each mask register controls corresponding internal address counter: writing mask register allows that increment response CNTINC, while writing masks (i.e., locks whatever value loaded CNTLD). mask register extremely flexible: every controlled independently every other bit. counter simply concatenates those bits that have been masked, giving user great selectivity determining which portions memory array available particular port burst operations. Figure illustrates operation Counter Mask Register simply constraining port selected portion array, specifically addresses 0000h 00FFh. step one, mask register loaded with 00FFh MKLD (see also Load Read Mask Register timing waveform page 19). step two, starting address 00FD asserted start point burst, CNTINC control enabled. Step three indicates address counter incrementing 00FFh. step four, internal counter determines that address values greater than 00FFh have been masked, increments past this `max' value 0000h. result reaching 0000h CNTINC
operation, CNTINT output this port automatically triggered will clock cycle then reset. example depicted Figure very simple one: also possible mask non-contiguous bits, such loading 5555h mask register. stated previously, address counter simply concatenates bits that have been masked continues increment those bits accordance with CNTINC control: this fashion, mask register 5555h start address 0007h asserted CNTLD, next value counter will increment response CNTINC control 0012h, then 0013h, then 0016h, etc. Besides supporting precise control which portions array available particular port burst operations, independent control mask register bits also provides excellent flexibility determining value which counter will increment. example, setting mask register masks from counter operation, effectively configuring that port count increments two. This very useful configuring ports work combination, effectively creating single 36-bit port. Thus, Port configured count starting even addresses (the start point asserted CNTLD), Port configured count starting addresses (again CNTLD). ports together will operate 36-bit data words, storing half each word even-numbered address, other half odd-numbered address. Setting bits mask register given port configures that port count
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
Industrial Commercial Temperature Ranges
increments four: masking bits configures that port count increments eight, ability increments which counters will advance gives user ability interleave memory operations among ports, minimizing concerns that given address might written more than port given point time operation that would have indeterminate results).
JTAG Support
IDT70V5388/78 provides serial boundary scan test access port JTAG tables starting page provide specific details JTAG implementation this device. IDT70V5388/78 executes JTAG test logic reset upon power-up. This power-up reset will initialize controller MBIST controller. most power environments further action required. However, user concern about system's voltage states during power-up, then user optional TRST input part board's power reset sequence. TRST also provides alternate means resetting JTAG test logic when required, available external JTAG controllers asynchronous reset signal. user does plan rely optional TRST pin, wants JTAG functionality, TRST should either tied HIGH (preferred implementation) left floating. JTAG operations desired, user number options disabling JTAG functions. would simply LOW, leaving other JTAG pins floating (alternatively, could tied HIGH). Since device executes JTAG reset upon power-up: with tied LOW, further clocking will occur JTAG operations will take place. Alternatively, user TRST (either lieu addition tying LOW) will locked reset condition, blocking JTAG operations.
while indicates that memory array passed. rest contains total number failed read cycles entire MBIST sequence. IDT70V5388/78 MBIST function been supplemented with ability user force failure report from device. This allows user flexibility validating MBIST function itself, verifying that device able report faults well passing results. modes operation, normal MBIST testing forced error reporting, controlled JTAG interface using instruction PROGRAM_MBIST_MODE_SELECT. further detail, please refer System Interface Parameters table page MBIST function executes once RUNBIST instruction input JTAG interface. entire MBIST test will performed with deterministic number cycles depending CLKMBIST frequency. This calculated using following formula:
tCYC
tCYC[CLKMBIST] tCYC[TCK]
SPC, where:
tCYC total number cycles required
MBIST. synchronization padding cycles (typically cycles, accommodate state machine overhead, turnaround cycles, etc.) constant that represents number read write operations required internal MBIST algorithms (14,811,136) both IDT70V5388 IDT70V5378.
Memory Built-In-Test Operations
Go-NoGo Testing IDT70V5388/78 equipped with self-test function that user result single instruction, implemented JTAG interface. multiple FourPort devices used same board, execute MBIST simultaneously, facilitating board checkout. MBIST function executes Go-NoGo test within device, which then captures pass-fail information failure count special register called MBIST Result Register (MRR). Upon completion test, scanned JTAG interface, using internal scan operation. zero (MRR[0]) don't care. (MRR[1])indicates pass/ fail status: indicates some sort failure noted,
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JTAG/BIST Controller Block Diagram
Bypass Register (BYR)
MBIST Mode Select Register (MSR) Selection Circuitry
Instruction Register (IR)
MBIST Result Register (MRR)
Identification Register (IDR)
(MUX)
Boundary Scan Register (BSR)
CLKMBIST
MBIST CONTROLLER
CONTROLLER
TRST
MEMORY CELL
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JTAG Timing Specifications
tTCYC
Device Inputs(1)/ TDI/TMS Device Outputs(2)/ TRST tJRST
NOTES: Device inputs device inputs except TDI, TMS, TRST. Device outputs device outputs except TDO. reset test (JTAG) port without resetting device, must held cycles, TRST must held cycle.
tJDC
tJRSR
tJCD
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Identification Register Definitions
Instruction Field Revision Number (31:28) Device (27:12) JEDEC (11:1) Register Indicator (Bit
NOTE: Device IDT70V5378 0x31E.
Value 0x31D
Description Reserved version number Defines part number Allows unique identification device vendor Indicates presence register
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0x33
Scan Register Sizes
Register Name Instruction (IR) MBIST Mode Select Register (MSR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) MBIST Result (MRR) Size Note
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System Interface Parameters
Instruction EXTEST BYPASS IDCODE
Code 0000 1111 0111 0110 0001
Description Forces contents boundary scan cells onto device outputs(1). Places boundary scan register (BSR) between TDO. Places ypass register (BYR) between TDO. Loads register (IDR) with vendor code places register between TDO. Places bypass register (BYR) etween TDO. Forces device output drivers High-Z state. Places boundary scan register (BSR) between TDO. SAMPLE allows data from device inputs(2) captured boundary scan cells shifted serially through TDO. PRELOAD allows data input serially into boundary scan cells TDI. Places MBIST Mode Register between TDO. value '00' written into this register will allow MBIST standard memory test mode, outputting valid results appropriate MBIST Result Register. value '11' written into MBIST Mode Register will force MBIST Result Register (MRR) report result 'FAIL'., with 8E0000 failed read cycles noted (i.e., content (8E0000h, value MBIST Mode Register guaranteed power-up affected Master reset JTAG reset. Invokes MBIST. Internally updates MBIST result register with Go-NoGo information number issues. PROGRAM_MBIST_MODE_REGISTER must prior executing RUNBIST order ensure valid results. There need repeat this instructio unless mode operation changed: will tain programmed value until overwritten device powered down. Scans partial information. Places MBIST result register (MRR) between TDO. Uses BYR. Forces contents boundary scan cells onto device outputs. Places Bypass ister (BYR) between TDO. Several combinations reserved. codes other than those identified above. Several combinations arePRIVATE (for internal use). codes other than those identified above.
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HIGHZ SAMPLE/PRELOAD
MBIST_MODE_SELECT
1010
RUNBIST
1000
INT_SCAN CLAMP RESERVED PRIVATE
0100 0101 0010, 0011 1001, 1011, 1100, 1101, 1110
NOTES: Device outputs device outputs except TDO. Device inputs device inputs except TDI, TMS, TRST. Boundary Scan Descriptive Language (BSDL) file this device available website (www.idt.com), contacting your local sales representative.
IDT70V5388/78 3.3V 64/32K Synchronous FourPortStatic
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Ordering Information
XXXXX Device Type Power Speed Package Process/ Temperature Range Blank I(1) G(2) Commercial (0°C +70°C) Industrial (-40°C +85°C) Green
272-ball (BG272-1) 256-ball (BC256-1)
Commercial Only Commercial Industrial Commercial Industrial Speed Commercial Industrial
Standard Power
70V5388 1152K (64K 3.3V FourPortRAM 70V5378 576K (32K 3.3V FourPortRAM
5649
NOTES: Contact your local sales office industrial temp. range other speeds, packages powers. Green parts available. specific speeds, packages powers contact your local sales office.
Datasheet Document History
08/20/02: 09/25/02: 08/20/03: 01/31/06: Initial Public Datasheet Added 0.5M Density Datasheet Changed power numbers Electrical Characteristics table Removed Preliminary status Added green availability features Added green indicator ordering information
Page Page Page
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SALES: 800-345-7015 408-284-8200 fax: 408-284-2775 www.idt.com
Tech Support: 408-284-2794 DualPortHelp@idt.com
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IDT70V5388/78 True four-ported memory cells which allow simultane

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