Download

PDF Abstract Text:

AS1506

1 General Description

AS1506
1 General Description
The AS1506 is a linear, 256-tap digital potentiometer specifically designed to replace discrete / mechanical potentiometers and is ideal for applications requiring a low-temperature-coefficient variable resistor, such as low-drift, programmable gain, and amplifier circuit configurations. The device is controlled via a 3-wire SPI-compatible interface and features an internal EEPROM for storing wiper positions. Several device variants are available differentiated by end-to-end resistance as shown in Table 1 (see also Ordering Information on page 16). Table 1. Standard Products Model AS1506-10 AS1506-50 AS1506-100 End-to-End Resistance (k) 10 50 100
2 Key Features
The 3-wire SPI-compatible serial interface allows communication at data rates up to 5MHz.The internal EEPROM stores the last wiper position for initialization during power-up and a low-power standby mode.
3 Applications
The devices are available in an 8-pin TDFN 3x3mm package. The device is ideal for mechanical potentiometer replacement, low-drift programmable gain amplifiers, audio volume control, LCD contrast control, and low-drift programmable filters.
Figure 1. Block Diagram
1 VDD 8-Bit Shift Register 8 8-Bit Latch 8 256 8 HIGH 256-Position Decoder 2 SCLK 3 SDIO 4 CSN SPI Interface PowerOn Reset 8-Bit EEPROM 7 WIPER
AS1506
www.austriamicrosystems.com
Revision 1.01
AS1506
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
8 HIGH
SCLK 2
7 WIPER
AS1506
SDIO 3 6 LOW
Pin Descriptions
Table 2. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 N / A Description 2.7 to 5.5V Supply Voltage. Bypass with a 0.1µF capacitor to GND. Serial Clock Input Serial Data Input / Output Active-Low Chip Select Ground Low Terminal. The voltage at this pin can be greater than or less than the voltage at LOW pin HIGH. Current can flow into or out of this pin. Wiper Terminal WIPER High Terminal. The voltage at this pin can be greater than or less than the voltage HIGH at pin LOW. Current can flow into or out of this pin. Exposed Pad The exposed pad is not internally connected. Leave floating. Pin Name VDD SCLK SDIO CSN GND
www.austriamicrosystems.com
Revision 1.01
AS1506
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter VDD to GND All Other Pins to GND AS1506-10 Maximum Continuous Current into Pins HIGH, WIPER, and LOW Electrostatic Discharge Latch-Up
Min -0.3 -0.3
Max +7.0 VDD + 0.3
Units V V
Comments
AS1506-50 AS1506-100
Thermal Resistance JA Operating Temperature Range Storage Temperature Range Junction Temperature
Package Body Temperature
1. The maximum rating voltage must not be exceeded during Latch-up test of the device.
www.austriamicrosystems.com
Revision 1.01
AS1506
6 Electrical Characteristics
Zero Scale Error DC Performance (Variable Resistor Mode) INL Integral Linearity
Differential Non-Linearity
DC Performance (Resistor Characteristics) RW CW REE Wiper Resistance
pF 12.5 62.5 125 k
Wiper Capacitance End-to-End Resistance
Inputs and Outputs WIPER Voltage Range HIGH Voltage Range LOW Voltage Range VIH VIL ILEAK CIN ICONT Digital Input High Voltage Digital Input Low Voltage
VDD+ 0.3
V 0.6 0.8 500 560 V nA pF µA
Digital Input Leakage Current Digital Input Capacitance Continuous DAC current
www.austriamicrosystems.com
Revision 1.01
AS1506
Wiper Settling Time
Non-Volatile Memory Reliability Data Retention Endurance tBUSY
Years Write Cycles ms
Write Non-Volatile Register Busy Time
Timing Characteristics
www.austriamicrosystems.com
Revision 1.01
AS1506
7 Typical Operating Characteristics
Figure 4. INL vs. TAP Position 10k, Divider Mode
DNL (LSB) .
INL (LSB) .
Tap Position
Figure 5. DNL vs. TAP Position 50k, Divider Mode
Figure 6. INL vs. TAP Position 50k, Divider Mode
DNL (LSB) .
INL (LSB) .
Tap Position
Figure 7. DNL vs. TAP Position 100k, Divider Mode
Figure 8. INL vs. TAP Position 100k, Divider Mode
DNL (LSB) .
INL (LSB) .
Tap Position
www.austriamicrosystems.com
Revision 1.01
AS1506
Figure 9. DNL vs. TAP Position 10k, Varistor Mode
Figure 10. INL vs. TAP Position 10k, Varistor Mode
DNL (LSB) .
INL (LSB) .
Tap Position
Figure 11. DNL vs. TAP Position 50k, Varistor Mode
Figure 12. INL vs. TAP Position 50k, Varistor Mode
DNL (LSB) .
INL (LSB) .
Tap Position
Figure 13. DNL vs. TAP Position 100k, Varistor Mode Mode
Figure 14. INL vs. TAP Position 100k, Varistor
DNL (LSB) .
INL (LSB) .
Tap Position
www.austriamicrosystems.com
Revision 1.01
AS1506
Figure 15. Wiper Resistance vs. TAP 5V
Figure 16. Wiper Resistance vs. TAP 3V
Resistance ()
Resistance ( )
Tap Position
Figure 17. DAC Resistor vs. Temperature
Figure 18. Gain vs. Bandwidth
Resistance (k)
Gain (dB) .
Temperature (°C)
Frequency (kHz)
Figure 19. EEPROM Data Retention vs. Temperature
Data Retension (years)
Temperature (°C)
www.austriamicrosystems.com
Revision 1.01
AS1506
8 Detailed Description
The AS1506 contains a resistor array with 255 resistive elements (tap points), and has a total end-to-end resistance of 10, 50, or 100k (see Ordering Information on page 16). The device provides high, low, and wiper terminals for a standard voltage-divider configuration. Pins HIGH, LOW, and WIPER can be connected in any configuration as long as their voltages fall between GND and VDD. A 3-wire, SPI-compatible serial interface controls movement of the wiper among the 256 tap points. The EEPROM stores the wiper position and recalls the stored wiper position upon power-up. The EEPROM typically holds wiper data for 150 years and up to 10M wiper store cycles.
Analog Circuit
The 256 tap points are accessible to the wiper along the resistor string between pins HIGH and LOW (similar to the end terminals of a mechanical potentiometer). The wiper tap point is selected by programming 8 data bits and a control byte via the 3-wire serial interface (see Programming the Device on page 10). Note: Integrated power-on reset circuitry loads the wiper position from the EEPROM at power-up.
Digital Interface
The AS1506 uses an SPI-compatible 3-wire interface for command settings of the device consisting of two input signals (chip-select - CSN, and data clock - SCLK) and one bi-directional data pin (SDIO). Driving CSN low enables serial interface and the command / data are passed into the device synchronously by each SCLK rising edge. There are 16-bit commands for write data into the wiper register or the non-volatile memory, and 8-bit commands for transferring data between wiper register and non-volatile memory and to read the data stored in the wiper register or non-volatile memory. The 8-bit commands can be implemented in 16-bit command structure alternatively. In this case the first 8 bits shifted through the SPI interface are not significant. The data byte passed at writing commands represents the position of the wiper. After loading the 8- or 16-bit command while CSN is low, the loaded command is executed at the next rising edge of CSN, simultaneously the serial interface is disabled. The CSN signal must be low during the whole serial input stream through the SPI, otherwise data on the SPI interface are corrupted. Note: If the data-in stream does not exactly contain 8 or 16 digits, no command is executed at the rising edge of CSN. Figure 20. Serial Data Timing
CSN tCS0 tCSS SCLK tCL tCH
tCSW tCS1 tCP tCSH
Standby Mode
www.austriamicrosystems.com
Revision 1.01
AS1506
EEPROM (Non-Volatile Register)
Power-Up
The AS1506 contains an integrated power-up circuit. At power up, the data are transferred from the non-volatile memory to the wiper register. The wiper register moves to the stored position. This data transfer takes 5µs after the supply has reached the POR trigger level.
Programming the Device
Write commands (see Table 6) require 16 clock cycles (see Figure 22 on page 12) to clock in the command and data. Copy and Read commands (see Table 6) can use 8 clock cycles to clock in the command (see Figure 21 on page 11) or 16 clock cycles. At 16 clock cycle commands the 8 data bits (D7:D0) are insignificant. Table 6. Command / Data Word Format Command Write Wiper Register Write to Non-Volatile Register Copy Wiper Register to NonVolatile Register Copy Non-Volatile Register to Wiper Register Read Non-Volatile Register Read Wiper Register 1 C7 0 0 0 0 0 0 2 C6 0 0 0 0 0 1 3 C5 0 0 1 1 1 1 4 C4 0 1 0 1 0 0 5 C3 0 0 0 0 1 1 6 C2 0 0 0 0 0 0 7 C1 0 0 0 0 0 0 8 C0 0 0 0 0 0 0 9 D7 D7 D7 10 D6 D6 D6 11 D5 D5 D5 12 D4 D4 D4 13 D3 D3 D3 14 D2 D2 D2 15 D1 D1 D1 16 D0 D0 D0 -
Commands
Write Wiper Register
This is a 16-bit command (see Figure 22 on page 12). The first byte represents the command word starting with the MSB bit of the command, the second byte represents the data written to the wiper register (starting with the MSB). Data 0000 0000 the wiper moves the closest position to LOW, with data 1111 1111 the wiper moves to the closest position to HIGH. Note: At power-up the wiper position stored in the non-volatile memory are automatically loaded into the wiper register, the wiper moves to the related position.
Write to Non-Volatile Register
This is a 16-bit command (see Figure 22 on page 12). The first byte represents the command word starting with the MSB bit of the command, the second byte represents the data written to the non-volatile memory. The wiper position is not changed by this command, since the wiper register is not affected. There is a write non-volatile register time defined in the timing specification, which is required for storing the data in the non-volatile register. During this time the device must not be powered down, otherwise the data stored in the non-volatile register is corrupted.
www.austriamicrosystems.com
Revision 1.01
AS1506
Copy Wiper Register to Non-Volatile Register
This command can be implemented as an 8- or 16-bit command. The data stored in the wiper register are transferred to the non-volatile memory, to keep the data during power-down. There is no automatic trigger of this command during power-down of the device. This command must be triggered before powering down the device. There is a write non-volatile register time defined in the timing specification, which is required for storing the data in the non-volatile register. During this time the device must not be powered down, otherwise the data stored in the non-volatile register is corrupted.
Copy Non-Volatile Register to Wiper Register
This command can be implemented as an 8- or 16-bit command. The data stored in the non-volatile register are transferred to the wiper register, the wiper register moves to the stored position. This command is automatically executed during power up of the system.
Read Non-Volatile Register
The AS1506 features the capability to read the data from the non-volatile register via the SPI interface (see Figure 23 on page 12). This command can be implemented as an 8- or 16-bit command. The SDIO pin is a bi-directional pin. During the CSN low phase of the sequence the SDIO pin is used as input pin to set the command byte. After CSN rising edge the pin SDIO is set as output pin, the data stored in the non-volatile register are read serially, MSB first. The data propagation starts at the second rising edge of SCLK after the rising edge of CSN. CSN must be high during the read operation. With the next falling edge of CSN the SDIO pin is set to an input pin again.
Read Wiper Register
The AS1506 features the capability to read the data from the wiper register via the SPI interface (see Figure 23 on page 12). This command can be implemented as an 8- or 16-bit command. The SDIO pin is a bi-directional pin. During the CSN low phase of the sequence, the SDIO pin is used as input pin to set the command byte. After CSN rising edge the pin SDIO is set as output pin, the data stored in the wiper register are read serially, MSB first. The wiper position is unchanged. The data propagation starts at the second rising edge of SCLK after the rising edge of CSN. CSN must be high during the read operation. With the next falling edge of CSN the SDIO pin is set to an input pin again. Figure 21. 8-Bit Command Word
www.austriamicrosystems.com
Revision 1.01
AS1506
Figure 22. 16-Bit Command / Data Word
Figure 23. 16-Bit Read Command Word
www.austriamicrosystems.com
Revision 1.01
AS1506
9 Application Information
The AS1506 is intended for circuits requiring digitally controlled adjustable resistance, such as LCD contrast control (where voltage biasing adjusts the display contrast), or programmable filters with adjustable gain and / or cutoff frequency.
Programmable Filter
CIN VIN HIGH + VOUT - WIPER R1
(EQ 1) (EQ 2)
AS1506 R3
AS1506 R2
WIPER
Offset Voltage and Gain Adjustment
Connect the AS1506 to an op amp to nullify the offset voltage over the operating temperature range. Install another AS1506 potentiometer in the feedback path to adjust the gain of the op amp (Figure 25). Figure 25. Offset Voltage Adjustment Circuit
AS1506
www.austriamicrosystems.com
Revision 1.01
AS1506
Positive LCD Bias Control
The device can be used in applications where a voltage-divider or variable resistor is used to make an adjustable, positive LCD-bias voltage, such as for the AS1120 LCD Driver. The op amp provides buffering and gain to the resistordivider network made by the potentiometer (Figure 26) or to a fixed resistor and a variable resistor (Figure 27). Figure 26. Positive LCD Bias Control using a Voltage Divider
5V HIGH
30V + VOUT -
AS1506
WIPER LOW
Figure 27. Positive LCD Bias Control using a Variable Resistor
5V 30V + VOUT - HIGH
AS1506
WIPER
Adjustable Voltage Reference
5V VIN OUT HIGH ADJ VOUTREF
WIPER LOW
AS1506
www.austriamicrosystems.com
Revision 1.01
AS1506
10 Package Drawings and Markings
The device is available in an 8-pin TDFN 3x3mm package. Figure 29. 8-pin TDFN 3x3mm Package
aaa C 2x PIN 1 INDEX AREA (D / 2 xE / 2)
PIN 1 INDEX AREA (D / 2 xE / 2) 4 aaa C 2x TOP VIEW
B VIEW
Term inal Tip
Symbol A A1 A3 L1 L2 aaa bbb ccc ddd eee ggg
Min 0.70 0.00
Typ 0.75 0.02 0.20 REF
Max 0.80 0.05 0.15 0.13
Typ 3.00 3.00
SEATING PLANE 7 NX 0.08 C
Notes: Dimensioning and tolerancing conform to ASME Y14.5M-1994. All dimensions are in millimeters, angle is in degrees. N is the total number of terminals. Terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the area indicated. The terminal #1 identifier may be either a mold, embedded metal or mark feature. 5. Dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. 6. ND refers to the maximum number of terminals on D side. 7. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 1. 2. 3. 4.
www.austriamicrosystems.com
Revision 1.01
AS1506
11 Ordering Information
The device is available as the standard products shown in Table 7. Table 7. Ordering Information Model AS1506-BTDT-10 AS1506-BTDT-50 AS1506-BTDT-100 Marking ASMO ASMN ASMM Description 256-Tap, Non-Volatile, SPI Digital Potentiometer 256-Tap, Non-Volatile, SPI Digital Potentiometer 256-Tap, Non-Volatile, SPI Digital Potentiometer End-to-End Resistance 10k 50k 100k Delivery Form Tape and Reel Tape and Reel Tape and Reel Package 8-pin TDFN 3x3mm 8-pin TDFN 3x3mm 8-pin TDFN 3x3mm
www.austriamicrosystems.com
Revision 1.01
AS1506
Data Sheet
Copyrights
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com / contact
www.austriamicrosystems.com
Revision 1.01