5V9885 EVALUATION BOARD USER GUIDE INTRODUCTION BOARD OVERVIEW BO

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5V9885 EVALUATION BOARD USER GUIDE INTRODUCTION BOARD OVERVIEW BO

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5V9885 EVALUATION BOARD USER GUIDE
5V9885 EVALUATION BOARD USER GUIDE
INTRODUCTION BOARD OVERVIEW BOARD VIEW INITIAL POWER-UP CONSIDERATION JUMPER DESCRIPTION DETAILED BOARD SETUP USAGE Voltage Supply Programming Interface Jumper Settings Input/Output Configuration indicators Jitter Performance Testing BOARD SCHEMATICS BOARD LAYOUTS
INTRODUCTION
purpose EV_5V9885 evaluation board demonstrate capability 5V9885 programmable clock generator. This board allows user program device through Serial Port (RS232) JTAG interfaces. also allows user check device performance, such DC/AC specifications, output clock frequencies, jitter. board demonstrates JTAG boundary scan capability combined with ASSET Technology Correlis JTAG emulation board. Board Overview shows block diagram board, while Board View (next page) shows location main components board. Each output connected connector evaluation. Reference Clock input supplied user through connector. Other reference input from external oscillator crystal oscillator. general purpose pins (GIN0-5) connected jumpers. Outputs GOUT0-1 driven indicator.
BOARD OVERVIEW
Panana Plug Power Decoupling (5V) Voltag Regulator (3.3V)
GOUT0
Jumpers JTAG Boundary Scan Testing OUT1 OUT2 OUT3 LVPECL/LVDS mination OUT4 /OUT4 OUT5 /OUT5
XTAL Oscillator Interface Chipset Convert from
GOUT1
RESET
SMAs
XTALIN/
3Ohms 3Ohms 33Ohms
Push Button
SCLK SDAT
CLK_IN
GINx
IDT5
Jumper Connector
3Ohms OUT6
Asset ellis JTAG connectors
JTAG Boundary Scan Test buffer)
logo registered trademark Integrated Device Technology, Inc.
JUNE 2005
6767/7
2005 Integrated Device Technology, Inc.
5V9885 EVALUATION BOARD USER GUIDE
BOARD VIEW
JTAG Interface External Interface
Serial Interface
Power Connector
Reset Button
Internal Jumper
JP12 JP19 Description
IDT5V9885
VDD-2 Reference
5V9885 EVALUATION BOARD USER GUIDE
INITIAL POWER-UP CONSIDERATON
internal programming mode, 5V9885 evaluation board, with logo left position, should have jumpers shown Programming Jumper Setting table. system powered with jumper connections table below, with pull-ups GIN0 GIN1 lines, then PLL0 will default config3.
PROGRAMMING JUMPER SETTING
Jumper name Internal Programming/ Ext. Programming Internal Programming/ Ext. Programming GIN5/CLK_SEL I2C/JTAG GIN3/SUSPEND SHUTDOWN/OE GIN0/SDA/TDI GIN1/SCK/TCK GIN2/TMS GIN4/TRST Position Connected Connected Note Select internal Programming Select internal Programming CLK_SEL I2C/JTAG HIGH SUSPEND GIN4 SDAT, control software interface SCLK, control software interface GIN2 GIN4
JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19
5V9885 EVALUATION BOARD USER GUIDE
GINx pins latch value present power levels these pins deterministic, outputs could switching with wrong configuration. device virtually powers mode2. GIN0 GIN1 pins determine configuration setting PLL0. programming evaluation board used with RS-232 cable, make sure JP2/JP3 left open JP16/JP17 PLL0 power config0. Remove jumpers JP16/JP17 JP2/JP3 internal programming. evaluation board powered with JP13 high latter case, remove jumper JP13). example jumper settings mode with three PLLs powered config0, table below.
JUMPER SETTINGS: CONFIG0 PLL0-2
Jumper name Internal Programming/ Ext. Programming Internal Programming/ Ext. Programming GIN5/CLK_SEL I2C/JTAG GIN3/SUSPEND SHUTDOWN/OE GIN0/SDA/TDI GIN1/SCK/TCK GIN2/TMS GIN4/TRST Position Note Power-up mode Power-up mode GIN5 I2C/JTAG MID, Power-up mode GIN3 GIN4 GIN0 GIN1 GIN2 GIN4
JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19
5V9885 EVALUATION BOARD USER GUIDE
JUMPER DESCRIPTION
Jumper Default Setting Connected Description SN74LVT18512 included JTAG scan chain SN74LVT18512 included JTAG scan chain
JP2-3 Connected
both connected, controller evaluation board will used. both disconnected, external from Programmercan used through Edge connector.
JP4-11 JP12-19
Opened Connected
JTAG Boundary scan jumper JP12 GIN5/CLK_SEL JP13 I2C/JTAG (HIGH programming, JTAG programming) JP14 GIN3/SUSPEND JP15 SHUTDOWN/OE JP16 GIN0/SDA/TDI JP17 GIN1/SCK/TCK JP18 GIN2/TMS JP19 GIN4/TRST
JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19
JP20-21 TP3-4 Opened Connects reference voltage(VDD terminator common voltage GOUT0 GOUT1 Ground Power indicator Programming indicator GOUT0 OFF: GOUT0 GOUT1 OFF: GOUT1
5V9885 EVALUATION BOARD USER GUIDE
DETAILED BOARD SETUP USAGE
VOLTAGE SUPPLY Utilizing full capability board requires only power supply banana jack ground connected banana jack J13. voltage regulator will provide 3.3V power supply IDT5V9885. PROGRAMMING INTERFACE JUMPER SETTINGS board includes RS232 controller, programming EEPROM, frequency crystal oscillator allow user program directly from through RS232 cable (J10). External Port connector (J1) also built facilitate programming register external cable from programmer Kit. addition, JTAG connectors (J11 J14) available JTAG programming option. Programmable Clock software allows user configure parameters 5V9885. spread spectrum, loop-bandwidth, pre-scaler feedbackdivider post-divider slew rate, input crystal load capacitance features configured this user interface. Please refer Programmable Clock Generator application note complete details programming software installation. Programming: Equipment Requirements
Programmable Clock software RS232 cable Programmer cable external port used)
After selecting optimum configuration settings Programmable Clock software, user program 5V9885 this evaluation board using RS232 cable. I2C/JTAG jumper JP13 should HIGH. Jumpers JP16 (GIN0/SDA) JP17 (GIN1/SCK) should removed during programming process. external port used, software will detect programmer, module, 5V9885 board. Jumpers JP2-3 should disconnected. Once programming finished, GINx pins (JP12, JP16-19) should setting desired state mode. That configuration selected, GINx pins "zero". JTAG Programming: Equipment Requirements
Asset Technology Corelis JTAG emulator applicable software JTAG cable
5V9885 evaluation board programmed using either Asset Technology JTAG connector interface Corelis JTAG connector interface. SVF, Intel Hex, Motorola device configuration files generated from Programmable Clock software. Please check with emulation software vendors what file formats their software supports. I2C/ JTAG jumper JP13 should LOW. GIN2/TMS jumper JP18 should floating.
5V9885 EVALUATION BOARD USER GUIDE
INPUT/OUTPUT CONFIGURATION IDT5V9885 dual reference clock inputs. input selection from external user source CLOCK_IN (J15), from crystal XTAL_IN (J16), from external oscillator crystal mounted board clock provided from J16, should removed. clock generated should removed reduce effect J16. When oscillator populated, signal source should connected CLOCK_IN J15. OUT1, have series resistors R69, thus active probes should used testing. These series could changed directly connect scope through connectors. OUT3 resistor series. available connector, resistor which will used load oscilloscope.
SOUT4
OUT4
JP20
VREP1
OUT4_N
SOUT4_N
Figure LVDS/LVPECL Termination
termination configured LVDS/LVPECL LVTTL OUT4 OUT5. shown figure with opened, termination across LVDS, with closed, termination VDD-2V both LVPECL. connectors intended LVTTL outputs OUT4, with LVPECL/LVDS R61, termination resistors removed. LVTTL terminated properly connector with resistor oscilloscope. GIN0-5 I2C/JTAG input configured High through jumpers JP12-19. When mode, should removed. When pressed, reset button will reset RS232 controller. INDICATORS GOUT0 (LED signal indicator loss lock GOUT1 (LED signal indicator loss primary clock Manual Frequency Control Programming modes. JTAG Programming mode, GOUT1 becomes JTAG signal. programming indicator will during programming process. indicates whether power active. JITTER PERFORMANCE TESTING JTAG boundary scan test jumpers (JP4-11) should left unconnected. This there will unnecessary loading output when jitter testing performed.
14.7456MHZ
CARDEDGE_2X5 +3.3V
10PF
10PF
0.1UF POWER
P82B96
0.1UF 16VCC 0.1UF 0.1UF
GIN0/SDA/TDI
RST_N IRQ_N
SDA1 SCL1 SDA2
C1+1 C1-3 0.1UF
RESET
GIN1/SCK/TCK
C2+4 0.1UF
SCL2 SDA3 SCL3
15GND
C2-5
14T1_OUT 7T2_OUT
T1_IN11 T2_IN10 BL233
SDA4 SCL4
Module
YELLOW
13R1_IN 8R2_IN
R1_OUT12 R2_OUT9 MAX3232E_CAE
SN74F04
CONN_DB9_FEM
0.1UF 3.6K
0.1UF
Programming indicator
POWER LM324 1.3K
VREF1
SN74F04
RESET
SN74F04
SW_BOT1 0.1UF LM324
VREF2
SN74F04
TITLE
RS232_I2C
SIZE
DRAWN SCALE SHEET
3-11-2005_10:54
DONGMING
OUT1 SOUT1
+3.3V +3.3V +3.3V
OUT2
SOUT2
11CLKAB 21LEAB 31OEAB SOUT1 SOUT2 OUT3 SOUT3 SOUT4 SOUT4_N SOUT5 SOUT5_N SOUT6 SOUT3 41A1 51A2 71A3 81A4 91A5 111A6 121A7 131A8 151A9 1CLKBA64 1LEBA63 1OEBA62 1B161 1B260 1B358 1B457 1B556 1B654 1B753 1B852 1B950
162A1
2B149 2B248 2B347 2B445 2B544 2B643 2B741 2B840 2B939 2OEBA37 2LEBA36 2CLKBA35 TDO31 TDO_B
SOUT4 OUT4 JP20 VREF1 OUT4_N
172A2 182A3 202A4 212A5 222A6 242A7 252A8 262A9 282OEAB 292LEAB GIN2/TMS 32TMS 33TCK 34TDI SOUT4_N 302CLKAB
GIN1/SCK/TCK GOUT0/TDO
SN74LVT18512 SOUT5 OUT5 JP21 VREF2 OUT5_N
SOUT5_N
JP10
+3.3V
0.1UF
0.1UF
0.1UF
OUT6
SOUT6
1.Place Jumper close possible associated connectors
2.Route traces from Jumper bottom layer 3.Keep clock trace lengths within each other
JP11
0.1UF
TITLE
JTAG TEST CIRCUIT
SIZE
DRAWN SCALE SHEET
3-11-2005_10:54
DONGMING
+3.3V +3.3V
stuffed normally
0.01UF
0.1UF 47UF
OUT3 0.1UF FLAG4
+3.3V
+3.3V
47UF
1NC/OE 2GND 25MHZ VDD4
0.1UF
0.1UF
0.1UF
0.1UF
MIC39101_3.3V
AVDD
OSC_F4100
CLKIN XTALIN/REF_IN
OUT1
OUT1
25.000MHZ
XTALOUT
OUT2
OUT2
OUT3
0.1UF
10NF
0.1NF
CLKIN
OUT3
OUT3
GIN5/CLK_SEL I2C/JTAG
GIN5/CLK_SEL
OUT4 OUT4_N
OUT4 OUT4_N +3.3V
I2C/JTAG OUT6
OUT6 GREEN GREEN
GIN3/SUSPEND +3.3V SHUTDOWN/OE
GIN3/SUSPEND SHUTDOWN/OE OUT5 OUT5_N GOUT1 GOUT1 GOUT0/TDO GOUT0/TDO OUT5 OUT5_N
Componts this block should removed oscillaor assembled
GIN0/SDA/TDI GIN1/SCK/TCK
GIN0/SDA/TDI GIN1/SCK/TCK GIN2/TMS GIN4/TRST
GIN2/TMS +3.3V GIN4/TRST
5V9885 JP12 GIN5/CLK_SEL JP13 I2C/JTAG TDO_B
JP14
GIN3/SUSPEND
JP15
SHUTDOWN/OE
JP16 GIN0/SDA/TDI GIN2/TMS GIN0/SDA/TDI JP17 GIN1/SCK/TCK JP18 GIN2/TMS GIN1/SCK/TCK
GIN4/TRST
JP19
GIN4/TRST CONN_2X7 GIN4/TRST GIN2/TMS GIN1/SCK/TCK
GIN0/SDA/TDI
1.Place CLKIN termination resistors close inputs 2.Route clocks layer 3.Route CLKIN single ohms line 4.Route single clock output single ohms lines 5.Route differential clock output differential ohms lines 6.Match clock output inch 100mils
CONN_2X5_MALE
TITLE
5V9885
SIZE
DRAWN SCALE SHEET
3-11-2005_10:54
DONGMING
5V9885 EVALUATION BOARD USER GUIDE
BOARD LAYOUT
5V9885 EVALUATION BOARD USER GUIDE
BOARD LAYOUT, LAYER
5V9885 EVALUATION BOARD USER GUIDE
BOARD LAYOUT, BOTTOM LAYER
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5V9885 EVALUATION BOARD USER GUIDE INTRODUCTION BOARD OVERVIEW BO

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