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Frequency Generator P4CPU, Express& Fully Buffered DIMM Clocks Re


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ICS9FG1901
Frequency Generator P4CPU, Express& Fully Buffered DIMM Clocks
Recommended Application:
DB1900G: Host Bus, Express Fully-Buffered DIMM clocking
Functionality Power (PLL Mode)
FS_A_4101 CLK_IN (CPU FSB) CLK_IN 200<= CLK_IN DIF_(18:0) CLK_IN CLK_IN
Features:
Power default outputs mode DIF_(16:0) "gear-shifted" from input Host Clock DIF_(18:17) "gear-shifted" from input Host Clock Spread spectrum compatible Supports output clock frequencies Selectable SMBus addresses SMBus address determines Bypass mode VDDA controlled power down mode
FS_A_410 low-threshold input. Please VIL_FS VIH_FS specifications Input/Supply/Common Output Parameters Table correct values.
Power Down Functionality
INPUTS OUTPUTS State VDDA/PD# CLK_IN/CLK_IN# DIF# Running 3.3V (NOM) Running Hi-Z Functionality Note recommended that Byte toggled from back first time VDDA applied. This ensures proper initialization device.
Specifications:
output cycle-to-cycle jitter 50ps (0:18) output-to-output skew 225ps (0:16) output-to-output skew 100ps
SMB_A2_PLLBYP#
Configuration
OE17_18# CLK_IN#
DIF_18#
DIF_17#
DIF_16#
DIF_15#
DIF_14#
CLK_IN
DIF_18
DIF_17
DIF_16
DIF_15
IREF GNDA VDDA/PD# HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# OE5# OE6# DIF_5 DIF_5# DIF_6 SMBCLK SMBDAT OE8# DIF_7 DIF_7# DIF_8 DIF_8# SMB_A0 SMB_A1 OE14# DIF_13# DIF_13 OE13# DIF_12# DIF_12 OE12# DIF_11# DIF_11 OE11# DIF_10# DIF_10 OE10# DIF_9# DIF_9 OE9#
ICS9FG1901
OE7# DIF_6#
72-pin
0962E-01/02/07
Other names brands claimed property others.
DIF_14
OE16#
OE15#
ICS9FG1901
Description
IREF GNDA VDDA/PD# HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# SMBCLK SMBDAT OE5# DIF_5 DIF_5# OE6# DIF_6 DIF_6# OE7# DIF_7 DIF_7# OE8# DIF_8 DIF_8# SMB_A0 SMB_A1 NAME TYPE DESCRIPTION This establishes reference current differential current-mode output pairs. This requires fixed precision resistor tied ground order establish appropriate current. ohms standard value. Ground core. 3.3V power core that also functions Power Down. Collapsing this power supply places device Power Down mode. 3.3V input selecting Band Width High, 3.3V tolerant threshold input frequency selection. This requires CK410 FSA. Refer input electrical characteristics Vil_FS Vih_FS threshold values. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pairs tri-state outputs, enable outputs Clock SMBUS circuitry, tolerant Data SMBUS circuitry, tolerant Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output SMBus address (LSB) SMBus address
0962E-01/02/07
ICS9FG1901
Description (Continued)
OE9# DIF_9 DIF_9# OE10# DIF_10 DIF_10# OE11# DIF_11 DIF_11# OE12# DIF_12 DIF_12# OE13# DIF_13 DIF_13# OE14# DIF_14 DIF_14# OE15# DIF_15 DIF_15# OE16# DIF_16 DIF_16# DIF_17 DIF_17# DIF_18 DIF_18# OE17_18# CLK_IN CLK_IN# SMB_A2_PLLBYP# NAME TYPE DESCRIPTION Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Ground pin. Power supply, nominal 3.3V Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pairs tri-state outputs, enable outputs Input reference clock. "Complementary" reference clock input. SMBus address When Low, part operates fanout buffer with bypassed. When High, part operates zero-delay buffer (ZDB) with operating. fanout mode (PLL bypassed), mode (PLL used)
0962E-01/02/07
ICS9FG1901
General Description
ICS9FG1901 follows Intel DB1900G Differential Buffer Specification. This buffer provides output clocks Host Bus, PCI-Express, Fully Buffered DIMM applications. outputs configured with groups. Both groups, DIF_(16:0) DIF_(18:17) equal have gear ratio input clock. differential clock from CK410 CK410B main clock generator, such ICS954101 ICS932S401, drives ICS9FG1901. ICS9FG1901 provide outputs 400MHz.
Block Diagram
OE_17_18#
SPREAD COMPATIBLE
GEAR SHIFT LOGIC
STOP LOGIC
DIF(18:17)
OE(16:5)#, OE_01234#
CLK_IN CLK_IN#
SPREAD COMPATIBLE
GEAR SHIFT LOGIC
STOP LOGIC
DIF(16:0)
HIGH_BW# FS_A_410 SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK CONTROL LOGIC
IREF
Power Groups
Number 11,27,47,63 10,28,46,64 Description Main PLL, Analog clocks
0962E-01/02/07
ICS9FG1901
ICS9FG1901 Programmable Gear Ratios
FS_A_410 SMBus Byte Input Output Gear Ratio (n/m) Input (CPU FSB) Output Frequencies (MHz) 200.0 266.7 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.750 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 320.0 333.3 400.0
66.7 88.9 106.7 111.1 133.3 80.0 106.7 128.0 133.3 160.0 83.3 111.1 133.3 138.9 166.7 100.0 133.3 160.0 166.7 200.0 120.0 160.0 192.0 200.0 240.0 125.0 166.7 200.0 208.3 250.0 133.3 177.8 213.3 222.2 266.7 150.0 200.0 240.0 250.0 300.0 166.7 222.2 266.7 277.8 333.3 200.0 266.7 320.0 333.3 400.0 240.0 320.0 384.0 400.0 250.0 333.3 400.0 266.7 355.6 300.0 400.0 333.3 400.0 (CPU FSB) Frequency (MHz) 133.33 166.67
0.333 0.400 53.3 64.0 66.7 0.417 55.6 66.7 69.4 0.500 50.0 66.7 80.0 83.3 0.600 60.0 80.0 96.0 100.0 0.625 62.5 83.3 100.0 104.2 0.667 66.7 88.9 106.7 111.1 0.800 80.0 106.7 128.0 133.3 0.833 111.1 133.3 138.9 1.000 100.0 133.3 160.0 166.7 1.200 120.0 160.0 192.0 200.0 1.250 125.0 166.7 200.0 208.3 1.333 133.3 177.8 213.3 222.2 1.500 150.0 200.0 1.667 166.7 222.2 266.7 277.8 2.000 200.0 266.7 320.0 333.3 Note: Lines BOLD Power-up defaults FS_A_410 respectively. Shaded areas shown reference only necessarily valid operating points
0962E-01/02/07
ICS9FG1901
Absolute
Symbol VDD_A VDD_In Tambient Tcase prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input protection human body model 0.5V 0.5V Units
2000
Electrical Characteristics Input/Supply/Common Output Parameters
70°C; Supply Voltage +/-5% PARAMETER Input High Voltage Input Voltage Input High Current Input Current IIL2 Threshold InputHigh Voltage Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Inductance Input Capacitance Stabilization Modulation Frequency Tracking SMBus Voltage Low-level Output Voltage Current sinking SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time
SYMBOL IIL1
CONDITIONS +/-5% +/-5% Inputs with pull-up resistors Inputs with pull-up resistors +/-5% +/-5% outputs driven differential pairs tri-stated Logic Inputs Output capacitance From Power-Up valid input clock, whichever comes last Triangular Modulation
-200
UNITS NOTES
VIH_FS VIL_FS IDD3.3OP IDD3.3PD Lpin COUT TSTAB
0.35
2.500 1.300
VMAX IPULLUP TRI2C TFI2C
Maximum input voltage IPULLUP
(Max 0.15) (Min 0.15) (Min 0.15) (Max 0.15)
1000
Guaranteed design characterization, 100% tested production. timing diagrams timing requirements. Output frequency accuracy dependent upon accuracy input frequency measured CLK_IN pins.
0962E-01/02/07
ICS9FG1901
Electrical Characteristics 0.7V Current Mode Differential Pair
70°C; +/-5%; =2pF, RS=33.2, RP=49.9, PARAMETER Current Source Output Impedance Voltage High Voltage Voltage Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL
CONDITIONS Statistical measurement single ended signal using oscilloscope math function. Measurement single ended signal using absolute value. Variation crossing over edges Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread 0.175V, 0.525V 0.525V 0.175V
3000 -150 -300 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720
1150 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533
UNITS
NOTES
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross
Average period
Tperiod
Absolute period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Output-to-Output Skew DIF(0:16) Output-to-Output Skew DIF(0:18) Input-to-Output Delay Jitter, Cycle cycle
d-tr d-tf tsk3_016 tsk3_018 tpdpll tpdbyp tjcyc-cyc
50.5
Measurement from differential wavefrom 50%, Skew within Group mode only 50%, Skew across outputs mode only Mode Bypass Mode mode, from differential wavefrom Bypass mode additive jitter
-500
Guaranteed design characterization, 100% tested production. Long Term Accuracy Clock Period specifications guaranteed assuming that input frequency meets CK410 accuracy requirements IREF VDD/(3xRR). (1%), IREF 2.32mA. IREF 0.7V ZO=50.
0962E-01/02/07
ICS9FG1901
Bandwidth Peaking
Parameter Jitter Peaking Jitter Peaking Bandwidth Bandwidth Output phase jitter impact PCIe* Gen1 Output phase jitter impact
NOTES: Measured down half power point. Measured maximum pass band gain. frequencies within loop highest point magnification called jitter peaking. Post processed evaluation through Intel supplied Matlab scripts. Refer FB-DIMM Specification: "High Speed Differential Point-to-Point Link updates this specification. PCIe* Gen2 filter characteristics subject final ratification ISIG. Please check PCI* latest specification. Tested with DBxx00G driven phase noise signal generator such Agilent 8133A. These jitter numbers defined 1E-12. Measured numbers smaller sample size have extrapolated this target. 0.54 implying jitter peaking Guaranteed design characterization, 100% tested production.
jpeak-hibw jpeak-lobw pllHIBW pllLOBW PCIe1
Conditions (HIGH_BW# (HIGH_BW# (HIGH_BW# (HIGH_BW#
(including 1.5-22 MHz, 0.54, Td=10 Ftrk=1.5 (including 0.54, Td=5 Ftrk=0.2 MHz)
Typical 1.28
Units
Notes 3,6,7,8
3,4,7,8
0962E-01/02/07
ICS9FG1901
9FG1901 SMBus Address Mapping when using CK410/CK410B, 9FG1201, 9DB104/108 SMB_A(2:0) Adr: 9FG1901 (DB1900G) SMB_A(2:0) Adr: 9FG1201/2 (DB1200G) Adr: 954101 932S401 (CK410/410B)
BYPASS MODE SMB_A2_PLLBYP#
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
MODE SMB_A2_PLLBYP#
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
Adr: 9DB104/108 (DB400/800)
SMB_A(2:0) Adr: 9FG1901 (DB1900G)
SMB_A(2:0) Adr: 9FG1201/2 (DB1200G)
0962E-01/02/07
ICS9FG1901
SMBusTable: Frequency Select Register Name Control Function Type Byte GRSEL_17 Group gear ratio select Gear Ratio DIF(16:0) GRSEL_2 Group gear ratio select Gear Ratio DIF(18:17) Reserved FS_A_410 Latched Input FSBG_3 FSBG_2 FSBG_1 FSBG_0 Gear Gear Gear Gear Ratio FS_3 Ratio FS_2 Ratio FS_1 Ratio FS_0
Latch
ICS9FG1901 Programmable Gear Ratios Table
SMBusTable: Output Control Register Name Byte DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable Enable Enable Enable
SMBusTable: Output Control Register Name Control Function Type Byte High note PLL_BW# adjust note BYPASS# test mode Bypass DIF_13 Output Control Hi-Z Enable DIF_12 Output Control Hi-Z Enable DIF_11 Output Control Hi-Z Enable DIF_10 Output Control Hi-Z Enable DIF_9 Output Control Hi-Z Enable DIF_8 Output Control Hi-Z Enable Note: wired HIGH_BW# input, selects High Note: wired SMB_A2_PLLBYP# input, selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte Name Control Function Readback OE9# Input Readback OE8# Input Readback OE7# Input Readback OE6# Input Readback OE5# Input Readback OE_01234# Input Readback HIGH_BW# Readback SMB_A2_PLLBYP#
Type
Readback Readback Readback Readback Readback Readback Readback Readback
0962E-01/02/07
ICS9FG1901
SMBusTable: Output Enable Readback Register Byte Name Control Function Readback OE17_18# Input Readback OE16# Input Readback OE15# Input Readback OE14# Input Readback OE13# Input Readback OE12# Input Readback OE11# Input Readback OE10# Input SMBusTable: Vendor Revision Register Name Byte RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 SMBusTable: DEVICE Byte
Type
Readback Readback Readback Readback Readback Readback Readback Readback
Control Function REVISION
VENDOR
Type
Name
Control Function Device (MSB) Device Device Device Device Device Device Device
Type
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBusTable: Byte Count Register Byte Name
Control Function
Writing this register configures many bytes will read back.
Type
0962E-01/02/07
ICS9FG1901
SMBusTable: Control Readback Register Name Control Function Byte Readback FS_A_410 RESERVED RESERVED DIF_18 Output Control DIF_17 Output Control DIF_16 Output Control DIF_15 Output Control DIF_14 Output Control SMBusTable: Reserved Register Name Byte
Type
Readback
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
SMBus Table: Programming Watchdog Safe Register Name Control Function Type Byte Gearing M/N_EN Programming Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SMBus Table: Gearing Frequency Control Register Byte Name Control Function Gearing Div8 Divider Prog Gearing Div9 Divider Prog Gearing Div5 Gearing Div4 Divider Programming Gearing Div3 (5:0) Gearing Div2 Gearing Div1 Gearing Div0
Disable
Enable
Type
0962E-01/02/07
ICS9FG1901
SMBus Table: Gearing Frequency Control Register Byte Name Control Function Gearing Div7 Gearing Div6 Gearing Div5 Divider Programming Gearing Div4 Byte12 bit(7:0) Byte11 Gearing Div3 bit(7:6) Gearing Div2 Gearing Div1 Gearing Div0 SMBusTable: Gearing Output Divider Register (Rev higher) Name Control Function Byte RESERVED RESERVED RESERVED RESERVED Gearing OutDiv Output Divider Gearing OutDiv Output Divider Gearing OutDiv Output Divider Gearing OutDiv Output Divider SMBusTable: Reserved Register Name Byte SMBusTable: Reserved Register Byte Name
Type
Type
Output Divider Table
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
0962E-01/02/07
ICS9FG1901
SMBusTable: Reserved Register Byte Name
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
SMBus Table: Frequency Control Register Name Control Function Type Byte Div8 Divider Prog Div9 Divider Prog Div5 Div4 Div3 Divider Programming bits Div2 Div1 Div0 SMBus Table: Frequency Control Register Name Control Function Byte Div7 Div6 Div5 Div4 Divider Programming b(7:0) Div3 Div2 Div1 Div0 SMBusTable: Output Divider Register (Rev higher) Name Control Function Byte RESERVED RESERVED RESERVED RESERVED OutDiv Output Divider OutDiv Output Divider OutDiv Output Divider OutDiv Output Divider
Type
Type
Output Divider Table
0962E-01/02/07
ICS9FG1901
SMBusTable: Reserved Register Byte Name
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
SMBusTable: Test Byte Register Byte Test Test Function ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST Note: write Erratic device operation will result!
Output Divider Table Devices only Byte 13(3:0) Byte 19(3:0) Divider Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Type
Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0962E-01/02/07
ICS9FG1901
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL MIN. MAX. 0.05 0.25 Reference 0.18 0.50 BASIC
DIMENSIONS SYMBOL BASIC MIN. MAX. MIN. MAX. MIN. MAX. TOLERANCE
10.00 10.00
5.75 6.15 5.75 6.15
Ordering Information
Reference: JEDEC Publication MO-220
ICS9FG1901yKLF-T
Example:
XXXX
Designation tape reel packaging Lead Free, RoHS Compliant (Optional) Package Type Revision Designator (will correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS, Standard Device
0962E-01/02/07
ICS9FG1901
Revision History
Rev. Issue Date Description Added Symbol Dimensions table. 4/25/2005 Preliminary Release. 12/19/2005 Rearranged page enlarge Configuration Updated actual values. Added Peaking Table. Updated Skew specs. 6/14/2006 Updated Paddle Dimensions. 8/17/2006 Final Release. Added Output Dividers Bytes devices. 1/2/2007 Changed PLL1 PLL2 naming Gearing Page
Various
Various
0962E-01/02/07

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