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ICS9FG1901

Frequency Generator for P4 CPU, PCI Express & Fully Buffered DIMM Clocks

Integrated Circuit Systems, Inc.
ICS9FG1901
Frequency Generator for P4 CPU, PCI Express & Fully Buffered DIMM Clocks
Recommended Application:
DB1900G: CPU Host Bus, PCI Express and Fully-Buffered DIMM clocking
Functionality at Power Up (PLL Mode)
Features:
Power Down Functionality
Key Specifications:
Pin Configuration
ICS9FG1901
72-pin MLF
0962E-01 / 02 / 07
Other names and brands may be claimed as the property of others.
OE16#
OE15#
Integrated Circuit Systems, Inc.
ICS9FG1901
Pin Description
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Integrated Circuit Systems, Inc.
ICS9FG1901
Pin Description (Continued)
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Integrated Circuit Systems, Inc.
ICS9FG1901
General Description
Block Diagram
SPREAD COMPATIBLE PLL
GEAR SHIFT LOGIC
STOP LOGIC
2 DIF(18:17)
SPREAD COMPATIBLE PLL
GEAR SHIFT LOGIC
STOP LOGIC
17 DIF(16:0)
Power Groups
Pin Number VDD GND 3 2 11, 27, 47, 63 10, 28, 46, 64 Description Main PLL, Analog DIF clocks
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Integrated Circuit Systems, Inc.
ICS9FG1901
ICS9FG1901 Programmable Gear Ratios
66.7 88.9 106.7 111.1 133.3 80.0 106.7 128.0 133.3 160.0 83.3 111.1 133.3 138.9 166.7 100.0 133.3 160.0 166.7 200.0 120.0 160.0 192.0 200.0 240.0 125.0 166.7 200.0 208.3 250.0 133.3 177.8 213.3 222.2 266.7 150.0 200.0 240.0 250.0 300.0 166.7 222.2 266.7 277.8 333.3 200.0 266.7 320.0 333.3 400.0 240.0 320.0 384.0 400.0 NA 250.0 333.3 400.0 NA NA 266.7 355.6 NA NA NA 300.0 400.0 NA NA NA 333.3 NA NA NA NA 400.0 NA NA NA NA CLK IN (CPU FSB) Frequency (MHz) 100 133.33 160 166.67
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Integrated Circuit Systems, Inc.
ICS9FG1901
Absolute Max
Electrical Characteristics - Input / Supply / Common Output Parameters
SYMBOL VIH VIL IIH IIL1
MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3
MAX VDD + 0.3 0.8 5
UNITS NOTES V V uA uA uA
VDD + 0.3 0.35 450 13 600 36 400 7 5
VMAX VOL IPULLUP TRI2C TFI2C
Maximum input voltage @ IPULLUP
(Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15)
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Integrated Circuit Systems, Inc.
ICS9FG1901
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
MIN 3000 660 -150 -300 250 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175
TYP 750
MAX 850 150 1150 550 140 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Output-to-Output Skew - DIF(0:16) Output-to-Output Skew - DIF(0:18) Input-to-Output Delay Jitter, Cycle to cycle
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Integrated Circuit Systems, Inc.
ICS9FG1901
PLL Bandwidth and Peaking
Parameter PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Output phase jitter impact - PCIe Gen1 Output phase jitter impact - FBD
jpeak-hibw jpeak-lobw pllHIBW pllLOBW PCIe1 FBD
Typical 1 1 2.3 1.28 77
Max 2.5 2 4 1.4 108 3
Units dB dB MHz MHz ps
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Integrated Circuit Systems, Inc.
ICS9FG1901
SMB Adr: DC 9DB104 / 108 (DB400 / 800)
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Integrated Circuit Systems, Inc.
ICS9FG1901
See ICS9FG1901 RW Programmable Gear Ratios RW Table RW RW
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 Enable Enable Enable Enable Enable Enable Enable Enable
0 Readback Readback Readback Readback Readback Readback Readback Readback
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Integrated Circuit Systems, Inc.
ICS9FG1901
0 Readback Readback Readback Readback Readback Readback Readback Readback
Control Function REVISION ID
VENDOR ID
Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0
Type RW RW RW RW RW RW RW RW
0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBusTable: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0
Control Function
Writing to this register configures how many bytes will be read back.
Type RW RW RW RW RW RW RW RW
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Integrated Circuit Systems, Inc.
ICS9FG1901
Type R
0 Readback
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
0 Disable
1 Enable
Type RW RW RW RW RW RW RW RW
0962E-01 / 02 / 07
Integrated Circuit Systems, Inc.
ICS9FG1901
SMBus Table: Gearing PLL Frequency Control Register Byte 12 Pin # Name Control Function Gearing PLL N Div7 Bit 7 Gearing PLL N Div6 Bit 6 Gearing PLL N Div5 Bit 5 N Divider Programming Gearing PLL N Div4 Bit 4 Byte12 bit(7:0) and Byte11 Gearing PLL N Div3 Bit 3 bit(7:6) Gearing PLL N Div2 Bit 2 Gearing PLL N Div1 Bit 1 Gearing PLL N Div0 Bit 0 SMBusTable: Gearing PLL Output Divider Register (Rev H and higher) Pin # Name Control Function Byte 13 RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 Gearing PLL OutDiv 3 Bit 3 PLL 1 Output Divider Gearing PLL OutDiv 2 Bit 2 PLL 1 Output Divider Gearing PLL OutDiv 1 Bit 1 PLL 1 Output Divider Gearing PLL OutDiv 0 Bit 0 PLL 1 Output Divider SMBusTable: Reserved Register Pin # Name Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Reserved Register Byte 15 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
See Output Divider Table
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
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Integrated Circuit Systems, Inc.
ICS9FG1901
SMBusTable: Reserved Register Byte 16 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
SMBus Table: 1:1 PLL Frequency Control Register Pin # Name Control Function Type Byte 17 1:1 PLL N Div8 N Divider Prog bit 8 RW Bit 7 1:1 PLL N Div9 N Divider Prog bit 9 RW Bit 6 1:1 PLL M Div5 RW Bit 5 1:1 PLL M Div4 RW Bit 4 1:1 PLL M Div3 RW Bit 3 M Divider Programming bits 1:1 PLL M Div2 RW Bit 2 1:1 PLL M Div1 RW Bit 1 1:1 PLL M Div0 RW Bit 0 SMBus Table: 1:1 PLL Frequency Control Register Pin # Name Control Function Byte 18 1:1 PLL N Div7 Bit 7 1:1 PLL N Div6 Bit 6 1:1 PLL N Div5 Bit 5 1:1 PLL N Div4 Bit 4 N Divider Programming b(7:0) 1:1 PLL N Div3 Bit 3 1:1 PLL N Div2 Bit 2 1:1 PLL N Div1 Bit 1 1:1 PLL N Div0 Bit 0 SMBusTable: 1:1 PLL Output Divider Register (Rev H and higher) Pin # Name Control Function Byte 19 RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 1:1 PLL OutDiv 3 Bit 3 PLL 2 Output Divider 1:1 PLL OutDiv 2 Bit 2 PLL 2 Output Divider 1:1 PLL OutDiv 1 Bit 1 PLL 2 Output Divider 1:1 PLL OutDiv 0 Bit 0 PLL 2 Output Divider
Type RW RW RW RW RW RW RW RW
See Output Divider Table
0962E-01 / 02 / 07
Integrated Circuit Systems, Inc.
ICS9FG1901
SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Output Divider Table Rev H Devices only Byte 13(3:0) Byte 19(3:0) Divider Value 0000 2 0001 3 0010 5 0011 NA 0100 4 0101 6 0110 10 0111 NA 1000 8 1001 12 1010 20 1011 NA 1100 NA 1101 nA 1110 NA 1111 NA
Type RW RW RW RW RW RW RW RW
Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Integrated Circuit Systems, Inc.
ICS9FG1901
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL A A1 A3 b e MIN. 0.8 0 MAX. 1.0 0.05 0.25 Reference 0.18 0.50 BASIC 0.3
DIMENSIONS ICS 72L SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. TOLERANCE
72 18 18 10.00 x 10.00
Ordering Information
Reference: JEDEC Publication 95, MO-220
ICS9FG1901yKLF-T
Example:
0962E-01 / 02 / 07
Integrated Circuit Systems, Inc.
ICS9FG1901
Revision History
Rev. A B Issue Date Description 1. Added Symbol "A" to Dimensions table. 4 / 25 / 2005 2. Preliminary Release. 12 / 19 / 2005 1. Rearranged page 1 to enlarge Pin Configuration 1. Updated TBD to actual values. 2. Added PLL BW and Peaking Table. 3. Updated Skew specs. 6 / 14 / 2006 4. Updated Paddle Dimensions. 8 / 17 / 2006 Final Release. 1. Added Output Dividers to Bytes 13 and 19 for Rev H devices. 1 / 2 / 2007 2. Changed PLL1 and PLL2 naming to 1:1 and Gearing PLL Page # 15 1
Various -
Various
0962E-01 / 02 / 07