6024 Silver Creek Valley Road, Jose, California 95138 Telephone: (800)
|
|
|
Top Searches for this datasheet
IDT79S334A Evaluation Board Manual
6024 Silver Creek Valley Road, Jose, California 95138 Telephone: (800) 345-7015 (408) 284-8200 FAX: (408) 284-2775 Printed U.S.A. ©2005 Integrated Device Technology, Inc.
Boards that fail function should returned replacement. Credit will given failed boards will Failure Analysis performed.
LIFE SUPPORT POLICY Integrated Device Technology's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer IDT. Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component components life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
logo, Dualsync, Dualasnyc registered trademarks Integrated Device Technology, Inc. IDT, QDR, RisController, RISCore, RC3041, RC3051, RC3052, RC3081, RC32134, RC32364, RC36100, RC4700, RC4640, RC64145, RC4650, RC5000, RC64474, RC64475, SARAM, Smart ZBT, SuperSync, SwitchStar, Terasync,Teraclock, trademarks Integrated Device Technology, Inc. Powering What's Next Enabling Digitally Connected World service marks Integrated Device Technology, Inc. QSI, SynchroSwitch Turboclock registered trademarks Quality Semiconductor, wholly-owned subsidiary Integrated Device Technology, Inc.
Table Contents
Description IDT79S334A Evaluation Board
Introduction .1-1 Revision History.1-1 Overview Features.1-2 Explanation Features.1-2 Specification Summary .1-2 Part Number .1-2 RISController.1-2 On-Board Memory Capacity.1-2 Debug Monitor Flash .1-3 Serial Ports.1-3 Interrupts .1-3 Physical Dimensions .1-3 Operating Temperature .1-3 Relative Humidity .1-3 Power Supply .1-3 Flash.1-3 SDRAM .1-3 SRAM .1-3 Programmable (PIO) .1-3 Interface .1-3
Notes
Installation IDT79S334A Evaluation Board
79S334A Installation.2-1 Getting Started Quickly.2-1 Video Terminal Requirements .2-1 Power Connector Type.2-1 Host Mode Power Connector (J12) .2-2 Satellite Mode Power Connector (J13).2-3 (EJTAG Connector) .2-3 Memory Blocks.2-4 Jumper Switch Settings .2-5 EPROM/Flash Selection.2-5 Core/IO Supply .2-5 Arbitration Jumper/Setting.2-5 Jumper Options .2-5 Switch Settings (Mode selection) .2-7 System Software IDT/sim .2-8 Serial Port Video Terminal Auxiliary Port .2-8 Initialization System Start-Up.2-9 Logic Analyzer Connections .2-10
IDT79S334A Evaluation Board Manual February 2001
Notes
Theory Operation Design Notes
Introduction .3-1 Address Space Decoding .3-1 SRAM Selected, 32Mbyte DRAM SODIMM.3-2 SRAM Selected, 32Mbyte DRAM SODIMM .3-2 Register Address Maps Channels .3-5 Interrupts.3-7
Schematics
Schematics .4-1
EPLD Equation
SYSCONSTG .5-1
IDT79S334A Evaluation Board Manual
February 2001
List Tables
Notes
Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 Table 2.18 Table Table Table Table Table Table Table Table Table Table 3.10 Table 3.11 Table 3.12 Table 3.13 Table 3.14 Table 3.15 Table 3.16 Table 3.17 Table 3.18
Power Connectors .2-2 Power Connectors .2-3 EJTAG Connector .2-3 JTAG Connector .2-4 S334A Evaluation Board Memory Block Connector Locations.2-4 EPROM Flash Setting.2-5 Core/IO Jumper Settings.2-5 Arbitration Jumper Setting .2-5 Jumper Options .2-5 Switch Settings .2-7 J2/J1 Connector Pins Signal Descriptions.2-9 J19/J18 Connector Pins Signal Descriptions.2-9 Analyzer Connector J4.2-10 Analyzer Connector 2-11 Analyzer Connector 2-11 Analyzer Connector J9.2-12 Analyzer Connector J20.2-13 Analyzer Connector J21.2-13 EPROM/FLASH Address Mapping .3-1 Physical Address Mapping 79S334 Board Resources .3-1 SRAM/DRAM Address Range, 32Mbyte DRAM SODIMM.3-2 DRAM Address Range, 32Mbyte DRAM SODIMM SRAM Selected.3-2 LED_Display .3-2 NVRAM (512 Bytes) .3-2 Interrupt Status .3-3 Controller Address Mapping .3-3 Interface Address Ranges Definitions .3-3 Register .3-4 Channel Register Mapping .3-5 Channel Register Mapping .3-5 Channel Register Mapping .3-5 Channel Register Mapping .3-6 Expansion Interrupt Controller Address Mapping .3-6 Timer Controller Address Mapping .3-6 UART Controller Address .3-7 Interrupt Assignment S334A Board .3-7
IDT79S334A Evaluation Board Manual
February 2001
Notes
IDT79S334A Evaluation Board Manual
February 2001
List Figures
Notes
Figure Figure Figure
79S334A Evaluation Board Block Diagram .1-1 Diagram 6-Pin Power Supply Connections S334A Evaluation Board .2-2 Initial Screen Display IDT/sim Debug Monitor .2-10
IDT79S334A Evaluation Board Manual
February 2001
Notes
IDT79S334A Evaluation Board Manual
February 2001
Chapter
Description IDT79S334A Evaluation Board
Notes Introduction
IDT79RC32334 high performance integrated communications processor that combines IDT's RISCore32300 core with system logic control boot memory, main memory, I/O, PCI. also includes on-chip peripherals such channels, reset circuitry, interrupts, timers UARTs. RC32334 complete subsystem embedded designs. IDT79S334A Evaluation Board provides RC32334 evaluation tool well cost effective boards through interface. 79S334A working example typical embedded host/satellite system. This board highly configurable contains hardware options various memory configurations.
Data Transceiver 1Mbyte (x32) SRAM 5Volt Data Quick Switch 3.3V)
Reset Generation Data Timers, UARTs, Interrupt Controller Voltage Distribution, (Regulator) Clock Synthesizer SDRAMs/ Interface
Quick Switch
DIMM Slot
SODIMM Slot
(1Mbyte)x8/ (4Mbyte)x32 wide EPROM Flash
Alphanumeric Intelligent Display with Memory/ Decoder/Driver
512byte(x8) NVRAM External UART
Address Buffer Logic Analyzer Connectors System EPLD Memory Control Core Bridge Interface with Arbiter Quick Switch Isolation Quick Switch Isolation Memory Address Control
RS232 Serial
SDRAM SODIMM Control RC32334 Serial Peripheral Interface
3.3V Slot Primary bus, 32bit @33MHz 3.3V Slot Slot Slot External Arbiter EPLD (RFU) Logic Analyzer Connectors Arbitration Signals Edge Connector
EJTAG
Channels
EJTAG/ JTAG Interface
Serial EEPROM SPI/ Boot
Figure 79S334A Evaluation Board Block Diagram
Revision History
July 2000: Initial publication. September 2000: block diagram, revised schematics, MHz, various minor revisions. January 2001: Revised re-organized Jumper Switch Settings Chapter February 2001: Changed Jumper numbers listed Controller paragraph page 3-3. Removed reference "timers" same paragraph.
IDT79S334A Evaluation Board Manual
February 2001
Description IDT79S334A Evaluation Board
Overview Features
Notes
Overview Features
Major features 79S334A Evaluation Board include:
Cost effective method adding boards through interface slots (two 5V-J14 J15, 3.3V-J16 J17) adding peripheral controllers. given instant, maximum slots available (J14 J17). Edge connector EPROM Mbyte
SRAM Mbyte SDRAM Mbytes Serial EEPROM (Microwire NM93C46 25256) on-chip serial ports (16550 Compatible UARTs) External 85C30 Serial Controller digit display Byte NVRAM
Explanation Features
IDT's S334A Evaluation Board complete working RC32334 system intended evaluation tool software development platform that uses high performance RC32334 RISController, which based IDT's proprietary RISCore32300 core. board requires simple video terminal emulator 5-volt power supply with least current. ±12-volt power supply also needed support requirements. board contains four slots adding peripheral controllers. board contains EPROM. on-board EPROM memory contains IDT's flexible System Integration Manager (IDT/sim), debugging monitor that supports code downloading from host system I/O. Execution control commands include single stepping instruction tracing, memory probing, register probing, line-based assembly disassembly code. Information using IDT/sim provided separate document that available from site (www.idt.com). S334A evaluation board constructed with both through-hole surface mount devices rectangular form factor board with standoffs intended stand-alone bench device.
Specification Summary
Part Number IDT79S334A Evaluation Board RISController RC32334 RISController (256BGA) On-Board Memory Capacity RISController on-chip Instruction Cache 8kByte Data Cache 2kByte shipped SDRAM 32MByte (144 SODIMM) EPROM 1MByte Maximum SDRAM 256MByte EPROM 4MB/Flash SRAM 1Mbyte
IDT79S334A Evaluation Board Manual
February 2001
Description IDT79S334A Evaluation Board
Specification Summary
Notes
Debug Monitor Flash MByte higher density EPROM 27C080 support, containing IDT/sim Serial Ports Controlled 85C30 controller
RS232 DB9P (9-pin male) connectors video terminal connects Software configurable features Default rate: 9600 Baud, bits, parity, stop
Interrupts unsynchronized Physical Dimensions Rectangular form factor: Operating Temperature 0-30°C Relative Humidity Power Supply 5.0V Amps typical
12.0V required
Flash Cached/non-cached, single access support Non-interleaved SDRAM Basic structure SODIMM socketed (socket board) DIMM PC100, CL=2 component Configurations allowed Either SODIMM DIMM Stays page between transfers SRAM Basic structure devices SRAM Zero wait-state operation block read block write Programmable (PIO) Input/Output/Interrupt source
Individually programmable
Interface Revision compliant
clock frequency speed synchronizer from local system
IDT79S334A Evaluation Board Manual
February 2001
Description IDT79S334A Evaluation Board
Specification Summary
Notes
IDT79S334A Evaluation Board Manual
February 2001
Chapter
Installation IDT79S334A Evaluation Board
Notes 79S334A Installation 79S334A Installation
This chapter discusses steps required install boot 79S334A Evaluation Board. primary installation steps follows: Connect power source This involves connecting external power supply board through J12. Connect video display terminal This involves connecting RS232-C serial cable from video terminal board through connector J19. Insert Ethernet adapter card either Ethernet download Configure jumper/switch options This involves altering reset initialization mode vector changing memory configuration. board shipped with jumpers/switches their default configurations. Software additional software required. Boot IDT/sim When power board turned board's IDT/sim program boots displays start-up message.
Started Quickly Getting Started Quickly
79S334A board shipped ready run. Before board shipped, jumpers switches configured default settings shown tables below, general, they require further modification setup. basic requirements board are:
power supply with least current ±12V power supply support requirements
Video Terminal Requirements video terminal typical VT100 type/ANSI terminal, emulator, running with 9600 baud, data bits, parity, stop bit. evaluation board, RS232-C connector uses male 9pin connector (J19) which uses pins shown Table 2.12. default stand-alone mode, power board provided using standard PC/AT power supply, available from wide variety computer equipment retailers. Power Connector Type power supply typical compatible power supply. connector board uses 12-pin power supply connector that mates with 6-pin power supply connectors standard power supply, shown Table 2.1.
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Getting Started Quickly
Notes
Host Mode Power Connector (J12) power connectors Host mode. power connector Satellite mode.
Definition +12V -12V Ground Ground Ground Ground (vcc) (vcc) (vcc) Color Mating Connector Wire Orange Yellow Blue Black Black Black Black White
Table Power Connectors
Figure Diagram 6-Pin Power Supply Connections S334A Evaluation Board
IDT79S334A Evaluation Board Manual
Evaluation Board
February 2001
Installation IDT79S334A Evaluation Board
(EJTAG Connector)
Notes
Satellite Mode Power Connector (J13) power connectors Satellite mode. power connectors Host mode. Note: When connecting J13, sure PC-AT compatible peripherals power source.
Definition +12V Ground Ground
Color Mating Connector Wire Yellow Black Black
Table Power Connectors
(EJTAG Connector)
number signal definitions provided Table 2.3.
EJTAG Connector1 Number Name TRST* Description TRST* active-low signal asynchronous reset debug unit, independent processor logic. rising edge Tclk, serial input data shifted into either Instruction Data register, depending controller state. During Real Mode, this input used interrupt line stop debug unit from Real Time mode return debug unit back Time Mode (standard JTAG). serial data shifted from instruction data register falling edge Tclk. When data shifted out, tri-stated. During Real Time Mode, this signal provides non-sequential program counter processor clock division processor clock. logic signal received input decoded controller control test operation. sampled rising edge TCLK. input test clock, used shift into Boundary-Scan register cells. Tclk independent system processor clock with nominal duty cycle. Reset input, active signal asynchronous reset entire target board. Trace Status Information (STL) Pipe line Stall (JMP) Branch/Jump forms with output (BRT) Branch/Jump forms with output (EXP) Exception generated with exception vector code output (SEQ) Sequential performance (TST) Trace outputted pipeline stall time (TSQ) Trace trigger output performance time (DBM) Debug Mode During power-on reset (cold reset), PCST(2:0) serves Mode Bit(2:0). Table EJTAG Connector (Part
TCLK
RST* PCST0 PCST1 PCST2
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
(EJTAG Connector) EJTAG Connector1
Notes
Number Name DCLK
Description Processor Clock. During Real Time Mode, this signal used capture address data from signal processor clock speed, division internal pipeline. DCLK will pipeline clock. Debugboot input used during reset forces core take debug exception reset sequence instead reset exception. This enables boot from probe without having external memory working. This input signal level sensitive latched internally. Power Status signal. Table EJTAG Connector (Part
Debugboot
even numbered pins ground pins.
JTAG Connector Number Even Name TRST* TRST* active-low signal asynchronous reset debug unit, independent processor logic. rising edge Tclk, serial input data shifted into either Instruction Data register, depending controller state. During Real Mode, this input used interrupt line stop debug unit from Real Time mode return debug unit back Time Mode (standard JTAG). serial data shifted from instruction data register falling edge Tclk. When data shifted out, tri-stated. During Real Time Mode, this signal provides non-sequential program counter processor clock division processor clock. logic signal received input decoded controller control test operation. sampled rising edge TCLK. input test clock, used shift into Boundary-Scan register cells. Tclk independent system processor clock with nominal duty cycle. Table JTAG Connector Description
TCLK
Memory Blocks DRAM Controller space maximum Mbytes that populated time with SDRAM DIMM connector slot shown Table 2.5.
Connector Memory Type SRAM SRAM SDRAM DIMM SODIMM
Table S334A Evaluation Board Memory Block Connector Locations
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Jumper Switch Settings
Notes
Jumper Switch Settings
EPROM/Flash Selection
Jumper Setting Short between Short between Short between Short between Short between Short between Short between Short between Short between Short between Short between Short between Short between Short between EPROM selected (Default) Flash selected Description
Table EPROM Flash Setting
Core/IO Supply
Core/IO Supply Jumpers hard-wired Provides 3.3V core Table Core/IO Jumper Settings
Arbitration Jumper/Setting
Internal (Default) Open Open Short between Open Short between External Close Close Short between Close Short between
Table Arbitration Jumper Setting
Jumper Options
Channel1 (Default-no jumper open) Short between External UART channel W/REQ controls Ready1 Short between External UART channel DTR/REQ controls Ready1 Channel0 (Default-no jumper open) Short between External UART channel W/REQ controls Ready0 Short between External UART channel DTR/REQ controls Ready0 Table Jumper Options (Part
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Jumper Switch Settings
Notes
SDRAM DIMM Open: SODIMM (Default) Close: Standard DIMM (Use 168-pin Std. DIMM SODIMM socket)
reset option Open: Standard reset (Default) Close: Asserts permanent reset case JTAG testing (code implemented EPLD)
EEPROM output selection Short Selects microwire serial EEPROM Short Selects serial EEPROM (Default)
mode selection Short Satellite mode Short Host mode (Default)
bits selection Close: Special function mode (UART) (Default) Open: General purpose mode Jumper Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Setting Close (Default) Open Close (Default) Open Close (Default) Open Close (Default) Open Close (Default) Open Close (Default) Open Close (Default) Open Close (Default) Open Description Signal UART General purpose data UART General purpose UART General purpose UART General purpose channel General purpose channel General purpose UART General purpose UART General purpose
capability selection Close: capability (Default) Open: Enable capability
control operation. JTAG probe controls test operation Controller. Short Selects control (Default) Short Selects control Table Jumper Options (Part
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Jumper Switch Settings
Notes
Switch Settings (Mode selection)
S3-1, S3-2 boot mode selection S3-1 S3-3 S3-4, S3-5 S3-4 (mode S3-6 S3-7 (Default) Timer interrupt enable/disable (Mode Enable TimerInterrupt (Default) Off: Disable Timer Interrupt S3-8, S2-1 S2-2 Mode bits Reserved bits Both switches always Big/Little endian selection (Mode Little endian Off: endian (Default) Table 2.10 Switch Settings (Part S3-5 (mode S3-2 Description Selects Boot from Memory Controller, Serial EEPROM supported (Default) Selects Boot from PCI, Serial EEPROM supported Reserved Reserved Host mode (Default) Satellite mode Port Width (Default) RESV
Host/Satellite mode selection
Boot PROM port width selection
Mode selection (Reserved)
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
System Software IDT/sim
Notes
S2-3, S2-4, S2-5
Clock multiplier selection S2-3 (bit mode S2-4 (bit mode S2-5 (bit mode Clock multiplier (Default) Reserved Reserved Reserved Reserved Reserved
S2-6, S2-7, S2-8
Other switch settings (unused) Always Table 2.10 Switch Settings (Part
System Software IDT/sim
EPROM 79S334A contains IDT's System Integration Manager (IDT/sim). IDT/sim software boot PROM debug monitor that provides functions downloading software integrating hardware with software. Using IDT/sim, software downloaded onto board from SPARCstationor PC/AT personal computer. IDT/sim source code acquired support other devices change addresses their specific application: example, change from big-endian little-endian addressing. S334A board's default configuration big-endian addressing. copy IDT/sim obtained through your local sales representative. Note: IDT/sim provides functions measuring elapsed execution time: timer_start() unsigned timer_stop(). function timer_stop() returns number microseconds elapsed since most recent call timer_start(). This functionality independent system clock crystal specification majority evaluation boards. However, IDT79S134 IDT79S334A boards exceptions. these boards, number microseconds returned accurate ONLY system clock crystal MHz. crystal with different frequency being used, MHz, must multiply result 50/X obtain actual microseconds elapsed time. above true "clock()" function supported Algorithmics C/C++ compiler shipped with board.
Serial Port Video Terminal Auxiliary Port
79S334A system board four RS232 serial port connectors with assignments shown Table 2.11 Table 2.12. console port board DB9P connector designated J2/J191 must data rate 9600 baud with bits data, parity bit, stop bit. J1/J18 auxiliary port also DB9P connector used functions such down loading software from SPARCstationTM.
Based (for external/internal UART) console will either shipped: J19).
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Initialization System Start-Up
Notes
Port Console Connector Signal connection (Output) (Input) connection Ground connection connection connection connection
Port Auxiliary Connector Signal connection (Output) (Input) connection Ground connection connection connection connection
Table 2.11 J2/J1 Connector Pins Signal Descriptions 79RC32334 UART Console Connector Signal connection (Output) (Input) (Input) Ground (Output) (Output) (Input) connection 79RC32334 UART- Auxiliary Connector Signal connection (Output) (Input) connection Ground connection connection connection connection
Table 2.12 J19/J18 Connector Pins Signal Descriptions
Initialization System Start-Up
System start-up performed turning power supply power board already been supplied, then pressing reset button will reinitialize board. Three board's four displays indicate that power been successfully applied indicates status reset, follows:
indicates that Cold Reset active (Red) indicates that 2.5V power supply (Red) indicates that 3.3V power supply (Yellow) indicates that power (Green)
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Logic Analyzer Connections
Notes
Once started, IDT/sim automatically boots sizes internal cache main memory. console connected serial port message indicating cache memory sizes-similar shown Figure 2.2-will appear along with first command line prompt. more information commands, refer IDT/ User/Developer's Manual. Note: Future upgrades will assigned different version number date. starting address free memory space differ slightly from example shown Figure 2.2. System Integration Manager Ver. 2000 Copyright 1994-2000 Integrated Device Technology, Inc. RC323xx CPU, 32-bit, Endian, MIPS-II, Write-Through cache Console: 9600 baud Instruction cache: Data cache: Memory Configuration: SDRAM only Primary User Memory: 0XA009B2A8 0XA1FBFFFC. Size: 31888 CAUTION: IDT/sim functions <timer_start> <timer_stop> will work accurately only crystal socket MHz. Higher (lower) rating will cause timer_stop return higher (lower) value! HELP enter <IDT>
Figure Initial Screen Display IDT/sim Debug Monitor
Logic Analyzer Connections
J4-6, J20, used connect directly Logic Analyzer. numbers signal descriptions each connector listed following tables.
N.C. CPU_LA_CLK1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. sdram_addr[21] sdram_addr[20] sdram_addr[19] Signal N.C. N.C. debug_cpu_ack_n mem_data[31] mem_data[30] mem_data[29] mem_data[28] mem_data[27] mem_data[26] mem_data[25] mem_data[24] mem_data[23] mem_data[22] mem_data[21] mem_data[20] mem_data[19] Signal
Table 2.13 Analyzer Connector (Part IDT79S334A Evaluation Board Manual February 2001
Installation IDT79S334A Evaluation Board
Logic Analyzer Connections Signal sdram_addr[18] sdram_addr[17] sdram_addr[16] Signal mem_data[18] mem_data[17] mem_data[16]
Notes
Table 2.13 Analyzer Connector (Part Signal N.C. cpu_masterclk sdram_addr[15] sdram_addr[14] sdram_addr[13] sdram_addr[12 sdram_addr[11] sdram_addr[10] sdram_addr[9] sdram_addr[8] sdram_addr[7] sdram_addr[6] sdram_addr[5] sdram_addr[4] sdram_addr[3] sdram_addr[2] sdram_addr[1] sdram_addr[0] N.C. N.C. debug_cpu_ads_n sdram_we_n sdram_s_n[1] sdram_s_n[0] sdram_ras_n sdram_cs_n[3] sdram_cs_n[2] sdram_cs_n[1] sdram_cs_n[0] sdram_cas_n sdram_bemask_n[3] sdram_bemask_n[2] sdram_bemask_n[1] sdram_bemask_n[0] sdram_245_oe_n sdram_cke_n sdram_addr[12] Signal
Table 2.14 Analyzer Connector Signal N.C. N.C. debug_cpu_dma_n mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] mem_oe_n mem_245_oe_n Signal
debug_cpu_i_d_n mem_data_15 mem_data_14 mem_data_13 mem_data_12 mem_data_11 mem_data_10
Table 2.15 Analyzer Connector (Part IDT79S334A Evaluation Board Manual February 2001
Installation IDT79S334A Evaluation Board
Logic Analyzer Connections Signal mem_data_9 mem_data_8 mem_data_7 mem_data_6 mem_data_5 mem_data_4 mem_data_3 mem_data_2 mem_data_1 mem_data_0 Signal mem_cs_n[5] mem_cs_n[4] mem_cs_n[3] mem_cs_n[2] mem_cs_n[1] mem_cs_n[0] cpu_coldreset_n cpu_nmi_n cpu_int_n[0] cpu_dt_r_n
Notes
Table 2.15 Analyzer Connector (Part
Signal N.C. ejtag_dclk N.C. ejtag_pcst[2] ejtag_pcst[1] ejtag_pcst[0] ejtag_tms ejtag_debugboot jtag_tdi ejtag_tpc jtag_tms jtag_tck jtag_trst_n spi_miso spi_mosi spi_ss_n spi_sck timer_tc_n
Signal N.C. N.C. mem_wait_n N.C. N.C. N.C. N.C. N.C. N.C. dma_ready_n[1] dma_ready_n[0] uart_tx[1] uart_tx[0] uart_rx[1] uart_rx[0] uart_dsr_n uart_dtr_n uart_rts_n uart_cts_n
Table 2.16 Analyzer Connector
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Logic Analyzer Connections Signal N.C. pci_clk pci_perr_n pci_serr_n pci_stop_n pci_par pci_cbe_n[3] pci_cbe_n[2] pci_cbe_n[1] pci_cbe_n[0] pci_lock_n pci_req_gnt_n[0] pci_req_n[2] pci_gnt_req_n[0] pci_gnt_n[2] pci_irdy_n pci_trdy_n pc_devsel_n Signal N.C. N.C. N.C. pci_ad[15] pci_ad[14] pci_ad[13] pci_ad[12] pci_ad[11] pci_ad[10] pci_ad[9] pci_ad[8] pci_ad[7] pci_ad[6] pci_ad[5] pci_ad[4] pci_ad[3] pci_ad[2] pci_ad[1] pci_ad[0]
Notes
Table 2.17 Analyzer Connector N.C. pci_clk N.C. N.C. N.C. N.C. N.C. N.C. N.C. pci_gnt_n[1] pci_req_n[1] pci_intd_n pci_intc_n Signal Signal N.C. N.C. N.C. pci_ad[31] pci_ad[30] pci_ad[29] pci_ad[28] pci_ad[27] pci_ad[26] pci_ad[25] pci_ad[24] pci_ad[23] pci_ad[22] pci_ad[21]
Table 2.18 Analyzer Connector (Part
IDT79S334A Evaluation Board Manual
February 2001
Installation IDT79S334A Evaluation Board
Logic Analyzer Connections Signal pci_intb_n pci_inta_n N.C. N.C. N.C. Signal pci_ad[20] pci_ad[19] pci_ad[18] pci_ad[17] pci_ad[16]
Notes
Table 2.18 Analyzer Connector (Part
IDT79S334A Evaluation Board Manual
February 2001
Chapter
Theory Operation Design Notes
Notes Introduction
This chapter provides information functional operation IDT79S334A evaluation board RC32334 integrated communications processor. detailed schematics refer Chapter detailed equations, refer Chapter
Address Space Decoding
physical addresses S334A board's resources listed tables that follow. EPROM/FLASH, SRAM, Serial Communication Controller, NVRAM, display, INTSTS subsystems accessed through selection Memory chip selects[0.5]. memory_I/O controller includes EPROM/FLASH subsystem, Serial SRAM subsystems. EPROM/FLASH module accessible through mem_chipselect[0]. address ranges shown Table 3.1. Selection between EPROM FLASH memory space achieved through jumpers, shown Table Chapter
Address Range EPROM FLASH EPROM FLASH 1FC0_0000 1FCF_FFFF 1FC0_0000 1FC7_FFFF 1FC0_0000 1FFF_FFFF 1FC0_0000 1FDF_FFFF Base Address 1FC0_0000 1FC0_0000 1FC0_0000 1FC0_0000 Base Mask FFF0_0000 FFF8_0000 FFC0_0000 FFE0_0000
Table EPROM/FLASH Address Mapping
85C30 controller interfaces RS232 connectors located fixed address space listed Table 3.2, which selected through mem_chipselect[5]. NVRAM selected through mem_chipselect[3], display through mem_chipselect[4] Interrupt status through mem_chipselect[2]. SRAM memory space Mbyte accessed through mem_chipselect[1] (see Table 3.3).
Description Flash SRAM DRAM (SDRAM) Bank size 16MB Bank size 16MB Bank size 16MB Bank size 16MB (85C30) LED_Display NV_RAM INT_Status 0000_0000 00FF_FFFF 0100_0000 01FF_FFFF 0200_0000 02FF_FFFF 0300_0000 03FF_FFFF 1600_0000 17FF_FFFF 1400_0000 15FF_FFFF 1200_0000 13FF_FFFF 1000_0000 11FF_FFFF mem_chipselect[5] mem_chipselect[4] mem_chipselect[3] mem_chipselect[2] Physical Address Locations 1FC0_0000 1FFF_FFFF 1FC0_0000 1FDF_FFFF 0400_0000 040F_FFFF Chipset Select Allocation mem_chipselect[0] mem_chipselect[0] mem_chipselect[1]
79RC32334 Internal Registers 1800_0000 1BFF_FFFF
Table Physical Address Mapping 79S334 Board Resources IDT79S334A Evaluation Board Manual February 2001
Theory Operation Design Notes
Address Space Decoding
Notes
DRAM Controller supports Mbytes. time, either SODIMM standard DIMM populated. Both sockets supports DRAM DIMMs. Table shows SRAM DRAM address locations when SRAM option selected. When SRAM selected, address mappings shown Table 3.4. SRAM Selected, 32Mbyte DRAM SODIMM
SRAM Address Range From 0000_0000 000F_FFFF DRAM Address Range From 0100_0000 02FF_FFFF DRAM Base Addresses Banks 0100_0000 0200_0000 0300_0000 0400_0000 Table SRAM/DRAM Address Range, 32Mbyte DRAM SODIMM DRAM Mask Addresses Banks FF00_0000
SRAM Selected, 32Mbyte DRAM SODIMM
DRAM Address Range From 0000_0000 01FF_FFFF 0000_0000 0100_0000 0200_0000 0300_0000 Table DRAM Address Range, 32Mbyte DRAM SODIMM SRAM Selected LED_Display Clear display (read this port) Digit Digit Digit Digit 1400_0400 1400_000F 1400_0008 1400_0007 1400_0003 Table LED_Display NVRAM (512 Bytes) Base Addr Read/Write Base Addr Recall/Store 1200_0000 1200_0400 DRAM Base Addresses DRAM Mask Addresses
Banks FF00_0000
Table NVRAM (512 Bytes)
IDT79S334A Evaluation Board Manual
February 2001
Theory Operation Design Notes
Address Space Decoding
Notes
Interrupt Status Base Addr (read only): 1000_0000 PCI_INT PCI_INT PCI_INT PCI_INT M66EN SCC_INT_N PCI_HOST_N UART_DCD_N Table Interrupt Status
Controller supports either 15-bit general purpose discrete specific peripheral functions. general purpose discrete pins, controller supports function such micro wire serial EEPROM. Specific peripheral functions such on-chip UART data pins, modem control, SPI, also supported. Each these functions implemented through jumpers W25, through W34, shown Table 2.9. address controller shown Table 3.8.
Controller Address Mapping From 1800_0600 1800_0608
Table Controller Address Mapping
interface resources include control core that provides master target controller that uses transmit receive FIFO sizes words. interface core provides arbitration selection, external request grant modes, internal RC32334 arbiter mode with fixed round robin priority selections, mailbox registers, software programmable endianness (selectable memory block). internal address interface shown Table 3.9. address mapping these registers shown Table 3.10.
From 1800_2000 1880_0000 18C0_0000 1FC0_0000 4000_0000 6000_0000
1800_2FFF 188F_FFFF 18FF_FFFF 1FFF_FFFF 5FFF_FFFF 7FFF_FFFF
Allocation Internal registers (4KB) Space (1MB) Memory space (4MB) (for non-pci boot reset option) Memory space (4MB) (for boot reset option) Memory Space (512MB) Memory Space (512MB)
Table Interface Address Ranges Definitions
IDT79S334A Evaluation Board Manual
February 2001
Theory Operation Design Notes
Address Space Decoding
Notes
Address 1800_05B0 1800_05B4 1800_05B8
Registers Controller Interrupt Pending Register Controller Interrupt Mask Register Controller Interrupt Clear Register
1800_05C0 1800_05C4 1800_05C8
Satellite Mode Mailbox Interrupt Pending Register Satellite Mode Mailbox Interrupt Mask Register Satellite Mode Mailbox Interrupt Clear Register
1800_05D0 1800_05D4 1800_05D8
Mailbox Interrupt Pending Register Mode Mailbox Interrupt Mask Register Mailbox Interrupt Clear Register
1800_20B0 1800_20B8 1800_20C0 1800_20C8 1800_20E0 1800_20E8 1800_2100 1800_2CF8 1800_2CFC
Memory Space Base Register Memory Space Base Register Memory Space Base Register Space Base Register Arbitration Register Host Memory Space Base Register Host space Base Register Configuration Address Register Configuration Data Register Table 3.10 Register
Four general purpose channels1 move data between source destination resources such system memory, external devices (8-, 16-, 32-bit devices treated memory-mapped word-aligned devices). Using flexible, memory-based descriptor structure, four channels efficiently supports "scatter/gather" capability. RC32334 supports byte, half-word (16-bit), word, quad-word burst transfers that crossover quad-word boundaries automatically split into single-word transfers until quad-word boundary reached. controller also automatically prevents burst transfers from crossing page boundaries supports little- big-endian data conversions. restrictions include:
When source destination address constant devices), must word aligned. supported internal UART. Source incremented destination decremented Source decremented destination incremented.
Note that following transfers supported:
Additional information operations located RC32334/RC32332 User Reference Manual.
channels have DMA_RDY pins cannot used perform transfers with slow
devices. IDT79S334A Evaluation Board Manual February 2001
Theory Operation Design Notes
Address Space Decoding
Notes
Register Address Maps Channels
Base Address Channel 1800_1400 Register Name Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register Offset Address Effective Address Channel Base Offset
Table 3.11 Channel Register Mapping Base Address Channel 1800_1400 Offset Address Effective Address Channel Base Offset
Register Name Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Table 3.12 Channel Register Mapping Base Address Channel 1800_1900 Offset Address Effective Address Channel Base Offset
Register Name Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Table 3.13 Channel Register Mapping
IDT79S334A Evaluation Board Manual
February 2001
Theory Operation Design Notes
Address Space Decoding
Notes
Base Address Channel 1800_1900
Register Name Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Offset Address
Effective Address Channel Base Offset
Table 3.14 Channel Register Mapping
Expansion Interrupt Controller extends CPU's interrupt control collating RC32334 generated interrupts into single interrupt. When general purpose interrupt received, Interrupt Service Routine (ISR) first saves registers, checks Cause Register then checks Pending Interrupt Register. pending interrupt from RC32334, then checks Expansion Interrupt Controller Pending Interrupt Register. After treating/noting interrupt condition, resets pending interrupt writing corresponding Expansion Interrupt Clear Register. then exit restoring register executing instruction. register address mapping Expansion Interrupt Controller shown Table 3.15.
Expansion Interrupt Controller Address Mapping From 1800_0500 1800_05e8
Table 3.15 Expansion Interrupt Controller Address Mapping
RC32334 eight on-chip Timers: Three general purpose timers five timers that optionally dedicated Watchdog, time-out, time-out, DRAM refresh, WarmReset. Beginning from zero, these eight system timers count each system clock, timing after reaching programmable compare value resetting zero automatically. Uses these timers include real-time clock, cascaded real-time clock time-slice clock. register address mapping Timer controller shown Table 3.16. Additional information functional aspects these timers located RC32334/RC32332 User Reference Manual.
Timer Controller Address Mapping From 1800_0700 1800_0778
Table 3.16 Timer Controller Address Mapping
16550 UARTs enhanced version 16450 UART. Functionally same 16450 power-up, these UARTs into 16550 mode, which then relieves software overhead. This feature allows execution 16450 16550 compatible software. sets 16-byte buffers enabled during 16550 mode: receive data path transmit data path. read UART status time during operation. Status information includes type condition transfer operation, well error condition (parity, overrun, framing, break interrupt). baud rate generator included that divides down system clock 65K. baud rate generator provides clock driving transmitter receiver logic.
IDT79S334A Evaluation Board Manual February 2001
Theory Operation Design Notes
Interrupts
Notes
UART controller provides fully programmable serial characteristics such 8-bit characters; even, odd, parity generation detection; 1-1/2, stop generation. register address mapping UART Controller shown Table 3.17.
UART Controller Address Mapping From 1800_0800 1800_083C
Table 3.17 UART Controller Address
Interrupts
Both on-board interface interrupts assigned shown Table 3.18.
Interrupts INT0* INT1* 32334 (85C30) INTR INTA# INTB# INTC# INTD# INTB# INTC# INTD# High (Unused)
INT2* INT4* INT5* NMI*
Table 3.18 Interrupt Assignment S334A Board
IDT79S334A Evaluation Board Manual
February 2001
Theory Operation Design Notes
Interrupts
Notes
IDT79S334A Evaluation Board Manual
February 2001
Chapter
Schematics
Schematics
Notes
IDT79S334A Evaluation Board Manual
February 2001
DESCRIPTION
79RC32334 79RC32332 SODIMM SDRAM QUICKSWITCHES SDRAM DIMM CLOCKS, RESET, CONFIGURATION SWITCHES JTAG, EJTAG, EEPROM, INTERNAL UART LOGIC ANALYZER CONNECTORS LOGIC ANALYZER CONNECTORS SLOT QUICKSWITCHES EDGE CONNECTOR QUICKSWITCHES SLOT SLOT SLOT SLOT EDGE CONNECTOR DATA, ADDRESS BUFFERS EPLD SRAM EPROM/FLASH MEMORY DISPLAY, NVRAM, EXTERNAL UART POWER SUPPLY BYPASS CAPACITORS
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
TABLE CONTENTS SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
VCC_IO VCC_IO 5.1K OHMS 5.1K OHMS 5.1K OHMS 5.1K OHMS 5.1K OHMS
79RC32V334_150
PCI_CLK PCI_CONTROL PCI_RST PCI_LOCK PCI_REQ0 PCI_REQ1 PCI_REQ2 PCI_GNT0 PCI_GNT1 PCI_GNT2 PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_PERR VCC_IO PCI_SERR PCI_FRM PCI_STOP PCI_PAR OHMS OHMS PCI_CBE0 PCI_CBE1 PCI_CBE2 PCI_CBE3 P_RST P_LOCK P_REQ0 P_REQ1 P_REQ2 P_GNT0 P_GNT1 P_GNT2 P_IRDY P_TRDY PCI_CLK P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 M_DATA PCI_INT M_WAIT PCI_AD CPU_MCLK CPU_CRST CPU_NMI CPU_INT0 PCI_INTA PCI_INTB PCI_INTC PCI_INTD
79RC32V334_150
MCLK CRST INT0 INT1 INT2 INT4 INT5 M_CS0 M_CS1 M_CS2 M_CS3 M_CS4 M_CS5 M_OE M_WE0 M_WE1 M_WE2 M_WE3 M_245_OE OUTPUT_CLK SODIMM_ADDR M_ADR2 M_ADR3 M_ADR4 M_ADR5 M_ADR6 M_ADR7 M_ADR8 M_ADR9 M_ADR10 M_ADR11 M_ADR12 M_ADR13 M_ADR14 M_ADR15 M_ADR16 M_ADR17 M_ADR18 M_ADR19 M_ADR20 M_ADR21 M_ADR22 M_ADR23 M_ADR24 M_ADR25 SD_ADR2 SD_ADR3 SD_ADR4 SD_ADR5 SD_ADR6 SD_ADR7 SD_ADR8 SD_ADR9 SD_ADR10 SD_ADR11 SD_ADR12 SD_ADR13 SD_ADR14 SD_ADR15 SD_ADR16 SD_ADR17 SD_ADR18 SD_ADR19 SD_ADR20 SD_ADR21 SD_ADR22 D_T/R CPU_D_T/R
OHMS
M_WAIT
M_CS0 M_CS1 M_CS2 M_CS3 M_CS4 M_CS5
P_DEVSEL P_AD11 P_PERR P_SERR P_FRM P_STOP P_PAR P_CBE0 P_CBE1 P_CBE2 P_CBE3 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21
M_D0
VCC_IO
C139
M_D0 M_D1 M_D2 M_D3 M_D4 M_D5
M_OE M_WE0 M_WE1 M_WE2 M_WE3 M_245_OE
PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
10PF
PCI_AD15
M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18
M_D6 OUTPUT_CLK M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31
DMA_RDY0 DMA_RDY1
DMA_RDY0 P_AD22 DMA_RDY1 P_AD23 P_AD24 P_AD25
TIMER_TC0
TIMER_TC P_AD26 P_AD27 P_AD28
UART_CTS0 UART_RTS0 UART_DTR0 UART_DSR0 UART_RX0 UART_RX1
UART_CTS0 P_AD29 UART_RTS0 P_AD30 UART_DTR0 P_AD31 UART_DSR0 UART_RX0 UART_TX0 UART_RX1 UART_TX1
UART_TX0 UART_TX1
M_D19 M_D20 M_D21
3.3V
SPI_MISO SPI_MISO SPI_MOSI SPI_SS SPI_SCK JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TRST EJ_DCLK EJTAG_DCLK EJ_TMS EJ_DBUGBOOT RP12-A 33_OHM EJ_DCK EJ_TMS EJ_PCST0 EJ_PCST1 RP12-B RP12-C RP12-D 33_OHM 33_OHM 33_OHM EJTAG_PCST0 EJTAG_PCST1 EJTAG_PCST2 RP13-A JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK JTAG_TRST 33_OHM SPI_MOSI SPI_SS SPI_SCK EJTAG_TPC JTAG_TDO EJ_PCST2 EJ_PCST1 EJ_PCST0
M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31
SOD_ADR12 SOD_RAS SOD_CAS SOD_WE SOD_CKE SOD_CS0 SOD_CS1 SOD_CS2 SOD_CS3 SOD_BMSK0 SOD_BMSK1 SOD_BMSK2 SOD_BMSK3 SOD_S0 SOD_S1 SOD_245_OE SODIMM_CTL
3.3V
S_ADR12 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO S_RAS S_CAS S_WE S_CKE S_CS0 S_CS1 S_CS2 S_CS3 S_BMSK0 S_BMSK1 S_BMSK2 S_BMSK3 S_S0 S_S1
EJ_DBGBTEJ_PCST2
D_CPU_DMA D_CPU_ACK VCC_IO
DBG_DMA DBG_I/D DBG_ACK DBG_ADS
VCC_IO
D_CPU_I/D D_CPU_ADS
VCC_CORE
VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO
VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO
VCC_CORE
BGA_PLL_FILTER
VCC_P VCC_CORE VCC_CORE VCC_CORE VCC_CORE VSS_P VCC_CORE
10uF_16V
C146
10PF
OHMS_1/4W
0.1UF
C149
VCC_IO S_245_OE
U16-A
U16-B
RC32334-BGA
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
79RC32334 SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: PART NUMBER: 003-A1550-003 ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
79RC32V332_133
PCI_AD PCI_CLK PCI_CONTROL PCI_RST PCI_LOCK PCI_REQ0 PCI_REQ2 PCI_GNT0 PCI_GNT1 PCI_GNT2 PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_PERR PCI_SERR PCI_FRM PCI_STOP PCI_PAR PCI_CBE0 PCI_CBE1 PCI_CBE2 PCI_CBE3 P_RST P_LOCK P_REQ0 P_REQ2 P_GNT0 P_GNT1 P_GNT2 P_IRDY P_TRDY PCI_CLK P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 M_DATA M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 UART_RX0 UART_RX0 UART_TX0 UART_TX0 M_D22 M_D23 SPI_MISO SPI_MISO SPI_MOSI SPI_SS SPI_SCK JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TRST SPI_MOSI SPI_SS SPI_SCK M_D24 M_D25 M_D26 M_D27 JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK JTAG_TRST EJ_PCST0 EJ_PCST1 EJ_PCST2 JTAG_TDO M_D28 M_D29 M_D30 M_D31 VCC_IO EJ_DCLK EJ_TMS EJ_DBUGBOOT EJ_DCK EJ_TMS EJ_PCST0 EJ_PCST1 D_CPU_DMA D_CPU_ACK VCC_IO VCC_CORE DBG_DMA DBG_I/D DBG_ACK DBG_ADS D_CPU_I/D D_CPU_ADS VCC_CORE VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO S_ADR12 S_RAS S_CAS S_WE S_CKE S_CS0 S_CS1 S_CS2 S_CS3 S_BMSK0 S_BMSK1 S_BMSK2 S_BMSK3 S_S0 S_S1 SOD_ADR12 SOD_RAS SOD_CAS SOD_WE SOD_CKE SOD_CS0 SOD_CS1 SOD_CS2 SOD_CS3 SOD_BMSK0 SOD_BMSK1 SOD_BMSK2 SOD_BMSK3 SOD_S0 SOD_S1 SOD_245_OE M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_WAIT CPU_MCLK CPU_CRST CPU_NMI CPU_INT0 PCI_INTA
79RC32V332_133
MCLK CRST INT0 INT1 D_T/R CPU_D_T/R
3.3V
M_WAIT M_CS0 M_CS1 M_CS2 M_CS3 M_CS4 M_CS5 M_OE M_WE0 M_WE1 M_WE2 M_WE3 M_245_OE M_CS0 M_CS1 M_CS2 M_CS3 M_CS4 M_CS5 M_OE M_WE0 M_WE1 M_WE2 M_WE3 M_245_OE OUTPUT_CLK SODIMM_ADDR M_ADR2 M_ADR3 M_ADR4 M_ADR5 M_ADR6 M_ADR7 M_ADR8 M_ADR9 M_ADR10 M_ADR11 M_ADR12 M_ADR13 M_ADR14 M_ADR15 M_ADR16 M_ADR17 M_ADR18 M_ADR19 M_ADR20 M_ADR21 M_ADR22 SD_ADR2 SD_ADR3 SD_ADR4 SD_ADR5 SD_ADR6 SD_ADR7 SD_ADR8 SD_ADR9 SD_ADR10 SD_ADR11 SD_ADR12 SD_ADR13 SD_ADR14 SD_ADR15 SD_ADR16 SD_ADR17 SD_ADR18 SD_ADR19 SD_ADR20 SD_ADR21 SD_ADR22
P_DEVSEL P_AD11 P_PERR P_SERR P_FRM P_STOP P_PAR P_CBE0 P_CBE1 P_CBE2 P_CBE3 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31
M_D6 OUTPUT_CLK M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31
DMA_RDY0
DMA_RDY0
EJ_DBGBTEJ_PCST2
3.3V
PQFP_PLL_FILTER
VCC_P VCC_CORE VCC_CORE VCC_CORE VCC_CORE VSS_P VCC_CORE
10PF
OHMS_1/4W
10uF_16V
C151
0.1UF
C147
U17-B
VCC_IO S_245_OE
U17-A
SODIMM_CTL
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
RC32332-PQFP
79RC32332 SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: PART NUMBER: 400-A1550-003 ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
M_DATA +3.3V M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 SOD_BMSK0 SOD_BMSK1 SD_ADR2 SD_ADR3 SD_ADR4 M_D8 M_D9 M_D10 M_D11 OUTPUT_CLK M_D12 M_D13 M_D14 M_D15 SOD_CLK0 SOD_RAS SOD_WE SOD_S0 SOD_S1 OHMS
SDRAM_SODIMM
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 CKE1 (A12)
+3.3V
M_D0 M_D1 M_D2 M_D3
M_D4 M_D5 M_D6 M_D7
SOD_CS0 SOD_CS1
SD_ADR5 SD_ADR6 SD_ADR7
M_D8 M_D9 M_D10 M_D11
M_D12 M_D13 M_D14 M_D15
SOD_CKE
SOD_CAS OUTPUT_CLK
3.3V
(A13) DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SOD_CLK1 OHMS
C113
10PF
M_D16 M_D17 M_D18 M_D19
M_D16 M_D17 M_D18 M_D19
M_D20 M_D21 M_D22 M_D23
M_D20 M_D21 M_D22 M_D23
SD_ADR8 SD_ADR10
SD_ADR9 SD_ADR14
SD_ADR11 SOD_ADR12
SD_ADR15 SD_ADR13
SOD_BMSK2 SOD_BMSK3
M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31 +3.3V OHMS
10PF
SOD_CS2 SOD_CS3
M_D24 M_D25 M_D26 M_D27
SODIMM CLOCK CONFIGURATION
M_D28 M_D29 M_D30 M_D31 +3.3V
FROM FROM BUFFER
OHMS
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SODIMM_ADDR
SODIMM INTERFACE
SODIMM SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI DRAWN J.A./GAIL SWAMI
QS34XR245
OHMS
QS34XR245
M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7
M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15
DIMM_D0 DIMM_D1 DIMM_D2 DIMM_D3 DIMM_D4 DIMM_D5 DIMM_D6 DIMM_D7
M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23
DIMM_D8 DIMM_D9 DIMM_D10 DIMM_D11 DIMM_D12 DIMM_D13 DIMM_D14 DIMM_D15
M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31
DIMM_D16 DIMM_D17 DIMM_D18 DIMM_D19 DIMM_D20 DIMM_D21 DIMM_D22 DIMM_D23
DIMM_D24 DIMM_D25 DIMM_D26 DIMM_D27 DIMM_D28 DIMM_D29 DIMM_D30 DIMM_D31
M_DATA
DIMM_DATA
NOTE: DRAM DIMM OPERATION, INSTALL ENABLE QUICKSWITCHES.
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SODIMM OPERATION, REMOVE W10.
SDRAM QUICKSWITCHES SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
SDRAM DIMM INTERFACE
DIMM_DATA
+3.3V
+3.3V
+3.3V
+3.3V
DIMM_3V_NSTD
DIMM_D0 DIMM_D1 DIMM_D2 DIMM_D3 DIMM_D4 DIMM_D5 DIMM_D6 DIMM_D7 DIMM_D8 DIMM_D9 DIMM_D10 DIMM_D11 DIMM_D12 DIMM_D13 DIMM_D14 DIMM_D15 SOD_WE SOD_BMSK0 SOD_BMSK1 SOD_CS0 SODIMM_ADDR SD_ADR2 SD_ADR4 SD_ADR6 SD_ADR8 SD_ADR10 SOD_ADR12 SD_ADR15 DIMM_CLK0 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB0 DQMB1 DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 VREFF/NC CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 OHMS OHMS OHMS +3.3V DIMM_CLK2 DIMM_D12 DIMM_D13 DIMM_D14 DIMM_D15 SODIMM_ADDR SD_ADR3 SD_ADR5 SD_ADR7 SD_ADR9 SD_ADR11 SD_ADR14 SD_ADR13 DIMM_D8 DIMM_D9 DIMM_D10 DIMM_D11 SOD_CAS SOD_BMSK2 SOD_BMSK3 SOD_CS2 SOD_RAS DIMM_D5 DIMM_D6 DIMM_D7 SOD_CKE DIMM_D4 DIMM_D30 DIMM_D31 DIMM_D0 DIMM_D1 DIMM_D2 DIMM_D3 DIMM_D25 DIMM_D26 DIMM_D27 DIMM_D28 DIMM_D29 DIMM_D20 DIMM_D21 DIMM_D22 DIMM_D23 DIMM_D24 SOD_CS1 SOD_BMSK0 SOD_BMSK1 DIMM_D16 DIMM_D17 DIMM_D18 DIMM_D19 DIMM_CLK1 OHMS
DIMM_3V_NSTD
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB4 DQMB5 CKE0 DQMB6 DQMB7 RSVD RSVD DQ48 DQ49 DQ50 DQ51 DQ52 VREFF/NC DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 OHMS OHMS OHMS OHMS +3.3V DIMM_CLK3 DIMM_D28 DIMM_D29 DIMM_D30 DIMM_D31 DIMM_D24 DIMM_D25 DIMM_D26 DIMM_D27 DIMM_D21 DIMM_D22 DIMM_D23 DIMM_D20 DIMM_D16 DIMM_D17 DIMM_D18 DIMM_D19 SOD_CKE SOD_CS3 SOD_BMSK2 SOD_BMSK3
U13-A
OHMS
U13-B C122 10PF
C114
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SODIMM_CTL
C116
10PF
C115
10PF
SDRAM DIMM SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
10PF
+3.3V 5.1K OHMS 5.1K OHMS OHMS OHMS OHMS
RESET CONTROL LOGIC
QS5810
SCLK SDRAM0 SDRAM1 SDATA SDRAM2 SDRAM3 BUF_IN SDRAM4 SDRAM5 SDRAM6 SDRAM7 VCLK1
SPST_MOM
CPU_MCLK SOD_CLK0 SOD_CLK1 DIMM_CLK0 OHMS COMM
TL7705BC
RESIN SENSE RESET RESET OHMS
0.1UF C126
OHMS
EPLD_RST
DIMM_CLK1 DIMM_CLK2 DIMM_CLK3 EPLD_CLK CPU_LA_CLK0 CPU_LA_CLK1
50.00MHZ_100PPM
NC/OE
SDRAM9
3.3V
3.3V
0.1UF C100
0.1UF C102
0.01UF C103
0.1UF
0.01UF
+3.3V
VCLK1
+3.3V
SDRAM8
10uF_16V
+3.3V
VCLK2
GNDI
VDDI
120_OHM/100MHZ 0.01UF C205 0.1UF 0.1UF 0.01UF 0.1UF 0.01UF
120_OHM/100MHZ 0.01UF
PCI_HOST
SDRAM CLOCK GENERATION
+3.3V
RP11-A
RP11-B
RP11-C
RP11-D
RP10-A
RP10-B
RP10-C
RP10-D
RP15-A
RP15-B
RP15-C
RP15-D
RP14-A
RP14-B
RP14-C
+3.3V
5.1K OHMS
RP14-D
OHMS
OHMS
OHMS
74LVCH16244A
10K_OHM CPU_CRST VCLK2
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
10K_OHM
QS5810
SCLK SDRAM0 SDRAM1 SDATA SDRAM2 SDRAM3 BUF_IN SDRAM4 SDRAM5 SDRAM6 SDRAM7 SLT_PCI_CLK SLT_PCI_CLK1 SLT_PCI_CLK2 SLT_PCI_CLK3 SLT_PCI_CLK4 PCI_LA_CLK0 PCI_LA_CLK1 EPLD_PCI_CLK SD_ADR22 SD_ADR21 SD_ADR20 SD_ADR19 SD_ADR18 SD_ADR17 D_CPU_DMA D_CPU_ADS D_CPU_ACK D_CPU_I/D
10K_OHM
3.3V
DIPSW_8POS_SPST
SDRAM8 SDRAM9
33.00MHZ_100PPM
NC/OE
3.3V
0.1UF C206
0.1UF C215
0.1UF C217
0.01UF C216
0.01UF C218
DIPSW_8POS_SPST
EJ_PCST2 EJ_PCST1 EJ_PCST0
GNDI
VDDI
CLOCK GENERATION
MODE SETTINGS CONFIGURATION
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
CLOCKS, RESET, CONFIG SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI ENGINEER'S NAME: DRAWN J.A./GAIL SWAMI
0.1UF C204
VCC_IO
VCC_IO
SERIAL EEPROM INTERFACE
+3.3V 5.1K OHMS RP9-C 10K_OHM
10K_OHM 10K_OHM 10K_OHM
RP9-B
RP9-A RP9-D
JTAG CONNECTOR
NM93C46A
PCI_GNT1 SPI_MOSI JTAG_TMS JTAG_TRST JTAG_TDI JTAG_TDO
+3.3V
CONN_2X5_MALE
JTAG_TCK VCC_IO EJ_TMS
+3.3V
SPI_MISO
5.1K OHMS OHMS OHMS 5.1K OHMS
EJTAG CONNECTOR
OHMS OHMS VCC_IO
+3.3V
AT25256
HOLD JTAG_TRST JTAG_TDI EJTAG_TPC EJ_TMS JTAG_TCK EJ_RST
SPI_SCK SPI_SS
HDR_2X12_MALE
SPI_MOSI
EJTAG_PCST0 EJTAG_PCST1 EJTAG_PCST2 EJTAG_DCLK EJ_DBUGBOOT
OHMS +3.3V OHMS R100 OHMS
DB9_MALE
1.0uF_50V
MAX238
1.0uF_50V
INT_UART_PORT_B
1.0uF_50V UART_TX0 UART_DTR0 UART_RTS0 UART_TX1 UART_RX0 UART_DSR0 UART_CTS0 UART_RX1
1.0uF_50V
T1IN T2IN T3IN T4IN R1OUT R2OUT R3OUT R4OUT T1OUT T2OUT T3OUT T4OUT R1IN R2IN R3IN R4IN
DTR0 RTS0 DSR0 CTS0 DCD0 DSR0
DB9_MALE
DTR0 CTS0 RTS0
INT_UART_PORT_A
RS232 INTERFACE INTERNAL UART
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SHEET TITLE: JTAG, EJTAG, EEPROM, UART PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: DRAWN J.A./GAIL SWAMI
M_DATA
CONN-2X19-FEM
D_CPU_I/D M_D15 M_D14 M_D13 M_D12 M_D11 M_D10 M_D9 M_D8 M_D7 M_D6 M_D5 M_D4 M_D3 M_D2 M_D1 M_D0 D_CPU_DMA M_WE3 M_WE2 M_WE1 M_WE0 M_OE M_245_OE M_CS5 M_CS4 M_CS3 M_CS2 M_CS1 M_CS0 CPU_CRST CPU_NMI CPU_INT0 CPU_D_T/R EJTAG_PCST2 EJTAG_PCST1 EJTAG_PCST0 EJ_TMS EJ_DBUGBOOT JTAG_TDI EJTAG_TPC JTAG_TMS JTAG_TCK JTAG_TRST SPI_MISO SPI_MOSI SPI_SS SPI_SCK TIMER_TC0 EJTAG_DCLK
CONN-2X19-FEM
M_WAIT
DMA_RDY1 DMA_RDY0 UART_TX1 UART_TX0 UART_RX1 UART_RX0 UART_DSR0 UART_DTR0 UART_RTS0 UART_CTS0
SHLD1 SHLD2 SHLD3
SHLD4 SHLD5
SHLD1 SHLD2 SHLD3
SHLD4 SHLD5
SODIMM_ADDR
CONN-2X19-FEM
CPU_LA_CLK0 SD_ADR15 SD_ADR14 SD_ADR13 SD_ADR12 OHMS SD_ADR11 SD_ADR10 SD_ADR9 SD_ADR8 SD_ADR7 SD_ADR6 SD_ADR5 SD_ADR4 SD_ADR3 SD_ADR2 M_WE2 M_WE1 SOD_WE SOD_S1 SOD_S0 SOD_RAS SOD_CS3 SOD_CS2 SOD_CS1 SOD_CS0 OHMS SOD_CAS SOD_BMSK3 SOD_BMSK2 SOD_BMSK1 SOD_BMSK0 SOD_245_OE SOD_CKE SOD_ADR12 D_CPU_ADS CPU_LA_CLK1
CONN-2X19-FEM
M_D31 M_D30 M_D29 M_D28 M_D27 M_D26 M_D25 M_D24 M_D23 M_D22 M_D21 M_D20 M_D19 M_D18 M_D17 M_D16 D_CPU_ACK
10PF C124
SD_ADR21 SD_ADR20
10PF C123
SD_ADR19 SD_ADR18 SD_ADR17 SD_ADR16
SHLD1 SHLD2 SHLD3
SHLD4 SHLD5
SHLD1 SHLD2 SHLD3
SHLD4 SHLD5
SODIMM_CTL
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
LOGIC ANALYZER CONN SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: PART NUMBER: 003-A1550-003 ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
SLT_PCI_AD
PCI_LA_CLK0 SLT_PCI_PERR SLT_PCI_SERR SLT_PCI_STOP SLT_PCI_PAR SLT_PCI_CBE3 SLT_PCI_CBE2 SLT_PCI_CBE1 SLT_PCI_CBE0 SLT_PCI_LOCK PCI_REQ0_GNT0 SLT2_PCI_REQ PCI_GNT0_REQ0 SLT2_PCI_GNT SLT_PCI_IRDY SLT_PCI_TRDY SLT_PCI_DEVSEL
CONN-2X19-FEM
SLT_PCI_AD15 SLT_PCI_AD14 SLT_PCI_AD13 SLT_PCI_AD12 SLT_PCI_AD11 SLT_PCI_AD10 SLT_PCI_AD9 SLT_PCI_AD8 SLT_PCI_AD7 SLT_PCI_AD6 SLT_PCI_AD5 SLT_PCI_AD4 SLT_PCI_AD3 SLT_PCI_AD2 SLT_PCI_AD1 SLT_PCI_AD0 SLT1_PCI_GNT SLT1_PCI_REQ SLT_PCI_INTD SLT_PCI_INTC SLT_PCI_INTB SLT_PCI_INTA
CONN-2X19-FEM
SLT_PCI_FRM SLT_PCI_AD31 SLT_PCI_AD30 SLT_PCI_AD29 SLT_PCI_AD28 SLT_PCI_AD27 SLT_PCI_AD26 SLT_PCI_AD25 SLT_PCI_AD24 SLT_PCI_AD23 SLT_PCI_AD22 SLT_PCI_AD21 SLT_PCI_AD20 SLT_PCI_AD19 SLT_PCI_AD18 SLT_PCI_AD17 SLT_PCI_AD16
PCI_LA_CLK1
SHLD1 OHMS R113 SHLD2 SHLD3
SHLD4 R114 SHLD5 OHMS
SHLD1 SHLD2 SHLD3
SHLD4 SHLD5
C249
C248
10PF
10PF
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
LOGIC ANALYZER CONN SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
SLT_PCI_INT SLT_PCI_CONTROL PCI_CONTROL PCI_INT SLT_PCI_AD PCI_AD
+3.3V
RP1-C
RP5-D
RP5-B
RP5-C
RP8-D
RP4-D
RP3-A
+3.3V
RP8-A 2.7K
QS34XR245
5.1K OHMS SLT_PCI_EN 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K SLT_PCI_EN RP8-B RP8-C RP5-A RP1-A RP1-B RP1-D RP2-B RP2-C
QS34XR245
2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_INTC PCI_INTD PCI_CBE0 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_CBE1 PCI_PAR PCI_SERR PCI_PERR PCI_LOCK PCI_STOP PCI_DEVSEL PCI_TRDY PCI_IRDY PCI_FRM PCI_CBE2
RP2-D
RP3-B
RP3-C
RP3-D
RP4-A
RP4-B
THESE RESISTORS WILL AFTER FOURTH SLOT BOARD
2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K
+3.3V
SLT_PCI_EN
EDG_PCI_EN
MODE CONFIGURATION HOST MODE (SLOT) SATELLITE MODE (EDGE)
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
QUICKSWITCHES HOST MODE
10PF C188
SLT_PCI_AD0 SLT_PCI_AD1 SLT_PCI_AD2 SLT_PCI_AD3 SLT_PCI_AD4 SLT_PCI_AD5 SLT_PCI_AD6 SLT_PCI_AD7
PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_CBE3 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_REQ0 PCI_GNT0 PCI_CLK
SLT_PCI_INTC SLT_PCI_INTD SLT_PCI_CBE0 SLT_PCI_AD8 SLT_PCI_AD9 SLT_PCI_AD10 SLT_PCI_AD11 SLT_PCI_AD12 SLT_PCI_AD13 SLT_PCI_AD14 SLT_PCI_AD15 SLT_PCI_CBE1 SLT_PCI_PAR SLT_PCI_SERR SLT_PCI_PERR SLT_PCI_LOCK SLT_PCI_STOP SLT_PCI_DEVSEL SLT_PCI_TRDY SLT_PCI_IRDY SLT_PCI_FRM SLT_PCI_CBE2
PCI_REQ1 PCI_INTB PCI_REQ2 PCI_GNT2 PCI_INTA
SLT_PCI_AD16 SLT_PCI_AD17 SLT_PCI_AD18 SLT_PCI_AD19 SLT_PCI_AD20 SLT_PCI_AD21 SLT_PCI_AD22 SLT_PCI_AD23
SLT_PCI_CBE3 SLT_PCI_AD24 SLT_PCI_AD25 SLT_PCI_AD26 SLT_PCI_AD27 SLT_PCI_AD28 SLT_PCI_AD29 SLT_PCI_AD30 SLT_PCI_AD31 SLT_PCI_INTB SLT_PCI_INTA OHMS SLT2_PCI_REQ SLT2_PCI_GNT PCI_REQ0_GNT0 PCI_GNT0_REQ0 SLT_PCI_CLK
SLOT QUICKSWITCHES SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
EDG_PCI_CONTROL PCI_CONTROL PCI_INT EDG_PCI_AD PCI_AD
QS34XR245
5.1K OHMS EDG_PCI_EN
QS34XR245
EDG_PCI_EN
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_INTC PCI_INTD PCI_CBE0 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_CBE1 PCI_PAR PCI_SERR PCI_PERR PCI_LOCK PCI_STOP PCI_DEVSEL PCI_TRDY PCI_IRDY PCI_FRM PCI_CBE2
EDG_PCI_AD0 EDG_PCI_AD1 EDG_PCI_AD2 EDG_PCI_AD3 EDG_PCI_AD4 EDG_PCI_AD5 EDG_PCI_AD6 EDG_PCI_AD7 EDG_PCI_CBE0 EDG_PCI_AD8 EDG_PCI_AD9 EDG_PCI_AD10 EDG_PCI_AD11 EDG_PCI_AD12 EDG_PCI_AD13 EDG_PCI_AD14 EDG_PCI_AD15 EDG_PCI_CBE1 EDG_PCI_PAR EDG_PCI_SERR EDG_PCI_PERR EDG_PCI_LOCK EDG_PCI_STOP EDG_PCI_DEVSEL EDG_PCI_TRDY EDG_PCI_IRDY EDG_PCI_FRM EDG_PCI_CBE2 PCI_CLK +3.3V
PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_CBE3 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_REQ0 PCI_GNT0
PCI_REQ1 PCI_INTB PCI_REQ2 PCI_GNT2 PCI_INTA
EDG_PCI_AD16 EDG_PCI_AD17 EDG_PCI_AD18 EDG_PCI_AD19 EDG_PCI_AD20 EDG_PCI_AD21 EDG_PCI_AD22 EDG_PCI_AD23 EDG_PCI_CBE3 EDG_PCI_AD24 EDG_PCI_AD25 EDG_PCI_AD26 EDG_PCI_AD27 EDG_PCI_AD28 EDG_PCI_AD29 EDG_PCI_AD30 EDG_PCI_AD31 EDG_PCI_REQ EDG_PCI_GNT EDG_PCI_IDSEL EDG_PCI_INTA EDG_PCI_CLK +3.3V
+3.3V
PCI_EPLD_GNT0 5.1K OHMS 5.1K OHMS
PCI_REQ0_GNT0 +3.3V
PCI_EPLD_REQ1
ARBITER CONFIGURATION
INSTALLED INSTALLED
SLT1_PCI_REQ
PCI_GNT0_REQ0 PCI_EPLD_REQ0 PCI_EPLD_GNT1 SLT1_PCI_GNT
INTERNAL ARBITER INSTALLED
EXTERNAL ARBITER INSTALLED
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
QUICKSWITCHES SATELLITE MODE
SHEET TITLE: CONN QUICKSWITCHES PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
+3.3V -12V SLT_PCI_CONTROL
+12V +3.3V 5.1K OHMS 5.1K OHMS
SLT_PCI_AD
5.1K OHMS 5.1K OHMS 5.1K OHMS SLT_PCI_INTB SLT_PCI_INTD
PCI_32BIT_ TRST -12V
INTB INTD PRSNT1 PRSNT2 +5V(IO) AD31 AD29 AD27 AD25 +3.3V C/BE3 AD23 AD21 AD19 +3.3V AD17 C/BE2 IRDY +3.3V DEVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 M66EN +12V INTA INTC +5V(IO) +5V(IO) AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME TRDY STOP +3.3V SDONE AD15 +3.3V AD13 AD11 AD09
5.1K OHMS SLT_PCI_FRM 5.1K OHMS 5.1K OHMS SLT_PCI_AD2 SLT_PCI_AD0 SLT_PCI_AD6 SLT_PCI_AD4 SLT_PCI_CBE0 SLT_PCI_AD9 SLT_PCI_AD13 SLT_PCI_AD11 SLT_PCI_AD15 SLT_PCI_PAR SLT_PCI_STOP SLT_PCI_TRDY SLT_PCI_AD18 SLT_PCI_AD16 SLT_PCI_AD22 SLT_PCI_AD20 SLT_PCI_AD24 SLT_PCI_AD12 SLT_PCI_AD28 SLT_PCI_AD26 SLT_PCI_AD30 SLT1_PCI_GNT PCI_RST SLT_PCI_INTA SLT_PCI_INTC 5.1K OHMS
0.1UF C186
0.1UF C197
SLT_PCI_CLK1 SLT1_PCI_REQ SLT_PCI_AD31 OHMS SLT_PCI_AD29 SLT_PCI_AD27 SLT_PCI_AD25 SLT_PCI_CBE3 SLT_PCI_AD23 SLT_PCI_AD21 SLT_PCI_AD19 SLT_PCI_AD17 SLT_PCI_CBE2 SLT_PCI_IRDY SLT_PCI_DEVSEL SLT_PCI_LOCK +3.3V SLT_PCI_PERR 5.1K OHMS SLT_PCI_SERR SLT_PCI_CBE1 SLT_PCI_AD14
10PF C199
R103
M66EN
SLT_PCI_AD12
0.1UF C187
SLT_PCI_AD10
SLT_PCI_AD8 SLT_PCI_AD7 SLT_PCI_AD5 SLT_PCI_AD3 SLT_PCI_AD1
C/BE0 +3.3V AD06 AD04 AD02 AD00 +5V(IO) REQ64
AD08 AD07 +3.3V AD05 AD03 AD01 +5V(IO) ACK64
5.1K OHMS
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
CONNECTOR-1
SLOT SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
+3.3V -12V SLT_PCI_CONTROL
+12V +3.3V 5.1K OHMS 5.1K OHMS
SLT_PCI_AD
5.1K OHMS 5.1K OHMS 5.1K OHMS SLT_PCI_INTC SLT_PCI_INTA
PCI_32BIT_ TRST -12V
INTB INTD PRSNT1 PRSNT2 +5V(IO) AD31 AD29 AD27 AD25 +3.3V C/BE3 AD23 AD21 AD19 +3.3V AD17 C/BE2 IRDY +3.3V DEVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 M66EN +12V INTA INTC +5V(IO) +5V(IO) AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME TRDY STOP +3.3V SDONE AD15 +3.3V AD13 AD11 AD09
SLT_PCI_AD2 SLT_PCI_AD0 SLT_PCI_AD6 SLT_PCI_AD4 SLT_PCI_CBE0 5.1K OHMS SLT_PCI_AD9 SLT_PCI_AD13 SLT_PCI_AD11 SLT_PCI_AD15 SLT_PCI_PAR SLT_PCI_STOP SLT_PCI_TRDY SLT_PCI_FRM SLT_PCI_AD18 SLT_PCI_AD16 5.1K OHMS 5.1K OHMS SLT_PCI_AD22 SLT_PCI_AD20 SLT_PCI_AD24 SLT_PCI_AD14 SLT_PCI_AD28 SLT_PCI_AD26 SLT_PCI_AD30 SLT2_PCI_GNT PCI_RST SLT_PCI_INTB SLT_PCI_INTD 5.1K OHMS
0.1UF C202
0.1UF C212
SLT_PCI_CLK2 SLT2_PCI_REQ OHMS SLT_PCI_AD31 SLT_PCI_AD29 SLT_PCI_AD27 SLT_PCI_CBE3 SLT_PCI_AD23 SLT_PCI_AD21 SLT_PCI_AD19 SLT_PCI_AD17 SLT_PCI_CBE2 SLT_PCI_IRDY SLT_PCI_DEVSEL SLT_PCI_LOCK SLT_PCI_PERR SLT_PCI_SERR SLT_PCI_CBE1 SLT_PCI_AD14 SLT_PCI_AD12 SLT_PCI_AD10 M66EN
10PF C214
SLT_PCI_AD25
0.1UF C201
SLT_PCI_AD8 SLT_PCI_AD7 SLT_PCI_AD5 SLT_PCI_AD3 SLT_PCI_AD1
AD08 AD07 +3.3V AD05 AD03 AD01 +5V(IO) ACK64 C/BE0 +3.3V AD06 AD04 AD02 AD00 +5V(IO) REQ64
5.1K OHMS
CONNECTOR-2
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SLOT SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAI/KASI DRAWN J.A./GAIL SWAMI
+3.3V -12V SLT_PCI_CONTROL
+12V +3.3V +3.3V 5.1K OHMS +3.3V 5.1K OHMS
SLT_PCI_AD
+3.3V 5.1K OHMS +3.3V 5.1K OHMS 5.1K OHMS SLT_PCI_INTB SLT_PCI_INTD
PCI_32BIT_3.3V TRST -12V
INTB INTD PRSNT1 PRSNT2 +3.3(IO) AD31 AD29 AD27 AD25 +3.3V C/BE3 AD23 AD21 AD19 +3.3V AD17 C/BE2 IRDY +3.3V DEVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 M66EN AD08 AD07 +3.3V AD05 AD03 AD01 +12V INTA INTC +3.3(IO) +3.3(IO) AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME TRDY STOP +3.3V SDONE AD15 +3.3V AD13 AD11 AD09 C/BE0 +3.3V AD06 AD04 AD02 AD00
SLT_PCI_AD2 SLT_PCI_AD0 SLT_PCI_AD6 SLT_PCI_AD4 SLT_PCI_CBE0 +3.3V 5.1K OHMS SLT_PCI_AD9 SLT_PCI_AD13 SLT_PCI_AD11 SLT_PCI_AD15 SLT_PCI_PAR SLT_PCI_STOP SLT_PCI_TRDY SLT_PCI_FRM SLT_PCI_AD18 SLT_PCI_AD16 +3.3V 5.1K OHMS +3.3V 5.1K OHMS SLT_PCI_AD22 SLT_PCI_AD20 SLT_PCI_AD24 SLT_PCI_AD12 SLT_PCI_AD28 SLT_PCI_AD26 SLT_PCI_AD30 SLT1_PCI_GNT PCI_RST SLT_PCI_INTA SLT_PCI_INTC 5.1K OHMS
0.1UF C221
0.1UF C230
SLT_PCI_CLK3 SLT1_PCI_REQ SLT_PCI_AD31 OHMS SLT_PCI_AD29 SLT_PCI_AD27 SLT_PCI_AD25 SLT_PCI_CBE3 SLT_PCI_AD23 SLT_PCI_AD21 SLT_PCI_AD19 SLT_PCI_AD17 SLT_PCI_CBE2 SLT_PCI_IRDY SLT_PCI_DEVSEL SLT_PCI_LOCK SLT_PCI_PERR SLT_PCI_SERR SLT_PCI_CBE1 SLT_PCI_AD14 SLT_PCI_AD12 SLT_PCI_AD10 M66EN
3.3V
10PF C232
0.1UF C220
SLT_PCI_AD8 SLT_PCI_AD7 SLT_PCI_AD5 SLT_PCI_AD3 SLT_PCI_AD1
+3.3V 5.1K OHMS
+3.3(IO) +3.3(IO) ACK64 REQ64
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
+3.3V CONNECTOR-1
SLOT SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
+3.3V -12V SLT_PCI_CONTROL
+12V +3.3V +3.3V 5.1K OHMS +3.3V 5.1K OHMS R106
SLT_PCI_AD
+3.3V 5.1K OHMS +3.3V 5.1K OHMS 5.1K OHMS R111 SLT_PCI_INTC SLT_PCI_INTA
PCI_32BIT_3.3V TRST -12V
INTB INTD PRSNT1 PRSNT2 +3.3(IO) AD31 AD29 AD27 AD25 +3.3V C/BE3 AD23 AD21 AD19 +3.3V AD17 C/BE2 IRDY +3.3V DEVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 M66EN AD08 AD07 +3.3V AD05 AD03 AD01 +12V INTA INTC +3.3(IO) +3.3(IO) AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME TRDY STOP +3.3V SDONE AD15 +3.3V AD13 AD11 AD09 C/BE0 +3.3V AD06 AD04 AD02 AD00
R107 SLT_PCI_INTB SLT_PCI_INTD PCI_RST SLT2_PCI_GNT SLT_PCI_AD30 SLT_PCI_AD28 SLT_PCI_AD26 SLT_PCI_AD24 SLT_PCI_AD14 SLT_PCI_AD22 SLT_PCI_AD20 SLT_PCI_AD18 SLT_PCI_AD16 +3.3V 5.1K OHMS SLT_PCI_FRM R105 +3.3V 5.1K OHMS R104 SLT_PCI_TRDY SLT_PCI_STOP SLT_PCI_PAR SLT_PCI_AD15 SLT_PCI_AD13 SLT_PCI_AD11 SLT_PCI_AD9 SLT_PCI_CBE0 +3.3V 5.1K OHMS SLT_PCI_AD4 SLT_PCI_AD2 SLT_PCI_AD0 R108 SLT_PCI_AD6 5.1K OHMS
R110
R101
0.1UF C247
0.1UF C235
SLT_PCI_CLK4 SLT2_PCI_REQ SLT_PCI_AD31 OHMS R109 SLT_PCI_AD29 SLT_PCI_AD27 SLT_PCI_AD25 SLT_PCI_CBE3 SLT_PCI_AD23 SLT_PCI_AD21 SLT_PCI_AD19 SLT_PCI_AD17 SLT_PCI_CBE2 SLT_PCI_IRDY SLT_PCI_DEVSEL SLT_PCI_LOCK SLT_PCI_PERR SLT_PCI_SERR SLT_PCI_CBE1 SLT_PCI_AD14 SLT_PCI_AD12 SLT_PCI_AD10 M66EN
3.3V
10PF C246
0.1UF C233
SLT_PCI_AD8 SLT_PCI_AD7 SLT_PCI_AD5 SLT_PCI_AD3 SLT_PCI_AD1
+3.3V 5.1K OHMS
R112
+3.3(IO) +3.3(IO) ACK64 REQ64
+3.3V CONNECTOR-2
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SLOT SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
R102
EDG_PCI_CONTROL EDG_PCI_AD
EDG_PCI_CLK EDG_PCI_REQ EDG_PCI_AD31 EDG_PCI_AD29 EDG_PCI_AD27 EDG_PCI_AD25 EDG_PCI_CBE3 EDG_PCI_AD23 EDG_PCI_AD21 EDG_PCI_AD19 EDG_PCI_AD17 EDG_PCI_CBE2 EDG_PCI_IRDY EDG_PCI_DEVSEL EDG_PCI_LOCK EDG_PCI_PERR EDG_PCI_SERR EDG_PCI_CBE1 EDG_PCI_AD14 EDG_PCI_AD12 EDG_PCI_AD10 M66EN EDG_PCI_AD8 EDG_PCI_AD7 EDG_PCI_AD5 EDG_PCI_AD3 EDG_PCI_AD1
PCI_32BIT TRST -12V
INTB INTD PRSNT1 PRSNT2 AD31 AD29 AD27 AD25 +3.3V C/BE3 AD23 AD21 AD19 +3.3V AD17 C/BE2 IRDY +3.3V DEVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 M66EN +12V INTA INTC AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME TRDY STOP +3.3V SDONE AD15 +3.3V AD13 AD11 AD09
EDG_PCI_AD2 EDG_PCI_AD0 EDG_PCI_AD6 EDG_PCI_AD4 EDG_PCI_CBE0 EDG_PCI_AD9 EDG_PCI_AD13 EDG_PCI_AD11 EDG_PCI_AD15 EDG_PCI_PAR EDG_PCI_STOP EDG_PCI_TRDY EDG_PCI_FRM EDG_PCI_AD18 EDG_PCI_AD16 EDG_PCI_AD22 EDG_PCI_AD20 EDG_PCI_AD24 EDG_PCI_IDSEL EDG_PCI_AD28 EDG_PCI_AD26 EDG_PCI_AD30 EDG_PCI_GNT EDG_PCI_RST EDG_PCI_INTA
3.3V
C/BE0 +3.3V AD06 AD04 AD02 AD00 REQ64
AD08 AD07 +3.3V AD05 AD03 AD01 ACK64
NOTE: +5V, +3.3V, +12V -12V CONNECTED EDGE CONNECTOR. SATELLITE MODE OPERATION, EXTERNAL SUPPLY CONNECTOR J13.
UNIVERSAL EDGE CONNECTOR
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
CONN SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
SODIMM_ADDR BAS16
SRAM_DATA
74LVCH16245A
M_245_OE CPU_D_T/R M_DATA M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 1DIR 2DIR
QS34XR245
74LVCH16244A
0.1UF
0.1UF
0.01UF
OHMS
0.01UF
3.3V
SRAM_D0 SRAM_D1 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_D8 SRAM_D9 SRAM_D10 SRAM_D11 SRAM_D12 SRAM_D13 SRAM_D14 SRAM_D15 SRAM_D0 SRAM_D1 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_D8 SRAM_D9 SRAM_D10 SRAM_D11 SRAM_D12 SRAM_D13 SRAM_D14 SRAM_D15 SRAM_D16 SRAM_D17 SRAM_D18 SRAM_D19 SRAM_D20 SRAM_D21 SRAM_D22
3.3V
SD_ADR2 SD_ADR3 SD_ADR4 SD_ADR5 SD_ADR6 M_WE0 M_WE1 M_WE2 M_WE3 MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7
MEM/IO_ADDRESS
74LVCH16245A
1DIR 2DIR
SRAM_D23 SRAM_D24 SRAM_D25 SRAM_D26 SRAM_D27
M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31
3.3V
SRAM_D28 SRAM_D16 SRAM_D17 SRAM_D18 SRAM_D19 SRAM_D20 SRAM_D21 SRAM_D22 SRAM_D23 SRAM_D24 SRAM_D25 SRAM_D26 SRAM_D27 SRAM_D28 SRAM_D29 SRAM_D30 SRAM_D31 SRAM_D29 SRAM_D30 SRAM_D31
MEM/IO_D0 MEM/IO_D1 MEM/IO_D2 MEM/IO_D3 MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 MEM/IO_D7 MEM/IO_D8 MEM/IO_D9 MEM/IO_D10 MEM/IO_D11 MEM/IO_D12 MEM/IO_D13 MEM/IO_D14 MEM/IO_D15 MEM/IO_D16 MEM/IO_D17 MEM/IO_D18 MEM/IO_D19 MEM/IO_D20 MEM/IO_D21 MEM/IO_D22 MEM/IO_D23 MEM/IO_D24 MEM/IO_D25 MEM/IO_D26 MEM/IO_D27 MEM/IO_D28 MEM/IO_D29 MEM/IO_D30 MEM/IO_D31
SD_ADR7
MEM/IO_WE0 MEM/IO_WE1 MEM/IO_WE2 MEM/IO_WE3
74LVCH16244A
3.3V
SD_ADR8 SD_ADR9 SD_ADR10 SD_ADR11 SD_ADR12 SD_ADR13 SD_ADR14 SD_ADR15 SD_ADR16 SD_ADR17 SD_ADR18 SD_ADR19 SD_ADR20 SD_ADR21 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19 MEM/IO_ADR20 MEM/IO_ADR21
MEM/IO_DATA
DATA ADDRESS BUFFERS
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
DATA, ADDRESS BUFFERS SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: DRAWN J.A./GAIL SWAMI
EPLD
+3.3V 5.1K OHMS +3.3V
EPM7128AE_5
VCCIO VCCIO VCCIO
EPLD_CLK EPLD_RST
GCLK1/IN GCLR/IN OE1/IN
VCCIO VCCIO VCCIO
EPLD_PCI_CLK SCC_INT SCC_RD SCC_WR SCC_CS SCC_CLK LED_CS LED_CLR LED_WE NV_WE NV_NE NV_CS IO_CS C166 10PF C165 10PF MEM/IO_WE0 MEM/IO_WE1 MEM/IO_WE2 MEM/IO_WE3 EJ_RST CPU_CRST CPU_INT0 CPU_NMI MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 M_CS0 M_CS1 M_CS2 M_CS3 M_CS4 M_CS5 M_OE M_WAIT MEM/IO_ADDRESS OHMS OHMS
OE2/IN/GCLK2 SRAM_CS SRAM_BE0 SRAM_BE1 SRAM_BE2 SRAM_BE3 SRAM_WE EPLD_TDI EPLD_TMS EPLD_TCK EPLD_TDO JUNK PCI_EPLD_GNT0 PCI_EPLD_GNT1 SLT2_PCI_GNT OHMS PCI_EPLD_REQ0 PCI_EPLD_REQ1 SLT2_PCI_REQ M66EN PCI_HOST EXT_ARB_ENB PCI_RST EDG_PCI_RST SLT_PCI_PERR SLT_PCI_STOP SLT_PCI_TRDY SLT_PCI_IRDY SLT_PCI_DEVSEL R115 SLT_PCI_FRM SLT_PCI_INTA SLT_PCI_INTB SLT_PCI_INTC SLT_PCI_INTD JTAG_RST_EN OHMS +3.3V +3.3V
3.3V
TDI/IO TMS/IO TCK/IO TDO/IO
OHMS
OHMS
CONN_2X5_MALE
EPLD_TCK EPLD_TDO EPLD_TMS
EPLD_TDI
OHMS
JTAG INTERFACE ALTERA EPLD SYSTEM PROGRAMMABLE)
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
EPLD SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
71V416S_15NS
SRAM_CS M_OE SRAM_WE SRAM_BE0 SRAM_BE1 MEM/IO_ADDRESS MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19 MEM/IO_ADR20 SRAM_DATA
3.3V
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 SRAM_D0 SRAM_D1 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_D8 SRAM_D9 SRAM_D10 SRAM_D11 SRAM_D12 SRAM_D13 SRAM_D14 SRAM_D15
71V416S_15NS
SRAM_BE2 SRAM_BE3
3.3V
MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19 MEM/IO_ADR20 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 SRAM_D16 SRAM_D17 SRAM_D18 SRAM_D19 SRAM_D20 SRAM_D21 SRAM_D22 SRAM_D23 SRAM_D24 SRAM_D25 SRAM_D26 SRAM_D27 SRAM_D28 SRAM_D29 SRAM_D30 SRAM_D31
SRAM INTERFACE
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
SRAM SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
MEM/IO_DATA M_CS0 M_OE
M27C801_100
OE/VPP
M27C801_100
OE/VPP
M27C801_100
OE/VPP
MEM/IO_WE1 MEM/IO_WE2 MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_D0 MEM/IO_D1 MEM/IO_D2 MEM/IO_D3 MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 MEM/IO_D7 MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19
MEM/IO_D0 MEM/IO_D1 MEM/IO_D2 MEM/IO_D3 MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 MEM/IO_D7 MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19
MEM/IO_D16 MEM/IO_D17 MEM/IO_D18 MEM/IO_D19 MEM/IO_D20 MEM/IO_D21 MEM/IO_D22 MEM/IO_D23
MEM/IO_ADR18 MEM/IO_WE0 MEM/IO_ADR18 MEM/IO_ADR19 MEM/IO_ADR20 MEM/IO_ADR2 MEM/IO_WE0 MEM/IO_ADR20 MEM/IO_ADR8 MEM/IO_WE2 MEM/IO_ADR20 MEM/IO_WE1 MEM/IO_ADR20 MEM/IO_WE3 MEM/IO_ADR20 MEM/IO_ADR21 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7
M27C801_100
OE/VPP
M27C801_100
OE/VPP
MEM/IO_D8 MEM/IO_D9 MEM/IO_D10 MEM/IO_D11 MEM/IO_D12 MEM/IO_D13 MEM/IO_D14 MEM/IO_D15 MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 MEM/IO_ADR9 MEM/IO_ADR10 MEM/IO_ADR11 MEM/IO_ADR12 MEM/IO_ADR13 MEM/IO_ADR14 MEM/IO_ADR15 MEM/IO_ADR16 MEM/IO_ADR17 MEM/IO_ADR18 MEM/IO_ADR19
MEM/IO_D24 MEM/IO_D25 MEM/IO_D26 MEM/IO_D27 MEM/IO_D28 MEM/IO_D29 MEM/IO_D30 MEM/IO_D31
MEM/IO_ADDRESS
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
EPROM/FLASH INTERFACE
EPROM/FLASH MEMORY SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
MEM/IO_DATA MEM/IO_ADDRESS
DSPLY_DLR2416
LED_CS LED_CLR LED_WE MEM/IO_WE1 MEM/IO_WE2 MEM/IO_ADR2 MEM/IO_D0 MEM/IO_D1 MEM/IO_D2 MEM/IO_D3 MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 MEM/IO_ADR2 MEM/IO_ADR3 MEM/IO_ADR3 MEM/IO_ADR4 MEM/IO_ADR5 MEM/IO_ADR6 MEM/IO_ADR7 MEM/IO_ADR8 NV_WE NV_NE NV_CS M_OE
X20C04J-15
MEM/IO_D0 MEM/IO_D1 MEM/IO_D2 MEM/IO_D3 MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 MEM/IO_D7
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
ALPHANUMERIC DISPLAY INTERFACE
IO_CS
NVRAM INTERFACE
FCT3244A
MEM/IO_D0 MEM/IO_D1
MEM/IO_DATA
3.3V
MEM/IO_D2 MEM/IO_D3 OHMS MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 MEM/IO_D7
PCI_INTA PCI_INTB PCI_INTC PCI_INTD M66EN SCC_INT PCI_HOST UART_DCD0
AM85C30_16
SCC_CLK SCC_CS SCC_RD SCC_WR MEM/IO_ADR3 MEM/IO_ADR2 PCLK MEM/IO_D0 MEM/IO_D1 MEM/IO_D2 MEM/IO_D3 MEM/IO_D4 MEM/IO_D5 MEM/IO_D6 1.0uF_50V MEM/IO_D7
DB9_MALE MAX238
1.0uF_50V TXDA RXDA
SCC_IACK INTACK SCC_INT
RXDA RXDA RTXCA CTSA DCDA TXDA TRXCA SYNCA W/REQA DTR/REQA RTSA TXDB DMA_RDY0 TXDA
3.6864MHZ_100PPM
NC/OE
1.0uF_50V TXDA RXDA RXDB
T1IN T2IN T3IN T4IN R1OUT R2OUT R3OUT R4OUT T1OUT T2OUT T3OUT T4OUT R1IN R2IN R3IN R4IN
1.0uF_50V TXDA RXDA TXDB
EXT_UART_PORT_A
DB9_MALE
TXDB
RXDB DCD0 RXDB
RXDB
RXDB RTXCB CTSB DCDB
TXDB TRXCB SYNCB W/REQB DTR/REQB RTSB
TXDB UART_DCD0
DMA_RDY1
EXT_UART_PORT_B
EXTERNAL UART INTERFACE
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
DISPLAY, NVRAM, UART SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: RITESH KAPAHI/KASI ENGINEER'S NAME: J.A./GAIL SWAMI DRAWN
POWER SUPPLY CONNECTOR HOST MODDE
-12V +12V
CONN_PWR_SPLY
5V_IN
BNX005 22UF_25V 22UF_25V
+3.3V
+2.5V
MIC39300-2.5
5V_IN
22UF_25V
10uF_16V
PSGND
22UF_25V
VCC_CORE PSGND PSGND
+2.5V
+3.3V
LT1584CT-3.3
CONNECTOR SATELLITE MODE
10uF_16V
+12V 5V_IN
GND/ADJ
PWR_4PIN_VERT
22UF_25V
VCC_IO
+2.5V
+3.3V
POWER-ON LED'S
+3.3V +2.5V
PSGND
PSGND
PWR_4PIN_VERT
22UF_25V
OHMS
OHMS
22UF_25V
VOLTAGE CONFIGURATION VCC_CORE: +2.5V VCC_CORE: +3.3V VCC_IO: +2.5V VCC_IO: +3.3V
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
POWER SUPPLY SHEET TITLE: PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
CONNECTOR VARIABLE POWER SUPPLY
OHMS
VCC_IO
VCC_CORE
22UF_25V
+3.3V
47uF_10V
GND/ADJ
MTG1 FD10 MTG3 FD26 FD24 FD13 FD25 FD22 FD20 FD19 FD17 FD18 FD23 FD15 FD21 MTG5 MTG7 FD12 FD11 MTG4 MTG6
MTG8
MTG2
FD16
FD14
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
0.1UF C118 0.1UF C119 0.1UF C120 0.1UF C121 0.1UF 0.01UF 0.01UF C143 0.01UF 0.01UF C226 0.01UF 0.01UF C164 0.01UF 0.1UF C211 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF C144 0.01UF 0.01UF 0.1UF C104 0.1UF C117 0.1UF 0.1UF C157 0.1UF 0.1UF C179 0.1UF C240 0.1UF C153 0.1UF C158 0.1UF C145 0.1UF C127 0.1UF C133 0.01UF 0.1UF C172 0.01UF C242 0.1UF C243 0.01UF C241 0.1UF C225 0.01UF C227 0.1UF C208 0.01UF C209 0.1UF C192 0.01UF C210 0.1UF C228
0.01UF C194
0.1UF
0.01UF C193
0.1UF C195
22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V
0.1UF C180
0.1UF C182 0.1UF C238 0.1UF C175 0.1UF C173 0.1UF 0.1UF C178 0.1UF C174 0.1UF C176 0.1UF C177 0.1UF C101 0.1UF C244 0.1UF C229 0.1UF C224 0.1UF C231 0.1UF C213 0.1UF C207 0.1UF C191 0.1UF C125 0.1UF
0.1UF
0.01UF C236 0.01UF C219 0.01UF C237 0.01UF C234 0.01UF 0.01UF C190 0.01UF C189 0.01UF C200 0.01UF C203 0.01UF C222
0.1UF C239
22UF_25V
0.1UF C245 0.1UF C198 0.1UF 0.1UF 0.1UF C196 0.1UF 0.1UF 0.1UF 0.1UF 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V 22UF_25V
0.1UF C184 0.1UF C106 0.1UF C181 0.1UF C183 0.1UF C185 0.1UF C112 0.1UF C109 0.1UF C108 0.01UF
VCC_IO
+3.3V
VCC_CORE
VCC_CORE
VCC_CORE
+3.3V
0.1UF C105 0.1UF C111 0.1UF C107 0.1UF C110
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0.1UF C171 0.1UF C152 0.1UF C163
0.01UF C135 0.01UF C148
0.1UF C169 0.1UF C154 0.1UF C150
VCC_IO
22UF_25V
VCC_IO
22UF_25V 0.1UF C168 0.1UF C137 0.1UF C162 0.1UF C156 0.1UF C161
+12V
0.1UF C130
VCC_IO
22UF_25V 0.1UF C223 0.01UF 0.01UF 0.1UF C160 0.1UF C167 0.1UF C170 0.1UF C140 0.1UF C134 0.01UF C129 0.01UF C141 0.01UF C132 0.01UF C155 0.01UF C138 0.1UF C142 0.1UF C159 0.1UF C131 0.1UF C128 22UF_25V 22UF_25V 22UF_25V
-12V
+3.3V
0.1UF C136
22UF_25V 22UF_25V 22UF_25V 22UF_25V
+3.3V VCC_CORE
VCC_IO
CONFIDENTIAL PROPERTY INTEGRATED DEVICE TECHNOLOGY, INC.
TP12
TP11
TP13
TP14
TP10
SHEET TITLE: BYPASS CAPACITORS PROJECT TITLE: 79S332/79S334A EVAL LEVEL: PAGE NUMBER: 003-A1550-003 PART NUMBER: ENGINEER'S NAME: RITESH KAPAHI/KASI J.A./GAIL SWAMI DRAWN
Schematics
Schematics
Notes
IDT79S334A Evaluation Board Manual
February 2001
Chapter
EPLD Equation
SYSCONSTG
Author: Viswanadha Chopperla (KASI) Company: Inc., Part (EPM7128AETC100-5) Project: 79S334A EVALUATION BOARD Language: AHDL Logic This logic consists Title Statement (optional) TITLE "sysconstg"; Subdesign Section SUBDESIGN SYSCONSTG epld_clk epld_rst_n epld_pci_clk scc_int_n scc_rd_n scc_wr_n scc_cs_n scc_clk led_cs_n led_clr_n led_we_n nv_cs_n nv_ne_n nv_we_n io_cs_n ej_rst_n edg_pci_rst_n IDT79S334A Evaluation Board Manual INPUT; INPUT; INPUT; INPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; INPUT; INPUT; February 2001 Reset (EJTAG) Interrupt Logic SRAM Control Control NVRAM Control Ext. uart pclk
Notes
EPLD Equation cpu_crst_n cpu_int0_n cpu_nmi_n mem_io_adrs[14.10] m_cs_n[5.0] m_oe_n mem_io_we_n[3.0] m_wait_n epld_tdi epld_tdo epld_tck epld_tms sram_cs_n sram_we_n sram_be_n[3.0] -slt_pci_inta_n slt_pci_inta_n slt_pci_intb_n slt_pci_intc_n slt_pci_intd_n slt_pci_frm_n slt_pci_devsel_n slt_pci_irdy_n slt_pci_trdy_n slt_pci_stop_n slt_pci_perr_n pci_rst_n ext_arb_enb_n pci_host_n m66en slt2_pci_req_n slt2_pci_gnt_n pci_epld_gnt_n[1.0] pci_epld_req_n[1.0] junc VARIABLE cpu_crst rst_dly[10.0] count[2.0] osc_10mhz mem_wait_tri intr_tri pci_gnt2_tri DFF; DFFE; DFF; DFF; TRI; TRI; TRI; OUTPUT; OUTPUT; OUTPUT; INPUT; OUTPUT; INPUT; INPUT; INPUT; INPUT; INPUT; INPUT; INPUT; INPUT; INPUT; OUTPUT; INPUT; INPUT; INPUT; INPUT; OUTPUT; OUTPUT; INPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; INPUT; INPUT; INPUT; INPUT; OUTPUT; INPUT; OUTPUT; INPUT; INPUT;
SYSCONSTG
IDT79S334A Evaluation Board Manual
February 2001
EPLD Equation tmp_junc DFF;
SYSCONSTG
BEGIN -LOGIC DEFAULTS cpu_crst DEFAULTS; -CPU_INTERRUPTS cpu_nmi_n -cpu_int0_n cpu_int0_n intr_tri.oe intr_tri.in slt_pci_inta_n -CPU_RESET -4/14/00 EJTAG reset rst_dly[].clk rst_dly[].clrn rst_dly[].ena rst_dly[] cpu_crst.d cpu_crst.clk cpu_crst.clrn cpu_crst_n JUNC unused tmp_junc.d m_cs_n0 pci_epld_req_n0 pci_epld_req_n1 slt_pci_frm_n slt_pci_devsel_n slt_pci_perr_n #slt_pci_trdy_n slt_pci_irdy_n slt_pci_stop_n m66en slt2_pci_req_n ext_arb_enb_n; tmp_junc.clk junc -SRAM sram_we_n sram_be_n3 sram_be_n2 sram_be_n1 sram_be_n0 sram_cs_n !epld_rst_n m_cs_n1 (mem_io_we_n3 mem_io_we_n2 mem_io_we_n1 mem_io_we_n0); !epld_rst_n m_cs_n1 (mem_io_we_n3 m_oe_n); !epld_rst_n m_cs_n1 (mem_io_we_n2 m_oe_n); !epld_rst_n m_cs_n1 (mem_io_we_n1 m_oe_n); !epld_rst_n m_cs_n1 (mem_io_we_n0 m_oe_n); m_cs_n1; GLOBAL(epld_pci_clk); tmp_junc.q; GLOBAL(epld_clk); epld_rst_n ej_rst_n; !rst_dly[10]; rst_dly[] rst_dly[10]; GLOBAL(epld_clk); epld_rst_n ej_rst_n (!pci_host_n edg_pci_rst_n); cpu_crst.q VCC; scc_int_n slt_pci_inta_n slt_pci_intb_n slt_pci_intc_n slt_pci_intd_n; scc_int_n; !(slt_pci_intb_n slt_pci_intc_n slt_pci_intd_n); GND; intr_tri.out; VCC;
IDT79S334A Evaluation Board Manual
February 2001
EPLD Equation -SCC Base Address chip select_5 $1600_0000 Soft_reset UART address $1600_0400 (Read this port) Channel_B command port address $1600_0003 Channel_B data port address $1600_0007 Channel_A command port address $1600_000B Channel_A data port address $1600_000F scc_cs_n scc_rd_n scc_wr_n m_cs_n5; epld_rst_n (m_oe_n m_cs_n5 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 epld_rst_n (mem_io_we_n0 m_cs_n5 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 (m_oe_n m_cs_n5 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 !mem_io_adrs10); PCLK approx. sixth epld_clk count[2.0].clrn count[2.0].clk count[2.0].q count[2.0].d ELSE count[2.0].d osc_10mhz.clrn osc_10mhz.d osc_10mhz.clk scc_clk GLOBAL(epld_rst_n); !osc_10mhz.q; count[1].q; osc_10mhz.q; count[2.0].q GLOBAL(epld_rst_n); GLOBAL(epld_clk); THEN
SYSCONSTG
-AN_DISPLAY/LED_DISPLAY Base address chip select_4 $1400_0000 Address clear digits $1400_0400 (Read this port) Address digit0 $1400_000F Address digit1 $1400_0007 Address digit2 $1400_000B Address digit3 $1400_0003 led_cs_n (!epld_rst_n m_cs_n4 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12# mem_io_adrs11 mem_io_adrs10);
IDT79S334A Evaluation Board Manual
February 2001
EPLD Equation led_clr_n led_we_n (!epld_rst_n m_cs_n4 m_oe_n mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 !mem_io_adrs10); (!epld_rst_n m_cs_n4 mem_io_we_n0 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 mem_io_adrs10); -NV_RAM Base address chip select_3 $1200_0000 Base address read/write cycle $1200_0000 (RAM operations) Base address recall/store cycle $1200_0400 (Non-volatile operations) nv_cs_n nv_ne_n nv_we_n (!epld_rst_n m_cs_n3 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11); (!epld_rst_n m_cs_n3 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 !mem_io_adrs10); (!epld_rst_n m_cs_n3 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 mem_io_we_n0); -IO_INTERRUPTS_SOURCE Base address chip select_2 $1000_0000 io_cs_n -WAIT_CONTROL m_wait_n mem_wait_tri.oe mem_wait_tri -PCI_CLK pci_rst_n pci_epld_gnt_n[1.0] -slt2_pci_gnt_n pci_gnt2_tri.in pci_gnt2_tri.oe slt2_pci_gnt_n END; cpu_crst.q ej_rst_n (!pci_host_n edg_pci_rst_n); VCC; VCC; GND; !ext_arb_enb_n; pci_gnt2_tri.out; mem_wait_tri; vcc; vcc; (!epld_rst_n m_oe_n m_cs_n2 mem_io_adrs14 mem_io_adrs13 mem_io_adrs12 mem_io_adrs11 mem_io_adrs10);
SYSCONSTG
IDT79S334A Evaluation Board Manual
February 2001
EPLD Equation
SYSCONSTG
Notes
IDT79S334A Evaluation Board Manual
February 2001
Other recent searches
TC7SG08AFS - TC7SG08AFS TC7SG08AFS Datasheet
SN74LVTH241 - SN74LVTH241 SN74LVTH241 Datasheet
SN54LVTH241 - SN54LVTH241 SN54LVTH241 Datasheet
SM5956A - SM5956A SM5956A Datasheet
SA-110 - SA-110 SA-110 Datasheet
PI2LVD512 - PI2LVD512 PI2LVD512 Datasheet
PF738-04 - PF738-04 PF738-04 Datasheet
L6258E - L6258E L6258E Datasheet
FAN5250 - FAN5250 FAN5250 Datasheet
APT-0403 - APT-0403 APT-0403 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
