R3081 RISController33MHz Evaluation Board User's Manual 1994
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IDT79S381
R3081 RISController33MHz Evaluation Board
User's Manual
1994 Revision
Integrated Device Technology, Inc.
©1994 Integrated Device Technology, Inc.
ABOUT THIS MANUAL
33MHz IDT79S381 hardware software Evaluation Board that based R3081 RISController microprocessor. board able R305x RISController family members including R3041, R3051(E), R3052(E), R3071(E), R3081(E). This manual, "The IDT79S381 R3081 Evaluation Board User's Manual," provides guide installing setting evaluation board well giving qualitative description functional operation evaluation board. addition, this manual includes detailed documentation design evaluation board. More information R3081 RISController microprocessor itself provided R3081 Hardware User's Manual R3081 Data Sheet. R3081 User's Manual describes qualitative functional operation R3081, while R3081 Data Sheet provides electrical specification R3081. Similar information also exists R3041, R3051, R3052, R3071. Additional information RISControllers, hardware software development tools, complementary support chips, these products various applications, provided additional data sheets applications notes. this information readily available from your local sales representative.
History: Revision 0.9,
1994: Final draft.
Integrated Device Technology, Inc. reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. does assume responsibility circuitry described other than circuitry embodied product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Integrated Device Technology, Inc.
LIFE SUPPORT POLICY Integrated Device Technology's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer IDT. Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component components life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
logo registered trademark BiCameral, BurstRAM, BUSMUX, CacheRAM, DECnet, Double-Density, FASTX, Four-Port, FLEXI-CACHE, Flexi-PAK, Flow-thruEDC, IDT/c, IDTenvY, IDT/sae, IDT/sim, IDT/ux, MacStation, MICROSLICE, PalatteDAC, REAL8, R3041, R3051, R3052, R3071, R3081, R3721, R4600, RISCompiler, RISController, RISCore, RISC Subsystem, RISC Windows, SARAM, SmartLogic, SyncFIFO, SyncBiFIFO, SPC, TargetSystem WideBus trademarks Integrated Device Technology, Inc. MIPS registered trademark MIPS Computer Systems, Inc. Other trademarks properties their respective companies.
TABLE CONTENTS
Integrated Device Technology, Inc.
Evaluation Board Description .1-1 Introduction .1-1 Overview Features .1-2 Explanation Features .1-3 Specification Summary .1-5 Getting Started Quickly .2-1 Getting Started Quickly .2-1 Installation .3-1 79S381 Installation .3-1 Power Connections .3-1 Serial Port Video Terminal Auxiliary Port .3-2 Jumpers .3-3 Switches .3-3 System Software IDT/sim .3-4 Initialization System Start-Up .3-5 Host Target Program Downloading .3-5 Theory Operation Design Notes (selected topics) .4-1 Control Mechanism Overview .4-1 Control Selector/Address Decode .4-2 Zero Wait-State SRAM Control .4-3 DRAM Control .4-4 Synchronous State Machine Control .4-4 ~SysClk Loading .4-5 Functionality ~BusReq Turn-Around Error Register .4-6 Wait-States .4-6 Schematics .5-1 Parts List .5-2 Upgrade Parts List .5-5 Schematics .5-6 Off-Sheet Cross-Reference Signals List .5-29
Equations .6-1 Error .6-2 Interrupt .6-6 Sonic Interface .6-8 State Machine Decoder .6-10 State Machine .6-13 State Machine .6-18 Controller .6-23 Data Driver Controller .6-25 Address Decoder .6-27 Signal Generator PLA.6-30 RdCEn Output Select .6-33 Sonic Address Data Control .6-35 SRAM Dual-Port Controller .6-38 SRAM Chip Select Decoder .6-40 Interface Controller .6-42 RdCEn Output .6-44 Timing Diagrams .7-1 Dual-Port Memory Timing .7-2 DRAM Timing.7-4 DUART Timing .7-9 EPROM Timing .7-10 SRAM Timing .7-12 Appendix .A-1 Tech Note SparcStation setup .A-2 Tech Note SparcStation DBXX setup .A-5 IDT/item terminal emulator software .A-7
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
1.1. 79S381 33MHz R3081 Evaluation Board Block Diagram 1.2. 79S381 Physical Layout .1-4 79S381 Power Supply Connection .3-2 3.2. Typical Terminal Setup. .3-16 79S381 Control Diagram .4-2 4.2. 79S381 Control Diagram Detail. .4-3 5.1. Power Connector Reset Circuitry 5.2. R3081 RISController .5-7 5.3. R3081 Address Latches .5-8 5.4. Control .5-9 5.5. Decoder, State Machine, RdCEn/Ack Controller .5-10 5.6. SRAM, DRAM, Dual-Port Transceiver Controller .5-11 5.7. Transceiver Debug Address Register .5-12 5.8. EPROMs .5-13 5.9. SRAM Memory Banks .5-14 5.10. DRAM Controller Termination Resistors .5-15 5.11. DRAM Bank .5-16 5.12. DRAM Bank .5-17 5.13. DRAM Transceiver .5-18 5.14. Sonic Controller .5-19
List Figures (continued) Figure 5.15. Sonic Data Address Buffer/Transceiver.5-20 Figure 5.16. Sonic Ethernet Controller .5-21 Figure 5.17. Sonic Dual-Port Memory .5-22 Figure 5.18. Sonic Dual-Port Memory .5-23 Figure 5.19. DUART, EEPROM, RS232 Connector .5-24 Figure 5.20. Initialization Configuration .5-25 Figure 5.21. Expansion Connector Transceivers .5-26 Figure 5.22. Expanstion Connector .5-27 Figure 5.23. Bypass Capacitors .5-28 Figure 7.1. Dual-Port Memory Single Datum Read .7-2 Figure 7.2. Dual-Port Memory 4Word Datum Read .7-2 Figure 7.3. Dual-Port Memory Single Datum Write .7-3 Figure 7.4. DRAM Single Datum Read (Page Miss Followed Hit) Figure 7.5. DRAM Single Datum Read (Page Hit) .7-4 Figure 7.6. DRAM Single Datum Read (Page Miss) .7-5 Figure 7.7. DRAM Word Datum Read (Page Miss Followed Hit) Figure 7.8. DRAM Word Datum Read (Page Hit) .7-6 Figure 7.9. DRAM Word Datum Read (Page Miss) .7-6 Figure 7.10. DRAM Single Datum Write (Page Miss Followed Hit) Figure 7.11. DRAM Single Datum Write (Page Hit) .7-7 Figure 7.12. DRAM Single Datum Write (Page Miss) .7-8 Figure 7.13. DUART Single Datum Read .7-9 Figure 7.14. DUART Single Datum Write .7-9 Figure 7.15. EPROM Single Datum Read .7-10 Figure 7.16. EPROM Word Datum Read .7-10 Figure 7.17. EPROM Single Datum Write .7-11 Figure 7.18. SRAM Single Datum Read Wait State).7-12 Figure 7.19. SRAM Word Datum Read Wait State) .7-12 Figure 7.20. SRAM Single Datum Write Wait State) .7-13 Figure 7.21. SRAM Single Datum Read Wait State).7-14 Figure 7.22. SRAM Word Datum Read Wait State) .7-14 Figure 7.23. SRAM Single Datum Write Wait State) .7-15
List Tables Table 1.1. Parts Speeds that 79S381 Evaluation Board Table 3.1. Serial Port Assignments .3-2 Table 3.2. Jumper Settings. EPROM Device Selection .3-3 Table 3.3. W[4:1} Jumper Settings. Debug Jumper Connections .3-3 Table 3.4. Switch Settings. Reset Mode Vector .3-3 Table 3.5. S2[2:1] Switch Settings. EPROM Decode Size Table 3.6. S2:3 Switch Settings. SRAM Base Address Selector .3-4 Table 3.7. S2:3 Switch Settings. Expansion Mode Selector .3-4 Table 3.8. Initial Screen Display IDT/sim Debug Monitor .3-5 Table 3.9. Screen Display IDT/sim Monitor Debug Command Table 3.10. Typical Terminal Emulator Download .3-6 Table 3.11. Typical Terminal Download .3-6 Table 4.1. 79S381 Address Memory .4-1 Table 4.2. 79S381 Wait-State Memory Latencies .4-6
EVALUATION BOARD DESCRIPTION
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R3081RISCONTROLLER33MHZ EVALUATION BOARD DESCRIPTION
INTRODUCTION
CHAPTER
Integrated Device Technology, Inc.
79S381 Evaluation Board example complete working MIPS R3000 RISC System. board high performance design example using highly integrated R3051 family RISController CPU. Primary uses board include: Evaluating R3041/51/52/71/81 architecture. Prototyping running software benchmarks. Figure shows 79S381 RISC evaluation board block diagram.
33MHz
E2PROM
Buffers
Dual Serial Ports
256kbytes wait state SRAM
2Mbytes EPROM
Buffers
Expansion Connector
R3081E RISController
V96BMC DRAM Controller
Buffer
Dual Port SRAM
16MB DRAM
Buffers
25MHz
SONIC Ethernet Controller
Figure 1.1. 79S381 33MHz R3081 Evaluation Board Block Diagram.
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EVALUATION BOARD DESCRIPTION
board designed demonstrate optimal performance R3051 family RISControllers. 33MHz Zero wait-state memory allows true performance R3051 family. Parts that evaluated listed Table 1.1. Part-Speed R3041-16, R3051-20, R3051E-20 R3052-20, R3052E-20, R3071-20, R3071E-20, R3081-20, R3081E-20, NOTES R3071/E R3081/E 50MHz using their half-speed-bus modes 25MHz, respectively. minimum board speed 10MHz limitation DRAM Controller.
Table 1.1. Parts Speeds that 79S381 Evaluation Board Use.
board comes with switches major options, including Reset Initialization/Configuration Vectors.
OVERVIEW FEATURES
major features 79S381 RISController Evaluation Board include: Complete 33MHz RISC System Board Supports R3081, R3071, R3052, R3051, R3041 CPUs interleaved DRAM expandable 8MB, 10MB, 16MB 256K zero-wait-state SRAM 512KB EPROM expandable serial ports IEEE 802.3 ethernet subsystem with dual-port memory 1024-bit serial EEPROM external user timers DUART, ethernet, DRAM Controller subsystems Expansion/debug connector switches major options including R3051 family reset initialization vectors Additional Error recovery logic
EVALUATION BOARD DESCRIPTION
CHAPTER
EXPLANATION FEATURES
79S381 Evaluation Board operated standalone board only requires standard RS232-C video terminal volt power supply operation (and supply optional Ethernet port used). board approximately 11x9 inches placed flat table-top surface. 79S381 Evaluation Board comes with 128Kx8 EPROM chips. EPROM contains IDT/sim, level operating system kernel debugger that supports download code from host systems, remote debug interface, execution control commands including single stepping instruction tracing, memory probing, register probing, line-based assembly, disassembly code. system comes with 2MBytes interleaved DRAM supports 16MBytes DRAM. There DRAM SIMM sockets which populated with either SIMMs. MacStation, MIPS workstation, SPARCstation, PC/AT connected 79S381 serial ports user developed code (generated using cross-compiler such GNU/GCC (IDT/c-5.0) MIPS/c downloaded board. those developing large segments code, IEEE 802.3 ethernet interface allows quick downloading large code blocks. ethernet subsystem contains Dual-Port memory message sharing between ethernet controller CPU. ethernet subsystem also includes 1024-bit serial EEPROM storage configuration parameters such address. external timers provided that instance used benchmarking purposes. Additional Error recovery logic allows write well read errors detected address recovered through external register containing error address. addition, logic analyzer/debug connector provided allowing additional hardware observability add-on card. 79S381 designed around IDT79R3081 RISController member R3051 family. R3081 highly integrated cost RISController includes 16KB instruction cache data cache (software re-configurable 8KB/8KB). further details R3081 RISController, please refer R3081 Hardware User's Manual R3081 Data Sheet. 79S381 board constructed using both through hole surface mount devices 11x9 inch 6-layer epoxy laminate board with standoffs. Figure shows physical layout board.
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EVALUATION BOARD DESCRIPTION
Figure 1.2. 79S381 Physical Layout.
EVALUATION BOARD DESCRIPTION
CHAPTER
SPECIFICATION SUMMARY
PART NUMBER: RISCONTROLLER: BOARD SPEED: IDT79S381 IDT79R3081E-33 33MHz max. 10MHz min.
ON-BOARD MEMORY CAPACITY: shipped: Maximum: DRAM SIMMs (2MByte) EPROM 128Kx8 (512KByte) DRAM SIMMs (16MByte) EPROM 512Kx8 (2MByte)
DEBUG MONITOR EPROM: 128Kx8 (512KByte) containing IDT/sim. SERIAL PORTS: Controlled SCN2681 DUART. Terminal connects Software configurable features. Default state: 9600 Baud, bits, parity, stop bit. Download port connects Software configurable features. Default state: 9600 Baud, bits, parity, stop bit. SERIAL PORT CONNECTORS: ETHERNET PORT CONNECTOR: TIMERS: DB25F connectors. Right angle female. 15-pin-D thick wire connector. Right angle female.
Programmable counter/timer 16-bit timer DUART. Programmable counter/timer 32-bit timer SONIC. Programmable counter/timer 24-bit timer
INTERRUPTS: EXPANSION CONNECTOR:
synchronized, unsynchronized used on-board with spare) Male compatible. Mates with Reverse DIN. Female.
PHYSICAL DIMENSIONS:
11.0" 9.0". (Some connectors extend further than length width board). 0-55°C 5.0V Amps typical max. 12.0V Amps (required Ethernet).
OPERATING TEMPERATURE: RELATIVE HUMIDITY: POWER SUPPLY:
GETTING STARTED QUICKLY
CHAPTER
GETTING STARTED QUICKLY
CHAPTER
Integrated Device Technology, Inc.
GETTING STARTED QUICKLY
Operating 79S381 Evaluation Board requires external power supply video terminal. Specifically, these are: power supply. Must supply least 3.5A. +12V power supply Ethernet connected. Must supply least 0.5A. Video Terminal with RS232-C port. standard power supply will suffice power supply. evaluation board uses 4-pin disk drive power supply connector, which directly mates connector standard power supply. video terminal typical VT100 type/ANSI terminal emulator running with 9600 baud, data bits, parity, stop bit. Traditional video terminals have 25-pin male connector. This directly mates with board's terminal connector,
INSTALLATION
CHAPTER
INSTALLATION
CHAPTER
Integrated Device Technology, Inc.
INSTALLATION
install boot 79S381 Evaluation Board default configuration, following steps need taken. Firstly, connect power source board's power connector, labeled POWER. Secondly, connect video display monitor. Connect video cable terminal connector, labeled TERMINAL. Thirdly, configure jumpers needed. 79S381 Evaluation Board only required jumper. This jumper, needed adjust pinout differences among 1Mbit (27C010), 2Mbit (27C020), 4Mbit (27C040) EPROMs. default setting short connections. other jumper blocks, W[4:1], should remain uninhabited. details concerning non-default operational modes with jumpers, refer section later this chapter called, "Jumpers". Fourthly, configure switches needed. 79S381 Evaluation Board sets switches: switches control RISController's reset, mode vectors. switches control features S381 Evaluation board. default setting used switches used switches board designates switch should set. There also some unused switches that have 'X'. details concerning non-default operational modes with switches, refer section later this chapter called "DIP Switches". Fifthly, install DRAMs. DRAM SIMMs need installed multiples two. Although DRAMs required operate board, since IDT/sim optionally booted with only SRAM operating default configuration operate board with DRAM. When installing DRAM SIMMs, install first sockets U40. These sockets labeled PAIR 1MByte, 256kbitx32 256kbitx36, 4MByte, 1Mbitx32 1Mbitx36, SIMMs supported. DRAM SIMM pairs different sizes (i.e., pair consists SIMMs other pair consists SIMMs) then larger SIMMs must installed into Pair slot. Sixthly, engage power supply. board's IDT/sim program will prompt user monitor additional input.
POWER CONNECTIONS
Power board provided using standard PC/AT power supply available from wide variety computer equipment retailers. PC/AT disk drive 4-pin connector PC/AT power supply mates with board's power connector. 4-pin splice plug also provided connection standard supplies (3.5A greater). supply should connect relatively thick gauge wires from appropriate locations power supply splice supply +5VDC pin; supply +12VDC pin; Ground supply either both) pins splice plug. splice plug then inserted into 79S381 board's 4-pin power connector. Note that supply only required Ethernet cable connected.
CHAPTER
INSTALLATION
PC/AT POWER SUPPLY
+12VDC +5VDC
YELLOW BLACK BLACK
NOTE: +12V REQUIRED 79S381 ETHERNET CONNECTED
POWER CONNECTOR 79S381 +12VDC VIEW +5VDC
Figure 3.1. 79S381 Power Supply Connection.
SERIAL PORT VIDEO TERMINAL AUXILIARY PORT
There RS232-C serial port connectors 79S381 System Board. assignments listed table below: Terminal Port Signal Port Signal
input output input output output ground input
NOTE: IDT/sim requires only these three wires establish serial communication.
Table 3.1. Serial Port Assignments.
port video terminal DB25F connector designated terminal must data rate 9600 baud with bits data, parity bits, stop (9600,N,8,1). port auxiliary use, such downloading software from MacStation, SPARCstation MIPS Workstation, described later this document. DB25F connector female uses (Data Communications Equipment) convention. DCE, board essentially acts like modem thus take straight wires from (Data Terminal Equipment) terminal such PC/AT almost video terminals.
INSTALLATION
CHAPTER
JUMPERS
79S381 Evaluation Board only required jumper. This jumper, needed adjust pinout differences among 1Mbit (27C010), 2Mbit (27C020), 4Mbit (27C040) EPROMs. Refer table below correct setting. EPROM Type 1Mbit (27C010) 2Mbit (27C020) 4Mbit (27C040) (default)
Table 3.2. Jumper Settings. EPROM Device Selection.
Changing EPROMs also requires change board's switches. next Section. other jumpers W[4:1] control RISController's reserved pins. designated 79R3051/71/81 data sheet, these signals should not, default, driven. (The R3041 internally pulls these signals correct logic level.) jumper blocks provided debugging purposes. Reserved1 Reserved2 used invoke diagnostic modes R3051/ R3081 devices. Refer Debug Mode Feature's chapter R3051/52 R3081 Hardware User's Manual. Jumper NOTES: Signal **** R3041 R3041 R3041 R3041 Signal R3081 R3081 R3081 R3081 Rsvd1* Rsvd2** Rsvd3*** Rsvd4**** Signal 4.7k pullup 4.7k pullup 4.7k pullup 4.7k pullup Default jumper jumper jumper jumper
Addr1 output pin. ~BE16(0) output pin. ~BE16(1) output pin. ~TriState input pin.
Table 3.3. W[4:1] Jumper Settings. Debug Jumper Connections.
SWITCHES
79S381 Evaluation Board sets switches: switches control RISController's reset, mode vectors. negating edge ~Reset, R3051 samples interrupt lines, INT[5:3],SInt[2:0], select among different operating modes. default modes selected setting S1[6:1] switches OFF. (Note: board denoting default configuration.) table below. Switch S1:1 S1:2 S1:3 S1:4 S1:5 S1:6 S1:7 S1:8 Interrupt ~SInt0 ~SInt1 ~SInt2 ~Int3 ~Int4 ~Int5 unused unused Mode Feature Endian ~Tri-State DBlock Refill ~Half-frequency ~1xClockEn ~CoherentDMAEn unused unused Default Setting unused unused
Table 3.4. Switch Settings. Reset Mode Vector.
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INSTALLATION
switches select different features 79R3081 Evaluation Board. These include enlargement EPROM space, ability reconfigure SRAM within address map, selection expansion connector diagnostic port. Switches S2:[2:1] select EPROM decode size. Switch S2:3 selects SRAM base address. Switch S2:4 selects whether expansion connector diagnostic port. tables below specifics each switch. Switch S2:2 S2:1 EPROM Size Selected Mbit (27C010) (default) Mbit (27C020) Mbit (27C040) Unused
Table 3.5. S2[2:1] Switch Settings. EPROM Decode Size.
Switch S2:3
SRAM Base Physical Address 0x0400 0000 (default) 0x0000 0000*
NOTE: DRAM disabled when SRAM base address mapped 0x0000 0000.
Table 3.6. S2:3 Switch Settings. SRAM Base Address Selector.
Mapping SRAM bottom physical address space intended benchmarking. References code being benchmarked, exception handler, system stack will within 0-wait state SRAM, therefore will show highest possible RISController performance.
Switch S2:4 Expansion Connector Mode Expansion. Input/Output Interface (default) Diagnostic. Output Interface Only
Table 3.7. S2:3 Switch Settings. Expansion Mode Selector.
With Expansion Connector diagnostic mode, connector will always driven with RISController's multiplexed A/D[31:0] bus. When selecting this mode, signals connector outputs. Switch numbers presently unused unassigned function.
SYSTEM SOFTWARE IDT/SIM
EPROM 79S381 contain IDT's System Integration Manager (IDT/sim). IDT/sim software boot PROM debug monitor kernel that provides functions downloading software integrating hardware with software. Software downloaded onto board from MIPS Workstation, MacStation, SPARCstation, PC/AT personal computer. Drivers easily added using Cross Development Software, IDT/kit user acquire IDT/sim source code support other devices change addresses their specific application (for instance change from endian little endian addressing).
INSTALLATION
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INITIALIZATION SYSTEM START-UP
Turning power supply, hitting reset button power already will reinitialize board. default configuration board endian. Once started, IDT/sim will automatically boot size R305x internal caches main memory then issue message screen asking keyboard input order configure console. Then message similar Table showing cache memory sizes will appear along with first command line prompt.
system Integration Manager Feb, 1994 Ported RS381. Feb, 1994. Copyright 1992, 1994. Integrated Device Technology, Inc. help enter Memory size: 2097152 (0x200000) bytes Icache size: 16384 (0x4000) bytes Dcache size: 4096 (0x1000) bytes Zero_wait state Memory size: 262144 (0x4000) bytes Dual port Memory size: 8192 (0x2000) bytes Free Memory Space 0xa0011414-0xa01ffffc <IDT>
Table 3.8. Initial Screen Display IDT/sim Debug Monitor (may differ slightly depending IDT/sim version).
using IDT/sim monitor, diagnostic menu entered executing "diagnostic" "dg" command. This menu lists several quick tests that used verify board's functionality. Select item "Run Tests." Please refer IDT/sim User's Manual more detailed information more advanced features.
<IDT> MENU PRINTS HERE PASS/FAIL DIAGNOSTIC MESSAGES PRINT HERE <IDT>
Table 3.9. Screen Display IDT/sim Monitor Debug Command.
HOST TARGET PROGRAM DOWNLOADING
Several download scenarios exist. "terminal emulator" mode, which involves terminal attached port interactive workstation port attached port. terminal (and keyboard) easily changed between board workstation. This scenario uses commands similar Table 3.10.
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INSTALLATION
BOARD DISPLAY <IDT> unix> program.sre unix>
Table 3.10. Typical Terminal Emulator Download.
dedicated terminal used workstation different terminal used board Figure then scenario Table 3.11 used.
DISPLAY
RS232C CABLE (DOWNLOAD LINK)
Workstation
J2-tty0 J1-tty1 79S381
KEYBOARD TARGET SYSTEM
TERMINAL
MACSTATION/SUN/MIPS/DOS SYSTEM
Figure 3.2. Typical Terminal Setup.
BOARD DISPLAY <IDT> load tty1
WORKSTATION DISPLAY unix> program.sre /dev/ttyd3
Table 3.11. Typical Terminal Download.
THEORY OPERATION
CHAPTER
THEORY OPERATION DESIGN NOTES (SELECTED TOPICS)
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Integrated Device Technology, Inc.
THEORY OPERATION DESIGN NOTES (SELECTED TOPICS)
following sections describe specific topics within scope functional operation 79S381 R3081 Evaluation board from hardware designer's point view. Extensive references made Schematics, PLA, Timing Diagrams which contained Chapters this manual.
CONTROL MECHANISM OVERVIEW
Interface control between R3081 RISController peripherals 79S381 evaluation board divided into three subsections: wait-state SRAM DRAM main synchronous state machine Depending upon address issued give cycle, these three controllers will mandate that particular interface cycle. address below defines memory locations. Address (Hex)* 0x0000 0000 0x03ff ffff 0x0400 0000 0x0410 0000 0x0420 0000 0x043f ffff 0x0440 0000 0x0450 0000 0x1f09 ffff 0x1fa0 0000 0x1fb0 0000 0x1fc0 0000 0x1fdf ffff 0x1fe0 0000 0x1ff0 0000 (Decimal) Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Device DRAM 256K SRAM (0-wait state) 256K SRAM (n-wait state) unused (2Mbytes) Dual Port SRAM unused (437 Mbytes) User Area SONIC Registers (Slave) EPROM DUART Error Address Register
NOTES: Minimum decode space 1Mbyte SRAMs 65Mbyte alias SRAM 64Mbyte with slower access time. benchmarking, SRAM configured 0x0000 0000 0x0010 0000 with DRAM disabled. This setting places n-wait state SRAM 0x0010 0000 removes SRAM from memory 0x0040 0000 0x0410 0000. Dual Port SRAM incorporates SONIC side read addresses starting 0x0448 0000. writes addresses above 0x04480 0000 supported.
Table 4.1. 79S381 Address Memory Map.
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THEORY OPERATION
zero wait-state SRAM control subsection mandates zero wait-state SRAM cycles. DRAM control subsection mandates DRAM cycles. other cycles, i.e.: EPROM cycles, DUART cycles, SONIC slave cycles, Dual Port SRAM cycles, multiple wait-state SRAM cycles, Error Register reads, User area cycles, mandated Synchronous State Machine subsection. Refer control diagram below.
0-Wait State SRAM Control
33MHz
Add. Latches
SRAM Ctl.
Synchronous State Machine
R3081E RISController
EPROM, DUART, etc. Ctl.
'373AT
DRAM Control
Control
Control Selector (Add. Decode)
DRAM Ctl.
~RdCEn ~Ack
Multiplexer
Figure 4.1. 79S381 Control Diagram.
With three separate controllers only processor, multiplexer used select whose pair handshaking signals sent back R3081. These signals ~RdCEn ~Ack. Three separate control subsections need norm designs. Given definitions this board, specifically need support zero waitstate SRAMs, least control subsections were instantaneously defined: being synchronous other being asynchronous.
CONTROL SELECTOR/ADDRESS DECODE
~RdCEn ~Ack multiplexing done with output enables. 33MHz, there barely enough time even assert ~RdCEn ~Ack within spec. additional nanoseconds multiplexer option, therefore, signals multiplexed with output enables that turned same time that valid ~RdCEn ~Ack signals being generated. RDCENOE functions Control Selector (Add. Decode) block seen Figure 4.1. Based predominantly input address, this selects which three control sub-sections enable turning appropriate ~RdCEn ~Ack drivers.
THEORY OPERATION
CHAPTER
~v3Ready
33MHz ~B/WrN
Control
16L8-5
Control
16Rx-5
State Machine
'162500 Reg.
22V10-10
Add. Latches
R3081E RISController ~SysClk
~Ack ~RdCen
Decode
22V10-10
'373AT
'806A
~BusReq
16Rx-7
Figure 4.2. 79S381 Control Diagram Detail.
ZERO WAIT-STATE SRAM CONTROL
zero wait-state SRAM control completely asynchronous. output '373 address latches feed RDCENOE which functions. Firstly, selects zero wait-state SRAM control subsection driver ~RdCEn ~Ack back R3081, therefore enables tri-stateable drivers disables other drivers. Secondly, generates ~RdCEn ~Ack zero wait-state SRAM subsection. zero wait-state SRAM subsection ~RdCEn ~Ack signals generated similarly asynchronous chip select. valid read write known zero wait-state SRAM address will cause both these signals asserted. Since ~Ack sampled once processor first assertion during interface cycle, keeping ~Ack four cycles during burst read valid solution. examining R3051 family interface, support zero waitstate interface requires assertion ~RdCEn (for reads) ~Ack (for writes) prior completion first clock cycle. Refer timing diagrams Chapter Generating this immediate ~RdCEn ~Ack done ways. first falling edge ~SysClk generate asserted ~RdCEn ~Ack signals. second asynchronously generate these signals. Simple calculations will show that first method relatively unfeasible 33MHz. Generating stable, valid input falling edge register during first cycle read write verge impossible. Therefore, zero wait-state controller generates ~RdCEn ~Ack asynchronously.
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THEORY OPERATION
SRAM used zero wait-state operations also mapped another space under control synchronous state machine. Addressing this same memory with virtual address used synchronous state machine allows users difference performance between zero wait-state three wait-state operations. more specifics, Synchronous State Machine Control description below.
DRAM CONTROL
S381 board's DRAM controlled V96BMC DRAM Controller some surrounding control logic. Designed support generic interface, input output needed support R3051 family interface. This control done V3CTL input V3OUT output. V3CTL generates address strobe, ~ADS, based current previous state RISController's signals. V3OUT generates ~RdCEn ~Ack from DRAM controller's ~V3Ready output. Note that V96BMC output timing little different from input timing requirements IDTR3051 family devices, therefore V3OUT also delayed version V96BMC's ~Ready signal. interleaved DRAM data busses '543 latch DRAM data rising edge DRAM ~CAS signals. V96BMC assumes data will sampled ~SysClk's rising edge instead falling edge done R3051 family parts. '543 latches hold valid data till they sampled RISController. Initialization V96BMC done through series writes physical addresses between 0xFF0F 0000 0xFF10 0000. Some memory timing options programmable writing different values V96BMC above space, although board guaranteed properly work under different DRAM timing configurations.
SYNCHRONOUS STATE MACHINE CONTROL
Synchronous State Machine controls accesses EPROMs, three wait-state SRAM, DUART, SONIC registers, Error Register, User area, Dual Port SRAM. beginning interface cycles, DECODE encodes physical address into three device code, DEVICE[2:0]. This encoding other control signals sampled state machines, STATES[2:1], which then count cycles, toggle control lines, generate correct ~RdCEn ~Ack back R3081. Determining one's clocking methodology when using R3051 family devices more difficult decisions make. following section related topic ~SysClk Loading. this board, R3081 clock through inverter then most board's control. Generating ~RdCEn, ~Ack, ~BusError back with this clock methodology difficult task, especially with cycle times 30ns when mid-cycle transfer needs take place. Within that mid-cycle, following propagation delays incurred: clock inverter delay, PAL/register clock-to-out, R3051 family signal setup time. Plus, output driver needs tristateable have quick enable/disable times. remove clock inverter delay from timing path, falling edge register, '162500, used drive ~RdCEn, ~Ack, ~BusError signals back R3081. This register also support necessary output enable times defined rest system. With additional register delay
THEORY OPERATION
CHAPTER
'162500 register, state machine PALs, STATE[2:1], count fewer state than actual memory latency first assertion ~Ack ~RdCEn. Normally starts state machine soon RISController initiates interface cycle. Again, slower frequencies this valid assumption, frequencies 33MHz higher this assumption longer valid. 33MHz, DEVICE[2:0] signals stable when falls therefore state machine should start this time. define when state machine should initiate counting, signal from generated always stable when STATES[1:0] PALs samples inputs. assertion signal, always second cycle read write, signals state machine starts counting.
~SYSCLK LOADING
Using relatively small number loads R3081 ~SysClk signal imperative stable hardware design. Many designers number loads ~SysClk order save buffer simplify timing skew complications. Although need adding more more loads single clock signal understandable, recommended lead difficult debug manufacturing issues. Therefore, keep number loads ~SysClk low. this board, there four loads. This good number loads abide designs. Boards with more loads have shown clocking problems. have noisy boards. keep loading ~SysClk low, following three criteria must met. Firstly, limit number devices needing clock four. embedded applications with ASIC generating control, this valid solution. Secondly, buffer ~SysClk generate control based this buffered clock. This solution also limitations. Meeting hold time processor output signal such improbable, generating valid R3081 ~RdCEn ~Ack quite easy. Thirdly, invert ~SysClk. default, inverter also buffer. largest limitations here generate valid ~RdCEn ~Ack. using '162500, this board inverted clock still meet critical specification. Whatever clocking methodology might use, important element keep loading ~SysClk low.
FUNCTIONALITY ~BUSREQ TURN-AROUND
turn-around defines certain condition where RISController's multiplexed changes ownership from driver processor. Especially higher speeds, there enough time driver stop driving before RISController starts driving other direction. alleviate this contention, R3041 R3081 devices have software controllable within their internal register that defines this transition great than default clock cycle. also support R3051 R3052 devices without such internal feature, turn-around must alleviated through external hardware. last cycle every read, ~BusReq asserted request clock cycle. drivers settle during this cycle avoid contention devices driving opposite directions. Note that this additional cycle only affects performance R3051 family devices when write pending write buffer. During other cases, RISController internally busy will issue another read least another clock cycle.
CHAPTER
THEORY OPERATION
ERROR REGISTER
Error Register read only register that stores physical word address last error along with R3081 signals. This register especially useful when debugging code that inadvertently generates errors during writes. Remember that R3051 family RISControllers does jump exception handler when error occurs write. Only when error occurs read does error cause jump exception handler. With this register, errors that occurred during writes traced examining physical address stored within this register.
WAIT-STATES
Memory 0-Wait SRAM 3-Wait SRAM DRAM (pg. hit) DRAM (pg. miss) Dual Port EPROM Duart Sonic Slave Control Single Read (min.) n.a. Quad Read 2-1-1-1 5-1-1-1 5-1-2-1 9-1-2-1 5-2-2-2 6-5-5-5 n.a. n.a. n.a. Write (min.)
NOTE: Numbers refer total amount clock cycles transaction. number wait-states initial latency 'number
Table 4.2. 79S381 Wait-State Latencies.
CHAPTER
SCHEMATICS
SCHEMATICS
CHAPTER
Integrated Device Technology, Inc.
SCHEMATICS
following pages include: Bill Materials Parts List DRAM/EPROM Upgrade Parts Board Schematics (see "Table Contents: Figures" page numbers). Off-Sheet Cross-Reference Signals List 5-29
CHAPTER
SCHEMATICS
79S381 PARTS LIST
PARTS LIST
name 167_003
Date 1994
Time 09:51:04
Item
Code -101-00008-020 101-00008-040 101-00008-120 101-00008-270 101-00008-300 101-00008-350 101-00010-009 101-00010-103 101-A0264-001 101-A0306-001 101-A0307-001 101-A0373-001 103-00003-003
Description -RES 1/8W 1206 1/8W 1206 1/8W 1206 1/8W 1206 1/8W 4.7K 1206 1/8W 1206 RPAK 4.7K RPAK SOIC ISOL RPAK SOIC BUSSED 4.7K 1/8W 1206 1/8W 39.2 1206 1/8W 680K 1206 0.1UF 10-20% 1206
Quantity RP10 RP11
RP13 RP12
CHAPTER
SCHEMATICS
103-00004-006 103-00004-008
1206 REEL 10-16V 22UF
103-00004-011 103-A0103-001 103-A0308-001 105-00009-001 106-00010-001 106-00011-001 107-00001-030 107-00003-030 107-00004-030 107-00005-030 107-A0285-001 107-A0286-001 107-A0287-001 108-00023-110
CERAMIC 0.01UF 1206 1000 1206 CERAMIC 2312 HLMP-3950 LAMP GREEN HIGH INTEN EPROM 128K 120ONS 27C010 NM93C66N 4096-BIT SERIAL EEPROM PAL16L8-7PC INPUT,8 OUTPUT,A STANDARD 16R8 10NS VERSATILE 22V10 PAL16R6-7PC PAL16L8-5PC INPUT,8 OUTPUT,A PAL16R4-7 STANDARD PALCE16V8-7 CMOS 20-PIN UNIV 71B256SA-15Y BICMOS 256K
108-71323-611 108-71423-611 109-00014-601 109-00016-102 109-00067-301 109-00133-303 109-00806-116 109-01240-126 109-01244-126 109-01373-126 109-03374-901 109-04373-901 109-07033-100 109-16224-961
7132SA35J PLCC DUAL-PORTRAM 7142SA35J PLCC DUAL-PORT 2681 PLCC DUART TL7705B SUPPLY VOLTAGE SUPERVIS MAX248CQH RS232 DRIVER/RECEIVER V96BMC-33 PQFP BURST MEMORY CONTROL 49FCT806ASO SOIC BUFFER CLOCK DRIVE 74FCT240ATSO OCTAL BUFFER/LINE DRIV 74FCT244ATSO SOIC D_OCTAL LINE DRIV 74FCT373ATSO SOIC TRANS LATCH 74FCT162374ATPV SSOP 16-BIT REGISTE 74FCT162373ATPV SSOP TRANSPA ST7033 SOLIC TRANSFORMER 74FCT162245ATPV SSOP 16-BIT BIDIREC
109-16254-001 109-83932-301 109-96250-961
74FCT162543ATPV SSOP 16-BIT LATCHED DP83932VF NETWORK INTERFACE CONTROL 74FCT162500ATPV SSOP 18-BIT TRANSCE
CHAPTER
SCHEMATICS
Item
Code -110-30813-503 113-00001-102 113-00003-103 113-A0166-001 113-A0220-001 116-00001-001 116-00004-001 117-00016-001 117-00018-003 117-00025-001 117-00033-001 130-00161-001
Description -79R3081E-33MJ QUAD RISC CONTROLLER CRYSTAL 3.6864 PLASTIC CRYSTAL OSCILLATOR HCMOS 66MHZ PLASTIC CRYSTAL PLASTIC SWITCH, SPDT, PUSHBUTTON, RESET SWITCH STRAIGHT CONN POWER 4-PIN STRAIGHT CONN NUBUS MALE CONN DSUB 25PIN FEMA CONN DB15 FEMALE .318 MOUNT STRIPLINE MALE SINGLE TESTP
Quantity
TP13
TP12 TP11 TP10 TP23 TP22 TP21 TP17 TP18 TP15 TP16 TP14 TP19 130-00161-003 210-A0178-001 IDT_FIDUCIAL STRIPLINE MALE SINGLE SIMM DRAM FIDUCIAL,GENERAL USAGE
FD34 FD33 FD38 FD32 FD35 FD37 FD31 FD40 FD39 FD36 FD41 FD49 FD47 FD45 FD50 FD46 FD44 FD51 FD48 FD43 FD52 FD42 FD15 FD19 FD17 FD18 FD16 FD14 FD20 FD24 FD27 FD23 FD22 FD25 FD30 FD21 FD29 FD26 FD28 FD56 FD55 FD53 FD54
FD10 FD11 IDT_MTG_HOLE MOUNTING HOLE,GENERIC
FD13 FD12
MTG6 MTG4 MTG5 MTG2 MTG3 MTG1
IDT_ORIGIN
PICK PLACE ORIGIN
REPORT
CHAPTER
SCHEMATICS
UPGRADE PARTS LIST
ITEM DRAM DRAM DESCRIPTION 256KX32 DRAM SIMM-72PIN 70NS (TOSHIBA THM32250AS-70) (MICRON MT8D25632-7) 1MX32 DRAM SIMM-72PIN 70NS (TOSHIBA THM321000S-70) (MICRON MT8D132-7) QUANTITY
NOTES: DRAM 'X36' EQUIVALENTS ALSO ACCEPTABLE. 256KX8 EPROM WDIP-32 120NS (AM27C020-120DC) (TMS27C020-12JL) 512KX8 EPROM WDIP-32 120NS (AM27C040-120DC) (TMS27C040-12JL)
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SCHEMATICS
OFF-SHEET CROSS-REFERENCE SIGNALS LIST
Design Name R3081 Evaluation Board Time 03/30/94 15:46
DESIGN -ADBUS_XDIR ADDR2 ADDR2_B ADDR3 ADDR3_B BRANCH0 BRANCH2 BRANCH3 CLK1 CLK2 CLK3 CLK4 CLKEXP CLKSONIC D0A0 D0A1 D0A2 D0A3 D0A4 D0A5 D0A6 D0A7 D0A8 D0A9 D1A0 D1A1 D1A2 D1A3 D1A4 D1A5 D1A6 D1A7 D1A8 D1A9 DEVICE0 DEVICE1 DEVICE2 DIAG0 DIAG1 DRAM0_A0 DRAM0_A1 DRAM0_A2 DRAM0_A3 DRAM0_A4 DRAM0_A5 DRAM0_A6 DRAM0_A7 DRAM0_A8 DRAM0_A9 DRAM0_PUP0 DRAM0_PUP1 DRAM0_PUP2 DRAM0_PUP3 DRAM0_PUP4 DRAM0_PUP5
SHEETS -6,7 2,3,4,6 3,6,8,15,17,17,18,18,22 2,3,4,6 3,6,8,15,17,17,18,18,22 2,3,22 2,4,5,5 4,6,6 4,4,6 4,22 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,10 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11
CHAPTER
SCHEMATICS
DRAM0_PUP6 DRAM0_PUP7 DRAM1_A0 DRAM1_A1 DRAM1_A2 DRAM1_A3 DRAM1_A4 DRAM1_A5 DRAM1_A6 DRAM1_A7 DRAM1_A8 DRAM1_A9 DRAM1_PUP0 DRAM1_PUP1 DRAM1_PUP2 DRAM1_PUP3 DRAM1_PUP4 DRAM1_PUP5 DRAM1_PUP6 DRAM1_PUP7 EPROM_SEL0 EPROM_SEL1 EXP_DIR IDLEBUS LT_DIAG0 LT_DIAG1 PALPUP0 PALPUP1 PALPUP10 PALPUP2 PALPUP3 PALPUP4 PALPUP5 PALPUP6 PALPUP7 PALPUP8 PALPUP9 PUP0 PUP1 PUP2 PUP3 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESET SRAMAT0000 STAT0 STAT1 STAT2 STATEOE S_DATAXVRDIR TESTMODE ~ADBUS_XOE ~B0_RDOE ~B1_RDOE ~BE0 ~BE1 ~BE2 ~BE3 ~BERROR_CS ~BERROR_OE ~BUSERROROE
10,12 10,12 10,12 10,12 10,12 10,12 10,12 10,12 10,12 10,12 5,20 5,20 6,21 5,6,6,6 4,14 4,14 4,14 4,5,8 4,15,16,21 4,19 2,20 2,20 2,20 2,20 1,2,19,19 5,6,6,20 14,15 6,20 6,13 6,13 3,6,10,21 3,6,10,21 3,6,10,21 3,6,10,21 2,5,6
CHAPTER
SCHEMATICS
~BUSERROR ~BUSGRANT ~BUSREQ ~CLKBERROR ~CLKSONIC ~D0CAS0 ~D0CAS1 ~D0CAS2 ~D0CAS3 ~D0RAS0 ~D0RAS1 ~D0WE ~D1CAS0 ~D1CAS1 ~D1CAS2 ~D1CAS3 ~D1RAS0 ~D1RAS1 ~D1WE ~DATAEN ~DLYV3_CS ~DLYV3_READY ~DP_BUSY ~DP_CS ~DRAM0_CAS0 ~DRAM0_CAS1 ~DRAM0_CAS2 ~DRAM0_CAS3 ~DRAM0_RAS0 ~DRAM0_RAS1 ~DRAM0_WE ~DRAM1_CAS0 ~DRAM1_CAS1 ~DRAM1_CAS2 ~DRAM1_CAS3 ~DRAM1_RAS0 ~DRAM1_RAS1 ~DRAM1_WE ~DRAMOE ~DRAMWROE ~DRSRAM_CS ~EPROM_CS ~EXPBE0 ~EXPBE1 ~EXPBE2 ~EXPBE3 ~EXP_OE ~LSMST_AS ~LS_BR ~LS_SMACK ~PRE_ACK ~PRE_BERR ~PRE_RDCEN ~R3081ACK ~R3081BURST ~R3081BURST_B ~R3081RDCEN ~R3081RDWR ~R3081RD ~R3081RD_B ~R3081WR ~R3081WR_B
2,2,4,5,22 2,22 2,4,5,22 14,14,16 10,10,13 10,10,13 10,10,13 10,10,13 10,10 10,10 10,10 10,10,13 10,10,13 10,10,13 10,10,13 10,10 10,10 10,10 2,4,6,8,13,14,17,18,22 14,17,18 5,14 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,12 10,12 10,12 10,12 10,12 10,12 10,12 3,13 14,18,17 21,22 21,22 21,22 21,22 6,21 14,14 14,14 14,14 5,6,6 2,4,5,22 2,3,4,5,5,5,5,6,6,22 2,4,5,5,22 2,3,4,5,5,5,5,6,6,9,10,14,22 3,6,7 2,3,4,5,5,5,5,6,6,14,22, 3,6,7
CHAPTER
SCHEMATICS
~REFRESH ~RESET ~SDP_BUSY ~SMST_AS ~SMST_RD ~SONIC_ACK ~SONIC_CS ~SONIC_INT ~SRAMCS_HI ~SRAMCS_LO ~SRAMWEB0 ~SRAMWEB1 ~SRAMWEB2 ~SRAMWEB3 ~STERM ~SYSCLK ~S_ADDXVROE ~S_AD ~S_BGACK ~S_BG ~S_BR ~S_DACK0 ~S_DACK1 ~S_DATAXVROE ~S_DPCE ~S_DPOE ~S_DPWE ~S_MEMREQ ~S_SLAVERD ~S_SMACK ~UART_CS ~UART_INT ~UART_RD ~UART_WR ~USER_ACK ~USER_CS ~USER_INT ~V3ADS ~V3BLAST ~V3_BTERM ~V3_CS ~V3_DEN ~V3_INT ~V3_READY
1,2,5,5,6,10,14,16,20 14,17,18 14,14,16 14,14,14,16 6,14,16 2,4,16 6,9,17 6,9,17 6,9,18 6,9,18 14,16 2,4,5,5,10 14,15 6,16 14,14,14,16, 14,16 14,14,16 5,14,14,14,16 14,14,16 14,15 14,17,18 14,17,18 14,17,18 14,16 6,16 5,14,16 5,19 2,4,19 5,19 5,19 6,22 5,22 2,22 6,10 6,10 4,10 5,6,10 4,10 2,10 4,5,5,10
EQUATIONS
CHAPTER
EQUATIONS
CHAPTER
Integrated Device Technology, Inc.
EQUATIONS
following pages contain listings sixteen PLAs S381 board: MacABEL 3.11 Files Error Interrupt Sonic Control Interface State Machine Decoder State Machine State Machine MacABEL 4.01 Files Controller Data Driver Controller Address Decoder Signal Generator 11.RdCEn Output Select Sonic Address Data Control SRAM Dual-Port Controller SRAM Chip Select Decoder Interface Controller RdCEn Output
6-10 6-13 6-18
6-23 6-25 6-27 6-30 6-33 6-35 6-38 6-40 6-42 6-44
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EQUATIONS
module BusError flag `-r2',"-r2: simpe PRESTO reduction `-t1';"-t1: trace level title Name ~BusError Generator Designer PMcD Date 12-May-94 Board rev.: Checksum: 0x5393 MacABEL 3.11 Refdes. "Function: "Note: BusError_ moved from problems board "concerning this PALs pinout. "Note: Haven't implemented buserror source routine whereby choose "either error buserror from this PAL. "Rev. History: BERR DEVICE `P16R8'; "Inputs idlebus berrsource v3_berr_ "Outputs ClkBErr BusErroroe_ BusError_ count0 count1 count2 count3 count4
"BusError Reg. Clock "BusError Output Enable Control "BusError Signal
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; "Variables st_00 ^b000000; st_01 ^b000001; st_02 ^b000010; st_03 ^b000011; st_04 ^b000100; st_05 ^b000101; st_06 ^b000110; st_07 ^b000111;
st_08 st_09 st_10 st_11 st_12 st_13 st_14 st_15
^b001000; ^b001001; ^b001010; ^b001011; ^b001100; ^b001101; ^b001110; ^b001111;
st_16 st_17 st_18 st_19 st_20 st_21 st_22 st_23
^b010000; ^b010001; ^b010010; ^b010011; ^b010100; ^b010101; ^b010110; ^b010111;
st_24 st_25 st_26 st_27 st_28 st_29 st_30 st_31
^b011000; ^b011001; ^b011010; ^b011011; ^b011100; ^b011101; ^b011110; ^b011111;
state_diagram [count4.count0] state st_31: goto st_00; state st_00: (idlebus then st_01 else st_00; state st_01: (idlebus then st_02 else st_00; state st_02: (idlebus then st_03
"Reset State "Idle State
EQUATIONS
CHAPTER
else st_00; state st_03: (idlebus else st_00; state st_04: (idlebus else st_00; state st_05: (idlebus else st_00; state st_06: (idlebus else st_00; state st_07: (idlebus else st_00; state st_08: (idlebus else st_00; state st_09: (idlebus else st_00; state st_10: (idlebus else st_00; state st_11: (idlebus else st_00; state st_12: (idlebus else st_00; state st_13: (idlebus else st_00; state st_14: (idlebus else st_00; state st_15: (idlebus else st_00; state st_16: (idlebus else st_00; state st_17: (idlebus else st_00; state st_18: (idlebus else st_00; state st_19: (idlebus else st_00; state st_20: (idlebus else st_00; state st_21: (idlebus then st_04
then st_05
then st_06
then st_07
then st_08
then st_09
then st_10
then st_11
then st_12
then st_13
then st_14
then st_15
then st_16
then st_17
then st_18
then st_19
then st_20
then st_21
then st_22
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EQUATIONS
else st_00; state st_22: (idlebus else st_00; state st_23: (idlebus else st_00; state st_24: (idlebus else st_00; state st_25: (idlebus else st_00; state st_26: (idlebus else st_00; state st_27: (idlebus else st_00; state st_28: (idlebus then st_23
then st_24
then st_25
then st_26
then st_27
then st_28
then st_29 with ClkBErr BusErroroe_ endwith;
else st_00; state st_29: (idlebus then st_30 with BusError_ BusErroroe_ endwith; else st_00; state st_30: (idlebus then st_31 with BusErroroe_ endwith; else st_00; "[st5:st0],rdcen_,ack_ test vectors test_vectors ([Clk,idlebus] [st_31,1,1,1]; [st_00,1,1,1]; [st_01,1,1,1]; [st_00,1,1,1]; [st_01,1,1,1]; [st_00,1,1,1]; [st_00,1,1,1]; [st_01,1,1,1]; [st_02,1,1,1]; [st_03,1,1,1]; [st_04,1,1,1]; [st_05,1,1,1]; [st_06,1,1,1]; [st_07,1,1,1]; [st_08,1,1,1]; [st_09,1,1,1]; [st_10,1,1,1]; [st_11,1,1,1]; [st_12,1,1,1];
EQUATIONS
CHAPTER
[st_13,1,1,1]; [st_14,1,1,1]; [st_15,1,1,1]; [st_16,1,1,1]; [st_17,1,1,1]; [st_18,1,1,1]; [st_19,1,1,1]; [st_20,1,1,1]; [st_21,1,1,1]; [st_22,1,1,1]; [st_23,1,1,1]; [st_24,1,1,1]; [st_25,1,1,1]; [st_26,1,1,1]; [st_27,1,1,1]; [st_28,1,1,1]; [st_29,0,1,0]; [st_30,1,0,0]; [st_31,1,1,0]; [st_00,1,1,1]; [st_00,1,1,1];
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EQUATIONS
module Interrupt flag '-r2',"-r2: simpe PRESTO reduction '-t1' "-t1: trace level title Name Interrupt Generator Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x2878 MacABEL 3.11 Refdes. "Function: buserrorcs_ will serve enable clearing buserror input chooses user buserror input drive interrupt. "Rev. History: DEVICE 'P16V8R'; "Inputs buserror_ v3int_ sonicint_ uartint_ userint_ buserrorcs_ oe0_ oe1_ "Outputs int0_ int1_ int2_ int3_ int4_ int5_
"Output enable combinatorial outputs "Output enable registered outputs
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations int0_ int1_ int2_ int3_ int4_ int5_ v3int_; sonicint_; uartint_;
"Reserved.
Default R3081 Int.
!enable !enable !enable !enable !enable !enable
int0_ int1_ int2_ int3_ int4_ int5_
oe1_; oe1_; oe1_; oe1_; oe1_; oe1_;
"Output Enable Equations
EQUATIONS
CHAPTER
"int[5:0]_, test vectors test_vectors br3])
[Z,Z,Z,Z,Z,Z, [X,X,1,1,1,X, [1,1,1,1,1,1, [0,1,1,1,1,1, [1,0,1,1,1,1, [1,1,1,1,1,0, [0,0,1,1,1,0, "oe_
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EQUATIONS
module Sonicctl flag '-r2',"-r2: simpe PRESTO reduction '-t1';"-t1: trace level title Name Sonic Control Interface Designer SKhan Date 16-May-94 Board rev.: Checksum: 0x29AC MacABEL 3.11 Refdes. "Function: "Rev. History: SONICCTL DEVICE 'P16R4'; "Inputs dclk BGACK_ S_RESET_ L_AS_ MRW_ L_BR_ LS_SMACK "Outputs CWE_ DACK_ bclk_ bclk 14;" 15;" 16;" "connected input
"CONSTANTS L,H,Z,X,C 0,1,.Z.,.X.,.C.; operation [S_RESET_, L_AS_]; Reset [0,1]; idle cyclestart Pstate [st1, st0]; st_0 st_1 st_2 equations !CWE_ (Pstate ==st_1) !BGACK_ !MRW_; !DACK_ (Pstate st_1); L_BR_
EQUATIONS
CHAPTER
bclk !dclk; bclk conected bclk_ dclk; !enable DACK_ !LS_SMACK; "Ouput Enable Equation
state_diagram Pstate state st_0: case (operation Reset): st_0; (operation idle): st_0; (operation cyclestart): st_1; endcase; state st_1: goto st_2; state st_2: goto st_0; TEST_VECTORS ([LS_SMACK, clk, S_RESET_, L_AS_, MRW_, BGACK_, L_BR_] [Pstate, CWE_, DACK_, BG_]) [st_0, [st_0, [st_0, [st_0, [st_1, [st_2, [st_0, [st_1, [st_2, write cycle begin read cycle begin
CHAPTER
EQUATIONS
module StateDcd flag '-r2',"-r2: simpe PRESTO reduction '-t1' "-t1: trace level title Name State Machine Decode Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0xD9A9 MacABEL 3.11 Refdes. "Function: "Rev. History: STATEDCD DEVICE 'P22V10'; "Inputs r3081rd_ r3081wr_ r3081burst_ state0 "generated main state machine state1 "ditto state2 "ditto state3 "ditto sonicsmack_ sonicdsack_ "Outputs UARTwr_ UARTrd_ stall sonicack_ count0 count1 count2 count3
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; "Variables Condition [state3.state0]; st_00 st_01 st_02 st_03 ^b00000; ^b00001; ^b00010; ^b00011; st_04 st_05 st_06 st_07 ^b00100; ^b00101; ^b00110; ^b00111; st_08 st_09 st_10 st_11 ^b01000; ^b01001; ^b01010; ^b01011; st_12 st_13 st_14 st_15 ^b01100; ^b01101; ^b01110; ^b01111;
state_diagram [count3.count0] state st_15: goto st_00; state st_00: (Condition then st_01 else (Condition then st_01 else (Condition then st_01 else
"Reset State "Idle State
EQUATIONS
CHAPTER
st_00; state st_01: goto st_02; state st_02: goto st_03; state st_03: (Condition then st_04 else st_15 with stall endwith; state st_04: goto st_05; state st_05: !r3081rd_ then st_06 with UARTrd_ endwith else st_06 with UARTwr_ endwith; state st_06: !r3081rd_ then st_07 with UARTrd_ endwith else st_07 with UARTwr_ endwith; state st_07: !r3081rd_ then st_08 with UARTrd_ endwith else st_08 with UARTwr_ endwith; state st_08: !r3081rd_ then st_09 with UARTrd_ endwith else st_09 with UARTwr_ endwith; state st_09: !r3081rd_ then st_10 with UARTrd_ stall endwith else st_10 with UARTwr_ endwith; state st_10: !r3081rd_ then st_11 with UARTrd_ endwith else st_11 with UARTwr_ endwith; state st_11: !r3081rd_ then st_12 with UARTrd_ endwith else st_12 with UARTwr_ stall endwith; state st_12: !r3081rd_ then st_15 with UARTrd_ endwith else st_15 with UARTwr_ endwith; equations !sonicack_ !sonicdsack_ !sonicsmack_; "[st5:st0],rdcen_,ack_ test vectors test_vectors
"SONIC signal
[st_15,1, 1,1]; [st_00,1, 1,1]; "Idle [st_01,1, 1,1]; "EPROM read [st_02,1, 1,1]; [st_03,1, 1,1]; [st_15,0, 1,1]; [st_00,1, 1,1];
CHAPTER
EQUATIONS
[st_01,1, [st_02,1, [st_03,1, [st_15,0, [st_00,1, [st_00,1, [st_00,1, [st_01,1, [st_02,1, [st_03,1, [st_04,1, [st_05,1, [st_06,1, [st_07,1, [st_08,1, [st_09,1, [st_10,0, [st_11,1, [st_12,1, [st_15,1, [st_00,1, [st_01,1, [st_02,1, [st_03,1, [st_04,1, [st_05,1, [st_06,1, [st_07,1, [st_08,1, [st_09,1, [st_10,1, [st_11,1, [st_12,0, [st_15,1, [st_00,1, [st_00,1, [st_00,1, [st_00,1, [st_00,1, [st_00,1, [st_00,1,
1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 0,1]; 0,1]; 0,1]; 0,1]; 0,1]; 0,1]; 0,1]; 0,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,0]; 1,0]; 1,0]; 1,0]; 1,0]; 1,0]; 1,0]; 1,0]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 1,1];
"invalid condition "Idle "DUART read
"Idle "DUART write
"Idle "invalid conditions
"sonicack_ test vectors test_vectors ([Clk,sonicdsack_,sonicsmack_]
[sonicack_]) [0]; [1]; [1]; [1];
EQUATIONS
CHAPTER
module StateofMind1 flag '-r2',"-r2: simpe PRESTO reduction '-t1' "-t1: trace level title Name State Machine Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x51D3 MacABEL 3.11 Refdes. "Function: "Rev. History: "Need resetable ~Bus Error user space only. part board "doesn't work other stuff, EPROM, UART, etc., then board won't "work anyway, point putting error negation since board "wont able read EPROM read write UART. STATES1 DEVICE 'P22V10'; "Inputs r3081rd_ r3081wr_ r3081burst_ device0 device1 device2 stallstate berror_ reset_
"generated address decoder "ditto "ditto "active output enable ack_ rdcen_
from another PAL. gets clock from R3081 clocks "read write lines processor. When sees low, waits cycle processor decode start before allows state "machine That know dealing with invalid decode. "Outputs epromwr_ ack_ rdcen_
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; "Device Select Decode: EPROM SRAM wait states) UART SONIC Error Register User DualPort SRAM
CHAPTER
EQUATIONS
Undefined (Default)
"Variables [device2.device0]; Operation Reset Idle EPROMrd EPROMwr SRAMrd SRAMwr UARTrd UARTwr
"Reset condition "Idle "EPROM Read "EPROM Write (ROM Emulators) "SRAM Read wait states) "SRAM Write wait states) "UART Read "UART Write
"These functions incorporated State Machine SONICrd "SONIC Read SONICwr "SONIC Write BERRrd "Bus Error Register Read BERRwr "Undefined Operations USERwr "User Read USERrd "User Write DPSRAMrd "DualPort SRAM Read DPSRAMwr "DualPort SRAM Write Otherrd Otherwr st_00 st_01 st_02 st_03 ^b00000; ^b00001; ^b00010; ^b00011; st_04 st_05 st_06 st_07 ^b00100; ^b00101; ^b00110; ^b00111; st_08 st_09 st_10 st_11 ^b01000; ^b01001; ^b01010; ^b01011; st_12 st_13 st_14 st_15 ^b01100; ^b01101; ^b01110; ^b01111;
state_diagram [st3.st0] state st_15: goto st_00; state st_00: case (Operation Reset) (Operation Idle) (Operation EPROMrd) (Operation EPROMwr) (Operation SRAMrd) (Operation SRAMwr) (Operation UARTrd) (Operation UARTwr) (Operation SONICrd) (Operation SONICwr) (Operation BERRrd) (Operation BERRwr) (Operation USERwr) (Operation USERrd) (Operation DPSRAMrd) (Operation DPSRAMwr) (Operation Otherrd) (Operation Otherwr) endcase; state st_01: !r3081rd_ then st_02 else st_02
"Reset State "Idle/Decode State :st_00; :st_00; :st_01; :st_01; :st_10; :st_10; :st_14; :st_14; :st_15; :st_15; :st_15; :st_15; :st_15; :st_15; :st_15; :st_15; :st_15; :st_15;
"EPROM read
EQUATIONS
CHAPTER
with epromwr_ endwith; state st_02: (!r3081rd_ r3081burst_) then st_00 with ack_ rdcen_ endwith; else !r3081wr_ then st_00 with ack_ rdcen_ epromwr_ endwith; else st_03 with rdcen_ endwith; state st_03: stallstate then st_03 else st_04 with rdcen_ endwith; state st_04: stallstate then st_04 else st_05 with rdcen_ endwith; state st_05: goto st_06; state st_06: ack_ goto st_07; state st_07: goto st_08; state st_08: goto st_09; state st_09: rdcen_ goto st_00; state st_10: (!r3081rd_ r3081burst_ !r3081wr_) then st_00 with ack_ rdcen_ endwith; else st_11 with ack_ rdcen_ endwith; state st_11: rdcen_ goto st_12; state st_12: rdcen_ goto st_13; state st_13: rdcen_ goto st_00; state st_14: stallstate then st_14 else st_00 with ack_ rdcen_ endwith; equations
"EPROM write
"Single word read
"EPROM write
"Burst "data0
"data1
"data2
"data3 "SRAM read/write wait state) "Single word read/write
"Burst read
"UART read/write
CHAPTER
EQUATIONS
!enable ack_ oe_; !enable rdcen_ oe_;
"Output Enable Equations
"[st3:st0],rdcen_,ack_ test vectors test_vectors [[st3.st0], rdcen_,ack_]) X,1] [st_15,1,1]; X,1] [st_15,Z,Z]; "oe_ X,1] [st_00,1,1]; X,1] [st_00,1,1]; "Idle X,1] [st_00,1,1]; 0,1] [st_00,1,1]; "EPROM Read 0,1] [st_01,1,1]; "Quad word 0,1] [st_02,1,1]; 0,1] [st_03,0,1]; 0,1] [st_03,1,1]; 0,0] [st_04,0,1]; 0,1] [st_04,1,1]; 0,0] [st_05,0,1]; 0,X] [st_06,1,1]; 0,X] [st_07,1,0]; 0,X] [st_08,1,1]; 0,X] [st_09,1,1]; 0,X] [st_00,0,1]; 0,X] [st_00,1,1]; 0,X] [st_00,1,1]; "Idle 0,X] [st_00,1,1]; "EPROM Read 0,X] [st_01,1,1]; "Single word 0,X] [st_02,1,1]; 0,X] [st_00,0,0]; 0,X] [st_00,1,1]; 0,X] [st_00,1,1]; X,X] [st_00,1,1]; "Idle 1,X] [st_00,1,1]; "SRAM Read 1,X] [st_10,1,1]; "Quad word 1,X] [st_11,0,0]; 1,X] [st_12,0,1]; 1,X] [st_13,0,1]; 1,X] [st_00,0,1]; X,X] [st_00,1,1]; "Idle 1,X] [st_00,1,1]; "SRAM Read 1,X] [st_10,1,1]; "Single word 1,X] [st_00,0,0]; X,X] [st_00,1,1]; "Idle 1,X] [st_00,1,1]; "SRAM Write 1,X] [st_10,1,1]; 1,X] [st_00,0,0]; X,X] [st_00,1,1]; "Idle 2,1] [st_00,1,1]; "UART Read 2,1] [st_14,1,1]; 2,1] [st_14,1,1]; 2,0] [st_00,0,0]; X,X] [st_00,1,1]; "Idle 2,1] [st_00,1,1]; "UART Write 2,1] [st_14,1,1]; 2,1] [st_14,1,1];
EQUATIONS
CHAPTER
2,0] [st_00,0,0]; X,X] [st_00,1,1]; "Idle
"devices controlled State Machine 3,1] [st_15,1,1]; "SONIC 3,1] [st_00,1,1]; 3,1] [st_00,1,1]; 3,1] [st_15,1,1]; 3,1] [st_00,1,1]; 3,1] [st_00,1,1]; 4,1] [st_15,1,1]; "Bus Error Register 4,1] [st_00,1,1]; 4,1] [st_00,1,1]; 4,1] [st_15,1,1]; 4,1] [st_00,1,1]; 4,1] [st_00,1,1]; 5,1] [st_15,1,1]; "User 5,1] [st_00,1,1]; 5,1] [st_00,1,1]; 5,1] [st_15,1,1]; 5,1] [st_00,1,1]; 5,1] [st_00,1,1]; 6,1] [st_15,1,1]; "DPSRAM 6,1] [st_00,1,1]; 6,1] [st_00,1,1]; 6,1] [st_15,1,1]; 6,1] [st_00,1,1]; 6,1] [st_00,1,1]; 7,1] [st_15,1,1]; "Undefined (Default) 7,1] [st_00,1,1]; 7,1] [st_00,1,1]; 7,1] [st_15,1,1]; 7,1] [st_00,1,1]; 7,1] [st_00,1,1];
CHAPTER
EQUATIONS
module StateofMind2 flag '-r2',"-r2: simpe PRESTO reduction '-t1' "-t1: trace level title Name State Machine Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x8C28 MacABEL 3.11 Refdes. "Function: "Rev. History: "Need resetable ~Bus Error user space only. part board "doesn't work other stuff, EPROM, UART, etc., then board won't "work anyway, point putting error negation since board "wont able read EPROM read write UART. "Output enable ack_ rdcen_ outputs. Don't know wether combine "the state output bits. think that would mean world hurt "second state machine. STATES2 DEVICE 'P22V10'; "Inputs r3081rd_ r3081wr_ r3081burst_ device0 device1 device2 userack_ buserror_ reset_ sonicack_
"generated address decoder "ditto "ditto "active high output enable ack_ rdcen_
from another PAL. gets clock from R3081 clocks "read write lines processor. When sees low, waits cycle processor decode start before allows state "machine That know dealing with invalid decode. "use another address line determine appropriate address. "only single word reads from user space supported. "Outputs sonicsas_ soniccs_ ack_ rdcen_
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.;
EQUATIONS
CHAPTER
"Device Select Decode: EPROM SRAM wait states) UART SONIC Error Register User DualPort SRAM Undefined (Default) "Variables [device2.device0]; Operation Reset Idle SONICrd SONICwr BERRrd BERRwr USERwr USERrd DPSRAMrd DPSRAMwr
"Reset condition "Idle "SONIC Read "SONIC Write "Bus Error Register Read "Undefined Operations "User Read "User Write "DualPort SRAM Read "DualPort SRAM Write
"These functions incorporated State Machine EPROMrd "EPROM Read EPROMwr "EPROM Write (ROM Emulators) SRAMrd "SRAM Read wait states) SRAMwr "SRAM Write wait states) UARTrd "UART Read UARTwr "UART Write Otherrd Otherwr st_00 st_01 st_02 st_03 ^b00000; ^b00001; ^b00010; ^b00011; st_04 st_05 st_06 st_07 ^b00100; ^b00101; ^b00110; ^b00111; st_08 st_09 st_10 st_11 ^b01000; ^b01001; ^b01010; ^b01011; st_12 st_13 st_14 st_15 ^b01100; ^b01101; ^b01110; ^b01111;
state_diagram [st3.st0] state st_15: goto st_00; state st_00: case (Operation Reset) (Operation Idle) (Operation SONICrd) (Operation SONICwr) (Operation BERRrd) (Operation BERRwr) (Operation USERrd) (Operation USERwr) (Operation DPSRAMrd) (Operation DPSRAMwr) (Operation EPROMrd) (Operation SRAMrd) (Operation SRAMwr) (Operation UARTrd) (Operation UARTwr)
"Reset State "Idle/Decode State :st_00; :st_00; :st_02; :st_02; :st_08; :st_15; :st_01; :st_01; :st_08; :st_08; :st_15; :st_15; :st_15; :st_15; :st_15;
CHAPTER
EQUATIONS
(Operation Otherrd) :st_15; (Operation Otherwr) :st_15; endcase; state st_01: (reset_ buserror_ userack_) then st_01 else st_00 with rdcen_ ack_ endwith; state st_02: sonicsas_ goto st_03; state st_03: (!r3081rd_) then st_05 with sonicsas_ soniccs_ endwith; else st_04 with sonicsas_ soniccs_ endwith; state st_04: (reset_ buserror_ sonicack_) then st_04 with sonicsas_ soniccs_ endwith; else st_00 with sonicsas_ soniccs_ rdcen_ ack_ endwith; state st_05: (reset_ buserror_ sonicack_) then st_05 with sonicsas_ soniccs_ endwith; else st_06 with sonicsas_ soniccs_ rdcen_ ack_ endwith; state st_06: sonicsas_ soniccs_ goto st_00; state st_08: (!r3081rd_ r3081burst_ !r3081wr_) then st_00 with rdcen_ ack_ endwith; else st_09 with rdcen_
"User read/write
"SONIC slave read/write
"read
"write
"read (continued)
"DPSRAM read/write "Single word read/write
"Burst "data
EQUATIONS
CHAPTER
endwith; state st_09: goto st_10; state st_10: rdcen_ goto st_11; state st_11: ack_ goto st_12; state st_12: rdcen_ goto st_13; state st_13: goto st_14; state st_14: rdcen_ goto st_00; equations enable ack_ enable rdcen_
"data
"data
"data
"Output Enable Equations
"[st3:st0],rdcen_,ack_ test vectors test_vectors buserror_] X,1,1,1] [st_15,1,1,1,1]; X,1,1,1] [st_15,Z,Z,1,1]; X,1,1,1] [st_00,1,1,1,1]; X,1,1,1] [st_00,1,1,1,1]; 5,1,1,1] [st_00,1,1,1,1]; 5,1,1,1] [st_01,1,1,1,1]; 5,1,1,1] [st_01,1,1,1,1]; 5,1,1,1] [st_00,0,0,1,1]; X,1,1,1] [st_00,1,1,1,1]; 5,1,1,1] [st_00,1,1,1,1]; 5,1,1,1] [st_01,1,1,1,1]; 5,1,1,1] [st_01,1,1,1,1]; 5,1,1,0] [st_00,0,0,1,1]; X,1,1,1] [st_00,1,1,1,1]; 5,1,1,1] [st_00,1,1,1,1]; 5,1,1,1] [st_01,1,1,1,1]; 5,1,1,1] [st_01,1,1,1,1]; 5,0,1,1] [st_00,0,0,1,1]; X,1,1,1] [st_00,1,1,1,1]; 6,1,1,1] [st_00,1,1,1,1]; 6,1,1,1] [st_08,1,1,1,1]; 6,1,1,1] [st_09,0,1,1,1]; 6,1,1,1] [st_10,1,1,1,1]; 6,1,1,1] [st_11,0,1,1,1]; 6,1,1,1] [st_12,1,0,1,1]; 6,1,1,1] [st_13,0,1,1,1]; 6,1,1,1] [st_14,1,1,1,1]; 6,1,1,1] [st_00,0,1,1,1]; 0,1,1,1] [st_00,1,1,1,1]; X,1,1,1] [st_00,1,1,1,1]; 6,1,1,1] [st_08,1,1,1,1]; 0,1,1,1] [st_00,0,0,1,1]; 0,1,1,1] [st_00,1,1,1,1]; X,1,1,1] [st_00,1,1,1,1]; 6,1,1,1] [st_00,1,1,1,1]; 6,1,1,1] [st_08,1,1,1,1]; 0,1,1,1] [st_00,0,0,1,1];
"Idle "User Read
"reset_ "Idle "User Read
"buserror_ "Idle "User Read
"userack_ "Idle "DPSRAM Read "Quad word
"Idle "Single word
"Idle "DPSRAM Write
CHAPTER
EQUATIONS
0,1,1,1] [st_00,1,1,1,1]; X,1,1,1] [st_00,1,1,1,1]; "Idle 6,1,1,1] [st_00,1,1,1,1]; "BusError Read 6,1,1,1] [st_08,1,1,1,1]; "Single word 0,1,1,1] [st_00,0,0,1,1]; 0,1,1,1] [st_00,1,1,1,1]; X,1,1,1] [st_00,1,1,1,1]; "Idle 3,1,1,1] [st_00,1,1,1,1]; "SONIC Read 3,1,1,1] [st_02,1,1,1,1]; "Single word 3,1,1,1] [st_03,1,1,0,1]; 3,1,1,1] [st_05,1,1,0,0]; 3,1,1,1] [st_05,1,1,0,0]; 3,1,0,1] [st_06,0,0,0,0]; 3,1,1,1] [st_00,1,1,0,0]; X,1,1,1] [st_00,1,1,1,1]; "Idle 3,1,1,1] [st_00,1,1,1,1]; "SONIC Write 3,1,1,1] [st_02,1,1,1,1]; 3,1,1,1] [st_03,1,1,0,1]; 3,1,1,1] [st_04,1,1,0,0]; 3,1,1,1] [st_04,1,1,0,0]; 3,1,0,1] [st_00,0,0,0,0]; X,1,1,1] [st_00,1,1,1,1]; "Idle
"devices controlled State Machine
1,1,1,1] 1,1,1,1] 1,1,1,1] 1,1,1,1] 1,1,1,1] 1,1,1,1] 2,1,1,1] 2,1,1,1] 2,1,1,1] 2,1,1,1] 2,1,1,1] 2,1,1,1] 7,1,1,1] 7,1,1,1] 7,1,1,1] 7,1,1,1] 7,1,1,1] 7,1,1,1]
[st_15,1,1,1,1]; "EPROM [st_00,1,1,1,1]; [st_00,1,1,1,1]; [st_15,1,1,1,1]; [st_00,1,1,1,1]; [st_00,1,1,1,1]; [st_15,1,1,1,1]; "SRAM [st_00,1,1,1,1]; [st_00,1,1,1,1]; [st_15,1,1,1,1]; [st_00,1,1,1,1]; [st_00,1,1,1,1]; [st_15,1,1,1,1]; "Uart [st_00,1,1,1,1]; [st_00,1,1,1,1]; [st_15,1,1,1,1]; [st_00,1,1,1,1]; [st_00,1,1,1,1];
EQUATIONS
CHAPTER
module ADBusCtl title Name A/D[31:0] Control Designer PMcD Date 14-Apr-94 Board rev.: Checksum: 0x3278 MacABEL 4.01 Refdes. "Function: Controls '245 '543 buffers driving data A/D[31:0] bus. '543 transceivers drive data from DRAMs. Data from other sources, EPROMs, SRAMs, DUART, Ethernet, Dual Ports, driven '245's. During writes, '245's always drives R3081 word Data[31:0] bus. During DRAM reads, '245's drive Data[31:0] with DRAM word A/D[31:0] expansion connector data. ADBUSCTL DEVICE 'P16L8'; "Inputs r3081rd_ r3081wr_ dataen_ v3cs_ dlyv3cs_ addr2 addr3 SRAMat0 "Outputs adbus_xdir adbus_xoe_ DRAMb0_oe_ DRAMb1_oe_
"'245 "'245 "'543 "'542
signal signal signal (DRAM even words) signal (DRAM words)
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations !adbus_xdir !r3081wr_ !r3081rd_ !SRAMat0 !(v3cs_ dlyv3cs_); "write cycle cycle DRAM
"read
!adbus_xoe_ !r3081wr_ !r3081rd_ !dataen_; !DRAMb0_oe_ !r3081rd_ !dataen_ !SRAMat0 !(v3cs_ !DRAMb1_oe_ !r3081rd_ !dataen_ !SRAMat0 !(v3cs_ dlyv3cs_) !addr2; dlyv3cs_) addr2;
"write cycle "read cyele
"read DRAM even "read DRAM
test vectors test_vectors DRAMb1_oe_]) [1,1, 1,1];
idle
CHAPTER
EQUATIONS
[0,0, [1,1, [1,0, [1,1, [1,0, [0,0, [0,0, [0,0, [0,1, [0,0, [0,0, [0,0, [0,1, [1,0, [1,1,
1,1]; 1,1]; 1,1]; 1,1]; 1,1]; 0,1]; 0,1]; 0,1]; 1,1]; 1,0]; 1,0]; 1,0]; 1,1]; 1,1]; 1,1];
write read read
"DRAM reads
"SRAM reads
EQUATIONS
CHAPTER
module DataCtl title Name Data Driver Control Designer PMcD Date 09-May-94 Board rev.: Checksum: 0x278D MacABEL 4.01 Refdes. "Function: generates SONIC Error ~OE, expansion connector control signals. Invoking testmode defines expansion connector output only connector whose Data[31:0] pins snoop RISController's A/D[31:0] bus. Testmode invokes setting switch S2:4 OFF. When S2:4 testmode invoked, expansion connector connector that drive (off board) writes drives board's data bus) User area reads. DATACTL DEVICE `P16L8'; "Inputs r3081rd_ r3081wr_ r3081burst_ dataen_ berrcs_ testmode usercs_ "Outputs sonicrd berroe_ expxvrdir expxvroe_
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations !berroe_ !berrcs_ !dataen_; !sonicrd !r3081wr_; !expxvrdir !testmode !r3081rd_; !expxvroe_ testmode !testmode !usercs_ (!r3081rd_ !dataen_ !r3081wr_); "berroe test vectors test_vectors ([berrcs_,dataen_]
[berroe_]) [0]; [1]; [1]; [1];
CHAPTER
EQUATIONS
"sonicrd test vectors test_vectors ([r3081wr_] [sonicrd]) [0]; [1]; "berroe test vectors test_vectors
[expxvrdir,expxvroe_]) [1,1]; "Bus idle [0,1]; "Read [0,1]; [0,0]; "Read User space [1,0]; "Write [1,0]; "testmode
EQUATIONS
CHAPTER
module Decode title Name Address Decode Designer PMcD Board rev.: MacABEL 4.01 "Function: "Rev. History: DECODE DEVICE 'P22V10'; "Inputs add29,add28 add27,add26 add25,add24 add23,add22 add21,add20 eprom_sel0 eprom_sel1 SRAMat0
Date 13-Apr-94 Checksum: 0xAE8B Refdes.
10,9; 8,7; 6,5; 4,3; 2,1;
"Eprom Select Decode: 128kx8 EPROMs 256kx8 EPROMs 512kx8 EPROMs undefined "Outputs device0 device1 device2 dpsram_ usercs_ epormcs_ uartcs_ buserrorcs_ stateoe_
"Device Select Decode: EPROM SRAM wait states) UART SONIC Error Register User DualPort SRAM Undefined (Default) "Constants L,H,Z,X,C eprom_1Mmax eprom_2Mmax eprom_4Mmax
0,1,.Z.,.X.,.C.; ^h1fc7ffff; 512k bytes (4x131,072 bytes) ^h1fcfffff; "1024k bytes (4x262,144 bytes) ^h1fdfffff; "2048k bytes (4x524,288 bytes)
"Variables [device2.device0]; eprom_sel [eprom_sel1,eprom_sel0];
CHAPTER
EQUATIONS
[add29.add20, X,X,X,X, X,X,X,X, X,X,X,X, X,X,X,X, X,X,X,X]; "Macros EPROM_1M macro {((eprom_sel (add eprom_1Mmax))}; EPROM_2M macro {((eprom_sel (add eprom_2Mmax))}; EPROM_4M macro {((eprom_sel (add eprom_4Mmax))}; equations "Note: Abel complies active definitions more efficiently than active high ones. Compiled version active high 'dev' equation will 20L8 PAL. !dev (((((add ^h00100000)) SRAMat0) (((add ^h04100000)) !SRAMat0)) [1,1,0]) ((add ^h04400000) [0,0,1]) (((add ^h1fa00000) [0,1,0]) ((add ^h1fb00000) [1,0,0]) ((add ^h1fc00000) (EPROM_1M EPROM_2M EPROM_4M) [1,1,1]) ((add ^h1fe00000) [1,0,1]) ((add ^h1ff00000) [0,1,1])); stateoe_ (add ^h1fb00000) (add ^h1ff00000) (add ^h1fa00000) (add ^h04400000); !dpsram_ !usercs_ !epormcs_ "SONIC "Bus Error Register "User "DualPort SRAM "Dual Port SRAM "reset 2048kb "reset 512kb "reset 1024kb "reset 2048kb "reset 2048b "reset 3072b "SRAM "SRAM 65Mb "DualPort SRAM "User "SONIC "EPROM 512kb "EPROM 1024kb "EPROM 2048kb "UART "Bus Error Register
(add ^h04400000); (add ^h1fa00000); (add ^h1fc00000) (EPROM_1M EPROM_2M EPROM_4M); (add ^h1fe00000);
!uartcs_
!buserrorcs_ (add ^h1ff00000);
test vectors test_vectors ([add,eprom_sel,SRAMat0] stateoe_]) [^h00000000, [1,1,1,1,1,7,0]; "DRAM (Decoded memory ctlr.) [^h00000000, [1,1,1,1,1,7,0]; "SRAM zero wait state ^h0000 0000 [^h00100000, [1,1,1,1,1,1,0]; "SRAM wait state ^h0010 0000 [^h04000000, [1,1,1,1,1,7,0]; "SRAM zero wait state ^h0400 0000 [^h04100000, [1,1,1,1,1,1,0]; "SRAM wait state ^h0410 0000 [^h04400000, [1,1,1,1,0,6,1]; "Dual Port SRAM [^h05000000, [1,1,1,1,1,7,0]; "undefined [^h1fa00000, [1,1,0,1,1,5,1]; "User [^h1fb00000, [1,1,1,1,1,3,1]; "SONIC slave mode [^h1fc00000, [0,1,1,1,1,0,0]; "128kx8 EPROMs [^h1fc7ffff, [0,1,1,1,1,0,0]; [^h1fc80000, [0,1,1,1,1,0,0];
EQUATIONS
CHAPTER
[^h1fcfffff, [^h1fd00000, [^h1fd7ffff, [^h1fd80000, [^h1fdfffff, [^h1fc00000, [^h1fc7ffff, [^h1fc80000, [^h1fcfffff, [^h1fd00000, [^h1fd7ffff, [^h1fd80000, [^h1fdfffff, [^h1fc00000, [^h1fc7ffff, [^h1fc80000, [^h1fcfffff, [^h1fd00000, [^h1fd7ffff, [^h1fd80000, [^h1fdfffff, [^h1fe00000, [^h1ff00000,
[0,1,1,1,1,0,0]; [1,1,1,1,1,7,0]; [1,1,1,1,1,7,0]; [1,1,1,1,1,7,0]; [1,1,1,1,1,7,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [1,1,1,1,1,7,0]; [1,1,1,1,1,7,0]; [1,1,1,1,1,7,0]; [1,1,1,1,1,7,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [0,1,1,1,1,0,0]; [1,0,1,1,1,2,0]; [1,1,1,0,1,4,1];
"256kx8 EPROMs
"512kx8 EPROMs
"Uart "Bus Error Register
Even though only 512kbytes EPROM exist, minimum decode space 1Mbyte this address will decoded valid EPROM space.
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EQUATIONS
module title Name Signal Generator Control Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x368E MacABEL 4.01 Refdes. "Function: Generates signal rising edge ~SysClk cycle after read write cycle started. State machine running falling edge ~SysClk needs cycle delay sample valid device decode bits. (Similar cycle-end concept except only very different.) ~BusReq ~Busreq used generate idle cycle between read write cycle solve turnaround issues. Yes, r3081 does incorporate turnaround mode internally, maintain compatibility with r3051/2 devices, turnaround problem solved asserting external ~busreq signal. asynchronous nature zero-wait state read, specifically one-word read, ~busreq asynchronously asserted during first cycle one-word read. Syncoutput intent here synchronize external signal with ~SysClk's rising edge. Since this only actually based ~SysClk, done here. Granted this function little superfluous PAL. Nonetheless, that's what does when want minimize ~SysClk loading. "Rev. History: DEVICE 'P16R6'; "Inputs r3081rd_ r3081wr_ r3081burst_ rdcen_ asyncIN0 asyncIN1 reset_ "Outputs busreq_ breqct0_ idlebus syncOUT0 syncOUT1
"v3_ready_ "v3_cs_
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations
EQUATIONS
CHAPTER
idlebus
reset_ (r3081rd_ r3081wr_) !reset_
"Runtime read write "Reset "Runtime read write "Reset
!go_
reset_ (idlebus !(r3081rd_ r3081wr_)) !reset_
!breqct0_ reset_ r3081burst_ r3081rd_) ((!rdcen_ breqct0_) "toggle rdcen_ rdcen_ !breqct0_)) "hold rdcen_ (!(!r3081burst_ r3081rd_) rdcen_)) !reset_ !busreq_ idlebus !r3081rd_ !idlebus !breqct0_; r3081burst_ "async ~busreq cycle "sync ~busreq other cycles
syncOUT0 asyncIN0; syncOUT1 asyncIN1; "idlebus,go_ test vectors test_vectors ([Clk,reset_,r3081rd_,r3081wr_]
"synchronize ~SysClk rising "synchronize ~SysClk rising
[idlebus,go_]) [0,1]; "reset [1,1]; "idle [1,1]; [0,0]; "read start [0,1]; [0,1]; [1,1]; [0,0]; "write start [1,1]; "write [0,0]; "write start [1,1];
"idlebus,breqct0_,busreq_ test vectors test_vectors
[idlebus,breqct0_,busreq_]) [0,0,0]; "reset [1,1,1]; "idle [1,1,0]; "read 0-wait state [0,1,1]; [1,1,1]; "idle [1,1,0]; "read n-wait state [0,0,0]; [0,0,0]; [0,1,1]; [1,1,1]; "idle [0,1,1]; "read burst [0,1,1]; "0-wait state [0,0,0]; [0,1,1]; [0,0,0]; [0,1,1]; [1,1,1]; "idle [0,1,1]; "read burst [0,1,1]; "throttled
CHAPTER
EQUATIONS
[0,0,0]; [0,0,0]; [0,1,1]; [0,1,1]; [0,0,0]; [0,0,0]; [0,1,1]; [1,1,1]; "idle [0,1,1]; "write [0,1,1]; [1,1,1]; "idle
"syncOUT0 test vectors test_vectors ([Clk,asyncIN0] [syncOUT0]) [0]; [1]; "syncOUT1 test vectors test_vectors ([Clk,asyncIN1] [syncOUT1]) [0]; [1];
EQUATIONS
CHAPTER
Finish 'Function:' documentation module RdcenOe title Name Ack_ RdCen_ Output Select Control Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x32DC MacABEL 4.01 Refdes. "Function: "This generates output enables control "The SRAM rdcen_ ack_ signals only asserted when valid memory cycle taking place. Using tri-state pull signal high valid pulling signal high. will take long! Therefore, tri-state "control based the. "Rev. History: RDCENOE DEVICE 'P16L8'; "Inputs add29,add28 add27,add26 add25,add24 add23,add22 add21,add20 SRAMat0 r3081rdwr_ buserroroe_ "Outputs stateoe dramoe_ sramoe_ sramack_ sramrdcen_
11,9; 8,7; 6,5; 4,3; 2,1;
"active high enable "active enable "active enable
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; "Variables [add29.add20, X,X, addr [add29.add24];
X,X, X,X,X,X, X,X,X,X, X,X,X,X, X,X,X,X];
"Macros zerowaitSRAM macro SRAMat0 (add ^h00000000)) (!SRAMat0 (add ^h04000000)))}; "64Mb equations !sramoe_ buserroroe_ zerowaitSRAM; !dramoe_ buserroroe_ ((!SRAMat0 (add ^h04000000)) "DRAM memory (add ^h3f0f0000)); "DRAM controller "stateoe SRAMat0 (add ^h00100000)) ""n-wait state SRAM
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EQUATIONS
(!SRAMat0 (add ^h04100000)) (add ^h04400000) (addr ^h1f) !buserroroe_;
""n-wait state SRAM ""Dual Port SRAM ""EPROM, SONIC, Uart, User, etc. ""Bus Error
!stateoe buserroroe_ (zerowaitSRAM (!SRAMat0 (add ^h04000000)) (add ^h3f0f0000)); !sramack_ !r3081rdwr_ zerowaitSRAM; !sramrdcen_ !r3081rdwr_ zerowaitSRAM; !sramack_.oe sramoe_; !sramrdcen_.oe sramoe_; "ack_ zero wait SRAM cycles "rdcen zero wait SRAM cycles "Output Enable Equations
test vectors test_vectors [^h00000000,0, X,1] [0,0,1, Z,Z]; DRAM [^h00000000,1, 0,1] [0,1,0, 0,0]; "rd/wr SRAM zero-wait ^h0000 0000 [^h00100000,1, 0,1] [1,1,1, Z,Z]; SRAM n-wait ^h0010 0000 [^h04000000,0, 0,1] [0,1,0, 0,0]; SRAM zero-wait [^h04100000,0, 0,1] [1,1,1, Z,Z]; SRAM n-wait [^h00000000,1, 1,1] [0,1,0, 1,1]; "idle SRAM zero-wait space [^h00100000,1, 1,1] [1,1,1, Z,Z]; SRAM n-wait space [^h04000000,0, 1,1] [0,1,0, 1,1]; SRAM zero-wait space [^h04100000,0, 1,1] [1,1,1, Z,Z]; SRAM n-wait space [^h04400000,X, [^h05000000,X, [^h1fa00000,X, [^h1fb00000,X, [^h1fc00000,X, [^h1fc7ffff,X, [^h1fc80000,X, [^h1fcfffff,X, [^h1fd00000,X, [^h1fd7ffff,X, [^h1fd80000,X, [^h1fdfffff,X, [^h1fe00000,X, [^h1ff00000,X, [^h3f0f0000,X, X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] X,1] [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [1,1,1, [0,0,1, Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; Z,Z]; "Daul Port SRAM "reserved/undefined "User "SONIC "EPROM
"Uart "Bus Error Register "DRAM controller DRAM error SRAM zero-wait error SRAM n-wait error
[^h00000000,0, X,0] [1,1,1, Z,Z]; [^h00000000,1, 0,0] [1,1,1, Z,Z]; "read [^h00100000,1, 0,0] [1,1,1, Z,Z];
EQUATIONS
CHAPTER
module SonicBus title Name Sonic Address Data Control Designer PMcD Date 17-May-94 Board rev.: Checksum: 0x4204 MacABEL 4.01 Refdes. "Function: Controls drivers SONIC address data busses. Whenever ~SONICSMACK asserted, SONIC servicing slave read write. accessing internal SONIC registers. ~DPSONICCS ~DPSONICOE control SONIC side Dual Ports. These signals function both R3081 SONIC, although SONIC higher priority. ~DPR3081CS chip enable dual port's side. R3081 issue dual port diagnostic reads starting 0xA4480 0000 that read data from SONIC side dual port. Note that dual port does support diagnostic writes. S_DACK[1:0] SONIC outputs during slave cycles. S_DACK[1:0] SONIC inputs during master cycles. When SONIC master ~SONICCS falls, SONIC will retain mastership bus, ~SONICBGACK will stay asserted, while master cycle interrupted service slave cycle with ~SONICSMACK low. SONICBUS DEVICE 'P16L8'; "Inputs r3081rd_ r3081wr_ dataen_ soniccs_ sonicbgack_ sonicmstrd_ dpram_ add19 s_dack0 sonicsmack_ "Outputs dataxvrdir dataxvroe_ addxvroe_ dpsonicoe_ dpsonicce_ dpr3081ce_ s_dack1
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations !dataxvrdir !r3081rd_ !dataen_ (!soniccs_ !dpram_ add19); "SONIC slave read diagnostic read "SONIC data idle "SONIC slave read "SONIC slave write
!dataxvroe_ sonicbgack_ sonicbgack_ !soniccs_ !r3081rd_ !dataen_ sonicbgack_ !soniccs_ !r3081wr_
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EQUATIONS
sonicbgack_ !dpram_ add19 !r3081rd_ !dataen_; diagnostic read !addxvroe_ sonicbgack_; diagnostic read
!dpsonicoe_ !sonicbgack_ sonicmstrd_ "SONIC master read sonicbgack_ !dpram_ add19 !r3081rd_; diagnostic read !dpsonicce_ !sonicbgack_ "SONIC master cycle sonicbgack_ !dpram_ add19 !r3081rd_; diagnostic read !dpr3081ce_ !dpram_ !add19; !s_dack1 !s_dack0; !s_dack1.oe !sonicsmack_; "Ouput Enable Equation
"dataxvrdir,dataxvroe_ test vectors test_vectors [dataxvrdir,dataxvroe_]) 1,1,X,X] [1,0]; "SONIC idle 1,1,X,X] [1,0]; 1,0,X,X] [1,1]; 1,0,X,X] [1,1]; "read 0,0,X,X] [1,1]; 0,0,X,X] [0,1]; 0,1,X,X] [0,0]; 1,1,X,X] [1,0]; 1,0,X,X] [1,1]; 1,0,X,X] [1,1]; "write 0,0,X,X] [1,1]; 0,1,X,X] [1,0]; 1,0,X,X] [1,1]; 1,1,1,1] [1,0]; diagnostic read 1,1,1,1] [1,0]; 1,1,1,1] [1,0]; 1,1,0,1] [0,0]; 1,1,0,1] [1,0]; "dualptoe_,dualptce_ test vectors test_vectors "addxvroe_ test vectors test_vectors ([sonicbgack_] [addxvroe_]) [1]; "SONIC master active [0]; "SONIC master idle "dpcpucs_ test vectors test_vectors ([dpram_,add19] [dpr3081ce_])
[dpsonicoe_,dpsonicce_]) [1,1]; [1,1]; [1,0]; "SONIC master write [0,0]; "SONIC master read [1,1]; read [0,0]; diagnostic read
EQUATIONS
CHAPTER
[1]; [1]; [0]; read [1]; diagnostic read
"s_dack1 test vectors test_vectors ([sonicsmack_,s_dack0] [s_dack1]) [Z]; "SONIC slave cycle [0]; "SONIC master cycle [1]; "SONIC master cycle
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EQUATIONS
module Sramctl title Name SRAM Byte Enalbe Control Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x1F2C MacABEL 4.01 Refdes. "Function: Generates write enable signals SRAM Dual Port memories. SRAM Dual Port writes controlled these byte enable signals. Idlebus used assure address stable before write signal asserted. SRAMCTL DEVICE 'P16L8'; "Inputs be_0,be_1 be_2,be_3 r3081rd_ r3081wr_ idelbus "Outputs sramwe_b0 sramwe_b1 sramwe_b2 sramwe_b3
1,2; 3,4;
"currently unused
"byte0 "byte1 "byte2 "byte3
SRAM, SRAM, SRAM, SRAM,
DPRAM DPRAM DPRAM DPRAM
write write write write
enable enable enable enable
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations !sramwe_b0 !sramwe_b1 !sramwe_b2 !sramwe_b3 !r3081wr_ !r3081wr_ !r3081wr_ !r3081wr_ !idelbus !idelbus !idelbus !idelbus !be_0; !be_1; !be_2; !be_3;
"sramwe_b[3:0] test vectors test_vectors 1,X,X,X,X,X] [1,1,1,1]; "non-write cycles 1,0,X,X,X,X] [1,1,1,1]; 1,X,0,X,X,X] [1,1,1,1]; 1,X,X,0,X,X] [1,1,1,1]; 1,X,X,X,0,X] [1,1,1,1]; 1,X,X,X,X,0] [1,1,1,1]; 0,0,0,0,0,0] 0,0,0,0,0,1] 0,0,0,0,1,0] 0,0,0,0,1,1] 0,0,0,1,0,0] 0,0,0,1,0,1] 0,0,0,1,1,0] 0,0,0,1,1,1] 0,0,1,0,0,0] [0,0,0,0]; "write cycles [0,0,0,1]; [0,0,1,0]; [0,0,1,1]; [0,1,0,0]; [0,1,0,1]; [0,1,1,0]; [0,1,1,1]; [1,0,0,0];
EQUATIONS
CHAPTER
0,0,1,0,0,1] 0,0,1,0,1,0] 0,0,1,0,1,1] 0,0,1,1,0,0] 0,0,1,1,0,1] 0,0,1,1,1,0] 0,0,1,1,1,1]
[1,0,0,1]; [1,0,1,0]; [1,0,1,1]; [1,1,0,0]; [1,1,0,1]; [1,1,1,0]; [1,1,1,1];
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EQUATIONS
module Sramdcd title Name SRAM Decode Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x23AC MacABEL 4.01 Refdes. "Function: Generates chip selects 0-wait state SRAMs. SRAMs also read from aliased memory location with number wait states determined memory controller. There banks 32kx32 memories, allowing total 256kbytes. "Rev. History: SRAMDCD DEVICE 'P16L8'; "Inputs add29,add28 add27,add26 add25,add24 add23,add22 add21,add20 r3081rd_ r3081wr_ SRAMat0 add17
11,9; 8,7; 6,5; 4,3; 2,1;
"Outputs zerowt_sram "zerowt_sram zero wait state SRAM sramcs_hi sramcs_lo "Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; "Variables [add29.add20, X,X, X,X, X,X,X,X, X,X,X,X, X,X,X,X, X,X,X,X]; addr [add29.add20, X,X,add17,X, X,X,X,X, X,X,X,X, X,X,X,X, X,X,X,X]; "Macro SRAMsel macro SRAMat0 ((add (add (!SRAMat0 ((add (add equations !zerowt_sram SRAMat0 (add ^h00000000)) (!SRAMat0 (add ^h04000000))); "64Mb !sramcs_lo SRAMsel !add17 !(r3081rd_ r3081wr_); !sramcs_hi SRAMsel add17 !(r3081rd_ r3081wr_); "sramcs_,zerowt_sram test vectors "low bank read write "high bank read write
^h00000000) ^h00100000))) ^h04000000) "64Mb ^h04100000))))}; "65Mb
EQUATIONS
CHAPTER
test_vectors [^h00000000,0, X,X] [1,1,1]; DRAM (Decoded memory ctlr.) [^h00000000,1, 0,1] [0,1,0]; "read SRAM zero wait ^h0000 0000 [^h00020000,1, 0,1] [1,0,0]; SRAM zero wait ^h0002 0000 high [^h00100000,1, 0,1] [0,1,1]; SRAM wait ^h0010 0000 [^h00120000,1, 0,1] [1,0,1]; SRAM wait ^h0012 0000 [^h04000000,0, 0,1] [0,1,0]; SRAM zero wait [^h04020000,0, 0,1] [1,0,0]; SRAM zero wait [^h04100000,0, 0,1] [0,1,1]; SRAM wait [^h04120000,0, 0,1] [1,0,1]; SRAM wait [^h00000000,1, 1,0] [0,1,0]; "write SRAM zero wait ^h0000 0000 [^h00020000,1, 1,0] [1,0,0]; SRAM zero wait ^h0002 0000 high [^h00100000,1, 1,0] [0,1,1]; SRAM wait ^h0010 0000 [^h00120000,1, 1,0] [1,0,1]; SRAM wait ^h0012 0000 [^h04000000,0, 1,0] [0,1,0]; SRAM zero wait [^h04020000,0, 1,0] [1,0,0]; SRAM zero wait [^h04100000,0, 1,0] [0,1,1]; SRAM wait [^h04120000,0, 1,0] [1,0,1]; SRAM wait [^h00000000,1, 1,1] [1,1,0]; "idle SRAM space [^h00100000,1, 1,1] [1,1,1]; SRAM space [^h04000000,0, 1,1] [1,1,0]; SRAM space [^h04100000,0, 1,1] [1,1,1]; SRAM space [^h05000000,X, [^h1fa00000,X, [^h1fb00000,X, [^h1fc00000,X, [^h1fc7ffff,X, [^h1fc80000,X, [^h1fcfffff,X, [^h1fd00000,X, [^h1fd7ffff,X, [^h1fd80000,X, [^h1fdfffff,X, [^h1fe00000,X, [^h1ff00000,X, X,X] X,X] X,X] X,X] X,X] X,X] X,X] X,X] X,X] X,X] X,X] X,X] X,X] [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; [1,1,1]; "undefined "User "SONIC "EPROM
"Uart "Bus Error Register
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EQUATIONS
module V3ctl title Name v96bmc Memory Interface Controller Designer PMcD Date 13-Apr-94 Board rev.: Checksum: 0x234F MacABEL 4.01 Refdes. "Function: "Rev. History: V3CTL DEVICE 'P16R4'; "Inputs r3081rd_ r3081wr_ r3081bwrn_ r3081add2 r3081add3 bClk_ idlebus asyncIN0 "Outputs v3blast_ v3ads_ syncOUT0
"v3_cs_
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; "Variables wordadd [r3081add3,r3081add2]; equations v3ads_ !idlebus (r3081rd_ r3081wr_); "R3081 read "R3081 write "Sonic? "write "single "block
!v3blast_ !r3081wr_ !r3081rd_ r3081bwrn_ (!r3081bwrn_ (((wordadd bClk_) (wordadd 3)))); syncOUT0 asyncIN0; "synchronize ~SysClk falling
"adsen_ test vectors test_vectors ([r3081rd_,r3081wr_,idlebus] [v3ads_]); [X]; "idle [0]; "read [1]; [1]; [1]; [1]; "read
EQUATIONS
CHAPTER
[1]; [0]; [1]; [1]; [1]; [1];
"idle "write
"write "idle
"v3blast_ test vectors test_vectors "syncOUT0 test vectors test_vectors ([Clk,asyncIN0] [syncOUT0]) [0]; [1];
[v3blast_]); [1]; "idle [0]; "write [0]; "single read [1]; "burst read [1]; [1]; [1]; [1]; [0]; "generate blast here [0]; [0]; [1];
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EQUATIONS
module v3out title Name DRAM RdCen_ Ack_ Control Designer PMcD Date 14-May-94 Board rev.: Checksum: 0x25D2 MacABEL 4.01 Refdes. "Function: Generates ~RdCEn ~Ack DRAM cycles. RDCENOE generates this PAL's output enable. ~RdCEn designed direct function ~v3ready during reads. ~Ack asserted with ~RdCEn during single word reads, first asserted cycle after ~RdCEn during burst reads, asserted alone funtion ~v3ready during writes. Since current rev. v96bmc deasserts ~v3ready soon during burst read, other control needed keep ~RdCEn asserted last word burst. assertion ~Ack during burst reads only particular first assertion. this board, first assertion cycle after first ~RdCEn asserted comply with streaming pipeline soon possible. V3OUT DEVICE `P16L8'; "Inputs r3081rd_ r3081wr_ r3081burst_ v3ready_ dlyv3ready_ addr2 addr3 "Outputs ack_ rdcen_ r3081rdwr_
"Constants L,H,Z,X,C 0,1,.Z.,.X.,.C.; equations !rdcen_ !r3081rd_ !v3ready_ !r3081rd_ !r3081burst_ !dlyv3ready_ addr2 addr3; "need generate !rdcen that longer than "one generated bug-ridden v96bmc "680ohm pull-up v3ready_. Need elongate "v3ready becomes necessity block reads "frequencies 16MHz less. !ack_ !r3081wr_ !v3ready_ !r3081rd_ r3081burst_ !v3ready_ !r3081rd_ !r3081burst_ !dlyv3ready_; "write "single read "burst read
r3081rdwr_ r3081rd_ r3081wr_;
EQUATIONS
CHAPTER
!rdcen_.oe oe_; !ack_.oe oe_;
"Output Enable Equations
"rdcen_,ack_ test vectors test_vectors "r3081rdwr_ test vectors test_vectors ([r3081rd_,r3081wr_] [r3081rdwr_]) [0]; [0]; "read [0]; "write [1]; "idle
[rdcen_,ack_]) [Z,Z]; [1,1]; "idle [1,1]; "write [1,0]; [1,1]; "single read [0,0]; [1,1]; "idle [1,1]; "burst read [0,1]; [0,0]; [1,0]; [0,1]; [0,0]; [1,X]; "bug ridden [1,X]; "bug ridden [1,X]; "bug ridden [1,X]; "bug ridden [1,X]; "bug ridden [1,X]; "bug ridden [1,X]; "bug ridden [0,X]; "bug ridden [1,X]; "idle [1,1]; "idle
cases cases cases cases cases cases cases cases
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TIMING DIAGRAMS
TIMING DIAGRAMS
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Integrated Device Technology, Inc.
TIMING DIAGRAMS
following pages include: Timing Timing Timing Timing Timing diagrams diagrams diagrams diagrams diagrams Dual-Port Subsystem DRAM Subsystem DUART Subsystem EPROM Subsystem SRAM Subsystem 7-10 7-12
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TIMING DIAGRAMS
Figure 7.1. Dual-Port Memory Single Datum Read.
Figure 7.2. Dual-Port Memory Word Datum Read.
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TIMING DIAGRAMS
Figure 7.3. Dual-Port Memory Single Datum Write.
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TIMING DIAGRAMS
Figure 7.4. DRAM Single Datum Read (Page Miss Followed Hit).
Figure 7.5. DRAM Single Datum Read (Page Hit).
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TIMING DIAGRAMS
Figure 7.6. DRAM Single Datum Read (Page Miss).
Figure 7.7. DRAM Word Datum Read (Page Miss Followed Hit).
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TIMING DIAGRAMS
Figure 7.8. DRAM Word Datum Read (Page Hit).
Figure 7.9. DRAM Word Datum Read (Page Miss).
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TIMING DIAGRAMS
Figure 7.10. DRAM Single Datum Write (Page Miss Followed Hit).
Figure 7.11. DRAM Single Datum Write (Page Miss Hit).
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TIMING DIAGRAMS
Figure 7.12. DRAM Single Datum Write (Page Miss).
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TIMING DIAGRAMS
Figure 7.13. DUART Single Datum Read.
Figure 7.14. DUART Single Datum Write.
CHAPTER
TIMING DIAGRAMS
Figure 7.15. EPROM Single Datum Read.
Figure 7.16. EPROM Word Datum Read.
CHAPTER
TIMING DIAGRAMS
Figure 7.17. EPROM Single Datum Write (Dummy Write).
CHAPTER
TIMING DIAGRAMS
Figure 7.18. SRAM Single Datum Read Wait State).
Figure 7.19. SRAM Word Datum Read Wait State).
CHAPTER
TIMING DIAGRAMS
Figure 7.20. SRAM Single Datum Write Wait State).
CHAPTER
TIMING DIAGRAMS
Figure 7.21. SRAM Single Datum Read Wait State).
Figure 7.22. SRAM Word Datum Read Wait State).
CHAPTER
TIMING DIAGRAMS
Figure 7.23. SRAM Single Datum Write Wait State).
TECH NOTES
APPENDIX
SOFTWARE TECHNICAL NOTES
APPENDIX
Integrated Device Technology, Inc.
APPENDIX SOFTWARE TECHNICAL NOTES
Contents include: Tech note setting SparcStation development environment. Tech note setting DBXX SparcStation. Documentation ITEM terminal emulator program using terminal/console RS232C port.
APPENDIX
TECH NOTES
TECHNICAL NOTE #1.02
Upendra Kulkarni (PDAE) Date: 9/17/93 Total pages: Subject: Setting SPARCstation development platform IDT's RISC eval-boards. This note explains started when using SPARCstation development platform developing code which will ultimately MIPS-RISC-based board (such IDT's eval-boards). order SPARCstation development platform RISC evaluation board (such board), need following items, particular order: SPARC workstation with least serial port. ports make life much easier debugging. RISC evaluation board from IDT. board must have Version (ROM monitor/debugger) later. IDT/C Version later) alone some other tool-chain KIT-1.0 later. IDT/C IDT/KIT, will responsible generating code initialize your target board perform level functions called standard functions (such "printf"). UUCP utility SPARC workstation. using IDT/C, will need some utility program which will convert your executable file format into Motorola-S-record file format (type S3). Examples: "convertr3000" from MIPS, "copy" from tool-chain, "idtconv" from IDT. Some software development tool chain which will compile, assemble, link produce executable code from your other HLL) "assembly" language source code. tool chain must available platform must produce target code MIPS processors. RS232C serial cable. serial cables plan source level debugging. power supply evaluation board.
ASSUMPTION: assumed that software tool chain workstation according manufacturer's instructions. have created small software program (which wish debug) "assembly" some other language which have tool-chain. have compiled and/or assembled program. have linked program with appropriate libraries from your tool-chain. have also linked files start-up code low-level kernel code. result have created executable file which will execute your expectations your target board. have created S-record file from your executable file. need S-record file download target board serial link from target board. HAVE COMPLETED ABOVE STEPS, PLEASE COMPLETE THEM NOW. PROCEEDING WITHOUT DOING WILL PRACTICAL USE.
HARDWARE: hardware downloading S-record file from target board need serial link between SPARC workstation evaluation board. This one-time-only effort. Debugging covered this note; covered technical note 2.02 great detail. Locate serial port back panel SUN. Locate tty0 serial port evaluation board using some other board, locate console port). connect these ports need serial cable with appropriate types connectors. Once have hooked serial cable, connect power supply evaluation board turn
TECH NOTES
APPENDIX
further discussion assumed that have hooked ttyb port although port will
SOFTWARE: First make sure that your ttyb port mode "rw-rw-rw-". view current mode with following command: /dev/ttyb". mode correct, will have root change mode correct using "chmod" command. need take steps order your UUCP utility. These steps one-time-only also. "root" workstation haven't done already. Change current directory "uucp" directory. most SPARCstations, this directory "/etc/uucp". Modify file Systems adding following line board bdev Modify file Devices adding following line bdev ttyb 9600 direct Note that replace "ttyb" with appropriate serial port. Note that there five separate items above line that items with spaces both sides have introduced your evaluation board UUCP utilities "board". replace word "board" with other word your choice. always your work "root", don't this point. Others need whatever userid they doing software development. directory which your S-record file exists. assumed that, this point, have physical serial connection between workstation evaluation box. normal shell prompt, enter following command: board system will respond second saying "connected". From this point assumed that using eval-board. explaination work equally well context other board. commands described from this point onwards specific IDT/sim. enter times. should "<IDT>" prompt. prompt, stop. Your serial port connection working. Please review this note upto this point more time, make sure that have missed steps. Reset eval-board couple times. prompt, type commands make sure that everything with evaluation board. When ready download program from workstation evaluation board, enter <IDT> prompt: load tty0 tty0)
After enter above command, cursor will next line will appear freeze there. This normal. evaluation board will mode where waiting receive s-records serial port "tty0".
APPENDIX
TECH NOTES
need send (download) program over serial connection. achieve this, enter following command: ~$cat your-s-record-filename-here Note that even though your window workstation working like "console" evaluation board, command starting with passed UNIX evaluation board. Notice that after type "~", your machine identification will appear screen though were part command were process typing! This expected. Simply continue type command. Again, cursor appear frozen seconds. This normal. Soon, when program download progress, will number rows dots (".") appearing screen. This proof that download working. your terminal does have "wrap-around" feature, only line dots; others will number lines dots depending length file being downloaded. After download complete, following message will displayed: "Done. (num) records, initial (address)" where (num) total number S-records downloaded (address) value which will loaded program counter when execution program begins. <IDT> prompt will return. Enter program. other commands wish out. When done with "cu" mode wish back UNIX (get <IDT> prompt), enter "~.". That followed quote marks, spaces between). display will read "Disconnected" <IDT> prompt will disappear. back using your ordinary mode.
TECH NOTES
APPENDIX
TECHNICAL NOTE #2.02
Upendra Kulkarni (PDAE) Date: 9/17/93 Total pages: Subject: Setting SPARC workstation DBXX. This note explains SPARC station with MIPS Cross-tools development platform debugging assembly code written RS385 evaluation board from IDT. This note only explains basic hardware software set-up required. This "user's guide" MIPS debugger (DBXX)! "dbxr3000" program which have received along with DBXX. "dbxr3000" compatible with RS385 evaluation board. DBXX! Note that DBXX works Endian boards only. assumed that know hook RS385 evaluation board from SPARC station serial link, download programs board, this point. have reached that stage yet, please refer Tech-Note #1.02. Please follow steps exact sequence which they described here. your SUN, "root". Modify create absent) file: /etc/remote.pdbx following line rdebug:dv=/dev/ttya:br#9600 always your work root, don't out. Others, back yourself. your home directory directory plan debug in), modify create, absent) file: .dbxinit following: $use_sockets $manual_load $pdbxport "rdebug" Check file /etc/ttytab make sure that ttya ttyb have following characteristics: name getty type status comments ttya "/usr/etc/getty std.9600" unknown local secure ttyb "/usr/etc/getty std.9600" unknown local secure /dev/ttya" /dev/ttyb" commands make sure that modes crw-rw-rwIf they not, "chmod" command make modes both ttya ttyb above. Connect ttya tty1 evaluation board. Connect ttyb tty0 board. Open windows console. window (pick one). directory which have source code program wish debug. Compile your source code with OPTIMIZATION with "-g" option. Please refer your compiler user's manual information these items. window same directory were window Enter board" whatever "<IDT>" prompt. <IDT> prompt, please refer Tech-note 1.02 make sure that have done set-up "tty0" connected "ttyb". beyond this step without seeing <IDT> prompt. "<IDT>" prompt, enter tty0" (not quote marks). cursor will appear frozen. That normal.
APPENDIX
TECH NOTES
enter "~$cat myfile.srec", where myfile.srec should replaced with actual name file which contains S-records pertaining program trying debug. moments, will number dots appearing window This indicates that code getting downloaded board. Once this process over, "<IDT>" prompt will return. "<IDT>" prompt window enter "debug". This will board mode where knows respond debugging commands tty1 port. window normal shell prompt, enter "dbxx -prom myfile". Note that myfile name your "executable" file S-record file. myfile myfile.srec distinct files. this point will debugging prompt window ready debug! simple command like list lines source code. break-point first line code inside "main()" your program. (command: stop main). Then issue "run". break point, your successful debugging!
TECH NOTES
APPENDIX
ITEM SOFTWARE
Terminal Emulator Downloader Machines (ITEM) ITEM (IDT Terminal Emulator) terminal emulator downloader program that used with target boards employing IDT/sim. communcate over COM1 COM2 seral parts speed 9600 bps. translation escape sequences cursor control desired, `DEVICE=ANSI.SYS' config.sys file boot disk. invoke `ITEM' following format command line:
item download_file [P{1|2}]
where command line options defined follows: download_file Thje full name record file download. `item' will COM1 (default). `item' will COM2. Once `ITEM' program started functions terminal emulator target machine. Control keys used command `ITEM' perfom such functions terminate, download file capture data printed onto screen. following keys recognized `ITEM' commands: CTRL-x Terminates `item' prgram. CTRL-a Start downloading target machine. user will prompted file name (default being command line). Prior this command, IDT/sim should given `load tty0' command. CTRL-y Takes input from file instead keyboard sends target board. prompt file name appears response CTRL-y. CTRL-w Closes active capture file, then opens capture file (there prompt name file) puts everything that appears screen from that moment into name capture file given, then current file closed. example, talk target machine connected COM1 port, default download file name `calc.sre', progarm, enter following: <DOS> item calc.exe COM1 status :6000 <IDT> load tty0 Load from calc.sre> [<ret> filename]: <IDT> <DOS> Once ITEM started, acts terminal IDT/sim target board until download capture mode initiated control sequence. `ITEM' program only works machiens such IBM/AT compatibles (depending compatible). Downloading target boards which contain IDT/sim also accomplished with most modem/terminal emulator programs which provide ASCII file transfer function.
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