89HPES4T4G2 Data Sheet Advance Information* Device Overview
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4-Lane 4-Port Gen2 Express® Switch
89HPES4T4G2 Data Sheet
Advance Information*
Device Overview
89HPES4T4G2, 4-lane 4-port Gen2 Express® switch, member IDT's PRECISEfamily Express switching solutions. PES4T4G2 peripheral chip that performs Express base switching with feature optimized servers, storage, communications, consumer applications. provides connectivity switching functions between Express upstream port three downstream ports peer-to-peer switching between downstream ports. High Performance Express Switch Four Gen2 Express lanes supporting Gbps Gbps operations Four switch ports upstream port Three downstream ports latency cut-through switch architecture Support Payload Size bytes Supports virtual channel eight traffic classes Express Base Specification Revision compliant Flexible Architecture with Numerous Configuration Options Automatic lane reversal ports Automatic polarity inversion Ability load device configuration from serial EEPROM
Features
Legacy Support compatible INTx emulation locking Highly Integrated Solution Requires external components Incorporates on-chip internal memory packet buffering queueing Integrates four Gbps embedded SerDes with 8b/10b encoder/decoder separate transceivers needed) Receive equalization (RxEQ) Reliability, Availability, Serviceability (RAS) Features Internal end-to-end parity protection TLPs ensures data integrity even systems that implement end-to-end (ECRC) Supports ECRC Advanced Error Reporting Supports Express Native Hot-Plug, Hot-Swap capable Compatible with Hot-Plug expanders used motherboards Supports Hot-Swap Power Management Utilizes advanced low-power design techniques achieve typical power consumption Support Power Management Interface specification (PCIPM 2.0)
Block Diagram
4-Port Switch Core Gen2 Express Lanes
Frame Buffer Route Table Port Arbitration Scheduler
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Demux
Logical Layer
Demux
Logical Layer
Demux
Logical Layer
Demux
Logical Layer
SerDes
SerDes
SerDes
SerDes
(Port
(Port
(Port
(Port
Figure Internal Block Diagram
logo registered trademarks Integrated Device Technology, Inc.
2007 Integrated Device Technology, Inc. *Notice: information this document subject change without notice
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Advance Information
89HPES4T4G2 Data Sheet
Product Description Utilizing standard Express interconnect PES4T4G2 provides most efficient high-performance connectivity device applications requiring high throughput, latency simple board layout. provides Express connectivity across lanes ports. Each lane provides Gbps bandwidth both directions fully compliant with Express Base specification 2.0. PES4T4G2 based flexible efficient layered architecture. Express layer consists SerDes, Physical, Data Link Transaction layers compliance with Express Base specification Revision 2.0. PES4T4G2 operate either store forward cut-through switch designed switch memory transactions. supports eight Traffic Classes (TCs) Virtual Channel (VC) with sophisticated resource management enable efficient switching connectivity servers, storage, embedded processors with limited connectivity.
PES4T4G2 contains SMBus interfaces. slave interface provides full access configuration registers PES4T4G2, allowing every configuration register device read written external agent. master interface allows default configuration register values PES4T4G2 overridden following reset with values programmed external serial EEPROM. master interface also used external Hot-Plug expander. pins make each SMBus interfaces. These pins consist SMBus clock SMBus data pin. Master SMBus address hardwired 0x50, slave SMBus address hardwired 0x77. shown Figure master slave SMBuses used unified split configuration. unified configuration, shown Figure 3(a), master slave SMBuses tied together PES4T4G2 acts both SMBus master well SMBus slave this bus. This requires that SMBus master processor that access PES4T4G2 registers supports SMBus arbitration. some systems, this SMBus master interface implemented using general purpose pins processor micro controller, support SMBus arbitration. support these systems, PES4T4G2 configured operate split configuration shown Figure 3(b). split configuration, master slave SMBuses operate independent buses thus multi-master arbitration never required. PES4T4G2 supports reading writing serial EEPROM master SMBus slave SMBus, allowing system programming serial EEPROM.
*Notice: information this document subject change without notice
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Supports device power management states: D3hot D3cold Support Express Active State Power Management (ASPM) link state Supports link power management states: L0s, L2/L3 Ready Supports Express Power Budgeting Capability Configurable SerDes power consumption Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode Supports numerous SerDes Transmit Voltage Margin settings Unused SerDes disabled Testability Debug Features Built Pseudo-Random Stream (PRBS) generator Numerous SerDes test modes Ability read write internal register SMBus Ability bypass link training force link into mode Provides statistics performance counters General Purpose Input/Output Pins Each individually configured input output Each individually configured interrupt input Some pins have selectable alternate functions Packaged 19mm 19mm, 324-ball with ball spacing
Processor
Processor
North Bridge
Memory Memory Memory Memory
PES4T4G2
Express Slot
4xGbE
4xGbE SATA SATA
Figure Expansion Application
SMBus Interface
89HPES4T4G2 Data Sheet
PES4T4G2
Processor SMBus Master
Serial EEPROM
Other SMBus Devices
PES4T4G2
Processor SMBus Master
Other SMBus Devices
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
Serial EEPROM
Unified Configuration Management
Split Configuration Management Buses
Figure SMBus Interface Configuration Examples
Hot-Plug Interface PES4T4G2 supports Express Hot-Plug each downstream port. reduce number pins required device, PES4T4G2 utilizes external expander, such that used motherboards, connected SMBus master interface. Following reset configuration, whenever state Hot-Plug output needs modified, PES4T4G2 generates SMBus transaction expander with value outputs. Whenever Hot-Plug input changes, expander generates interrupt which received IOEXPINTN input (alternate function GPIO) PES4T4G2. response expander interrupt, PES4T4G2 generates SMBus transaction read state Hot-Plug inputs from expander. General Purpose Input/Output PES4T4G2 provides General Purpose Input/Output (GPIO) pins that used system designer ports. Each GPIO configured independently input output through software control. Some GPIO pins shared with other on-chip functions. These alternate functions enabled software, SMBus slave interface, serial configuration EEPROM.
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89HPES4T4G2 Data Sheet
Description
following tables list functions pins provided PES4T4G2. Some functions listed multiplexed onto same pin. active polarity signal defined using suffix. Signals ending with defined being active, asserted, when logic zero (low) level. other signals (including clocks, buses, select lines) will interpreted being active, asserted, when logic (high) level.
Signal PE0RP[0] PE0RN[0] PE0TP[0] PE0TN[0] PE1RP[0] PE1RN[0] PE1TP[0] PE1TN[0] PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PEREFCLKP PEREFCLKN
Type
Name/Description Express Port Serial Data Receive. Differential Express receive pair port Port upstream port. Express Port Serial Data Transmit. Differential Express transmit pair port Port upstream port. Express Port Serial Data Receive. Differential Express receive pair port Express Port Serial Data Transmit. Differential Express transmit pair port Express Port Serial Data Receive. Differential Express receive pair port Express Port Serial Data Transmit. Differential Express transmit pair port Express Port Serial Data Receive. Differential Express receive pair port Express Port Serial Data Transmit. Differential Express transmit pair port Express Reference Clock. Differential reference clock pair input. This clock used reference clock on-chip PLLs generate clocks required system logic on-chip SerDes. frequency differential reference clock 100MHz. Table Express Interface Pins
Signal MSMBCLK MSMBDAT SSMBCLK SSMBDAT
Type
Name/Description Master SMBus Clock. This bidirectional signal used synchronize transfers master SMBus which operates KHz. Master SMBus Data. This bidirectional signal used data master SMBus which operates KHz. Slave SMBus Clock. This bidirectional signal used synchronize transfers slave SMBus. Slave SMBus Data. This bidirectional signal used data slave SMBus. Table SMBus Interface Pins
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89HPES4T4G2 Data Sheet
Signal GPIO[0]
Type
Name/Description General Purpose I/O. This configured general purpose pin. Alternate function name: P2RSTN Alternate function type: Output Alternate function: Reset output downstream port General Purpose I/O. This configured general purpose pin. General Purpose I/O. This configured general purpose pin. Alternate function name: IOEXPINTN0 Alternate function type: Input Alternate function: expander interrupt input. General Purpose I/O. This configured general purpose pin. Alternate function name: GPEN Alternate function type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This configured general purpose pin. Alternate function name: P1RSTN Alternate function type: Output Alternate function: Reset output downstream port General Purpose I/O. This configured general purpose pin. Alternate function name: P3RSTN Alternate function type: Output Alternate function: Reset output downstream port General Purpose I/O. This configured general purpose pin. Table General Purpose Pins
GPIO[1] GPIO[2]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
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89HPES4T4G2 Data Sheet
Signal CCLKDS
Type
Name/Description Common Clock Downstream. assertion this indicates that downstream ports using same clock source that provided downstream devices.This used initial value Slot Clock Configuration Link Status Registers downstream ports. value overridden modifying SCLK each downstream port's PCIELSTS register. Common Clock Upstream. assertion this indicates that upstream port using same clock source upstream device. This used initial value Slot Clock Configuration Link Status Register upstream port. value overridden modifying SCLK P0_PCIELSTS register. Fundamental Reset. Assertion this signal resets logic inside PES4T4G2 initiates Express fundamental reset. Switch Mode. These configuration pins determine PES4T4G2 switch operating mode. Normal switch mode Normal switch mode with Serial EEPROM initialization through Reserved These pins should static change following negation PERSTN. Table System Pins
CCLKUS
PERSTN SWMODE[2:0]
Signal JTAG_TCK
Type
Name/Description JTAG Clock. This input test clock used clock shifting data into boundary scan logic JTAG Controller. JTAG_TCK independent system clock with nominal duty cycle. JTAG Data Input. This serial data input boundary scan logic JTAG Controller. JTAG Data Output. This serial data shifted from boundary scan logic JTAG Controller. When data being shifted out, this signal tri-stated. JTAG Mode. value this signal controls test mode select boundary scan logic JTAG Controller. JTAG Reset. This active signal asynchronously resets boundary scan logic JTAG Controller. external pull-up board recommended meet JTAG specification cases where tester access this signal. However, systems running functional mode, following should occur: actively drive this signal with control logic statically drive this signal with external pull-down board Table Test Pins
JTAG_TDI JTAG_TDO
JTAG_TMS JTAG_TRST_N
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89HPES4T4G2 Data Sheet
Signal REFRES0
Type
Name/Description Port External Reference Resistor. Provides reference Port SerDes bias currents calibration circuitry. kOhm resistor should connected from this ground. Port External Reference Resistor. Provides reference Port SerDes bias currents calibration circuitry. kOhm resistor should connected from this ground. Port External Reference Resistor. Provides reference Port SerDes bias currents calibration circuitry. kOhm resistor should connected from this ground. Port External Reference Resistor. Provides reference Port SerDes bias currents calibration circuitry. kOhm resistor should connected from this ground. Core VDD. Power supply core logic. VDD. LVTTL buffer power supply. Express Analog High Power. Serdes analog power supply (2.5V). Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). Ground. Express Analog Power. Serdes analog power supply (1.0V).
REFRES1
REFRES2
REFRES3
VDDCORE VDDI/O VDDPEA VDDPEHA VDDPETA
Table Power, Ground, SerDes Resistor Pins
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89HPES4T4G2 Data Sheet
Characteristics
Note: Some input pads PES4T4G2 contain internal pull-ups pull-downs. Unused inputs should tied appropriate levels. This especially critical unused control signal inputs which, left floating, could adversely affect operation. Also, input left floating cause slight increase power consumption.
Function Express Interface
Name PE0RN[0] PE0RP[0] PE0TN[0] PE0TP[0] PE1RN[0] PE1RP[0] PE1TN[0] PE1TP[0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PEREFCLKN PEREFCLKP
Type
Buffer
Type Serial Link
Internal Resistor1
Notes
Diff. Clock Input STI2 LVTTL LVTTL STI, High Drive Input Input Input LVTTL pull-down pull-up pull-up pull-up pull-up pull-up pull-up pull-up
Refer Table pull-up board pull-up board pull-up board pull-up board
SMBus
MSMBCLK MSMBDAT SSMBCLK SSMBDAT
General Purpose System Pins
GPIO[10:7, 2:0] CCLKDS CCLKUS PERSTN SWMODE[2:0]
EJTAG JTAG
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
Table Characteristics (Part
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89HPES4T4G2 Data Sheet Function SerDes Reference Resistors Name REFRES0 REFRES1 REFRES2 REFRES3
Type
Buffer Analog
Type Input
Internal Resistor1
Notes
Table Characteristics (Part
Internal resistor values under typical operating conditions pull-up pull-down.
Schmitt Trigger Input (STI).
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89HPES4T4G2 Data Sheet
Logic Diagram PES4T4G2
Reference Clocks Express Switch SerDes Input Port
PEREFCLKP PEREFCLKN PE0RP[0] PE0RN[0] PE0TP[0] PE0TN[0]
Express Switch SerDes Output Port
Express Switch SerDes Input Port
PE1RP[0] PE1RN[0]
PE1TP[0] PE1TN[0]
Express Switch SerDes Output Port
Express Switch SerDes Input Port
PE2RP[0] PE2RN[0]
PE2TP[0] PE2TN[0]
Express Switch SerDes Output Port
Express Switch SerDes Input Port
PE3RP[0] PE3RN[0]
PE3TP[0] PE3TN[0]
Express Switch SerDes Output Port
PES4T4G2
Master SMBus Interface
GPIO[10:7,2:0]
MSMBCLK MSMBDAT
General Purpose
Slave SMBus Interface
SSMBCLK SSMBDAT
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N REFRES0 REFRES1 REFRES2 REFRES3
JTAG Pins
System Pins
CCLKDS CCLKUS PERSTN SWMODE[2:0]
SerDes Reference Resistors
VDDCORE VDDI/O VDDPEA VDDPEHA VDDPETA
Power/Ground
Figure PES4T4G2 Logic Diagram
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89HPES4T4G2 Data Sheet
System Clock Parameters
Values based systems running recommended supply voltages operating temperatures, shown Tables
Parameter RefclkFREQ TC-RISE TC-FALL VCROSS VCROSS-DELTA TSTABLE TPERIOD-AVG TPERIOD-ABS TCC-JITTER VMAX VMIN Duty Cycle Rise/Fall Matching ZC-DC
Description Input reference clock frequency range Rising edge rate Falling edge rate Differential input high voltage Differential input voltage Absolute single-ended crossing point voltage Variation VCROSS over rising clock edges Ring back voltage margin Time before allowed Average clock period accuracy Absolute period, including spread-spectrum jitter Cycle cycle jitter Absolute maximum input voltage Absolute minimum input voltage Duty cycle Single ended rising Refclk edge rate versus falling Refclk edge rate Clock source output impedance
Condition
Typical
1001
Unit V/ns V/ns
Differential Differential Differential Differential Single-ended Single-ended Differential Differential
+150
-150 +250 +550 +140 -100 -300 9.847 2800 10.203 +1.15 -0.3 +100
Table Input Clock Requirements
input clock frequency MHz.
Timing Characteristics
Min1 Typ1 Max1 Min1 Typ1 Max1
Parameter PCIe Transmit TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Units
Unit Interval Minimum Width Maximum time between jitter median maximum deviation from median Rise/Fall Time: Minimum time idle
399.88 0.75
400.12
199.94 0.75
200.06
0.125 0.125 0.15
TTX-RISE, TTX-FALL TTX- IDLE-MIN
Table PCIe Timing Characteristics (Part
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89HPES4T4G2 Data Sheet Min1 Typ1 Max1 HPF: 1.5MHz HPF: 1.0MHz 0.15 Min1 Typ1 Max1
Parameter TTX-IDLE-SET-TOIDLE
Description Maximum time transition valid Idle after sending Idle ordered Maximum time transition from valid idle diff data Transmitter data skew between lanes Minimum Instantaneous Lone Pulse Width Transmit Jitter Measurement Filter Transmitter Deterministic Jitter 1.5MHz Bandwidth Rise/Fall Time Differential Mismatch
Units
TTX-IDLE-TO-DIFFDATA
TTX-SKEW TMIN-PULSED TMEAS-HPF TTX-HF-DJ-DD TRF-MISMATCH PCIe Receive TRX-EYE (with jitter) TRX-EYE-MEDIUM
JITTER
Unit Interval Minimum Receiver Width (jitter tolerance) time between jitter median deviation Lane lane input skew jitter Maximum tolerable receiver jitter Minimum receiver instantaneous width
399.88
400.12
199.94
200.06
TRX-SKEW TRX-HF-RMS TRX-HF-DJ-DD TRX-LF-RMS TRX-MIN-PULSE
Table PCIe Timing Characteristics (Part
Minimum, Typical, Maximum values meet requirements under Specification
Signal GPIO GPIO[10:7,2:0]1
Symbol
Reference Unit Edge
Timing Diagram Reference
Tpw2
None
Table GPIO Timing Characteristics
GPIO signals must meet setup hold times they synchronous minimum pulse width
they asynchronous.
values this symbol were determined calculation, testing.
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89HPES4T4G2 Data Sheet
Signal JTAG JTAG_TCK
Symbol
Reference Edge
Unit
Timing Diagram Reference
Tper_16a Thigh_16a, Tlow_16a
none
50.0 10.0
25.0
Figure
JTAG_TMS1, JTAG_TDI JTAG_TDO
Tsu_16b Thld_16b Tdo_16c Tdz_16c
JTAG_TCK rising
JTAG_TCK falling
JTAG_TRST_N
Tpw_16d2
none
25.0
Table JTAG Timing Characteristics
values this symbol were determined calculation, testing.
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure JTAG Timing Waveform Tdz_16c Tper_16a
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JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should held while signal applied JTAG_TRST_N changes from Otherwise, race occur JTAG_TRST_N deasserted (going from high) rising edge JTAG_TCK when JTAG_TMS low, because controller might either Run-Test/Idle state stay Test-Logic-Reset state.
89HPES4T4G2 Data Sheet
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPEA1 VDDPEHA VDDPETA
Parameter Internal logic supply supply except SerDes LVPECL/CML Express Analog Power
Minimum 3.135 0.95 2.25 0.95
Typical
Maximum 3.465 2.75
Unit
Express Analog High Power Express Transmitter Analog Voltage Common ground
Table PES4T4G2 Operating Voltages should have more than 25mVpeak-peak power supply noise superimposed 1.0V nominal value.
VDDPEHA should have more than 50mVpeak-peak power supply noise superimposed 2.5V nominal value.
During power supply ramp-up, VDDCORE must remain least 1.0V below VDDI/O times. There other power-up sequence requirements various operating supply voltages. power-down sequence occur order.
Recommended Operating Temperature
Grade Commercial Temperature +70°C Ambient
Table PES4T4G2 Operating Temperatures
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Power-Up/Power-Down Sequence
89HPES4T4G2 Data Sheet
Power Consumption
Typical power measured under following conditions: 25°C Ambient, total link usage ports, typical voltages defined Table (and also listed below). Maximum power measured under following conditions: 70°C Ambient, total link usage ports, maximum voltages defined Table (and also listed below).
Number active Lanes Port
Core Supply 1.0V 1.1V
PCIe Analog Supply 1.0V 1.1V
PCIe Analog High Supply 2.5V 2.75V
PCIe Termination Supply 1.0V 1.1V
Supply 3.3V 3.465V
Total Power Power
1/1/1/1 Full Swing 1/1/1/1 Half Swing
Watts Watts
0.38 0.38
0.77 0.77
0.70 0.70
0.83 0.83
0.19 0.19
0.23 0.23
0.36 0.18
0.47 0.24
0.007 0.007
0.01 0.01 1.45 2.07 1.63 2.31
Thermal Considerations
This section describes thermal considerations PES4T4G2 (19mm2 FCBGA324 package). data Table below contains information that relevant thermal performance PES4T4G2 switch.
Symbol TJ(max) TA(max)
Parameter Junction Temperature Ambient Temperature Thermal Resistance, Junction-to-Case Power Dissipation Device
Value 2.31
Units
oC/W
Conditions Maximum Maximum Maximum
Watts
Table Thermal Specifications PES4T4G2, 19x19 FCBGA324 Package
Note: important reliability this device user environment that junction temperature exceed TJ(max) value specified Table Consequently, effective junction ambient thermal resistance (JA) worst case scenario must maintained below value determined formula: (TJ(max) TA(max))/P Given that values TJ(max), TA(max), known, value desired becomes known entity system designer. achieve desired left board system designer, general, achieved adding effects (value provided Table 15), thermal resistance chosen adhesive (CS), that heat sink (SA), amount airflow, properties circuit board (number layers size board). general guideline, this device will need heat sink board more layers board size larger than 4"x12" airflow excess available. strongly recommended that users perform their thermal analysis their board system design scenarios.
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Table PES4T4G2 Power Consumption
89HPES4T4G2 Data Sheet
Electrical Characteristics
Values based systems running recommended supply voltages, shown Table Note: Table Characteristics, complete listing.
Min1 Serial Link PCIe Transmit VTX-DIFFp-p VTX-DIFFp-p-LOW VTX-DE-RATIO3.5dB
Type
Parameter
Description
Max1 Min1 Typ1 Max1
Unit
Conditions
Typ1
Differential peak-to-peak output voltage Low-Drive Differential Peak Peak Output Voltage De-emphasized differential output voltage De-emphasized differential output voltage Common mode voltage peak common mode output voltage delta common mode voltage between idle delta common mode voltage between DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss
1200 1200
-3.0 -5.5 -3.5 -6.0
1200 1200 -4.0 -6.5
6.0dB
VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
10dB: 0.05 1.25GHz 8dB: 1.25 2.5GHz
VTX-CM-DC-linedelta
VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF
RLTX-CM ZTX-DIFF-DC VTX-CM-ACpp VTX-DC-CM
Transmitter Common Mode Return loss Differential impedance Peak-Peak Common Transmit Driver Common Mode Voltage
VTX-RCV-DETECT amount voltage change allowed during Receiver Detection ITX-SHORT Transmitter Short Circuit Current Limit
Table Electrical Characteristics (Part
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VTX-DE-RATIO-
89HPES4T4G2 Data Sheet Min1 Serial Link (cont.) PCIe Receive VRX-DIFFp-p RLRX-DIFF Differential input voltage (peakto-peak) Receiver Differential Return Loss 1200 1200 10dB: 0.05 1.25GHz 8dB: 1.25 2.5GHz 350k Refer return loss spec Typ1 Max1 Min1 Typ1 Max1 Unit Conditions
Type
Parameter
Description
RLRX-CM ZRX-DIFF-DC ZRX-DC ZRX-COMM-DC ZRX-HIGH-IMPDC-POS
Receiver Common Mode Return Loss Differential input impedance (DC) common mode impedance Powered down input common mode impedance (DC) input input impedance during reset power down input input impedance during reset power down Electrical idle detect threshold Receiver common-mode peak voltage
200k
ZRX-HIGH-IMPDC-NEG
1.0k
1.0k
VRX-IDLE-DETDIFFp-p
VRX-CM-ACp
VRX-CM-ACp PCIe REFCLK Other I/Os Drive Output High Drive Output Schmitt Trigger Input (STI) Input
Input Capacitance
-0.3 -0.3
-5.5 12.0 -20.0
VDDI/O VDDI/O
-0.3 -0.3
-5.5 12.0 -20.0
VDDI/O VDDI/O
0.4v 1.5V 0.4v 1.5V
Table Electrical Characteristics (Part
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89HPES4T4G2 Data Sheet Min1 Capacitance Leakage Inputs I/OLEAK Pull-ups/downs I/OLEAK WITH Pull-ups/downs Typ1 Max1 Min1 Typ1 Max1 VDDI/O (max) VDDI/O (max) VDDI/O (max) Unit Conditions
Type
Parameter
Description
Table Electrical Characteristics (Part
Minimum, Typical, Maximum values meet requirements under Specification 2.0.
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89HPES4T4G2 Data Sheet
Package Pinout 324-BGA Signal Pinout PES4T4G2
following table lists numbers signal names PES4T4G2 device.
VDDI/O VDDI/O VDDI/O VDDI/O JTAG_TDI MSMBDAT VDDI/O GPIO_00 VDDI/O VDDI/O VDDI/O VDDI/O VDDPETA VDDI/O VDDI/O JTAG_TMS SSMBCLK VDDI/O SWMODE_1 GPIO_01 GPIO_10 VDDPETA Function VDDPEA JTAG_TCK JTAG_TRST_N SSMBDAT CCLKDS SWMODE_2 GPIO_02 GPIO_09 VDDPEA JTAG_TDO MSMBCLK CCLKUS SWMODE_0 PERSTN GPIO_07 GPIO_08 Function VDDPETA VDDPEHA VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDPEHA VDDPETA PE3TP00 PE3TN00 VDDPEA PE3RP00 PE3RN00 VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE Function VDDPEA REFRES2 REFRES3 VDDPEHA VDDCORE VDDCORE VDDCORE VDDPEHA VDDPEA VDDCORE VDDCORE VDDCORE Function
Table PES4T4G2 324-pin Signal Pin-Out (Part
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89HPES4T4G2 Data Sheet Function VDDCORE VDDCORE VDDPEA VDDPETA VDDPEHA VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDPEHA VDDPETA VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDPEA VDDPEHA VDDCORE VDDCORE VDDCORE VDDPEHA VDDPEA PE2TP00 PE2TN00 VDDPETA PE2RP00 PE2RN00 VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE Function VDDPETA VDDPEHA VDDPEHA VDDPEHA VDDPEHA VDDCORE PE1RN00 VDDCORE PE0RN00 Function VDDCORE VDDCORE VDDCORE PE1RP00 VDDCORE PE0RP00 VDDCORE VDDCORE VDDCORE VDDPEA VDDPETA VDDPEA VDDPETA VDDCORE VDDPEA VDDPETA VDDPEA VDDPETA VDDCORE Function
Table PES4T4G2 324-pin Signal Pin-Out (Part
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89HPES4T4G2 Data Sheet Function VDDCORE PEREFCLKN PE1TN00 REFRES1 PE0TN00 VDDCORE Function PEREFCLKP PE1TP00 REFRES0 Function PE0TP00 Function
Table PES4T4G2 324-pin Signal Pin-Out (Part
Alternate Signal Functions
GPIO GPIO_00 GPIO_02 GPIO_07 GPIO_08 GPIO_09 Alternate P2RSTN IOEXPINTN0 GPEN P1RSTN P3RSTN
Table PES4T4G2 Alternate Signal Functions
Connection Pins
Pins Pins Pins Pins Pins Pins
Table PES4T4G2 Connection Pins
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89HPES4T4G2 Data Sheet
Power Pins
VDDCore VDDCore Table PES4T4G2 Power Pins VDDCore VDDI/O VDDPEA VDDPEHA VDDPETA
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89HPES4T4G2 Data Sheet
Ground Pins
Table PES4T4G2 Ground Pins
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89HPES4T4G2 Data Sheet
Signals Listed Alphabetically
Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBCLK MSMBDAT CONNECTION PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE1RN00 PE1RP00 PE1TN00 PE1TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 Type Location Table Express SMBus JTAG General Purpose Input/Output Signal Category System
Table 89PES4T4G2 Alphabetical Signal List (Part
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89HPES4T4G2 Data Sheet Signal Name PEREFCLKN PEREFCLKP PERSTN REFRES0 REFRES1 REFRES2 REFRES3 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 VDDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA Type Location System SMBus System SerDes Reference Resistors Signal Category Express (cont.)
Table listing ground pins. Table 89PES4T4G2 Alphabetical Signal List (Part
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Table listing power pins.
89HPES4T4G2 Data Sheet
PES4T4G2 Pinout View
VDDCore (Power) VDDI/O (Power)
VDDPETA (Power) VDDPEA (Power) VDDPEHA (Power)
(Ground)
Signals Connect
December 2007
Advance Information
89HPES4T4G2 Data Sheet
PES4T4G2 Package Drawing 324-Pin AL324/AR324
December 2007
Advance Information
89HPES4T4G2 Data Sheet
PES4T4G2 Package Drawing Page
December 2007
Advance Information
89HPES4T4G2 Data Sheet
Revision History
November 2007: Initial publication Advanced data sheet. December 2007: Added address location MSMBADDR (0x50) SSMBADDR (0x77).
December 2007
Advance Information
89HPES4T4G2 Data Sheet
Ordering Information
Product Family Operating Voltage Device Family Product Detail Legend Alpha Character Numeric Character
Generation Device Revision Series
Package Temp Range
Blank
Commercial Temperature (0°C +70°C Ambient) 324-ball FCBGA 324-ball FCBGA, RoHS revision PCIe 4-lane, 4-port Express Switch
1.0V 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES4T4G2ZAAL 89HPES4T4G2ZAAR 324-ball FCBGA package, Commercial Temperature 324-ball RoHS FCBGA package, Commercial Temperature
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Tech Support: email: ssdhelp@idt.com phone: 408-284-8208
December 2007
Advance Information
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