SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful

Datasheet Thumbnail

Top Searches for this datasheet

ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fully integrated Eleven LVCMOS LVTTL outputs, typical output impedance LVCMOS LVTTL REF_CLK input Output frequency range 180MHz 3.3V range: 240MHz 480MHz External feedback "zero delay" clock regeneration Cycle-to-cycle jitter: 100ps (maximum) 3.3V supply voltage -40°C 85°C ambient operating temperature Available both standard lead-free RoHS compliant packages
GENERAL DESCRIPTION
ICS87952I-147 voltage, skew LVCMOS/LVTTL Clock Generator memHiPerClockSber HiPerClockSfamily High Performance Clock Solutions from ICS. With output frequencies 180MHz, ICS87952I-147 targeted high performance clock applications. Along with fully integrated PLL, ICS87952I-147 contains frequency configurable outputs external feedback input regenerating clocks with "zero delay".
test system debug purposes, nPLL_EN input allows bypassed. When HIGH, MR/nOE input resets internal dividers forces outputs high impedance state. impedance LVCMOS/LVTTL outputs ICS87952I-147 designed drive terminated transmission lines. effective fanout each output doubled utilizing ability each output drive series terminated transmission lines.
BLOCK DIAGRAM
nPLL_EN
ASSIGNMENT
GNDO GNDO VDDO VDDO
REF_CLK
PHASE DETECTOR 480MHz
÷4/÷6
VDDO GNDO GNDO
÷4/÷2
VCO_SEL
VDDO GNDO VDDA nPLL_EN
FB_IN
ICS87952I-147
VCO_SEL F_SELA
VDDO
F_SELC
F_SELB
F_SELA
MR/nOE
REF_CLK
GNDI
FB_IN
REV. APRIL 2006
F_SELB
÷2/÷4
F_SELC MR/nOE
87952AYI-147
32-Lead LQFP 1.4mm package body package View
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Input Input Input Input Description
TABLE DESCRIPTIONS
Number Name VCO_SEL F_SELC F_SELB F_SELA Pulldown select input. LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Active High Master Reset. Active output enable. When logic HIGH, internal dividers reset outputs Hi-Z. Pulldown When logic LOW, internal dividers outputs enabled. Reset required power-up. LVCMOS LVTTL interface levels. Pulldown Reference clock input. LVCMOS LVTTL interface levels. Internal power supply ground. Feedback input phase detector generating clocks with Pulldown "zero delay". LVCMOS LVTTL interface levels. select input. Selects between REF_CLK PLL. Pulldown When HIGH, selects REF_CLK. When LOW, selects PLL. LVCMOS LVTTL interface levels. Analog supply pin. Core supply pin. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output power supply ground. Output supply pins. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels.
MR/nOE REF_CLK GNDI FB_IN nPLL_EN VDDA QA0, QA1, QA2, QA3, GNDO VDDO QB0, QB1, QB2, QC0,
Input Input Power Input Input Power Power Output Power Power Output Output
NOTE: Pulldown refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN ROUT Parameter Input Capacitance Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical VDD, VDDA, VDDO 3.465V Maximum Units
TABLE CONTROL INPUT FUNCTION TABLE
Input F_SELA
87952AYI-147
TABLE CONTROL SELECT FUNCTION TABLE
Input F_SELC Output QC0:QC1 Control Input VCO_SEL MR/nOE nPLL_EN Logic fVCO Output Enable Enable Logic fVCO/2 Disable
REV. APRIL 2006
Output QA0:QA4
Input F_SELB
Output QB0:QB3
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V -0.5V VDDO 0.5V 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage REF_CLK, Input MR/nOE, FB_IN, VCO_SEL, High Current F_SELA:F_SELC, nPLL_EN REF_CLK, Input MR/nOE, FB_IN, VCO_SEL, Current F_SELA:F_SELC, nPLL_EN Output High Voltage; NOTE Test Conditions Minimum Typical -0.3 3.465V Maximum Units
3.465V, -20mA
-120
Output Voltage; NOTE 20mA NOTE Outputs terminaed with VDDO/2. Parameter Measurement Information Section, "3.3V Output Load Test Circuit" diagram.
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Reference Frequency NOTE: Input reference frequency limited fREF divider selection lock range. Test Conditions Minimum Typical Maximum Units
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions (÷2) (÷4) Minimum REF_CLK 50MHz -100 Frequency Output Frequencies Mixed Same Frequency Output Frequencies Mixed Same Frequency 0.8V 2.0V 0.10 Typical Maximum Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX Parameter Maximum Output Frequency (PLL Mode)
fVCO
(÷6) Propagation Delay, REF_CLK FB_IN Delay, (Static Phase Offset); NOTE Lock Range Outputs Output Skew; NOTE Within Bank Within Bank Within Bank
sk(o)
jit(cc)
Cycle-to-Cycle Jitter NOTE Period Jitter
Outputs
jit(per) tPLZ, tPHZ tPZL
Outputs Lock Time Output Rise/Fall Time Output Disable Time Output Enable Time Output Duty Cycle
parameters measured fMAX unless noted otherwise. outputs loaded VDDO/2. NOTE Measured from VDD/2 input VDDO/2 output. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE This parameter defined accordance with JEDEC Standard
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDDA 1.65V±5%
VDD, VDDO
SCOPE
LVCMOS
tsk(o)
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
OUTPUT SKEW
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
REF_CLK
FB_IN
VDDO
REF_CLK FB_IN DELAY
VDDO PERIOD
VDDO
QAx, QBx,
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87952AYI-147
QAx, QBx,
VREF
tcycle
tcycle
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
0.8V
0.8V
Clock Outputs
OUTPUT RISE/FALL TIME
VDDO
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87952I-147 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10mF .01mF bypass capacitor should connected each VDDA pin.
3.3V .01F .01F
FIGURE POWER SUPPLY FILTERING
RECOMMENDATIONS UNUSED INPUT OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: control pins have internal pull-downs; additional resistance required added additional protection. resistor used. LVCMOS OUTPUT: unused LVCMOS output left floating. There should trace attached.
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
lected component types, density components, density traces, stack P.C. board.
LAYOUT GUIDELINE
schematic ICS87952I-147 layout example shown Figure This layout example used general guideline. layout actual system will depend
Receiv VDDO
F_SELC F_SELB F_SELA ICS87952 ICS87952I-147
VDDO GNDO GNDO VDDO
Driv er_LVCMOS
Logic Input Examples
nPLL_EN VDDA GNDO VDDO
VCO_SEL F_SELC F_SELB F_SELA MR/nOE REF_CLK GNDI FB_IN
GNDO VDDO VDDO GNDO
Logic Input
Logic Input
Install
0.01u 0.1u Receiv
VDD=3.3V
(U1-16) (U1-20) (U1-21) (U1-25) (U1-32)
Logic Input pins
Install
Logic Input pins
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
FIGURE ICS87952I-147 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER SCHEMATIC EXAMPLE
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
back cause system failure. shape trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. series termination resistors should located close driver pins possible.
following component footprints used this layout example: resistors capacitors size 0603.
POWER GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring
Trace
Other signals
VCCA
Trace
FIGURE BOARD LAYOUT ICS87952I-147
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87952I-147 2882 Compatible with MPC952, MPC9352, MPC93R52
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE SUFFIX LEAD LQFP
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Marking Package Lead LQFP Lead LQFP Lead "Lead-Free" LQFP Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape reel tray 1000 tape reel Temperature -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87952AYI-147 ICS87952AYI-147T ICS87952AYI-147LF ICS87952AYI-147LFT
ICS87952AI147 ICS87952AI147 ICS7952AI147L ICS7952AI147L
NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS compliant.
aforementioned trademark, HiPerClockS trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87952AYI-147
REV. APRIL 2006
ICS87952I-147
SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET
Table
Page
Description Change Characteristics Table tPD, deleted typical deleted row.
Date 4/10/06
87952AYI-147
REV. APRIL 2006

SKEW, 1-TO-11 LVCMOS LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful

Top Searches for this datasheet

Other recent searches