8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable

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8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable

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8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash ATmega640/V ATmega1280/V ATmega1281/V ATmega2560/V ATmega2561/V Preliminary Summary
Configurations
Figure 1-1. TQFP-pinout ATmega640/1280/2560
(ADC10/PCINT18) (ADC11/PCINT19) (ADC12/PCINT20) (ADC13/PCINT21) (ADC14/PCINT22) (ADC6/TDO) (ADC7/TDI) (ADC15/PCINT23) (ADC8/PCINT16) (ADC5/TMS) (ADC4/TCK) (ADC9/PCINT17)
(ADC1)
(ADC2)
(ADC0)
(ADC3)
(AD0)
(AD1)
(OC0B) (RXD0/PCINT8) (TXD0) (XCK0/AIN0) (OC3A/AIN1) (OC3B/INT4) (OC3C/INT5) (T3/INT6) (CLKO/ICP3/INT7) (RXD2) (TXD2) (XCK2) (OC4A) (OC4B) (OC4C) (OC2B) (SS/PCINT0) (SCK/PCINT1) (MOSI/PCINT2) (MISO/PCINT3) (OC2A/PCINT4) (OC1A/PCINT5) (OC1B/PCINT6)
(OC0A/OC1C/PCINT7)
(AD2)
AVCC
AREF
(AD3) (AD4) (AD5) (AD6) (AD7) (ALE) (PCINT15) (PCINT14) (PCINT13) (PCINT12) (XCK3/PCINT11) (TXD3/PCINT10) (RXD3/PCINT9) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (RD) (WR)
INDEX CORNER
(T4)
(TOSC2)
(TOSC1)
RESET
XTAL2
XTAL1
(ICP4)
(ICP5)
(T5)
(OC5A)
(OC5B)
(OC5C)
(SCL/INT0)
(SDA/INT1)
(RXD1/INT2)
(TXD1/INT3)
(ICP1)
(XCK1)
(T1)
(T0)
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Figure 1-2. CBGA-pinout ATmega640/1280/2560
view
Bottom view
Table 1-1.
AVCC
CBGA-pinout ATmega640/1280/2560.
AREF RESET XTAL2 XTAL1
2549LS-AVR-08/07
Figure 1-3.
Pinout ATmega1281/2561
(ADC6/TDO) (ADC4/TCK) (ADC5/TMS) (ADC7/TDI) (ADC0) (ADC1) (ADC2) (ADC3)
(AD0)
(AD1)
(OC0B) (RXD0/PCINT8/PDI) (TXD0/PDO) (XCK0/AIN0) (OC3A/AIN1) (OC3B/INT4) (OC3C/INT5) (T3/INT6) (ICP3/CLKO/INT7) (SS/PCINT0) (SCK/ PCINT1) (MOSI/ PCINT2) (MISO/ PCINT3) (OC2A/ PCINT4) (OC1A/PCINT5) (OC1B/PCINT6)
INDEX CORNER
(AD2)
AVCC
AREF
(AD3) (AD4) (AD5) (AD6) (AD7) (ALE) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (RD) (WR)
ATmega1281/2561
(T1)
(RXD1/INT2)
(SCL/INT0)
(TXD1/INT3)
(OC0A/OC1C/PCINT7)
(XCK1)
(ICP1)
Note:
large center underneath QFN/MLF package made metal internally connected GND. should soldered glued board ensure good mechanical stability. center left unconnected, package might loosen from board.
Disclaimer
Typical values contained this datasheet based simulations characterization other microcontrollers manufactured same process technology. Min. values will available after device characterized.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
(SDA/INT1)
(TOSC2)
(TOSC1)
(T0)
XTAL2
RESET
XTAL1
ATmega640/1280/1281/2560/2561
Overview
ATmega640/1280/1281/2560/2561 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATmega640/1280/1281/2560/2561 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed.
Block Diagram
Block Diagram
PF7.0
Figure 2-1.
PK7.0
PJ7.0
PE7.0
RESET
Power Supervision RESET
PORT
PORT
PORT
PORT
Watchdog Timer
Watchdog Oscillator
JTAG
Converter
Analog Comparator
USART
XTAL1
Oscillator Circuits Clock Generation
EEPROM
Internal Bandgap reference
16bit
XTAL2
16bit
USART
PA7.0
PORT
16bit USART
PG5.0
PORT
XRAM
FLASH
SRAM
16bit
PC7.0
PORT
8bit
8bit
USART
NOTE: Shaded parts only available 100-pin version. Complete functionality ADC, T/C4, T/C5 only available 100-pin version.
PORT PORT PORT PORT
PD7.0
PB7.0
PH7.0
PL7.0
2549LS-AVR-08/07
core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega640/1280/1281/2560/2561 provides following features: 64K/128K/256K bytes In-System Programmable Flash with Read-While-Write capabilities, bytes EEPROM, bytes SRAM, 54/86 general purpose lines, general purpose working registers, Real Time Counter (RTC), flexible Timer/Counters with compare modes PWM, USARTs, byte oriented 2-wire Serial Interface, 16-channel, 10-bit with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, serial port, IEEE std. 1149.1 compliant JTAG test interface, also used accessing On-chip Debug system programming software selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counters, port, interrupt system continue functioning. Power-down mode saves register contents freezes Oscillator, disabling other chip functions until next interrupt Hardware Reset. Powersave mode, asynchronous timer continues run, allowing user maintain timer base while rest device sleeping. Noise Reduction mode stops modules except Asynchronous Timer ADC, minimize switching noise during conversions. Standby mode, Crystal/Resonator Oscillator running while rest device sleeping. This allows very fast start-up combined with power consumption. Extended Standby mode, both main Oscillator Asynchronous Timer continue run. device manufactured using Atmel's high-density nonvolatile memory technology. Onchip Flash allows program memory reprogrammed in-system through serial interface, conventional nonvolatile memory programmer, On-chip Boot program running core. boot program interface download application program application Flash memory. Software Boot Flash section will continue while Application Flash section updated, providing true Read-While-Write operation. combining 8-bit RISC with In-System Self-Programmable Flash monolithic chip, Atmel ATmega640/1280/1281/2560/2561 powerful microcontroller that provides highly flexible cost effective solution many embedded control applications. ATmega640/1280/1281/2560/2561 supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, in-circuit emulators, evaluation kits.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Comparison Between ATmega1281/2561 ATmega640/1280/2560
Each device ATmega640/1280/1281/2560/2561 family differs only memory size number pins. Table summarizes different configurations devices.
Table 2-1.
Device ATmega640 ATmega1280 ATmega1281 ATmega2560 ATmega2561
Configuration Summary
Flash 64KB 128KB 128KB 256KB 256KB EEPROM General Purpose pins bits resolution channels Serial USARTs Channels
2.3.1
Descriptions
Digital supply voltage.
2.3.2
Ground.
2.3.3
Port (PA7.PA0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various ATmega640/1280/1281/2560/2561 listed page special features
2.3.4
Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port better driving capabilities than other ports. Port also serves functions various ATmega640/1280/1281/2560/2561 listed page special features
2.3.5
Port (PC7.PC0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up
2549LS-AVR-08/07
resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions special features ATmega640/1280/1281/2560/2561 listed page 2.3.6 Port (PD7.PD0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various ATmega640/1280/1281/2560/2561 listed page 2.3.7 special features
Port (PE7.PE0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various ATmega640/1280/1281/2560/2561 listed page special features
2.3.8
Port (PF7.PF0) Port serves analog inputs Converter. Port also serves 8-bit bi-directional port, Converter used. Port pins provide internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. JTAG interface enabled, pull-up resistors pins PF7(TDI), PF5(TMS), PF4(TCK) will activated even reset occurs. Port also serves functions JTAG interface.
2.3.9
Port (PG5.PG0) Port 6-bit port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various ATmega640/1280/1281/2560/2561 listed page special features
2.3.10
Port (PH7.PH0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 2.3.11 Port (PJ7.PJ0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 2.3.12 Port (PK7.PK0) Port serves analog inputs Converter. Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 2.3.13 Port (PL7.PL0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 2.3.14 RESET Reset input. level this longer than minimum pulse length will generate reset, even clock running. minimum pulse length given "System Reset Characteristics" page 375. Shorter pulses guaranteed generate reset. 2.3.15 XTAL1 Input inverting Oscillator amplifier input internal clock operating circuit. 2.3.16 XTAL2 Output from inverting Oscillator amplifier.
2549LS-AVR-08/07
2.3.17
AVCC AVCC supply voltage Port Converter. should externally connected VCC, even used. used, should connected through low-pass filter.
2.3.18
AREF This analog reference Converter.
Resources
comprehensive development tools application notes, datasheets available download http://www.atmel.com/avr.
Data Retention
Reliability Qualification results show that projected data retention failure rate much less than over years 85°C years 25°C.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Register Summary
Address
(0x1FF) (0x13F) (0x13E) (0x13D) (0x13C) (0x13B) (0x13A) (0x139) (0x138) (0x137) (0x136) (0x135) (0x134) (0x133) (0x132) (0x131) (0x130) (0x12F) (0x12E) (0x12D) (0x12C) (0x12B) (0x12A) (0x129) (0x128) (0x127) (0x126) (0x125) (0x124) (0x123) (0x122) (0x121) (0x120) (0x11F) (0x11E) (0x11D) (0x11C) (0x11B) (0x11A) (0x119) (0x118) (0x117) (0x116) (0x115) (0x114) (0x113) (0x112) (0x111) (0x110) (0x10F) (0x10E) (0x10D) (0x10C) (0x10B) (0x10A) (0x109) (0x108) (0x107) (0x106) (0x105) (0x104) (0x103) (0x102) (0x101)
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR3 UBRR3H UBRR3L Reserved UCSR3C UCSR3B UCSR3A Reserved Reserved OCR5CH OCR5CL OCR5BH OCR5BL OCR5AH OCR5AL ICR5H ICR5L TCNT5H TCNT5L Reserved TCCR5C TCCR5B TCCR5A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTL DDRL PINL PORTK DDRK PINK PORTJ DDRJ PINJ PORTH DDRH
Page
USART3 Data Register UMSEL31 RXCIE3 RXC3 UMSEL30 TXCIE3 TXC3 UPM31 UDRIE3 UDRE3 UPM30 RXEN3 USBS3 TXEN3 DOR3 USART3 Baud Rate Register High Byte UCSZ31 UCSZ32 UPE3 UCSZ30 RXB83 U2X3 UCPOL3 TXB83 MPCM3 USART3 Baud Rate Register Byte
page page page page page page
Timer/Counter5 Output Compare Register High Byte Timer/Counter5 Output Compare Register Byte Timer/Counter5 Output Compare Register High Byte Timer/Counter5 Output Compare Register Byte Timer/Counter5 Output Compare Register High Byte Timer/Counter5 Output Compare Register Byte Timer/Counter5 Input Capture Register High Byte Timer/Counter5 Input Capture Register Byte Timer/Counter5 Counter Register High Byte Timer/Counter5 Counter Register Byte FOC5A ICNC5 COM5A1 PORTL7 DDL7 PINL7 PORTK7 DDK7 PINK7 PORTJ7 DDJ7 PINJ7 PORTH7 DDH7 FOC5B ICES5 COM5A0 PORTL6 DDL6 PINL6 PORTK6 DDK6 PINK6 PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 FOC5C COM5B1 PORTL5 DDL5 PINL5 PORTK5 DDK5 PINK5 PORTJ5 DDJ5 PINJ5 PORTH5 DDH5 WGM53 COM5B0 PORTL4 DDL4 PINL4 PORTK4 DDK4 PINK4 PORTJ4 DDJ4 PINJ4 PORTH4 DDH4 WGM52 COM5C1 PORTL3 DDL3 PINL3 PORTK3 DDK3 PINK3 PORTJ3 DDJ3 PINJ3 PORTH3 DDH3 CS52 COM5C0 PORTL2 DDL2 PINL2 PORTK2 DDK2 PINK2 PORTJ2 DDJ2 PINJ2 PORTH2 DDH2 CS51 WGM51 PORTL1 DDL1 PINL1 PORTK1 DDK1 PINK1 PORTJ1 DDJ1 PINJ1 PORTH1 DDH1 CS50 WGM50 PORTL0 DDL0 PINL0 PORTK0 DDK0 PINK0 PORTJ0 DDJ0 PINJ0 PORTH0 DDH0
page page page page page page page page page page page page page
page page page page page page page page page page page
2549LS-AVR-08/07
Address
(0x100) (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF)
Name
PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR2 UBRR2H UBRR2L Reserved UCSR2C UCSR2B UCSR2A Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved
PINH7 UMSEL21 RXCIE2 RXC2 UMSEL11 RXCIE1 RXC1 UMSEL01 RXCIE0 RXC0
PINH6 UMSEL20 TXCIE2 TXC2 UMSEL10 TXCIE1 TXC1 UMSEL00 TXCIE0 TXC0
PINH5 UPM21 UDRIE2 UDRE2 UPM11 UDRIE1 UDRE1 UPM01 UDRIE0 UDRE0
PINH4 UPM20 RXEN2 UPM10 RXEN1 UPM00 RXEN0
PINH3
PINH2
PINH1
PINH0
Page
page
USART2 Data Register USART2 Baud Rate Register High Byte USBS2 TXEN2 DOR2 UCSZ21 UCSZ22 UPE2 UCSZ20 RXB82 U2X2 UCPOL2 TXB82 MPCM2 USART2 Baud Rate Register Byte
page page page page page page page USART1 Baud Rate Register High Byte page page UCSZ11 UCSZ12 UPE1 UCSZ10 RXB81 U2X1 UCPOL1 TXB81 MPCM1 page USART0 Baud Rate Register High Byte page page UCSZ01 UCSZ02 UPE0 UCSZ00 RXB80 U2X0 UCPOL0 TXB80 MPCM0 page page page page page page
USART1 Data Register USART1 Baud Rate Register Byte USBS1 TXEN1 DOR1
USART0 Data Register USART0 Baud Rate Register Byte USBS0 TXEN0 DOR0
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Address
(0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D)
Name
Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A Reserved Reserved OCR4CH OCR4CL OCR4BH OCR4BL OCR4AH OCR4AL ICR4H ICR4L TCNT4H TCNT4L Reserved TCCR4C TCCR4B TCCR4A Reserved Reserved OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 DIDR2
TWAM6 TWINT TWA6 TWS7
TWAM5 TWEA TWA5 TWS6 EXCLK
TWAM4 TWSTA TWA4 TWS5
TWAM3 TWSTO TWA3 TWS4 TCN2UB
TWAM2 TWWC TWA2 TWS3 OCR2AUB
TWAM1 TWEN TWA1 OCR2BUB
TWAM0 TWA0 TWPS1 TCR2AUB
TWIE TWGCE TWPS0 TCR2BUB
Page
page page page page page page page page page page
2-wire Serial Interface Data Register
2-wire Serial Interface Rate Register
Timer/Counter2 Output Compare Register Timer/Counter2 Output Compare Register Timer/Counter2 Bit) FOC2A COM2A1 FOC2B COM2A0 COM2B1 COM2B0 WGM22 CS22 CS21 WGM21 CS20 WGM20
page page
Timer/Counter4 Output Compare Register High Byte Timer/Counter4 Output Compare Register Byte Timer/Counter4 Output Compare Register High Byte Timer/Counter4 Output Compare Register Byte Timer/Counter4 Output Compare Register High Byte Timer/Counter4 Output Compare Register Byte Timer/Counter4 Input Capture Register High Byte Timer/Counter4 Input Capture Register Byte Timer/Counter4 Counter Register High Byte Timer/Counter4 Counter Register Byte FOC4A ICNC4 COM4A1 FOC4B ICES4 COM4A0 FOC4C COM4B1 WGM43 COM4B0 WGM42 COM4C1 CS42 COM4C0 CS41 WGM41 CS40 WGM40
page page page page page page page page page page page page page
Timer/Counter3 Output Compare Register High Byte Timer/Counter3 Output Compare Register Byte Timer/Counter3 Output Compare Register High Byte Timer/Counter3 Output Compare Register Byte Timer/Counter3 Output Compare Register High Byte Timer/Counter3 Output Compare Register Byte Timer/Counter3 Input Capture Register High Byte Timer/Counter3 Input Capture Register Byte Timer/Counter3 Counter Register High Byte Timer/Counter3 Counter Register Byte FOC3A ICNC3 COM3A1 FOC3B ICES3 COM3A0 FOC3C COM3B1 WGM33 COM3B0 WGM32 COM3C1 CS32 COM3C0 CS31 WGM31 CS30 WGM30
page page page page page page page page page page page page page
Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Byte FOC1A ICNC1 COM1A1 ADC7D ADC15D FOC1B ICES1 COM1A0 ADC6D ADC14D FOC1C COM1B1 ADC5D ADC13D WGM13 COM1B0 ADC4D ADC12D WGM12 COM1C1 ADC3D ADC11D CS12 COM1C0 ADC2D ADC10D CS11 WGM11 AIN1D ADC1D ADC9D CS10 WGM10 AIN0D ADC0D ADC8D
page page page page page page page page page page page page page page page page
2549LS-AVR-08/07
Address
(0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B)
Name
ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved XMCRB XMCRA TIMSK5 TIMSK4 TIMSK3 TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 EICRB EICRA PCICR Reserved OSCCAL PRR1 PRR0 Reserved Reserved CLKPR WDTCSR SREG EIND RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR
REFS1 ADEN
REFS0 ACME ADSC
ADLAR ADATE
MUX4 ADIF
MUX3 MUX5 ADIE
MUX2 ADTS2 ADPS2
MUX1 ADTS1 ADPS1
MUX0 ADTS0 ADPS0
Page
page page 272,291,,295 page page page
Data Register High byte Data Register byte XMBK PCINT23 PCINT15 PCINT7 ISC71 ISC31 PRTWI CLKPCE WDIF SP15 SPMIE OCDR7 SPIF SPIE SRL2 PCINT22 PCINT14 PCINT6 ISC70 ISC30 PRTIM2 WDIE SP14 RWWSB OCDR6 ACBG WCOL SRL1 ICIE5 ICIE4 ICIE3 ICIE1 PCINT21 PCINT13 PCINT5 ISC61 ISC21 PRTIM5 PRTIM0 WDP3 SP13 SIGRD OCDR5 DORD SRL0 PCINT20 PCINT12 PCINT4 ISC60 ISC20 PRTIM4 WDCE SP12 RWWSRE JTRF OCDR4 MSTR SRW11 OCIE5C OCIE4C OCIE3C OCIE1C PCINT19 PCINT11 PCINT3 ISC51 ISC11 PRTIM3 PRTIM1 CLKPS3 SP11 BLBSET WDRF OCDR3 ACIE Data Register CPOL CPHA SPR1 SPI2X SPR0 XMM2 SRW10 OCIE5B OCIE4B OCIE3B OCIE2B OCIE1B OCIE0B PCINT18 PCINT10 PCINT2 ISC50 ISC10 PCIE2 PRUSART3 PRSPI CLKPS2 WDP2 SP10 PGWRT BORF OCDR2 ACIC XMM1 SRW01 OCIE5A OCIE4A OCIE3A OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 ISC41 ISC01 PCIE1 PRUSART2 PRUSART0 CLKPS1 WDP1 RAMPZ1 PGERS IVSEL EXTRF OCDR1 ACIS1 XMM0 SRW00 TOIE5 TOIE4 TOIE3 TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 ISC40 ISC00 PCIE0
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Oscillator Calibration Register PRUSART1 PRADC CLKPS0 WDP0 EIND0 RAMPZ0 SPMEN IVCE PORF OCDR0 ACIS0
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General Purpose Register General Purpose Register Timer/Counter0 Output Compare Register Timer/Counter0 Output Compare Register Timer/Counter0 Bit) FOC0A COM0A1 FOC0B COM0A0 COM0B1 COM0B0 EEPROM Data Register INT7 INTF7 INT6 INTF6 EEPM1 INT5 INTF5 EEPM0 INT4 INTF4 EERIE INT3 INTF3 EEMPE INT2 INTF2 PCIF2 EEPE INT1 INTF1 PCIF1 EERE INT0 INTF0 PCIF0 General Purpose Register WGM02 CS02 CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC
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EEPROM Address Register High Byte
EEPROM Address Register Byte
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Address
0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
TIFR5 TIFR4 TIFR3 TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA
PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7
PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6
ICF5 ICF4 ICF3 ICF1 PORTG5 DDG5 PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5
PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4
OCF5C OCF4C OCF3C OCF1C PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3
OCF5B OCF4B OCF3B OCF2B OCF1B OCF0B PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2
OCF5A OCF4A OCF3A OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1
TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0
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Notes:
compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. registers within address range directly bit-accessible using instructions. these registers, value single bits checked using SBIS SBIC instructions. Some status flags cleared writing logical them. Note that instructions will operate bits register, writing back into flag read set, thus clearing flag. instructions work with registers 0x00 0x1F only. When using specific commands OUT, addresses must used. When addressing registers data space using instructions, must added these addresses. ATmega640/1280/1281/2560/2561 complex microcontroller with more peripheral units than supported within location reserved Opcode instructions. Extended space from $1FF SRAM, only ST/STS/STD LD/LDS/LDD instructions used.
2549LS-AVR-08/07
Instruction Summary
Mnemonics
ADIW SUBI SBCI SBIW ANDI MULS MULSU FMUL FMULS FMULSU RJMP IJMP EIJMP RCALL ICALL EICALL CALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC Rd,Rr Rd,Rr Rd,Rr Rd,K
Operands
Rdl,K Rdl,K Rd,K Rd,K Registers
Description
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None None None None N,V,C,H N,V,C,H N,V,C,H None None None None None None None None None None None None None None None None None None None None
#Clocks
1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
ARITHMETIC LOGIC INSTRUCTIONS with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump Extended Indirect Jump Direct Jump Relative Subroutine Call Indirect Call Extended Indirect Call Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half Carry Flag Branch Half Carry Flag Cleared Branch Flag Branch Flag Cleared Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl 0xFF 0x00 (0xFF 0xFF R1:R0 R1:R0 R1:R0
R1:R0 R1:R0
(EIND:Z) (EIND:Z) STACK STACK (Rr(b)=0) (Rr(b)=1) (P(b)=0) (P(b)=1) (SREG(s) then PCPC+k (SREG(s) then PCPC+k then then then then then then then then then then then then then then
R1:R0
BRANCH INSTRUCTIONS
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Mnemonics
BRVS BRVC BRIE BRID SWAP BSET BCLR DATA TRANSFER INSTRUCTIONS MOVW ELPM ELPM Rd,Y+q Y+q,Rr Z+q,Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Load Program Memory Load Program Memory Post-Inc Extended Load Program Memory Extended Load Program Memory Rd+1:Rd Rr+1:Rr (X), (Y), (Z), (Z), (RAMPZ:Z) (RAMPZ:Z) None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
Operands
Description
Branch Overflow Flag Branch Overflow Flag Cleared Branch Interrupt Enabled Branch Interrupt Disabled Register Clear Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Twos Complement Overflow. Clear Twos Complement Overflow SREG Clear SREG Half Carry Flag SREG Clear Half Carry Flag SREG
Operation
then then then then I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7) Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0.6 Rd(3.0)Rd(7.4),Rd(7.4)Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b)
Flags
None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None
#Clocks
BIT-TEST INSTRUCTIONS
2549LS-AVR-08/07
Mnemonics
ELPM PUSH SLEEP BREAK
Operands
Store Program Memory Port Port Push Register Stack
Description
Extended Load Program Memory R1:R0 STACK STACK
Operation
(RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1
Flags
None None None None None None None
#Clocks
Register from Stack Operation Sleep Watchdog Reset Break
CONTROL INSTRUCTIONS (see specific descr. Sleep function) (see specific descr. WDR/timer) On-chip Debug Only None None None
Note:
EICALL EIJMP exist ATmega640/1280/1281. ELPM does exist ATmega640.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Ordering Information
ATmega640
Power Supply 5.5V 5.5V Ordering Code ATmega640V-8AU ATmega640V-8CU ATmega640-16AU ATmega640-16CU Package(1)(3) 100A 100C1 100A 100C1 Operation Range Industrial (-40°C 85°C) Industrial (-40°C 85°C) Notes: Speed (MHz)(2)
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. "Speed Grades" page Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 64M2 100A 100C1 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA)
2549LS-AVR-08/07
ATmega1281
Power Supply 5.5V 5.5V Ordering Code ATmega1281V-8AU ATmega1281V-8MU ATmega1281-16AU ATmega1281-16MU Package(1)(3) 64M2 64M2 Operation Range Industrial (-40°C 85°C) Industrial (-40°C 85°C)
Speed (MHz)(2)
Notes:
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. "Speed Grades" page Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 64M2 100A 100C1 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA)
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
ATmega1280
Power Supply 5.5V 5.5V Ordering Code ATmega1280V-8AU ATmega1280V-8CU ATmega1280-16AU ATmega1280-16CU Package(1)(3) 100A 100C1 100A 100C1 Operation Range Industrial (-40°C 85°C) Industrial (-40°C 85°C) Notes:
Speed (MHz)(2)
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. "Speed Grades" page Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 64M2 100A 100C1 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA)
2549LS-AVR-08/07
ATmega2561
Power Supply 5.5V 5.5V Ordering Code ATmega2561V-8AU ATmega2561V-8MU ATmega2561-16AU ATmega2561-16MU Package(1)(3) 64M2 64M2 Operation Range Industrial (-40°C 85°C) Industrial (-40°C 85°C)
Speed (MHz)(2)
Notes:
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. "Speed Grades" page Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 64M2 100A 100C1 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA)
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
ATmega2560
Power Supply 5.5V 5.5V Ordering Code ATmega2560V-8AU ATmega2560V-8CU ATmega2560-16AU ATmega2560-16CU Package(1)(3) 100A 100C1 100A 100C1 Operation Range Industrial (-40°C 85°C) Industrial (-40°C 85°C) Notes:
Speed (MHz)(2)
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. "Speed Grades" page Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 64M2 100A 100C1 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA)
2549LS-AVR-08/07
Packaging Information
100A
IDENTIFIER
0°~7°
COMMON DIMENSIONS (Unit Measure SYMBOL 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 1.00 16.00 14.00 16.00 14.00 0.50 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note Note NOTE
Notes:
This package conforms JEDEC reference MS-026, Variation AED. Dimensions include mold protrusion. Allowable protrusion 0.25 side. Dimensions maximum plastic body size dimensions including mold mismatch. Lead coplanarity 0.08 maximum.
10/5/2001 2325 Orchard Parkway Jose, 95131 TITLE 100A, 100-lead, Body Size, Body Thickness, Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING 100A REV.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
100C1
0.12
Marked Identifier
SIDE VIEW
VIEW
0.90
Corner
0.90
COMMON DIMENSIONS (Unit Measure SYMBOL
BOTTOM VIEW
1.10 0.30 8.90 8.90 7.10 7.10 0.35
0.35 9.00 9.00 7.20 7.20 0.40 0.80
1.20 0.40 9.10 9.10 7.30 7.30 0.45
NOTE
5/25/06 2325 Orchard Parkway Jose, 95131 TITLE 100C1, 100-ball, Body, Ball Pitch 0.80 Chip Array Package (CBGA) DRAWING 100C1 REV.
2549LS-AVR-08/07
IDENTIFIER
0°~7°
COMMON DIMENSIONS (Unit Measure SYMBOL 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 1.00 16.00 14.00 16.00 14.00 0.80 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note Note NOTE
Notes: 1.This package conforms JEDEC reference MS-026, Variation AEB. Dimensions include mold protrusion. Allowable protrusion 0.25 side. Dimensions maximum plastic body size dimensions including mold mismatch. Lead coplanarity 0.10 maximum.
10/5/2001 2325 Orchard Parkway Jose, 95131 TITLE 64A, 64-lead, Body Size, Body Thickness, Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING REV.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
64M2
Marked Pin#
VIEW
SEATING PLANE
Corner
0.08
SIDE VIEW
Option
Triangle
COMMON DIMENSIONS (Unit Measure SYMBOL
Option
Chamfer 0.30)
0.80 0.18 8.90 7.50 8.90 7.50
0.90 0.02 0.25 9.00 7.65 9.00 7.65 0.50
1.00 0.05 0.30 9.10 7.80 9.10 7.80
NOTE
Option
Notch (0.20
BOTTOM VIEW
0.35 0.20
0.40 0.27
0.45 0.40
Note: JEDEC Standard MO-220, (SAW Singulation) Fig. VMMD. Dimension tolerance conform ASMEY14.5M-1994.
5/25/06 TITLE 2325 Orchard Parkway 64M2, 64-pad, Body, Lead Pitch 0.50 Jose, 95131 7.65 Exposed Pad, Micro Lead Frame Package (MLF) DRAWING 64M2 REV.
2549LS-AVR-08/07
Errata
ATmega640 rev.
Inaccurate conversion differential mode with 200x gain High current consumption sleep mode Inaccurate conversion differential mode with 200x gain With AVCC 3.6V, random conversions will inaccurate. Typical absolute accuracy reach LSB. Problem Fix/Workaround None High current consumption sleep mode. pending interrupt cannot wake part from selected sleep mode, current consumption will increase during sleep when executing SLEEP instruction directly after instruction. Problem Fix/Workaround Before entering sleep, interrupts used wake part from sleep mode should disabled.
ATmega1280 rev.
Inaccurate conversion differential mode with 200x gain High current consumption sleep mode Inaccurate conversion differential mode with 200x gain With AVCC 3.6V, random conversions will inaccurate. Typical absolute accuracy reach LSB. Problem Fix/Workaround None High current consumption sleep mode. pending interrupt cannot wake part from selected sleep mode, current consumption will increase during sleep when executing SLEEP instruction directly after instruction. Problem Fix/Workaround Before entering sleep, interrupts used wake part from sleep mode should disabled.
ATmega1281 rev.
Inaccurate conversion differential mode with 200x gain High current consumption sleep mode Inaccurate conversion differential mode with 200x gain With AVCC 3.6V, random conversions will inaccurate. Typical absolute accuracy reach LSB. Problem Fix/Workaround None
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
High current consumption sleep mode. pending interrupt cannot wake part from selected sleep mode, current consumption will increase during sleep when executing SLEEP instruction directly after instruction. Problem Fix/Workaround Before entering sleep, interrupts used wake part from sleep mode should disabled.
ATmega2560 rev.
known errata.
ATmega2560 rev.
sampled.
ATmega2560 rev.
High current consumption sleep mode High current consumption sleep mode. pending interrupt cannot wake part from selected sleep mode, current consumption will increase during sleep when executing SLEEP instruction directly after instruction. Problem Fix/Workaround Before entering sleep, interrupts used wake part from sleep mode should disabled.
ATmega2560 rev.
sampled.
ATmega2560 rev.
Non-Read-While-Write area flash functional Part does work under volts Incorrect reading differential mode Internal reference value IN/OUT instructions executed twice when Stack external EEPROM read from application code does work Lock Mode
Non-Read-While-Write area flash functional Non-Read-While-Write area flash working expected. problem related speed part when reading flash this area. Problem Fix/Workaround Only first 248K flash. boot functionality needed, code Non-Read-While-Write area maximum 1/4th maximum frequency device given voltage. This done writing CLKPR register before entering boot section code
Part does work under volts part does execute code correctly below volts
2549LS-AVR-08/07
Problem Fix/Workaround part voltages below volts. Incorrect reading differential mode high noise differential mode. give error. Problem Fix/Workaround only result when using differential mode. Internal reference value internal reference value lower than specified Problem Fix/Workaround AVCC external reference actual value reference measured applying known voltage when using internal reference. result when doing later conversions then calibrated. IN/OUT instructions executed twice when Stack external either instruction executed directly before interrupt occurs stack pointer located external ram, instruction will executed twice. some cases this will cause problem, example: reading SREG will appear that I-flag cleared. writing registers, port will toggle twice. reading registers with interrupt flags, flags will appear cleared. Problem Fix/Workaround There application work-arounds, where selecting them, will omitting issue: Replace with LD/LDS/LDD ST/STS/STD instructions internal stack pointer.
EEPROM read from application code does work Lock Mode When Memory Lock Bits programmed mode EEPROM read does work from application code. Problem Fix/Workaround Lock Protection Mode when application code needs read from EEPROM.
ATmega2561 rev.
known errata.
9.10
ATmega2561 rev.
sampled.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
9.11 ATmega2561 rev.
High current consumption sleep mode High current consumption sleep mode. pending interrupt cannot wake part from selected sleep mode, current consumption will increase during sleep when executing SLEEP instruction directly after instruction. Problem Fix/Workaround Before entering sleep, interrupts used wake part from sleep mode should disabled.
9.12
ATmega2561 rev.
sampled.
9.13
ATmega2561 rev.
Non-Read-While-Write area flash functional Part does work under Volts Incorrect reading differential mode Internal reference value IN/OUT instructions executed twice when Stack external EEPROM read from application code does work Lock Mode
Non-Read-While-Write area flash functional Non-Read-While-Write area flash working expected. problem related speed part when reading flash this area. Problem Fix/Workaround Only first 248K flash. boot functionality needed, code Non-Read-While-Write area maximum 1/4th maximum frequency device given voltage. This done writing CLKPR register before entering boot section code.
2549LS-AVR-08/07
Part does work under volts part does execute code correctly below volts Problem Fix/Workaround part voltages below volts. Incorrect reading differential mode high noise differential mode. give error. Problem Fix/Workaround only result when using differential mode
Internal reference value internal reference value lower than specified Problem Fix/Workaround AVCC external reference actual value reference measured applying known voltage when using internal reference. result when doing later conversions then calibrated. IN/OUT instructions executed twice when Stack external either instruction executed directly before interrupt occurs stack pointer located external ram, instruction will executed twice. some cases this will cause problem, example: reading SREG will appear that I-flag cleared. writing registers, port will toggle twice. reading registers with interrupt flags, flags will appear cleared. Problem Fix/Workaround There application workarounds, where selecting them, will omitting issue: Replace with LD/LDS/LDD ST/STS/STD instructions internal stack pointer. EEPROM read from application code does work Lock Mode When Memory Lock Bits programmed mode EEPROM read does work from application code. Problem Fix/Workaround Lock Protection Mode when application code needs read from EEPROM.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
Datasheet Revision History
Please note that referring page numbers this section referring this document.The referring revision this section referring document revision.
10.1
Rev. 2549L-08/07
Updated note Table 10-10 page Updated Table 10-3 page Table 10-5 page Table 10-8 page Updated typos Characteristics" page 370. Updated "Clock Characteristics" page 374. Updated "External Clock Drive" page 374. Added "System Reset Characteristics" page 375. Updated "SPI Timing Characteristics" page 377. Updated "ADC Characteristics Preliminary Data" page 379. Updated ordering code "ATmega640" page
10.2
Rev. 2549K-01/07
Updated Table page Updated "Pin Descriptions" page Updated "Stack Pointer" page Updated "Bit EEPE: EEPROM Programming Enable" page Updated Assembly code example "Thus, when enabled, after setting ACBG enabling ADC, user must always allow reference start before output from Analog Comparator used. reduce power consumption Power-down mode, user avoid three conditions above ensure that reference turned before entering Power-down mode" page Updated "EIMSK External Interrupt Mask Register" page 115. Updated description "PCIFR Change Interrupt Flag Register" page 116. Updated code example "USART Initialization" page 211. Updated Figure 26-8 page 284. Updated Characteristics" page 370.
10.3
Rev. 2549J-09/06
Updated "Calibrated Internal Oscillator" page Updated code example "Moving Interrupts Between Application Boot Section" page 109. Updated "Timer/Counter Prescaler" page 187.
2549LS-AVR-08/07
Updated "Device Identification Register" page 304. Updated "Signature Bytes" page 340. Updated "Instruction Summary" page 419.
10.4
Rev. 2549I-07/06
Added "Data Retention" page Updated Table 16-3 page 129, Table 16-6 page 130, Table 16-8 page 131, Table 17-2 page 148, Table 17-4 page 160, Table 17-5 page 160, Table 20-3 page 188, Table 20-6 page Table 20-8 page 190. Updated "Fast Mode" page 150.
10.5
Rev. 2549H-06/06
Updated "Calibrated Internal Oscillator" page Updated "OSCCAL Oscillator Calibration Register" page Added Table 31-1 page 374.
10.6
Rev. 2549G-06/06
Updated "Features" page Added Figure page Table page Updated "Calibrated Internal Oscillator" page Updated "Power Management Sleep Modes" page Updated note Table 12-1 page Updated Figure 26-9 page Figure 26-10 page 285. Updated "Setting Boot Loader Lock Bits SPM" page 325. Updated "Ordering Information" page Added Package information "100C1" page Updated "Errata" page
10.7
Rev. 2549F-04/06
Updated Figure page Figure page Figure page Updated Table 20-2 page Table 20-3 page 188. Updated Features "ADC Analog Digital Converter" page 275. Updated "Fuse Bits" page 338.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
ATmega640/1280/1281/2560/2561
10.8 Rev. 2549E-04/06
Updated "Features" page Updated Table 12-1 page Updated note Table 12-1 page Updated "Bit ACBG: Analog Comparator Bandgap Select" page 272. Updated "Prescaling Conversion Timing" page 278. Updated "Maximum speed VCC" page 373. Updated "Ordering Information" page
10.9
Rev. 2549D-12/05
Advanced Information Status changed Preliminary. Changed number Ports from Updatet typos "TCCR0A Timer/Counter Control Register page 129. Updated Features "ADC Analog Digital Converter" page 275. Updated Operation in"ADC Analog Digital Converter" page Updated Stabilizing Time "Changing Channel Reference Selection" page 282. Updated Figure 26-1 page 276, Figure 26-9 page 285, Figure 26-10 page 285. Updated Text "ADCSRB Control Status Register page 291. Updated Note Table page Table 13-14 page Table 26-3 page Table 26-6 page 296. Updated Table 31-7 page Table 31-8 page 380. Updated "Filling Temporary Buffer (Page Loading)" page 324. Updated "Typical Characteristics" page 387. Updated "Packaging Information" page Updated "Errata" page
10.10 Rev. 2549C-09/05
Updated Speed Grade section "Features" page Added "Resources" page Updated "SPI Serial Peripheral Interface" page 196. Slave mode, high period clock must larger than cycles. Updated "Bit Rate Generator Unit" page 247. Updated "Maximum speed VCC" page 373. Updated "Ordering Information" page Updated "Packaging Information" page Package 64M1 replaced 64M2. Updated "Errata" page
2549LS-AVR-08/07
10.11 Rev. 2549B-05/05
JTAG ID/Signature ATmega640 updated: 0x9608. Updated Table 13-7 page Updated "Serial Programming Instruction set" page 354. Updated "Errata" page
10.12 Rev. 2549A-03/05
Initial version.
ATmega640/1280/1281/2560/2561
2549LS-AVR-08/07
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2549LS-AVR-08/07

8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable

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