MPC853T Hardware Specification This hardware specification contai

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MPC853TEC Rev. 12/2004
MPC853T Hardware Specification
This hardware specification contains detailed information power considerations, DC/AC electrical characteristics, timing specifications MPC853T. MPC853T contains PowerPCprocessor core. This hardware specification describes pertinent electrical physical characteristics MPC853T. functional characteristics processor, refer MPC866 PowerQUICCFamily User's Manual (MPC866UM).
Overview
MPC853T PowerQUICCis 0.18-micron derivative MPC860 PowerQUICC family. operate MPC8xx core with 66-MHz external bus. MPC853T 1.8-V core 3.3-V operation with compatibility. MPC853T integrated communications controller versatile one-chip integrated microprocessor peripheral combination that used variety controller applications. particularly excels Ethernet control applications, including equipment, Ethernet routers hubs, VoIP clients, Wi-Fi access points. MPC853T PowerPC architecture-based derivative Freescale's MPC860 quad integrated communications controller (PowerQUICC). MPC853T MPC8xx core, 32-bit microprocessor that implements PowerPC architecture
Contents Overview Features Maximum Tolerated Ratings Thermal Characteristics Power Dissipation Characteristics Thermal Calculation Measurement Power Supply Power Sequencing Mandatory Reset Configurations Layout Practices Signal Timing IEEE 1149.1 Electrical Specifications Electrical Characteristics Electrical Characteristics Mechanical Data Ordering Information References Document Revision History
This document contains information product. Specifications information herein subject change without notice.
Freescale Semiconductor, Inc., 2004. rights reserved.
Features
incorporates memory management units (MMUs), instruction data caches. MPC853T subset this family devices main focus this document.
Features
MPC853T comprised three modules that each 32-bit internal bus: MPC8xx core, system integration unit (SIU), communications processor module (CPM). MPC853T block diagram shown Figure following list summarizes MPC853T features: Embedded MPC8xx core Maximum frequency operation external 50-/66-MHz core frequencies support both modes. 80-/100-MHz core frequencies support mode only. Single-issue, 32-bit core (compatible with PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) core performs branch prediction with conditional prefetch without conditional execution. 4-Kbyte data cache 4-Kbyte instruction cache Instruction cache two-way, set-associative with sets Data cache two-way, set-associative with sets Cache coherency both instruction data caches maintained 128-bit (4-word) cache blocks. Caches physically addressed, implement least recently used (LRU) replacement algorithm, lockable cache block basis. MMUs with 32-entry translation look-aside buffer (TLB), fully associative instruction, data TLBs MMUs support multiple page sizes Kbytes, Kbytes, Kbytes, Mbytes; virtual address spaces protection groups 32-bit data (dynamic sizing bits) address lines Memory controller (eight banks) Contains complete dynamic (DRAM) controller Each bank chip select support DRAM bank. wait states programmable memory bank Glueless interface DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, other memory devices DRAM controller programmable support most size speed memory interfaces Four lines, four lines, line Boot chip-select available reset (options 16-, 32-bit memory) Variable block sizes Kbytes-256 Mbytes) Selectable write protection On-chip arbitration logic Fast Ethernet Controller (FEC)
MPC853T Hardware Specification, Rev.
Features
General-purpose timers 16-bit timers 32-bit timer Gate mode enable/disable counting Interrupt masked reference match event capture System integration unit (SIU) monitor Software watchdog Periodic interrupt timer (PIT) Clock synthesizer Decrementer time base Reset controller IEEE 1149.1 test access port (JTAG) Interrupts Seven external interrupt request (IRQ) lines Seven port pins with interrupt capability Eighteen internal interrupt sources Programmable priority between SCCs Programmable highest priority request Communications processor module (CPM) RISC controller Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, RESTART TRANSMIT) Supports continuous mode transmission reception serial channels 8-Kbytes dual-port Eight serial (SDMA) channels Three parallel registers with open-drain capability baud-rate generators Independent (can connected SCC3/4 SMC1) Allow changes during operation Autobaud support option SCCs (serial communication controllers) Ethernet/IEEE 802.3 optional SCC3 SCC4, supporting full 10-Mbps operation HDLC/SDLC HDLC (implements HDLC-based local area network (LAN)) Universal asynchronous receiver transmitter (UART) Totally transparent (bit streams) Totally transparent (frame based with optional cyclic redundancy check (CRC)) (serial management channels) UART
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Features
(serial peripheral interface) Supports master slave modes Supports multiple-master operation same MPC853T time-slot assigner (TSA) that supports (TDMb) Allows SCCs multiplexed and/or non-multiplexed operation Supports CEPT, highway, ISDN basic rate, ISDN primary rate, user defined 8-bit resolution Allows independent transmit receive routing, frame synchronization, clocking Allows dynamic changes internally connected three serial channels (two SCCs SMC) PCMCIA interface Master (socket) interface, release compliant Supports independent PCMCIA socket, memory windows Debug interface Eight comparators: four operate instruction address, operate data address, operate data Supports conditions: Each watchpoint generate break point internally Normal high normal power modes conserve power 1.8-V core 3.3-V operation with compatibility. Refer Table listing tolerant pins.
MPC853T Hardware Specification, Rev.
Features
4-Kbyte Instruction Instruction Cache
System Interface Unit (SIU) Unified Memory Controller
External Internal Interface Interface Unit Unit System Functions PCMCIA-ATA Interface
Embedded MPC8xx Processor Core
Instruction 32-Entry ITLB
Load/Store
4-Kbyte Data Cache Data 32-Entry DTLB
Fast Ethernet Controller DMAs FIFOs
10/100 BaseT Media Access Control
Parallel Baud Rate Generators
Interrupt 8-Kbyte Timers Controllers Dual-Port 32-Bit RISC Controller Program Timers
Virtual IDMA Serial Channels
SCC3
SCC4
SMC1
Time-Slot Assigner Serial Interface (NMSI)
Figure MPC853T Block Diagram
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Maximum Tolerated Ratings
Maximum Tolerated Ratings
Table Maximum Tolerated Ratings
Rating Supply voltage Symbol VDDL (core voltage) VDDH (I/O voltage) VDDSYN Difference between VDDL VDDSYN Input voltage Storage temperature range
This section provides maximum tolerated voltage temperature ranges MPC853T. Table provides maximum ratings operating temperatures.
Value -0.3 -0.3 -0.3 GND-0.3 VDDH +150
Unit
Tstg
power supply device must start ramp from Functional operating conditions provided with electrical specifications Table Absolute maximum ratings stress ratings only; functional operation maxima guaranteed. Stress beyond those listed affect device reliability cause permanent damage device. Caution: inputs that tolerate cannot more than greater than DDH. This restriction applies power normal operation (that MPC853T unpowered, voltage greater than must applied inputs).
Table Operating Temperatures
Rating Temperature (standard) Symbol TA(min) Tj(max) Temperature (extended) TA(min) Tj(max)
Value
Unit
Minimum temperatures guaranteed ambient temperature, Maximum temperatures guaranteed junction temperature,
This device contains circuitry protecting against damage caused high-static voltage electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (for example, either GND, VDDL, VDDH).
MPC853T Hardware Specification, Rev.
Thermal Characteristics
Thermal Characteristics
Table MPC853T Thermal Resistance Data
Rating Junction-to-ambient Natural convection Environment Single-layer board (1s) Four-layer board (2s2p) Airflow (200 ft/min) Single-layer board (1s) Four-layer board (2s2p) Junction-to-board Junction-to-case
Table shows thermal characteristics MPC853T.
Symbol RJMA
Value
Unit °C/W
RJMA3 RJMA3
Junction-to-package
Natural convection Airflow (200 ft/min)
Junction temperature function on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation other components board, board thermal resistance. SEMI G38-87 JEDEC JESD51-2 with single-layer board horizontal. JEDEC JESD51-6 with board horizontal. Thermal resistance between printed circuit board JEDEC JESD51-8. Board temperature measured surface board near package. Indicates average thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1) with cold plate temperature used case temperature. exposed packages where would expected soldered, junction-to-case thermal resistance simulated value from junction exposed without contact resistance. Thermal characterization parameter indicating temperature difference between package junction temperature JEDEC JESD51-2.
Power Dissipation
Table provides power dissipation information. modes 1:1, where speeds equal, mode, where frequency twice speed.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Characteristics
Table Power Dissipation (PD)
Revision Mode Frequency (MHz)
Typical
Maximum
Unit
Typical power dissipation measured Maximum power dissipation VDDL VDDSYN VDDH 3.465
NOTE Values Table represent DDL-based power dissipation include power dissipation over VDDH. power dissipation varies widely application buffer current, which depends external circuitry. DDSYN power dissipation negligible.
Characteristics
Table Electrical Specifications
Characteristic Operating voltage Symbol VDDH VDDL VDDSYN Difference between VDDL VDDSYN Input high voltage (all inputs except PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO) Input voltage EXTAL, EXTCLK input high voltage Input leakage current, (except TMS, TRST, DSCK, DSDI pins) tolerant pins Input leakage current, VDDH (except TMS, TRST, DSCK, DSDI) Input leakage current, (except TMS, TRST, DSCK, DSDI) Input capacitance 3.135 3.465 3.465 Unit
Table provides electrical characteristics MPC853T.
VIHC
VDDH
VDDH
MPC853T Hardware Specification, Rev.
Thermal Calculation Measurement
Table Electrical Specifications (continued)
Characteristic Output high voltage, -2.0 VDDH (except XTAL open-drain pins) Output voltage (CLKOUT) (Txd1/pa14, txd2/pa12) (TS, TEA, HRESET, SRESET)
Symbol
Unit
PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO tolerant pins. Input capacitance periodically sampled. A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IWP(0:1)/VFLS(0:1), RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CLK5/PA3, BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24, BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14, MII-RXD1/PD13, MII-MDC/PD12, MII-TXERR/RXD3/PD11, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4, MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, MII_COL BDIP/GPL_B(5), FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)
Thermal Calculation Measurement
NOTE VDDSYN power dissipation negligible.
following discussions, (VDDL IDDL) PI/O, where PI/O power dissipation drivers.
Estimation with Junction-to-Ambient Thermal Resistance
estimation chip junction temperature, obtained from following equation: (RJA where: ambient temperature package junction-to-ambient thermal resistance power dissipation package junction-to-ambient thermal resistance industry standard value that provides quick easy estimation thermal performance. However, answer only estimate; test cases have demonstrated that errors factor quantity possible.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Thermal Calculation Measurement
Estimation with Junction-to-Case Thermal Resistance
Historically, thermal resistance frequently been expressed junction-to-case thermal resistance case-to-ambient thermal resistance: where: junction-to-ambient thermal resistance junction-to-case thermal resistance case-to-ambient thermal resistance device related cannot influenced user. user adjusts thermal environment affect case-to-ambient thermal resistance, RCA. instance, user change airflow around device, heat sink, change mounting arrangement printed circuit board, change thermal dissipation printed circuit board surrounding device. This thermal model most useful ceramic packages with heat sinks where some heat flows through case heat sink ambient environment. most packages, better model required.
Estimation with Junction-to-Board Thermal Resistance
simple package thermal model which demonstrated reasonable accuracy (about 20%) two-resistor model consisting junction-to-board junction-to-case thermal resistance. junction-to-case thermal resistance covers situation where heat sink used substantial amount heat dissipated from package. junction-to-board thermal resistance describes thermal performance when most heat conducted printed circuit board. been observed that thermal performance most plastic packages, especially PBGA packages, strongly dependent board temperature. board temperature known, estimate junction temperature environment made using following equation: (RJB where: junction-to-board thermal resistance board temperature power dissipation package board temperature known heat loss from package case ignored, acceptable predictions junction temperature made. this method work, board board mounting must similar test board used determine junction-to-board thermal resistance, namely 2s2p (board with power ground plane) vias attaching thermal balls ground plane.
Estimation Using Simulation
When board temperature known, thermal simulation application needed. simple resistor model used with thermal simulation application [2], more accurate complex model package used thermal simulation.
MPC853T Hardware Specification, Rev.
Power Supply Power Sequencing
Experimental Determination
determine junction temperature device application after prototypes available, thermal characterization parameter (JT) used. determines junction temperature with measurement temperature center package case using following equation: where: thermal characterization parameter thermocouple temperature package power dissipation package thermal characterization parameter measured JESD51-2 specification published JEDEC using gauge type thermocouple epoxied center package case. thermocouple should positioned that thermocouple junction rests package. small amount epoxy placed over thermocouple junction over about wire extending from junction. thermocouple wire placed flat against package case avoid measurement errors caused cooling effects thermocouple wire.
Power Supply Power Sequencing
This section provides design considerations MPC853T power supply. MPC853T core voltage (VDDL) voltage (VDDSYN), which both operate lower voltages than voltage VDDH. section MPC853T supplied with across VDDH (GND). signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO tolerant. inputs cannot more than greater than VDDH. addition, tolerant pins exceed remaining input pins cannot exceed 3.465 This restriction applies power up/down normal operation. consequence multiple power supplies that when power initially applied, voltage rails ramp different rates. rates depend nature power supply, type load each power supply, manner which different voltages derived. following restrictions apply: VDDL must exceed during power power down. VDDL must exceed VDDH must exceed 3.465
These cautions necessary long-term reliability part. they violated, electrostatic discharge (ESD) protection diodes forward-biased, excessive current flow through these diodes. system power supply design does control voltage sequencing, circuit shown Figure added meet these requirements. MUR420 Schottky diodes control maximum potential difference between external core power supplies power 1N5820 diodes regulate maximum potential difference power down.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mandatory Reset Configurations
VDDH MUR420
VDDL
1N5820
Figure Example Voltage Sequencing Circuit
Mandatory Reset Configurations
MPC853T requires mandatory configuration during reset. hardware reset configuration word (HRCW) enabled, HRCW[DBGC] value needs binary HRCW, SIUMCR[DBGC] should programmed with same value boot code after reset. This done asserting RSTCONF during HRESET assertion. HRCW disabled, SIUMCR[DBGC] should programmed with binary boot code after reset negating RSTCONF during HRESET assertion. MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, PCDIR registers need configured with mandatory value Table boot code after reset negated.
Table Mandatory Reset Configuration MPC853T
Register/Configuration HRCW (Hardware reset configuration word) SIUMCR (SIU module configuration register) MBMR (Machine mode register) PAPAR (Port assignment register) PADIR (Port data direction register) PBPAR (Port assignment register) HRCW[DBGC] Field Value (binary) 0bx1
SIUMCR[DBGC]
0bx1
MBMR[GPLB4DIS}
PAPAR[4:7] PAPAR[12:15] PADIR[4:7] PADIR[12:15] PBPAR[14] PBPAR[16:23] PBPAR[26:27] PBDIR[14] PBDIR[16:23] PBDIR[26:27]
PBDIR (Port Data direction register)
MPC853T Hardware Specification, Rev.
Layout Practices
Table Mandatory Reset Configuration MPC853T (continued)
Register/Configuration PCPAR (Port assignment register) PCDIR (Port data direction register) PCPAR[8:11] PCDIR[14] PCDIR[8:11] PCDIR[14] Field Value (binary)
Layout Practices
Each MPC853T should provided with low-impedance path board's supply. Each should likewise provided with low-impedance path ground. power supply pins drive distinct groups logic chip. power supply should bypassed ground using least four 0.1-µF bypass capacitors located close possible four sides package. Each board designed should characterized, additional appropriate decoupling capacitors should used required. Capacitor leads associated printed circuit traces connecting chip should kept less than half inch capacitor lead. minimum, four-layer board employing inner layers planes should used. output pins MPC853T have fast rise fall times. Printed circuit (PC) trace interconnection length should minimized order minimize undershoot reflections caused these fast output switching times. This recommendation particularly applies address data busses. Maximum trace lengths inches recommended. Capacitance calculations should consider device loads, well parasitic capacitances caused traces. Attention proper layout bypassing becomes especially critical systems with higher capacitive loads because these loads create higher transient currents circuits. Pull unused inputs signals that will inputs during reset. Special care should taken minimize noise levels supply pins. more information, please refer Section 14.4.3, "Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1)" MPC866 PowerQUICC Family User's Manual.
Signal Timing
maximum speed supported MPC853T MHz. Table shows frequency ranges standard part frequencies mode.
Table Frequency Ranges Standard Part Frequencies (1:1 Mode)
Part Frequency Core Frequency Frequency 66.67 66.67
Table shows frequency ranges standard part frequencies mode.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table Frequency Ranges Standard Part Frequencies (2:1 Mode)
Part Frequency Core Frequency Frequency 66.67 33.33
Table provides operation timing MPC853T MHz. timing MPC853T shown assumes 50-pF load maximum delays 0-pF load minimum delays. CLKOUT assumes 100-pF load maximum delay.
Table Operation Timings
Characteristic period (CLKOUT), Table EXTCLK CLKOUT phase skew CLKOUT integer multiple EXTCLK, then rising edge EXTCLK aligned with rising edge CLKOUT. non-integer multiple EXTCLK, this synchronization lost, rising edges EXTCLK CLKOUT have continuously varying phase skew. CLKOUT frequency jitter peak-to-peak Frequency jitter EXTCLK CLKOUT phase jitter peak-to-peak OSCLK CLKOUT phase jitter peak-to-peak OSCLK CLKOUT pulse width (MIN CLKOUT pulse width high (MIN CLKOUT rise time CLKOUT fall time CLKOUT A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN 0.25 CLKOUT TSIZ(0:1), REG, RSV, BDIP, output hold (MIN 0.25 Unit
0.50
0.50
0.50
0.50
12.1 12.1 7.60
18.2 18.2 4.00 4.00
10.0 10.0 6.30
15.0 15.0 4.00 4.00
5.00
12.0 12.0 4.00 4.00
3.80
4.00 4.00
7.60
6.30
5.00
3.80
MPC853T Hardware Specification, Rev.
Signal Timing
Table Operation Timings (continued)
Characteristic CLKOUT FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), output hold (MIN 0.25 CLKOUT A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31), DP(0:3) valid (MAX 0.25 6.3) CLKOUT TSIZ(0:1), REG, RSV, BDIP, valid (MAX 0.25 6.3) CLKOUT VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), valid (MAX 0.25 6.3) CLKOUT A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, High-Z (MAX 0.25 6.3) CLKOUT assertion (MAX 0.25 6.0) 7.60 6.30 5.00 3.80 Unit
13.80
12.50
11.30
10.00
13.80 13.80
12.50 12.50
11.30 11.30
10.00 10.00
7.60
13.80
6.30
12.50
5.00
11.30
3.80
10.00
7.60 2.50
13.60 9.30
6.30 2.50
12.30 9.30
5.00 2.50
11.00 9.30
3.80 2.50
9.80 9.80
B11a CLKOUT assertion (when driven memory controller PCMCIA interface) (MAX 0.00 9.30 CLKOUT negation (MAX 0.25 4.8)
7.60 2.50
12.30 9.00
6.30 2.50
11.00 9.00
5.00 2.50
9.80 9.00
3.80 2.50
8.50 9.00
B12a CLKOUT negation (when driven memory controller PCMCIA interface) (MAX 0.00 9.00) CLKOUT High-Z (MIN 0.25
7.60 2.50
21.60 15.00
6.30 2.50
20.30 15.00
5.00 2.50
19.00 15.00
3.80 2.50
14.00 15.00
B13a CLKOUT High-Z (when driven memory controller PCMCIA interface) (MIN 0.00 2.5) CLKOUT assertion (MAX 0.00 9.00) CLKOUT High-Z (MIN 0.00 2.50) valid CLKOUT (setup time) (MIN 0.00 6.00)
2.50 2.50 6.00 4.50 4.00
9.00 15.00
2.50 2.50 6.00 4.50 4.00
9.00 15.00
2.50 2.50 6.00 4.50 4.00
9.00 15.00
2.50 2.50 6.00 4.50 4.00
9.00 15.00
B16a TEA, RETRY, valid CLKOUT (setup time) (MIN 0.00 4.5) B16b valid CLKOUT (setup time) (4MIN 0.00 0.00)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table Operation Timings (continued)
Characteristic CLKOUT TEA, valid (hold time) (MIN 0.00 1.00 1.00 1.00 1.00 2.00 Unit
B17a CLKOUT RETRY, valid (hold time) (MIN 0.00 2.00) D(0:31), DP(0:3) valid CLKOUT rising edge (setup time) (MIN 0.00 6.00) CLKOUT rising edge D(0:31), DP(0:3) valid (hold time) (MIN 0.00 1.00 D(0:31), DP(0:3) valid CLKOUT falling edge (setup time) 7(MIN 0.00 4.00) CLKOUT falling edge D(0:31), DP(0:3) valid (hold Time) (MIN 0.00 2.00) CLKOUT rising edge asserted GPCM (MAX 0.25 6.3)
2.00 6.00
2.00 6.00
2.00 6.00
2.00 6.00
1.00
1.00
1.00
2.00
4.00
4.00
4.00
4.00
2.00
2.00
2.00
2.00
7.60
13.80
6.30
12.50
5.00
11.30
3.80
10.00
B22a CLKOUT falling edge asserted GPCM TRLX (MAX 0.00 8.00) B22b CLKOUT falling edge asserted GPCM TRLX EBDF (MAX 0.25 6.3) B22c CLKOUT falling edge asserted GPCM TRLX EBDF (MAX 0.375 6.6) CLKOUT rising edge negated GPCM read access, GPCM write access TRLX CSNT (MAX 0.00 8.00) A(0:31) BADDR(28:30) asserted GPCM TRLX (MIN 0.25 2.00)
8.00
8.00
8.00
8.00
7.60
13.80
6.30
12.50
5.00
11.30
3.80
10.00
10.90 18.00 10.90 16.00
7.00
14.10
5.20
12.30
2.00
8.00
2.00
8.00
2.00
8.00
2.00
8.00
5.60
4.30
3.00
1.80
B24a A(0:31) BADDR(28:30) asserted GPCM TRLX (MIN 0.50 2.00) CLKOUT rising edge WE(0:3)/BS_B[0:3] asserted (MAX 0.00 9.00)
13.20
10.50
8.00
5.60
9.00
9.00
9.00
9.00
MPC853T Hardware Specification, Rev.
Signal Timing
Table Operation Timings (continued)
Characteristic CLKOUT rising edge negated (MAX 0.00 9.00) A(0:31) BADDR(28:30) asserted GPCM TRLX (MIN 1.25 2.00) 2.00 35.90 9.00 2.00 29.30 9.00 2.00 23.00 9.00 2.00 16.90 9.00 Unit
B27a A(0:31) BADDR(28:30) asserted GPCM TRLX (MIN 1.50 2.00) CLKOUT rising edge WE(0:3)/BS_B[0:3] negated GPCM write access CSNT (MAX 0.00 9.00)
43.50
35.50
28.00
20.70
9.00
9.00
9.00
9.00
B28a CLKOUT falling edge WE(0:3)/BS_B[0:3] negated GPCM write access TRLX CSNT EBDF (MAX 0.25 6.80) B28b CLKOUT falling edge negated GPCM write access TRLX CSNT EBDF (MAX 0.25 6.80)
7.60
14.30
6.30
13.00
5.00
11.80
3.80
10.50
14.30
13.00
11.80
10.50
10.90 18.00 10.90 18.00 B28c CLKOUT falling edge WE(0:3)/BS_B[0:3] negated GPCM write access TRLX CSNT write access TRLX CSNT EBDF (MAX 0.375 6.6) B28d CLKOUT falling edge negated GPCM write access TRLX CSNT EBDF (MAX 0.375 6.6) WE(0:3)/BS_B[0:3] negated D(0:31), DP(0:3) High-Z GPCM write access, CSNT EBDF (MIN 0.25 2.00) 18.00 18.00
7.00
14.30
5.20
12.30
14.30
12.30
5.60
4.30
3.00
1.80
B29a WE(0:3)/BS_B[0:3] negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 0.50 2.00) B29b negated D(0:31), DP(0:3), High-Z GPCM write access, TRLX CSNT (MIN 0.25 2.00)
13.20
10.50
8.00
5.60
5.60
4.30
3.00
1.80
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table Operation Timings (continued)
Characteristic B29c negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 0.50 2.00) B29d WE(0:3)/BS_B[0:3] negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 1.50 2.00) B29e negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 1.50 2.00) B29f WE(0:3/BS_B[0:3]) negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 0.375 6.30) B29g negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 0.375 6.30) B29h WE(0:3)/BS_B[0:3] negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 0.375 3.30) B29i negated D(0:31), DP(0:3) High-Z GPCM write access, TRLX CSNT EBDF (MIN 0.375 3.30) WE(0:3)/BS_B[0:3] negated A(0:31), BADDR(28:30) invalid GPCM write access (MIN 0.25 2.00) 13.20 10.50 8.00 5.60 Unit
43.50
35.50
28.00
20.70
43.50
35.50
28.00
20.70
5.00
3.00
1.10
0.00
5.00
3.00
1.10
0.00
38.40
31.10
24.20
17.50
38.40
31.10
24.20
17.50
5.60
4.30
3.00
1.80
B30a WE(0:3)/BS_B[0:3] negated A(0:31), BADDR(28:30) invalid GPCM, write access, TRLX CSNT negated A(0:31) invalid GPCM write access TRLX CSNT EBDF (MIN 0.50 2.00)
13.20
10.50
8.00
5.60
B30b WE(0:3)/BS_B[0:3] negated A(0:31) 43.50 Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX CSNT negated A(0:31) invalid GPCM write access TRLX CSNT EBDF (MIN 1.50 2.00)
35.50
28.00
20.70
MPC853T Hardware Specification, Rev.
Signal Timing
Table Operation Timings (continued)
Characteristic B30c WE(0:3)/BS_B[0:3] negated A(0:31), BADDR(28:30) invalid GPCM write access, TRLX CSNT negated A(0:31) invalid GPCM write access, TRLX CSNT EBDF (MIN 0.375 3.00) B30d WE(0:3)/BS_B[0:3] negated A(0:31), BADDR(28:30) invalid GPCM write access TRLX CSNT negated A(0:31) invalid GPCM write access TRLX CSNT EBDF CLKOUT falling edge valid, requested control CST4 corresponding word (MAX 0.00 6.00) 8.40 6.40 4.50 2.70 Unit
38.67
31.38
24.50
17.83
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
B31a CLKOUT falling edge valid, requested control CST1 corresponding word (MAX 0.25 6.80) B31b CLKOUT rising edge valid, requested control CST2 corresponding word (MAX 0.00 8.00) B31c CLKOUT rising edge valid, requested control CST3 corresponding word (MAX 0.25 6.30) B31d CLKOUT falling edge valid, requested control CST1 corresponding word EBDF (MAX 0.375 6.6) CLKOUT falling edge valid, requested control BST4 corresponding word (MAX 0.00 6.00)
7.60
14.30
6.30
13.00
5.00
11.80
3.80
10.50
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
7.60
13.80
6.30
12.50
5.00
11.30
3.80
10.00
13.30 18.00 11.30 16.00
9.40
14.10
7.60
12.30
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
B32a CLKOUT falling edge valid, requested control BST1 corresponding word UPM, EBDF (MAX 0.25 6.80) B32b CLKOUT rising edge valid, requested control BST2 corresponding word (MAX 0.00 8.00)
7.60
14.30
6.30
13.00
5.00
11.80
3.80
10.50
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table Operation Timings (continued)
Characteristic B32c CLKOUT rising edge valid, requested control BST3 corresponding word (MAX 0.25 6.80) B32d CLKOUT falling edge valid, requested control BST1 corresponding word UPM, EBDF (MAX 0.375 6.60) CLKOUT falling edge valid, requested control GxT4 corresponding word (MAX 0.00 6.00) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 Unit
13.30 18.00 11.30 16.00
9.40
14.10
7.60
12.30
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
B33a CLKOUT rising edge valid, requested control GxT3 corresponding word (MAX 0.25 6.80) A(0:31), BADDR(28:30), D(0:31) valid, requested control CST4 corresponding word (MIN 0.25 2.00)
7.60
14.30
6.30
13.00
5.00
11.80
3.80
10.50
5.60
4.30
3.00
1.80
B34a A(0:31), BADDR(28:30), D(0:31) valid, requested control CST1 corresponding word (MIN 0.50 2.00) B34b A(0:31), BADDR(28:30), D(0:31) valid, requested CST2 corresponding word (MIN 0.75 2.00) A(0:31), BADDR(28:30) valid, requested control BST4 corresponding word (MIN 0.25 2.00)
13.20
10.50
8.00
5.60
20.70
16.70
13.00
9.40
5.60
4.30
3.00
1.80
B35a A(0:31), BADDR(28:30), D(0:31) valid, requested BST1 corresponding word (MIN 0.50 2.00) B35b A(0:31), BADDR(28:30), D(0:31) valid, requested control BST2 corresponding word (MIN 0.75 2.00) A(0:31), BADDR(28:30), D(0:31) valid, requested control GxT4 corresponding word (MIN 0.25 2.00)
13.20
10.50
8.00
5.60
20.70
16.70
13.00
9.40
5.60
4.30
3.00
1.80
MPC853T Hardware Specification, Rev.
Signal Timing
Table Operation Timings (continued)
Characteristic UPWAIT valid CLKOUT falling edge (MIN 0.00 6.00) CLKOUT falling edge UPWAIT valid (MIN 0.00 1.00) valid CLKOUT rising edge (MIN 0.00 7.00) A(0:31), TSIZ(0:1), RD/WR, BURST, valid CLKOUT rising edge (MIN 0.00 7.00) valid CLKOUT rising edge (setup time) (MIN 0.00 7.00) CLKOUT rising edge valid (hold time) (MIN 0.00 2.00) negation memory controller signals negation (MAX TBD) 6.00 1.00 7.00 7.00 6.00 1.00 7.00 7.00 6.00 1.00 7.00 7.00 6.00 1.00 7.00 7.00 Unit
7.00 2.00
7.00 2.00
7.00 2.00
7.00 2.00
rate change frequency EXTAL slow (that does jump between minimum maximum values cycle) frequency jitter fast (that does stay extreme value long time) maximum allowed jitter EXTAL part speeds above MHz, 9.80 B11a. timing required input relevant when MPC853T selected work with internal arbiter. timing input relevant when MPC853T selected work with external arbiter. part speeds above MHz, B17. D(0:31) DP(0:3) input timings refer rising edge CLKOUT which input signal asserted. part speeds above MHz, B19. D(0:31) DP(0:3) input timings refer falling edge CLKOUT. This timing valid only read accesses controlled chip-selects under control memory controller data beats where DLT3 words. (This only case where data latched falling edge CLKOUT. timing refers when WE(0:3) when CSNT signal UPWAIT considered asynchronous CLKOUT synchronized internally. timings specified specified enable freeze output signals described Figure signal considered asynchronous CLKOUT. timing specified order allow behavior specified Figure
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Figure provides control timing diagram.
Outputs Outputs Inputs Inputs
CLKOUT
Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification
Figure Control Timing
Figure provides timing external clock.
CLKOUT
Figure External Clock Timing
MPC853T Hardware Specification, Rev.
Signal Timing
Figure provides timing synchronous output signals.
CLKOUT Output Signals Output Signals Output Signals
Figure Synchronous Output Signals Timing
Figure provides timing synchronous active pull-up open-drain output signals.
CLKOUT
B13a B11a B12a
Figure Synchronous Active Pull-Up Resistor Open-Drain Outputs Signals Timing
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Figure provides timing synchronous input signals.
CLKOUT
B16a B17a
TEA, RETRY,
B16b
Figure Synchronous Input Signals Timing
Figure provides normal case timing input data. also applies normal read accesses under control memory controller.
CLKOUT D[0:31], DP[0:3]
Figure Input Data Timing Normal Case
MPC853T Hardware Specification, Rev.
Signal Timing
Figure provides timing input data controlled data beats where DLT3 words. (This only case where data latched falling edge CLKOUT.)
CLKOUT
D[0:31], DP[0:3]
Figure Input Data Timing When Controlled Memory Controller DLT3
Figure through Figure provide timing external read controlled various GPCM factors.
CLKOUT A[0:31] WE[0:3] D[0:31], DP[0:3]
Figure External Read Timing (GPCM Controlled-ACS
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
CLKOUT A[0:31]
B22a
D[0:31], DP[0:3]
Figure External Read Timing (GPCM Controlled-TRLX
CLKOUT A[0:31]
B22c B22b
B24a
D[0:31], DP[0:3]
Figure External Read Timing (GPCM Controlled-TRLX
MPC853T Hardware Specification, Rev.
Signal Timing
CLKOUT A[0:31]
B22a
B27a B22b B22c
D[0:31], DP[0:3]
Figure External Read Timing (GPCM Controlled-TRLX
Figure through Figure provide timing external write controlled various GPCM factors.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
CLKOUT A[0:31] WE[0:3] D[0:31], DP[0:3]
B29b
Figure External Write Timing (GPCM Controlled-TRLX CSNT
MPC853T Hardware Specification, Rev.
Signal Timing
CLKOUT A[0:31] WE[0:3] D[0:31], DP[0:3]
B28a B28c B29a B29f B29c B29g B28b B28d B30a B30c
Figure External Write Timing (GPCM Controlled-TRLX CSNT
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
CLKOUT A[0:31] WE[0:3] D[0:31], DP[0:3]
B28a B28c B29d B29h B29e B29i B28b B28d B30b B30d
B29b
Figure External Write Timing (GPCM Controlled-TRLX CSNT
MPC853T Hardware Specification, Rev.
Signal Timing
Figure provides timing external controlled UPM.
CLKOUT A[0:31]
B31a B31d B31c B31b
B34a B34b B32a B32d
B32c B32b
BS_A[0:3]
B35a B35b B33a
GPL_A[0:5], GPL_B[0:5]
Figure External Timing (UPM-Controlled Signals)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Figure provides timing asynchronous asserted UPWAIT signal controlled UPM.
CLKOUT UPWAIT
BS_A[0:3]
GPL_A[0:5], GPL_B[0:5]
Figure Asynchronous UPWAIT Asserted Detection UPM-Handled Cycles Timing
Figure provides timing asynchronous negated UPWAIT signal controlled UPM.
CLKOUT UPWAIT
BS_A[0:3]
GPL_A[0:5], GPL_B[0:5]
Figure Asynchronous UPWAIT Negated Detection UPM-Handled Cycles Timing
MPC853T Hardware Specification, Rev.
Signal Timing
Figure provides timing synchronous external master access controlled GPCM.
CLKOUT A[0:31], TSIZ[0:1], R/W, BURST
Figure Synchronous External Master Access Timing (GPCM Handled-ACS
Figure provides timing asynchronous external master memory access controlled GPCM.
CLKOUT A[0:31], TSIZ[0:1],
Figure Asynchronous External Master Memory Access Timing (GPCM Controlled-ACS
Figure provides timing asynchronous external master control signals negation.
CSx, WE[0:3], GPLx, BS[0:3]
Figure Asynchronous External Master-Control Signals Negation Timing
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table provides interrupt timing MPC853T.
Table Interrupt Timing
Frequencies Characteristic
Unit
IRQx valid CLKOUT rising edge (setup time) IRQx hold time after CLKOUT IRQx pulse width IRQx pulse width high IRQx edge-to-edge time
6.00 2.00 3.00 3.00 TCLOCKOUT
timings describe testing conditions under which lines tested when being defined level sensitive. lines synchronized internally have asserted negated with reference CLKOUT. timings I41, I42, specified allow correct function lines detection circuitry have direct relation with total system interrupt latency that MPC853T able support.
Figure provides interrupt detection timing external level-sensitive lines.
CLKOUT IRQx
Figure Interrupt Detection Timing External Level-Sensitive Lines
Figure provides interrupt detection timing external edge-sensitive lines.
CLKOUT
IRQx
Figure Interrupt Detection Timing External Edge-Sensitive Lines
MPC853T Hardware Specification, Rev.
Signal Timing
Table shows PCMCIA timing MPC853T.
Table PCMCIA Timing
Characteristic A(0:31), valid PCMCIA strobe asserted (MIN 0.75 2.00) A(0:31), valid negation1 (MIN 1.00 2.00) CLKOUT valid (MAX 0.25 8.00) CLKOUT invalid (MIN 0.25 1.00) CLKOUT CE1, asserted (MAX 0.25 8.00) CLKOUT CE1, negated (MAX 0.25 8.00) CLKOUT PCOE, IORD, PCWE, IOWR assert time (MAX 0.00 11.00) CLKOUT PCOE, IORD, PCWE, IOWR negate time (MAX 0.00 11.00) CLKOUT assert time (MAX 0.25 6.30) CLKOUT negate time (MAX 0.25 8.00) PCWE, IOWR negated D(0:31) invalid1 (MIN 0.25 2.00) WAITA WAITB valid CLKOUT rising edge1 (MIN 0.00 8.00) CLKOUT rising edge WAITA WAITB invalid1 (MIN 0.00 2.00) 20.70 28.30 7.60 8.60 7.60 7.60 15.60 15.60 15.60 11.00 16.70 23.00 6.30 7.30 6.30 6.30 14.30 14.30 14.30 11.00 13.00 18.00 5.00 6.00 5.00 5.00 13.00 13.00 13.00 11.00 9.40 13.20 3.80 4.80 3.80 3.80 11.80 11.80 11.80 11.00 Unit
2.00
11.00
2.00
11.00
2.00
11.00
2.00
11.00
7.60 5.60 8.00 2.00
13.80 15.60
6.30 4.30 8.00 2.00
12.50 14.30
5.00 3.00 8.00 2.00
11.30 13.00
3.80 1.80 8.00 2.00
10.00 11.80
PSST Otherwise PSST times cycle time. PSHT Otherwise PSHT times cycle time. These synchronous timings define when WAITA signals detected order freeze relieve) PCMCIA current cycle. WAITA assertion will effective only detected cycles before timer expiration. Chapter "PCMCIA Interface," MPC866 PowerQUICC Family User's Manual.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Figure provides PCMCIA access cycle timing external read.
CLKOUT
A[0:31] CE1/CE2 PCOE, IORD D[0:31]
Figure PCMCIA Access Cycles Timing External Read
MPC853T Hardware Specification, Rev.
Signal Timing
Figure provides PCMCIA access cycle timing external write.
CLKOUT
A[0:31] CE1/CE2 PCWE, IOWR D[0:31]
Figure PCMCIA Access Cycles Timing External Write
Figure provides PCMCIA WAIT signals detection timing.
CLKOUT WAITA
Figure PCMCIA WAIT Signals Detection Timing
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table shows PCMCIA port timing MPC853T.
Table PCMCIA Port Timing
Characteristic
21.70 5.00 1.00 19.00
18.00 5.00 1.00 19.00
Unit 14.40 5.00 1.00 19.00
19.00
CLKOUT valid (MAX 0.00 19.00) HRESET negated drive 1(MIN 0.75 3.00) IP_Xx valid CLKOUT rising edge (MIN 0.00 5.00) CLKOUT rising edge IP_Xx invalid (MIN 0.00 1.00)
25.70 5.00 1.00
only.
Figure provides PCMCIA output port timing MPC853T.
CLKOUT Output Signals
HRESET OP2,
Figure PCMCIA Output Port Timing
Figure provides PCMCIA port timing MPC853T.
CLKOUT Input Signals
Figure PCMCIA Input Port Timing
MPC853T Hardware Specification, Rev.
Signal Timing
Table shows debug port timing MPC853T.
Table Debug Port Timing
Frequencies Characteristic DSCK cycle time DSCK clock pulse width DSCK rise fall times DSDI input data setup time DSDI data hold time DSCK DSDO data valid DSCK DSDO invalid TCLOCKOUT 1.25 TCLOCKOUT 0.00 8.00 5.00 0.00 0.00 15.00 2.00 3.00 Unit
Figure provides input timing debug port clock.
DSCK
Figure Debug Port Clock Input Timing
Figure provides timing debug port.
DSCK DSDI DSDO
Figure Debug Port Timings
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Signal Timing
Table shows reset timing MPC853T.
Table Reset Timing
Characteristic CLKOUT HRESET high impedance (MAX 0.00 20.00) CLKOUT SRESET high impedance (MAX 0.00 20.00) RSTCONF pulse width (MIN 17.00 Configuration data HRESET rising edge setup time (MIN 15.00 50.00) 20.00 20.00 20.00 20.00 Unit
20.00
20.00
20.00
20.00
515.20 504.50
425.00 425.00
340.00 350.00
257.60 277.30
Configuration data RSTCONF 350.00 rising edge setup time (MIN 0.00 350.00) Configuration data hold time after RSTCONF negation (MIN 0.00 0.00) Configuration data hold time after HRESET negation (MIN 0.00 0.00) HRESET RSTCONF asserted data drive (MAX 0.00 25.00) RSTCONF negated data high impedance (MAX 0.00 25.00) CLKOUT last rising edge before chip three-states HRESET data high impedance (MAX 0.00 25.00) DSDI, DSCK setup (MIN 3.00 DSDI, DSCK hold time (MIN 0.00 0.00) SRESET negated CLKOUT rising edge DSDI DSCK sample (MIN 8.00 0.00
350.00
350.00
350.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
90.90 0.00 242.40
75.00 0.00 200.00
60.00 0.00 160.00
45.50 0.00 121.20
MPC853T Hardware Specification, Rev.
Signal Timing
Figure shows reset timing data configuration.
HRESET RSTCONF D[0:31] (IN)
Figure Reset Timing-Configuration from Data
Figure provides reset timing data weak drive during configuration.
CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak)
Figure Reset Timing-Data Weak Drive During Configuration
MPC853T Hardware Specification, Rev. Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
Figure provides reset timing debug port configuration.
CLKOUT SRESET DSCK, DSDI
Figure Reset Timing-Debug Port Configuration
IEEE 1149.1 Electrical Specifications
Table provides JTAG timings MPC853T shown Figure Figure
Table JTAG Timing
Frequencies Characteristic cycle time clock pulse width measured rise fall times TMS, data setup time TMS, data hold time data valid data invalid high impedance TRST assert time TRST setup time falling edge output valid falling edge output valid high impedance falling edge output high impedance Boundary scan input valid rising edge rising edge boundary scan input invalid 100.00 40.00 0.00 5.00 25.00 0.00 100.00 40.00 50.00 50.00 10.00 27.00 20.00 50.00 50.00 50.00 Unit
MPC853T Hardware Specification, Rev.
IEEE 1149.1 Electrical Specifications
J83v
Figure JTAG Test Clock Input Timing
TMS,
Figure JTAG Test Access Port Timing Diagram
TRST
Figure JTAG TRST Timing Diagram
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
Output Signals Output Signals Output Signals
Figure Boundary Scan (JTAG) Timing Diagram
Electrical Characteristics
This section provides electrical specifications communications processor module (CPM) MPC853T.
13.1 Port Interrupt Electrical Specifications
Table provides timings port interrupts.
Table Port Interrupt Timing
33.34 Characteristic Port interrupt pulse width (edge-triggered mode) Port interrupt minimum time between active edges Unit
Figure shows port interrupt detection timing.
Port (Input)
Figure Port Interrupt Detection Timing
MPC853T Hardware Specification, Rev.
Electrical Characteristics
13.2 IDMA Controller Electrical Specifications
Table provides IDMA controller timings shown Figure Figure
Table IDMA Controller Timing
Frequencies Characteristic
Unit
DREQ setup time clock high DREQ hold time from clock high
SDACK assertion delay from clock high SDACK negation delay from clock SDACK negation delay from SDACK negation delay from clock high assertion falling edge clock setup time (applies external
Applies high-to-low mode (EDM=1)
CLKO (Output) DREQ (Input)
Figure IDMA External Requests Timing Diagram
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
CLKO (Output)
(Output)
(Output) DATA (Input)
SDACK
Figure SDACK Timing Diagram-Peripheral Write, Externally-Generated
CLKO (Output)
(Output)
(Output) DATA
(Output)
SDACK
Figure SDACK Timing Diagram-Peripheral Write, Internally-Generated
MPC853T Hardware Specification, Rev.
Electrical Characteristics
CLKO (Output)
(Output)
(Output) DATA
(Output)
SDACK
Figure SDACK Timing Diagram-Peripheral Read, Internally-Generated
13.3 Baud-Rate Generator Electrical Specifications
Table provides baud-rate generator timings shown Figure
Table Baud Rate Generator Timing
Frequencies Characteristic BRGO rise fall time BRGO duty cycle BRGO cycle Unit
BRGOX
Figure Baud Rate Generator Timing Diagram
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
13.4 Timer Electrical Specifications
Table provides general-purpose timer timings shown Figure
Table Timer Timing
Frequencies Characteristic TIN/TGATE rise fall time TIN/TGATE time TIN/TGATE high time TIN/TGATE cycle time CLKO TOUT valid Unit
CLKO TIN/TGATE (Input) TOUT (Output)
Figure General-Purpose Timers Timing Diagram
13.5 Serial Interface Electrical Specifications
Table provides serial interface (SI) timings shown Figure Figure
Table Timing
Frequencies Characteristic L1RCLKB, L1TCLKB frequency (DSC L1RCLKB, L1TCLKB width (DSC L1RCLKB, L1TCLKB width high (DSC L1TXDB, L1ST1 L1ST2, L1RQ, L1CLKO rise/fall time L1RSYNCB, L1TSYNCB valid L1CLKB edge (SYNC setup time) L1CLKB edge L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 20.00 35.00 SYNCCLK/2 15.00 Unit
MPC853T Hardware Specification, Rev.
Electrical Characteristics
Table Timing (continued)
Frequencies Characteristic
Unit 15.00 45.00 45.00 45.00 55.00 55.00 42.00 16.00 SYNCCLK/2 30.00 0.00 L1TC
L1RSYNCB, L1TSYNCB rise/fall time L1RXDB valid L1CLKB edge (L1RXDB setup time) L1CLKB edge L1RXDB invalid (L1RXDB hold time) L1CLKB edge L1ST1 L1ST2 valid
17.00 13.00 10.00 10.00 10.00 10.00
L1SYNCB valid L1ST1 L1ST2 valid L1CLKB edge L1ST1 L1ST2 invalid L1CLKB edge L1TXDB valid L1TSYNCB valid L1TXDB valid
10.00 0.00 1.00 42.00 42.00
L1CLKB edge L1TXDB high impedance L1RCLKB, L1TCLKB frequency (DSC L1RCLKB, L1TCLKB width (DSC L1RCLKB, L1TCLKB width high (DSC
L1CLKB edge L1CLKOB valid (DSC L1RQB valid before falling edge L1GRB setup time2 L1GRB hold time L1CLKB edge L1SYNCB valid (FSD 0000, L1TSYNCB
ratio SyncCLK/L1RCLKB must greater than 2.5/1. These specs valid mode only. Where 1/CLKOUT. Thus 25-MHz CLKO1 rate, These strobes first frame become valid after L1CLKB edge L1SYNCB, whichever comes later.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
L1RCLKB (FE=0, CE=0) (Input) L1RCLKB (FE=1, CE=1) (Input) RFSD=1 L1RSYNCB (Input) L1RXDB (Input) L1ST(2-1) (Output) BIT0
Figure Receive Timing Diagram with Normal Clocking (DSC
MPC853T Hardware Specification, Rev.
Electrical Characteristics
L1RCLKB (FE=1, CE=1) (Input) L1RCLKB (FE=0, CE=0) (Input) RFSD=1 L1RSYNCB (Input) L1RXDB (Input) L1ST(2-1) (Output) BIT0
L1CLKOB (Output)
Figure Receive Timing with Double-Speed Clocking (DSC
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
L1TCLKB (FE=0, CE=0) (Input) L1TCLKB (FE=1, CE=1) (Input) TFSD=0 L1TSYNCB (Input) L1TXDB (Output) BIT0 L1ST(2-1) (Output)
Figure Transmit Timing Diagram (DSC
MPC853T Hardware Specification, Rev.
Electrical Characteristics
L1RCLKB (FE=0, CE=0) (Input) L1RCLKB (FE=1, CE=1) (Input) TFSD=0 L1RSYNCB (Input) L1TXDB (Output) BIT0 L1ST(2-1) (Output) L1CLKOB (Output)
Figure Transmit Timing with Double Speed Clocking (DSC
MPC853T Hardware Specification, Rev. Freescale Semiconductor
L1RCLKB (Input)
Electrical Characteristics
L1RSYNCB (Input)
L1TXDB (Output)
Figure Timing
L1RXDB (Input)
MPC853T Hardware Specification, Rev.
L1ST(2-1) (Output)
L1RQB (Output)
L1GRB (Input)
Electrical Characteristics
13.6 NMSI Mode Electrical Specifications
Table provides NMSI external clock timing.
Table NMSI External Clock Timing
Frequencies Characteristic
Unit 15.00 50.00 50.00
RCLK3 TCLK3 width high RCLK3 TCLK3 width RCLK3 TCLK3 rise/fall time TXD3 active delay (from TCLK3 falling edge) RTS3 active/inactive delay (from TCLK3 falling edge) CTS3 setup time TCLK3 rising edge RXD3 setup time RCLK3 rising edge RXD3 hold time from RCLK3 rising edge
1/SYNCCLK 1/SYNCCLK 0.00 0.00 5.00 5.00 5.00 5.00
setup Time RCLK3 rising edge
ratios SyncCLK/RCLK3 SyncCLK/TCLK3 must greater than equal 2.25/1. Also applies hold time when they used external sync signals.
Table provides NMSI internal clock timing.
Table NMSI Internal Clock Timing
Frequencies Characteristic
Unit SYNCCLK/3 30.00 30.00
RCLK3 TCLK3 frequency RCLK3 TCLK3 rise/fall time TXD3 active delay (from TCLK3 falling edge) RTS3 active/inactive delay (from TCLK3 falling edge) CTS3 setup time TCLK3 rising edge RXD3 setup time RCLK3 rising edge RXD3 hold time from RCLK3 rising edge setup time RCLK3 rising edge
0.00 0.00 0.00 40.00 40.00 0.00 40.00
ratios SyncCLK/RCLK3 SyncCLK/TCLK3 must greater than equal 3/1. Also applies hold time when they used external sync signals.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
Figure through Figure show NMSI timings.
RCLK3 RxD3 (Input) (Input)
SYNC Input)
Figure NMSI Receive Timing Diagram
TCLK3 TxD3 (Output) RTS3 (Output)
CTS3 (Input)
CTS3 (SYNC Input)
Figure NMSI Transmit Timing Diagram
MPC853T Hardware Specification, Rev.
Electrical Characteristics
TCLK3 TxD3 (Output)
RTS3 (Output) CTS3 (Echo Input)
Figure HDLC Timing Diagram
13.7 Ethernet Electrical Specifications
Table provides Ethernet timings shown Figure Figure
Table Ethernet Timing
Frequencies Characteristic CLSN width high RCLK3 rise/fall time RCLK3 width RCLK3 clock period RXD3 setup time RXD3 hold time RENA active delay (from RCLK3 rising edge last data bit) RENA width TCLK3 rise/fall time TCLK3 width TCLK3 clock period1 Unit
TXD3 active delay (from TCLK3 rising edge) TXD3 inactive delay (from TCLK3 rising edge) TENA active delay (from TCLK3 rising edge)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
Table Ethernet Timing (continued)
Frequencies Characteristic
Unit
TENA inactive delay (from TCLK3 rising edge) RSTRT active delay (from TCLK3 falling edge) RSTRT inactive delay (from TCLK3 falling edge) REJECT width CLKO1 SDACK asserted CLKO1 SDACK negated
ratios SyncCLK/RCLK3 SyncCLK/TCLK3 must greater than equal 2/1. SDACK asserted whenever SDMA writes incoming frame into memory.
CLSN(CTS1) (Input)
Figure Ethernet Collision Timing Diagram
RCLK3 RxD3 (Input) RENA(CD3) (Input) Last
Figure Ethernet Receive Timing Diagram
MPC853T Hardware Specification, Rev.
Electrical Characteristics
TCLK3 TxD3 (Output) TENA(RTS3) (Input)
RENA(CD3) (Input) (NOTE
NOTES: Transmit clock invert (TCI) GSMR set. RENA negated before TENA RENA asserted during transmit, then buffer descriptor frame transmission.
Figure Ethernet Transmit Timing Diagram
RCLK3
RxD3 (Input)
Start Frame
BIT1
BIT2
RSTRT (Output)
Figure Interface Receive Start Timing Diagram
REJECT
Figure Interface REJECT Timing Diagram
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
13.8 Master Electrical Specifications
Table provides master timings shown Figure Figure
Table Master Timing
Frequencies Characteristic MASTER cycle time MASTER clock (SCK) high time MASTER data setup time (inputs) Master data hold time (inputs) Master data valid (after edge) Master data hold time (outputs) Rise time output Fall time output 1024 tcyc tcyc Unit
SPICLK (CI=0) (Output) SPICLK (CI=1) (Output) SPIMISO (Input) Data SPIMOSI (Output) Data
Figure Master Timing Diagram
MPC853T Hardware Specification, Rev.
Electrical Characteristics
SPICLK (CI=0) (Output) SPICLK (CI=1) (Output) SPIMISO (Input) Data SPIMOSI (Output) Data
Figure Master Timing Diagram
13.9 Slave Electrical Specifications
Table provides slave timings shown Figure Figure
Table Slave Timing
Frequencies Characteristic Slave cycle time Slave enable lead time Slave enable time Slave clock (SPICLK) high time Slave sequential transfer delay (does require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time tcyc tcyc tcyc Unit
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
SPISEL (Input) SPICLK (CI=0) (Input) SPICLK (CI=1) (Input) SPIMISO (Output) SPIMOSI (Input) Data Data Undef
Figure Slave Timing Diagram
MPC853T Hardware Specification, Rev.
Electrical Characteristics
SPISEL (Input) SPICLK (CI=0) (Input) SPICLK (CI=1) (Input) SPIMISO (Output) Undef SPIMOSI (Input) Data Data
Figure Slave Timing Diagram
Electrical Characteristics
This section provides electrical specifications Fast Ethernet controller (FEC). Note that timing specifications signals independent system clock frequency (part speed designation). Also, signals signal levels compatible with devices operating either
14.1 Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK)
receiver functions correctly MII_RX_CLK maximum frequency 25MHz There minimum frequency requirement. addition, processor clock frequency must exceed MII_RX_CLK frequency Table provides information receive signal timing.
Table Receive Signal Timing
Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ER MII_RX_CLK setup MII_RX_CLK MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width Unit MII_RX_CLK period MII_RX_CLK period
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
Figure shows receive signal timing.
MII_RX_CLK (input) MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER
Figure Receive Signal Timing Diagram
14.2 Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK)
transmitter functions correctly MII_TX_CLK maximum frequency There minimum frequency requirement. addition, processor clock frequency must exceed MII_TX_CLK frequency Table provides information transmit signal timing.
Table Transmit Signal Timing
Characteristic MII_TX_CLK MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid MII_TX_CLK pulse width high MII_TX_CLK pulse width MII_TX_CLK period MII_TX_CLK period Unit
MPC853T Hardware Specification, Rev.
Electrical Characteristics
Figure shows transmit signal timing diagram.
MII_TX_CLK (input) MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER
Figure Transmit Signal Timing Diagram
14.3 Async Inputs Signal Timing (MII_CRS, MII_COL)
Table provides information async inputs signal timing.
Table Async Inputs Signal Timing
Characteristic MII_CRS, MII_COL minimum pulse width Unit MII_TX_CLK period
Figure shows asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
Figure Async Inputs Timing Diagram
14.4 Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table provides information serial management channel signal timing. functions correctly with maximum frequency excess MHz. exact upper bound under investigation.
Table Serial Management Channel Timing
Characteristic MII_MDC falling edge MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge MII_MDIO output valid (max prop delay) MII_MDIO (input) MII_MDC rising edge setup Unit
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Electrical Characteristics
Table Serial Management Channel Timing (continued)
Characteristic MII_MDIO (input) MII_MDC rising edge hold MII_MDC pulse width high MII_MDC pulse width Unit MII_MDC period MII_MDC period
Figure shows serial management channel timing diagram.
MM15 MII_MDC (output)
MII_MDIO (output)
MII_MDIO (input)
Figure Serial Management Channel Timing Diagram
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Mechanical Data Ordering Information
Table identifies packages operating frequencies orderable MPC853T.
Table MPC853T Package/Frequency Orderable
Package Type Plastic ball grid array suffix) Temperature (Tj) 95°C Frequency (MHz) Order Number MPC853TVR50 MPC853TZT50 MPC853TVR66 MPC853TZT66 MPC853TVR80 MPC853TZT80 MPC853TVR100 MPC853TZT100
Plastic ball grid array (CVR suffix)
-40°C 100°C
15.1 Assignments
following sections give pinout listing JEDEC Compliant non-JEDEC versions PBGA package.
15.1.1 JEDEC Compliant Pinout
Figure shows JEDEC pinout PBGA package viewed from surface. additional information, MPC866 PowerQUICC Family User's Manual.
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
NOTE: This view device.
GPL_A2 BS_A0 VDDL CE2_A GPL_A3 MII_CRS BS_A3 VDDL GPL_A4 GPL_A0 BS_A2 PC15 BDIP BS_A1 PB29 VDDL GPL_A5 CE_1A TSIZ1 TSIZ0 PB31 PC13 PC12 PA11 MII_COL PB30 TRST VFLS_1 BURST PB28 VDDL MDIO ALE_A DSCK VFLS_0 PB25 PA10 PB24 BADDR30 HRESET RSTCONF VDDH PD13 BADDR29 BADDR28 VDDL PB15 EXTAL VDDL SRESET IP_A3 IP_A1 IP_A6 IRQ1 PD15 VDDL XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT IRQ7 PD12 PD14 PORST VDDSYN VSSSYN1 IRQ0 PD11 VDDL IP_A7 IP_A0 IP_A2 IP_A4 VDDL PD10 MII_TXEN
Figure Pinout PBGA Package JEDEC Standard
Table contains list MPC853T input output signals shows multiplexing assignments.
Table Assignments JEDEC Standard
Name A[0:31] Number Type
B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12, Bidirectional B12, A12, D11, C11, A11, D10, C10, A10, Three-state (3.3V only) B11, B10, Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only)
TSIZ0 TSIZ1 RD/WR
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Table Assignments JEDEC Standard (continued)
Name BURST BDIP GPL_B5 IRQ2 IRQ4 RETRY SPKROUT IRQ3 D[0:31] Number Type Bidirectional Three-state (3.3V only) Output Bidirectional Active Pull-up (3.3V only) Bidirectional Active Pull-up (3.3V only) Open-drain Bidirectional Active Pull-up (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only)
Input (3.3V only)
Bidirectional R13, T11, R10, T10, T12, T13, M10, N10, P10, P12, R12, N11, P11, R11, Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional (3.3V only) Bidirectional (3.3V only) Bidirectional Active Pull-up (3.3V only) Bidirectional (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only)
IRQ3 IRQ4 IRQ5 IRQ6 IRQ6 IRQ0 IRQ1 M_TX_CLK IRQ7
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments JEDEC Standard (continued)
Name CS[0:5] BS_B0 IORD BS_B1 IOWR BS_B2 PCOE BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2-3] UPWAITA GPL_A4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A Number Output Output Output Output Type
Output
Output
Output
Output Output Output
Output
Bidirectional (3.3V only) Output Input (3.3V only) Input (3.3V only) Open-drain Open-drain Analog Output Analog Input (1.8V only) Output Input (1.8V only) Output Output Output
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Table Assignments JEDEC Standard (continued)
Name WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK IWP[0:1] VFLS[0:1] MODCK1 MODCK2 DSDO BADDR[28:29] BADDR30 PA11 RXD3 L1TXDB PA10 TXD3 L1RXDB RXD4 TXD4 Number Type Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional (3.3V only) Bidirectional (3.3V only) Output Bidirectional (3.3V only)
Bidirectional (3.3V only)
Output Output Input (3.3V only) Bidirectional (Optional: Open-drain) tolerant) Bidirectional tolerant)
Bidirectional (Optional: Open-drain) tolerant) Bidirectional tolerant)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments JEDEC Standard (continued)
Name CLK5 BRGO3 TIN3 CLK6 TOUT3 L1RCLKB CLK7 BRGO4 TIN4 CLK8 TOUT4 L1TCLKB PB31 SPISEL PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 PB25 SMTXD1 PB24 SMRXD1 PB15 BRGO3 PC15 DREQ0 PC13 RTS3 L1RQB L1ST3 Number Type Bidirectional tolerant)
Bidirectional tolerant)
Bidirectional tolerant)
Bidirectional tolerant)
Bidirectional (Optional: Open-drain) tolerant) Bidirectional (Optional: Open-drain) tolerant) Bidirectional (Optional: Open-drain) tolerant) Bidirectional (Optional: Open-drain) tolerant) Bidirectional (Optional: Open-drain) tolerant) Bidirectional (Optional: Open-drain) tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant)
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Table Assignments JEDEC Standard (continued)
Name PC12 RTS4 L1ST4 L1TSYNCB CTS3 L1RSYNCB CTS4 SDACK1 PD15 MII-RXD3 PD14 MII-RXD2 PD13 MII-RXD1 PD12 MII-MDC PD11 RXD3 MII-TXERR PD10 TXD3 MII-RXD0 RXD4 MII-TXD0 TXD4 MII_RX_CLK RTS3 MII_RX_ER RTS4 MII_RX_DV Number Type Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments JEDEC Standard (continued)
Name MII-TXD3 MII-TXD2 MII-TXD1 DSDI DSCK TRST DSDO MII_CRS MII_MDIO MII_TXEN MII_COL VSSSYN VSSSYN1 VDDSYN VDDL VDDH Number Type Bidirectional tolerant) Bidirectional tolerant) Bidirectional tolerant) Input tolerant) Input tolerant) Input tolerant) Input tolerant) Output tolerant) Input Bidirectional tolerant) Output tolerant) Input analog analog analog
G10, G11, H10, H11, Power J10, J11, K10, D16, G15, M15, F10, F11, F12, G12, H12, J12, K12, L10, L11, A16, B16, C15, D14, E12, L13, P15, R16, Power Power No-connect
15.1.2 Non-JEDEC Pinout
Figure shows non-JEDEC pinout PBGA package viewed from surface. additional information, MPC866 PowerQUICC Family User's Manual.
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
NOTE: This view device.
GPL_A2 BS_A0 VDDL CE2_A GPL_A3 MII_CRS BS_A3 VDDL GPL_A4 GPL_A0 BS_A2 PC15 BDIP BS_A1 PB29 VDDL GPL_A5 CE_1A TSIZ1 TSIZ0 PB31 PC13 PC12 PA11 MII_COL PB30 TRST VFLS_1 BURST PB28 VDDL MDIO ALE_A DSCK VFLS_0 PB25 PA10 PB24 BADDR30 HRESET RSTCONF VDDH PD13 BADDR29 BADDR28 VDDL PB15 EXTAL VDDL SRESET IP_A3 IP_A1 IP_A6 IRQ1 PD15 VDDL XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT IRQ7 PD12 PD14 PORST VDDSYN VSSSYN1 IRQ0 PD11 VDDL IP_A7 IP_A0 IP_A2 IP_A4 VDDL PD10 MII_TXEN
Figure Pinout PBGA Package-non-JEDEC
Table contains list MPC853T input output signals shows multiplexing assignments.
Table Assignments-Non-JEDEC
Name A[0:31] Number Type
C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, Bidirectional C13, B13, E12, F10, D12, B10, B12, E11, D11, B11, E10, D10, Three-state (3.3 only) C12, C11, C10, Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only)
TSIZ0 TSIZ1 RD/WR
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name BURST BDIP GPL_B5 Number Type Bidirectional Three-state (3.3 only) Output
Bidirectional Active pull-up (3.3 only) Bidirectional Active pull-up (3.3 only) Open drain Bidirectional Active pull-up (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only)
IRQ2 IRQ4 RETRY SPKROUT IRQ3 D[0:31]
Input (3.3 only)
T14, U12, T11, U11, U13, T10, U14, N11, P11, R11, R13, T13, N10, P10, R10, P12, U10, R12, T12,
Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional (3.3 only) Bidirectional (3.3 only) Bidirectional Active pull-up (3.3 only) Bidirectional (3.3 only)
IRQ3 IRQ4 IRQ5 IRQ6
IRQ6
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name IRQ0 IRQ1 IRQ7 M_TX_CLK CS[0:5] BS_B0 IORD BS_B1 IOWR BS_B2 PCOE BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2-3] UPWAITA GPL_A4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL Number Type Input (3.3 only) Input (3.3 only) Input (3.3 only)
Output Output Output Output
Output
Output
Output
Output Output
Output
Output
Bidirectional (3.3 only)
Output Input (3.3 only) Input (3.3 only) Open drain Open drain Analog output Analog Input (3.3 only)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK IWP[0:1] VFLS[0:1] MODCK1 MODCK2 DSDO BADDR[28:29] BADDR30 PA11 RXD3 L1TXDB Number Output Input (3.3 only) Output Output Output Input (3.3 only) Input (3.3 only) Input (3.3 only) Input (3.3 only) Type
Input (3.3 only) Input (3.3 only) Input (3.3 only) Input (3.3 only) Input (3.3 only) Bidirectional Three-state (3.3 only) Bidirectional (3.3 only)
Bidirectional (3.3 only) Output Bidirectional (3.3 only)
Bidirectional (3.3 only)
Output Output
Input (3.3 only) Bidirectional (Optional: open-drain) (5-V tolerant)
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name PA10 TXD3 L1RXDB RXD4 TXD4 CLK5 BRGO3 TIN3 CLK6 TOUT3 L1RCLKB CLK7 BRGO4 TIN4 CLK8 TOUT4 L1TCLKB PB31 SPISEL PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 PB25 SMTXD1 Number Type Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant)
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name PB24 SMRXD1 PB15 BRGO3 PC15 DREQ0 PC13 RTS3 L1RQB L1ST3 PC12 RTS4 L1ST4 L1TSYNCB CTS3 L1RSYNCB CTS4 SDACK1 PD15 MII_RXD3 PD14 MII_RXD2 PD13 MII_RXD1 PD12 MII_MDC PD11 RXD3 MII_TX_ER PD10 TXD3 MII_RXD0 Number Type Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name RXD4 MII_TXD0 TXD4 MII_RX_CLK RTS3 MII_RX_ER RTS4 MII_RX_DV MII_TXD3 MII_TXD2 MII_TXD1 Number Type Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant)
Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Output (5-V tolerant) Input Bidirectional (5-V tolerant) Output (5-V tolerant) Input analog analog analog
DSDI DSCK TRST
DSDO MII_CRS MII_MDIO
MII_TX_EN
MII_COL VSSSYN VSSSYN1 VDDSYN
MPC853T Hardware Specification, Rev. Freescale Semiconductor
Mechanical Data Ordering Information
Table Assignments-Non-JEDEC (continued)
Name VDDL VDDH Number H10, H11, H12, J10, J11, J12, K10, K11, K12, L10, L11, E17, H16, N16, G10, G11, G12, G13, H13, J13, K13, L13, M10, M11, M12, B17, C17, D16, E15, F13, M14, R16, T17, Power Power Power Type
No-connect
MPC853T Hardware Specification, Rev.
Mechanical Data Ordering Information
15.2 Mechanical Dimensions PBGA Package
Figure shows mechanical dimensions PBGA package.
NOTES: DIMENSIONS MILLIMETERS. INTERPRET DIMENSIONS TOLERANCES ASME Y14.5M-1994. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL DATUM DATUM SEATING PLANE, DEFINED SPHERICAL CROWNS SOLDER BALLS.
Note: Solder sphere composition 95.5%Sn 45%Ag 0.5%Cu MPC853TVRXXX
Solder sphere composition 62%Sn 36%Pb 2%Ag MPC853TZTXXX
Figure Mechanical Dimensions Bottom Surface Nomenclature PBGA Package
MPC853T Hardware Specification, Rev. Freescale Semiconductor
References
References
Semiconductor Equipment Materials International East Middlefield Mountain View, 94043 MIL-SPEC EIA/JESD (JEDEC) specifications (Available from Global Engineering Documents) JEDEC Specifications (415) 964-5111
800-854-7179 303-397-7956 http://www.jedec.org
C.E. Triplett Joiner, Experimental Characterization PBGA Within Automotive Engine Controller Module," Proceedings SemiTherm, Diego, 1998, 47-54. Joiner Adams, "Measurement Simulation Junction Board Thermal Resistance Application Thermal Modeling," Proceedings SemiTherm, Diego, 1999, 212-220.
Document Revision History
Table lists significant changes between revisions this hardware specification.
Table Document Revision History
Revision Number Date 10/2003 12/2003 12/2004 Initial release. Added overbars signals (pin WAIT_A (pin Figure page Added sentence Spec about EXTCLK CLKOUT being Alignment Integer Values Added footnote Spec specifying that Broke Section 15.1, "Pin Assignments" into smaller sections JEDEC non-JEDEC pinouts. Changes
MPC853T Hardware Specification, Rev.
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MPC853T Hardware Specification, Rev. Freescale Semiconductor
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MPC853TEC Rev. 12/2004

MPC853T Hardware Specification This hardware specification contai

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