MPC7441 reduced instruction computing (RISC) microprocessor that imple

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MPC7441EC/D Rev. 10/2001 MPC7441 RISC Microprocessor Hardware Specifications
MPC7441 reduced instruction computing (RISC) microprocessor that implements PowerPC instruction architecture. This document describes pertinent electrical characteristics processor, refer physical characteristics MPC7441. functional MPC7450 RISC Microprocessor Family User's Manual. This document contains following topics: Topic Page Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "Comparison with MPC7400" "General Parameters" Section 1.4, IV1.5, "Electrical Thermal Characteristics" Section Section 1.6, "Pin Assignments"
Section 1.7, "Pinout Listings CBGA Package" Section 1.8, "Package Description" Section 1.9, "System Design Information" Section 1.10, "Document Revision History" Section 1.11, "Ordering Information" locate published updates this document, refer website
Overview
MPC7441 third implementation fourth generation (G4) microprocessors from Motorola. MPC7441 implements full PowerPC 32-bit architecture targeted networking computing systems applications. MPC7441 consists processor core 256-Kbyte Figure shows block diagram MPC7441. core high-performance superscalar design supporting double-precision floating-point unit SIMD multimedia unit. memory storage subsystem supports interface main memory other system resources.
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Overview
Instruction Unit Branch Processing Unit Fetcher Tags IBAT Array (2048-Entry) Dispatch Unit Data (Original) Issue (2-Entry/1-Issue) DBAT Array 128-Entry DTLB Tags BTIC (128-Entry) Instruction Queue (12-Word) (Shadow) 128-Entry ITLB Instruction 128-Bit Instructions) 32-Kbyte Cache
Additional Features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor
32-Kbyte Cache
96-Bit Instructions) Issue (4-Entry/2-Issue) Issue (6-Entry/3-Issue)
Reservation Stations (2-Entry)
Vector Touch Queue
Load/Store Unit Vector Touch Engine Calculation) Finished Stores Castout File Rename Buffers Reservation Stations
Reservation Reservation Reservation Reservation Station Station Station Station File Rename Buffers Integer Unit Integer Integer Integer Unit Unit Unit Rename Buffers Reservation Stations File Reservation Reservation Reservation Station Station Station
Vector Permute Unit Vector
Vector Integer Unit
Vector Integer Unit
FloatingPoint Unit Push
32-Bit 128-Bit 128-Bit
32-Bit 32-Bit
Figure MPC7441 Block Diagram
Completed Stores Memory Subsystem System Interface Prefetch Store Queue Push Castout Queue
FPSCR Load Miss 64-Bit 64-Bit
Completion Unit
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256-Kbyte Unified Cache/Cache Controller Line Block (32-Byte) Block (32-Byte) Tags Status Status Castouts Accumulator 36-Bit Address 64-Bit Data Store Queue (L2SQ) Snoop Push/ Interventions
Completion Queue (16-Entry)
Service Queues Store Queue (LSQ)
Load Queue (LLQ) Load Miss Instruction Fetch Cacheable Store Request
MOTOROLA
Completes three instructions clock
Features
Features
This section summarizes features MPC7441 implementation PowerPC architecture. Major features MPC7441 follows: Major features MPC7441 follows: High-performance, superscalar microprocessor many instructions fetched from instruction cache time many instructions dispatched issue queues time many instructions instruction queue (IQ) Single-cycle execution most instructions many instructions some stage execution simultaneously
instruction clock cycle throughput most instructions Seven-stage pipeline control Eleven independent execution units three registerM files Branch processing unit (BPU) features static dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), cache branch instructionsEE have been encountered branch/loop code sequences. that target instruction FRBTIC, fetched into instruction queue cycle sooner than madeBY available from instruction cache. Typically, fetch that hits BTIC provides first four instructions target stream. history table (BHT) with bits entry four levels 2048-entry branch prediction- not-taken, strongly not-taken, taken, strongly taken
three outstanding speculative branches Branch instructions that update count register (CTR) link register (LR) often removed from instruction stream. 8-entry link register stack predict target address Branch Conditional Link Register (bclr) instructions. Four integer units (IUs) that share GPRs integer operands Three identical (IU1a, IU1b, IU1c) execute integer instructions except multiply, divide, move to/from special-purpose register instructions. executes miscellaneous instructions including logical operations, integer multiplication division instructions, move to/from special-purpose register instructions. Five-stage 32-entry file Fully IEEE 754-1985-compliant both single- double-precision operations Supports non-IEEE mode time-critical operations Hardware support denormalized numbers Thirty-two 64-bit FPRs single- double-precision operands Four vector units 32-entry vector register file (VRs) Vector permute unit (VPU)
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Features
Vector integer unit (VIU1) handles short-latency AltiVec integer instructions, such vector instructions (vaddsbs, vaddshs, vaddsws, example) Vector integer unit (VIU2) handles longer -latency AltiVec integer instructions, such vector multiply instructions (vmhaddshs, vmhraddshs, vmladduhm, example). Vector floating-point unit (VFPU) Three-stage load/store unit (LSU) Supports integer, floating-point vector instruction load/store traffic
Four-entry vector touch queue (VTQ) supports four architected AltiVec data stream operations
Three-cycle AltiVec load latency (byte, half-word, word, vector) with 1-cycle throughput
Four-cycle load latency (single, double) with 1-cycle throughput Dedicated adder calculates effective addresses (EAs) Supports store gathering
additional delay misaligned access withinIC double-word boundary
Performs alignment, normalization, precision conversion floating-point data Executes cache control instructions Performs alignment, zero padding, sign extension integer data misses (multiple outstanding misses) Supports hits under SupportsH big- little-endian modes, including misaligned little-endian accesses both FIQ, VIQ, accept many one, two, three instructions, Three issue queues
respectively, cycle. Instruction dispatch requires following: Instructions dispatched only from three lowest entries-IQ0, IQ1, IQ2. maximum three instructions dispatched issue queues clock cycle. Space must available instruction dispatch (this includes instructions that assigned space issue queue).
Rename buffers rename buffers rename buffers rename buffers
Dispatch unit decode/dispatch stage fully decodes each instruction. Completion unit completion unit retires instruction from 16-entry completion queue (CQ) when instructions ahead have been completed, instruction finished execution, exceptions pending. Guarantees sequential programming model (precise exception model) Monitors dispatched instructions retires them order
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Features
Tracks unresolved branches flushes instructions after mispredicted branch Retires many three instructions clock cycle Separate on-chip instruction data caches (Harvard architecture) 32-Kbyte, eight-way set-associative instruction data caches Pseudo least-recently-used (PLRU) replacement algorithm 32-byte (eight-word) cache block Physically indexed/physical tags Cache write-back write-through operation programmable per-page per-block basis Instruction cache provide four instructions clock cycle; data cache provide four words clock cycle Caches disabled software
Caches locked software
MESI data cache coherency maintained hardwareIC Separate copy data cache tags efficient snooping Parity support cache tags
snooping instruction cache except icbi instruction Data cache supports AltiVec transient instructions Critical double- and/orBY quad-word forwarding performed needed. Critical quad-word forwarding used AltiVec loads instruction fetches. Other accesses critical double-word forwarding. Level (L2)RC interface cache
On-chip, 256-Kbyte, 8-way associative unified instruction data cache Fully pipelined provide bytes clock cycle caches total 9-cycle load latency data cache miss that hits Pseudo least-recently-used (PLRU) replacement algorithm Cache write-back write-through operation programmable per-page per-block basis 64-byte, two-sectored line size Parity support cache
Separate memory management units (MMUs) instructions data 52-bit virtual address; 36-bit physical address Address translation 4-Kbyte pages, variable-sized blocks, 256-Mbyte segments Memory programmable write-back/write-through, memory coherency enforced/memory coherency enforced page block basis Separate IBATs DBATs (four each) also defined SPRs Separate instruction data translation lookaside buffers (TLBs) Both TLBs 128-entry, two-way associative, replacement algorithm TLBs hardware- software-reloadable (that miss page table search performed hardware system software)
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Features
Efficient data flow Although VR/LSU interface bits, L1/L2 interface allows bits. data cache fully pipelined provide bits/cycle from cache fully pipelined provide bits processor clock cycle cache. many outstanding, out-of-order, cache misses allowed between data cache bus. many out-of-order transactions present Store merging multiple store misses same line. Only coherency action taken (address-only) store misses merged bytes cache block data tenure needed).
Three-entry finished store queue five-entry completed store queue between data cache
Multiprocessing support features include following:
Separate additional queues efficient buffering outbound data (such cast outs write through stores) from data cache cache
Hardware-enforced, MESI cache coherency protocols data cache
Load/store with reservation instruction pair atomic memory references, semaphores, other multiprocessor operations
Power thermal management 1.5-V processor core
following three power-saving modes available system:
Nap-Instruction fetching halted. Only those clocks thermal assist unit (TAU), time base, decrementer, JTAG logic remain running. part goes into doze state snoop memory operations then back using QREQ/QACK processor-system handshake protocol. Sleep-Power consumption further reduced disabling snooping, leaving only locked running state. internal functional units disabled. Deep sleep-When part sleep state, system disable resulting. system then disable SYSCLK source greater system power savings. Power-on reset procedures restarting relocking must followed exiting deep sleep state.
Thermal management facility provides software-controllable thermal management. Thermal management performed through three supervisor-level registers MPC7441-specific thermal management exception. Instruction cache throttling provides control instruction fetching limit power consumption. Performance monitor used help debug system designs improve software efficiency. In-system testability debugging features through JTAG boundary-scan capability Testability LSSD scan design IEEE 1149.1 JTAG interface Array built-in self test (ABIST)-factory test only
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Comparison with MPC7400
Reliability serviceability Parity checking system Parity checking
Comparison with MPC7400
Table compares features MPC7441 with features earlier MPC7400. achieve higher frequency, number logic levels cycle reduced. Also, achieve this higher frequency, pipeline MPC7441 extended (compared MPC7400), while maintaining same level performance measured number instructions executed cycleC (IPC).
MPC7400/MPC7410 Microarchitectural Specs MPC7441 Basic Pipeline Functions Logic Inversions Cycle Pipeline Stages Execute Total Pipeline Stages (Minimum) Pipeline Maximum Instruction Throughput Branch Branch Pipeline Resources Instruction Buffer Size Completion Buffer Size Renames (Integer, Float, Vector) Maximum Execution Throughput
Table Microarchitecture Comparison
Vector Scalar Floating-Point (Any Units) Out-of-Order Window Size Execution Queues Integer Units Entry Queues Order, Queues Order Branch Processing Resources Entry Queues Order, Queues Order (Permute/Fixed)
Vector Units Scalar Floating-Point Unit
Prediction Structures BTIC Size, Associativity Size Link Stack Depth Unresolved Branches Supported Branch Taken Penalty (BTIC Hit) Minimum Misprediction Penalty
BTIC, BHT, Link Stack 128-Entry, 4-Way 2K-Entry
BTIC, 64-Entry, 4-Way 512-Entry None
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Comparison with MPC7400 Table Microarchitecture Comparison (continued)
Microarchitectural Specs MPC7441 MPC7400/MPC7410
Execution Unit Timings (Latency-Throughput) Aligned Load (Integer, Float, Vector) Misaligned Load (Integer, Float, Vector) Miss, Latency (aDd Sub, Shift, Rot, Cmp, Logicals) Integer Multiply Scalar Float VSFX (Vector Simple) 3-1, 4-1, 4-2, 5-2, 2-1, 2-1, 3-2, 3-2, (11)1
VCFX (Vector Complex) VFPU (Vector Float) VPER (Vector Permute)
MMUs (Instruction Data) Tablewalk Mechanism
Size Associativity Locking Granularity/Style Parity Cache Parity Cache
RCache/D Cache Features
MMUs
IC2-1
128-Entry, 2-Way
3-1, 3-1,
2-1, 3-2,
128-Entry, 2-Way Hardware
Hardware Software
32K/32K 8-Way 4-Kbyte/Way Word Byte Streams On-Chip Cache Features
32K/32K 8-Way Full Cache None None (Any Combination) Streams
Number Cache Misses (Load/Store) Data Stream Touch Engines
Cache Level Size/Associativity Access Width Number 32-Byte Sectors/Line Parity Off-Chip Cache Support Cache Level On-Chip Logical Size Associativity Number 32-Byte Sectors/Line Off-Chip Data SRAM Support Data Path Width
256-Kbyte/8-Way Bits Byte
None (Except
0.5MB, 1MB, 2-Way PB2,
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General Parameters Table Microarchitecture Comparison (continued)
Microarchitectural Specs Direct Mapped SRAM Sizes Parity
MPC7441
MPC7400/MPC7410 Mbyte, Mbyte, Mbytes Byte
Numbers parentheses SRAM.
size
General Parameters
0.18 CMOS, six-layer metal 8.69 12.17 (106 mm2) million Fully static
following list provides summary general parameters MPC7441: Technology
Transistor count Logic design Packages
Core power supply nominal power supply Electrical Thermal Characteristics This section provides electrical specifications thermal characteristics MPC7441.
MPC7441: Surface mount ceramic ball grid array (CBGA)
1.5.1
Electrical Characteristics
tables this section describe MPC7441 electrical characteristics. Table provides absolute maximum ratings.
Table Absolute Maximum Ratings1
Characteristic Core supply voltage supply voltage Processor supply voltage BVSEL BVSEL HRESET OVDD Input voltage Processor JTAG signals Symbol AVDD OVDD OVDD Maximum Value -0.3 1.95 -0.3 1.95 -0.3 1.95 -0.3 -0.3 OVDD -0.3 OVDD Unit Notes
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Electrical Thermal Characteristics Table Absolute Maximum Ratings1 (continued)
Characteristic Storage temperature range Notes: Functional tested operating conditions given Table Absolute maximum ratings stress ratings only, functional operation maximums guaranteed. Stresses beyond those listed affect device reliability cause permanent damage device. Caution: must exceed OVDD more than time including during power-on reset. Caution: OVDD must exceed VDD/AVDD more than time including during power-on reset. Caution: VDD/AVDD must exceed OVDD more than time including during power-on reset. overshoot/undershoot voltage maximum duration shown Figure BVSEL must such that mode. BVSEL must HRESET such that mode. Symbol Tstg Maximum Value Unit Notes
Figure shows undershoot overshoot voltage MPC7441. OVDD OVDD OVDD
Exceed tSYSCLK
Figure Overshoot/Undershoot Voltage
MPC7441 provides several voltages support both compatibility with existing systems migration future systems. MPC7441 core voltage must always provided nominal (see Table actual recommended core voltage). Voltage processor interface I/Os provided through separate sets supply pins provided voltages shown Table input voltage threshold each selected sampling state voltage select pins negation signal HRESET. output voltage will swing from maximum voltage applied OVDD power pins.
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Electrical Thermal Characteristics Table Input Threshold Voltage Setting
BVSEL Signal HRESET Processor Input Threshold Relative Available Notes
Table provides recommended operating conditions MPC7441. Conditions Table Recommended1 Operating Recommended Value Characteristic Symbol Core supply voltage supply voltage AVDD Processor supply voltage BVSEL OVDD BVSEL HRESET OVDD OVDD
Input voltage Processor JTAG signals Die-junction temperature OVDD OVDD
Notes: Caution: input threshold selection must agree with OVDD/GVDD voltages supplied. notes Table NCthat select 2.5-V threshold option processor bus, BVSEL should tied HRESET signals change state together. This preferred method selecting this mode operation. inverse HRESET. used, pulldown resistors should less than
Unit
Notes
Notes: These recommended tested operating conditions. Proper device operation outside these conditions guaranteed. This voltage input filter discussed Section 1.9.2, "PLL Power Supply Filtering" necessarily voltage AVDD which reduced from filter.
Table provides package thermal characteristics MPC7441.
Table Package Thermal Characteristics
Characteristic CBGA package thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, junction-to-lead thermal resistance (typical) Symbol Value <0.1 Rating °C/W °C/W
Note: Refer Section 1.9, "System Design Information," more details about thermal management.
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Electrical Thermal Characteristics
Table provides electrical characteristics MPC7441.
Table Electrical Specifications
recommended operating conditions. Table
Characteristic
Nominal Voltage1
Symbol
OVDD 0.65 -0.3 -0.3
Unit
Notes
Input high voltage (all inputs except SYSCLK) Input voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input voltage Input leakage current, OVDD High impedance (off-state) leakage current, OVDD Output high voltage, Output voltage, Capacitance, inputs
CVIH CVIL ITSI
OVDD OVDD OVDD 0.35
B2.5
-0.3
OVDD
0.45
OVDD 0.45
Notes: Nominal voltages; Table recommended operating conditions. processor signals, reference OVDD. Excludes test signals IEEE 1149.1 boundary scan (JTAG) signals. Capacitance periodically sampled rather than 100% tested. leakage measured nominal OVDD VDD, both OVDD must vary same direction (for example, both OVDD vary either -5%).
Table provides power consumption MPC7441.
Table Power Consumption MPC7441
Processor (CPU) Frequency Unit Full-Power Mode Typical Maximum Doze Mode Typical 11.5 15.4 13.4 17.6 Notes
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Electrical Thermal Characteristics Table Power Consumption MPC7441 (continued)
Processor (CPU) Frequency Unit Mode Typical Sleep Mode Typical Deep Sleep Mode (PLL Disabled) Typical Notes
Notes: These values apply valid processor ratios. values include supply power (OVDD) supply power (AVDD). OVDD power system dependent, typically <20% power. Worst case power consumption AVDD Maximum power measured nominal (see Table while running entirely cache-resident, contrived sequence instructions which keep execution units, with without AltiVec, maximally busy. Typical power average value measured nominal recommended (see Table system while running typical code sequence. Doze mode user-definable state; intermediate state between full-power either sleep mode. result, power consumption this mode tested. 1.5.2 ElectricalB Characteristics This section provides electrical characteristics MPC7441. After fabrication, functional parts sorted maximum processor core frequency shown Section 1.5.2.1, "Clock Specifications," tested conformance specifications that frequency. processor core frequency
determined (SYSCLK) frequency settings PLL_EXT PLL_CFG[0:3] signals. Parts sold maximum processor core frequency; Section 1.11, "Ordering Information."
1.5.2.1
Clock Specifications
Table Clock Timing Specifications
Table provides clock timing specifications defined Figure
recommended operating conditions. Table
Maximum Processor Core Frequency Characteristic Symbol Processor frequency frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise fall time fcore fVCO fSYSCLK tSYSCLK 1000 1200 1000 1400 Unit Notes
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Electrical Thermal Characteristics Table Clock Timing Specifications (continued)
recommended operating conditions. Table
Maximum Processor Core Frequency Characteristic Symbol SYSCLK duty cycle measured OVDD/2 tKHKL/tSYSCLK Unit Notes
SYSCLK jitter ±150 ±150 ,100 Internal relock time Notes: Caution: SYSCLK frequency, PLL_EXT PLL_CFG[0:3] settings mustU chosen such that resulting SYSCLK (bus) frequency, (core) frequency, (VCO) frequency exceed their respective maximum minimum operating frequencies. Refer PLL_EXT, PLL_CFG[0:3] signal description Section 1.9.1, "PLL Configuration," valid PLL_EXT PLL_CFG[0:3] settings. Rise fall times SYSCLK input measured from Timing guaranteed design characterization. This represents total input jitter-short term long combined-and guaranteed design. term Relock timing guaranteed design characterization. PLL-relock time maximum amount time required lock after stable SYSCLK reached during power-on reset sequence. This Rbeen disabled subsequently re-enabled during sleep mode. Also specification also applies when note that HRESET must held asserted minimum clocks after PLL-relock time during power-on reset sequence. SYSCLK driver's closed loop jitter bandwidth should <500 bandwidth must allow cascade connected PLL-based devices track SYSCLK drivers with specified jitter. Figure provides SYSCLK input timing diagram.
SYSCLK tKHKL tSYSCLK Midpoint Voltage (OVDD/2) CVIH CVIL
Figure SYSCLK Input Timing Diagram
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Electrical Thermal Characteristics
1.5.2.2
Processor Specifications
Table provides processor timing specifications MPC7441 defined Figure Figure
Table Processor Timing Specifications
recommended operating conditions. Table
Speed Grades Parameter Symbol2 Mode select input setup HRESET HRESET mode select input hold tMVRH tMXRH tAVKH tIVKH Unit Notes
Input setup times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], D[0:63], DP[0:7] AACK, ARTRY, CKSTP_IN, DBG, DTI[0:3], HRESET, INT, MCP, QACK, SMI, SRESET, TBEN, TEA, EXT_QUAL, PMON_IN, SHD[0:1] Input hold times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], D[0:63], DP[0:7] AACK, ARTRY, CKSTP_IN, DBG, DTI[0:3], HRESET, INT, MCP, QACK, SMI, SRESET, TBEN, TEA, EXT_QUAL, PMON_IN, SHD[0:1]
tsysclk
tAXKH tIXKH
Output valid times: TSIZ[0:2], A[0:35], AP[0:4], GBL,C TBST, D[0:63], DP[0:7] ARTRY/SHD0/SHD1 CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ]
tKHAV tKHTSV tKHDV tKHARV tKHOV tKHAX tKHTSX tKHDX tKHARX tKHOX tKHOE tKHOZ tKHTSPZ tKHARP tsysclk tsysclk
Output hold times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], D[0:63], DP[0:7] ARTRY/SHD0/SHD1 CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ SYSCLK output enable SYSCLK output high impedance (all except ARTRY, SHD0, SHD1) SYSCLK high impedance after precharge Maximum delay ARTRY/SHD0/SHD1 precharge
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Electrical Thermal Characteristics Table Processor Timing Specifications (continued)
recommended operating conditions. Table
Speed Grades Parameter Symbol2 SYSCLK ARTRY/SHD0/SHD1 high impedance after precharge tKHARPZ tsysclk Unit Notes
Notes: input specifications measured from midpoint signal question midpoint rising edge input SYSCLK. output specifications measured from midpoint rising edge SYSCLK Figure Input midpoint signal question. output timings assume purely resistive load (see output timings measured pin; time-of-flight delays must added trace lengths, vias, connectors system. symbology used timing specifications herein follows pattern inputs outputs. example, tIVKH symbolizes time input signals reach valid state relative SYSCLK reference going high state input setup time. tKHOV symbolizes time from SYSCLK(K) going high until outputs valid output valid time. Input hold time read time that input signal went invalid with respect rising clock edge (KH) (note position reference state inputs) output hold time read time from rising edge (KH) until output went invalid (OX). setup hold time with respect rising edge HRESET (see Figure only. This specification configuration mode select tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must actual time duration parameter question. multiplied period SYSCLK compute Mode select signals are: BVSEL, PLL_CFG[0:3], PLL_EXT, BMODE[0:1]. According protocol, driven only currently active master. asserted then high impedance shown Figure nominal precharge width precharged high before returning tSYSCLK, i.e., less than minimum tSYSCLK period, ensure that another master asserting following clock will contend with precharge. Output valid output hold timing tested signal asserted. Output valid time tested precharge.The high impedance behavior guaranteed design. According protocol, ARTRY driven multiple masters through clock period immediately following AACK. contention issue because master asserting ARTRY will driving low. master asserting first clock following AACK will then high impedance clock before precharging high during second cycle after assertion AACK. nominal precharge width ARTRY tsysclk; that should high impedance shown Figure before first opportunity another master assert ARTRY. Output valid output hold timing tested signal asserted.The high-impedance behavior guaranteed design. According protocol, SHD0 SHD1 driven multiple masters beginning cycle Timing same ARTRY, i.e., signal high impedance fraction cycle, then negated entire cycle (crossing cycle boundary) before being three-stated again. nominal precharge width SHD0 SHD1 tsysclk. edges precharge vary depending programmed ratio core (PLL configurations). Guaranteed design tested.
Figure provides test load MPC7441.
Output OVDD/2
Figure Test Load
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Electrical Thermal Characteristics
Figure provides mode select input timing diagram MPC7441.
HRESET tMVRH tMXRH Mode Signals Midpoint Voltage (OVDD/2)
Figure Mode Input Timing Diagram
Figure provides input/output timing diagram MPC7441.
SYSCLK
tAVKH tIVKH
Inputs
Outputs (Except ARTRY, SHD0, SHD1) Outputs (Except ARTRY, SHD0, SHD1)
REKHAV
tAXKH
tIXKH
tKHAX tKHDX tKHOX
tKHDV tKHOV
tKHOE
tKHOZ
tKHTSPZ tKHTSV tKHTSX tKHTSV tKHARPZ tKHARV ARTRY, SHD0, SHD1 tKHARP tKHARX
Midpoint Voltage (OVDD/2)
Figure Input/Output Timing Diagram
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Electrical Thermal Characteristics
1.5.2.3
IEEE 1149.1 Timing Specifications
Table provides IEEE 1149.1 (JTAG) timing specifications defined Figure Figure Figure Figure
Table JTAG Timing Specifications (Independent SYSCLK)1
recommended operating conditions. Table
Parameter frequency operation cycle time clock pulse width measured rise fall times
Symbol fTCLK TCLK tJHJL
33.3
Unit
Notes
TRST assert time Input setup times: Boundary-scan data TMS, Input hold times: Boundary-scan data TMS, Valid times: Boundary-scan data Output hold times: Boundary-scan dataRC
tTRST tDVJH tIVJH tDXJH
tIXJH tJLDV tJLOV tJLDX tJLOX tJLDZ tJLOZ
output high impedance: Boundary-scan data
Notes: outputs measured from midpoint voltage falling/rising edge TCLK midpoint signal question. output timings measured pins. output timings assume purely resistive load (see Figure Time-of-flight delays must added trace lengths, vias, connectors system. TRST asynchronous level sensitive signal. setup time test purposes only. Non-JTAG signal input timing with respect TCK. Non-JTAG signal output timing with respect TCK. Guaranteed design characterization.
Figure provides test load boundary-scan outputs MPC7441.
Output OVDD/2
Figure Alternate Test Load JTAG Interface
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Electrical Thermal Characteristics
Figure provides JTAG clock input timing diagram.
TCLK tJHJL tTCLK Midpoint Voltage (OVDD/2)
Figure JTAG Clock Input Timing Diagram
Figure provides TRST timing diagram.
TRST tTRST Midpoint Voltage (OVDD/2)
Figure TRST Timing Diagram Figure provides boundary-scan timing diagram. tDVJH Boundary Input Data Valid Data InputsH tJLDV
JLDX
tDXJH
Boundary Data Outputs tJLDZ Boundary Data Outputs Output Data Valid Midpoint Voltage (OVDD/2)
Output Data Valid
Figure Boundary-Scan Timing Diagram
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Electrical Thermal Characteristics
Figure provides test access port timing diagram.
tIVJH TDI, tJLOV tJLOX Output Data Valid Input Data Valid
tIXJH
tJLOZ Output Data Valid
Midpoint Voltage (OVDD/2) Figure Test Access Port Timing Diagram
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Assignments
Part
Assignments
Figure Part shows pinout MPC7441, CBGA package viewed from surface. Part shows side profile CBGA package indicate direction surface view.
Scale
Part
Substrate Assembly Encapsulant View
Figure Pinout MPC7441, CBGA Package Viewed from Surface
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Pinout Listings CBGA Package
Pinout Listings CBGA Package
NOTE This pinout compatible with MPC750, MPC755, MPC7400, MPC7410 package.
Table Pinout Listing MPC7441, CBGA Package
Table provides pinout listing MPC7441, CBGA package.
Signal Name A[0:35]
Number E11, C11, F10, D11, C10, D12, B12, G10,
Active High
AACK AP[0:4] ARTRY AVDD BMODE0 BMODE1 BVSEL CKSTP_IN CKSTP_OUT CLK_OUT D[0:63]
High
High High High
,BVSEL
Input Input Input Input Input Output Input Output Input Output Output BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
Select1
Notes
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14, W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, P10, U10, W10, P17, R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17, V17,
DP[0:7] DRDY DTI[0:3] EXT_QUAL
High High High
Input Output Input Input
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
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Pinout Listings CBGA Package Table Pinout Listing MPC7441, CBGA Package (continued)
Signal Name Number D13, E17, G17, H11, H13, J10, J12, K11, K13, L10, L12, M11, M13, P12, R14, R17, T10, U13, U17, V11, A13, A14, A15, A16, A17, A18, A19, B13, B14, B15, B16, B17, B18, B19, C13, C14, C15, C16, C17, C18, C19, D14, D15, D16, D17, D18, D19, E12, E13, E14, E15, E16, E19, F12, F13, F14, F15, F16, F17, F18, F19, G11, G12, G13, G14, G15, G16, G19, H14, H15, H16, H17, H18, H19, J14, K17, J15, J16, J17, J18, J19, K15, K16, K18, K19, L14, L15, L16, L17, L18, L19, M14, M15, M16, M18, M19, N12, M17, N13, N14, N15, N16, N17, N18, N19, P15, P16, P18, Active Select1 Notes
HRESET L1_TSTCLK L2_TSTCLK
High High
Output Input Input
BVSEL BVSEL.
Connect
,BVSEL Input BVSEL Input BVSEL
LSSD_MODE OVDD
Input Input
BVSEL BVSEL
C12, E18, G18, P11, R13, R16, U12, U16, V10,
PLL_CFG[0:3] PLL_EXT PMON_IN PMON_OUT QACK QREQ SHD[0:1] SRESET SYSCLK TBEN TBST
High High High High
Input Input Input Output Input Output Input Input Input Input Input Output Input
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
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Pinout Listings CBGA Package Table Pinout Listing MPC7441, CBGA Package (continued)
Signal Name TEST[0:3] TEST[4] TRST A12, B10, H10, H12, J11, J13, K10, K12, K14, L11, L13, M10, Number Active High High High Input Output Input Input Input Select1 BVSEL BVSEL BVSEL BVSEL BVSEL Notes
TSIZ[0:2] TT[0:4]
High
High
Input BVSEL. ,BVSEL Input BVSEL Output BVSEL BVSEL BVSEL Output
Notes: OVDD supplies power processor bus,E JTAG, control signals; supplies power processor core (after filtering become AVDD). program voltage, connect BVSEL either (selects HRESET (selects used, pulldown resistor should less than supply voltages Table actual recommended value These input signals factory only must pulled OVDD normal machine operation. These signals factory only must left unconnected normal machine operation. Ignored mode. This signal selects between mode (asserted) mode (negated) will sampled HRESET going high. This signal must negated during reset, pull-up OVDD negation (inverse HRESET), ensure proper operation. Internal pull-up die. These pins require weak pull-up resistors (for example, maintain control signals negated state after they have been actively negated released MPC7441 other masters. These input signals factory only must pulled down normal machine operation. This externally enable performance monitor counters (PMC) they internally enabled software. will used control PMC, should pulled down that software enable PMC. Unused address pins must pulled down GND. This test signal recommended tied HRESET; however, other configurations will adversely affect performance. These signals must pulled down unused, MPC7441 mode. This signal must asserted during reset, pull-down assertion HRESET, ensure proper operation.
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Package Description
1.8.1
Package Description
Package Parameters MPC7441, CBGA
Package outline Interconnects Pitch Minimum module height ball array 1.27 mil) 2.72 3.24
following sections provide package parameters mechanical dimensions CBGA package.
package parameters provided following list. package type 360-lead ceramic ball grid array (CBGA).
Maximum module height Ball diameter
0.89 mil)
1.8.2
Figure provides mechanical dimensionsSC bottom surface nomenclature MPC7441, CBGA package.
Mechanical DimensionsLfor MPC7441, CBGA
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Package Description
Capacitor Region
CORNER
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M, 1994. DIMENSIONS MILLIMETERS. SIDE CORNER INDEX METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE CORNER DESIGNATED WITH BALL MISSING FROM ARRAY.
1213141516 171819
Millimeters 2.72 0.80 1.10 0.82 3.24 1.00 1.34 0.93 6.15
25.00 1.27 25.00 8.28 10.2
360X
0.15
Figure Mechanical Dimensions Bottom Surface Nomenclature MPC7441, CBGA
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System Design Information
System Design Information
This section provides system thermal design recommendations successful application MPC7441.
1.9.1
Configuration
MPC7441 configured PLL_EXT PLL_CFG[0:3] signals. given SYSCLK (bus) frequency, configuration signals internal frequency operation. PLL_EXT will normally pulled asserted extended modes operation. configuration MPC7441 shown Table example frequencies. this example, shaded cells represent settings that, given SYSCLK frequency, result core and/or frequencies that comply with 600-MHz column Table
Parts Table MPC7441 Microprocessor Configuration Example Example Bus-to-Core FrequencyIin (VCO Frequency MHz) PLL_CFG Bus-toCore-toPLL_EXT [0:3] Core 33.3 66.6 Multiplier Multiplier 0000 0.5x (33) (50) (66) (75) (83) (100) (133) 0100 (133) (200) (266) (300) (333) (400) (533) 0110 2.5x (166) (250) (333) (375) (415) (500) (666) 1000
(200) 1110 1010 0111 1011 1001 1101 0101 0010 0001 1100 3.5x 4.5x 5.5x 6.5x 7.5x (233) (266) (300) (333) (366) (400) (433) (466) (500) (533) (300) (350) (400) (450) (500) (550) (600) (630) (700) (750) (800) (400) (466) (533) (600) (666) (733) (800) (866) (933) (1000) (1066) (450) (525) (600) (675) (750) (825) (900) (975) (1050) (1125) (1200) (500) (581) (666) (747) (830) (913) (996) (1080) (1162) (1245) (1328) (600) (700) (800) (900) (1000) (1100) (1200) (1300) (1400) (1500) (800) (933) (1066) (1200) (1333) (1466)
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System Design Information Table MPC7441 Microprocessor Configuration Example Parts (continued)
Example Bus-to-Core Frequency (VCO Frequency MHz) PLL_EXT PLL_CFG [0:3] Bus-toCore-toBus Core 33.3 66.6 Multiplier Multiplier (600) (666) (733) (800 (866) (933) (900) (1000) (1100) (1200) (1300) (1200) (1333) (1466) (1350) (1500) (1494)
0111 1010 1001 1011 0101 1100 0001 1101 0011 1111
off/bypass
Notes: PLL_CFG[0:3] settings listed reserved.
(1066)
(1000) (1500)
(1400)
off, SYSCLK clocks core circuitry directly off, core clocking occurs
sample bus-to-core frequencies shown reference only. Some configurations select bus, core, frequencies which useful, supported, tested MPC7441; Section 1.5.2.1, "Clock Specifications," valid SYSCLK, core, frequencies. PLL-bypass mode, SYSCLK input signal clocks internal processor directly disabled. However, interface unit requires clock function. Therefore, additional signal, EXT_QUAL, must driven one-half frequency SYSCLK offset phase meet required input setup tIVKH hold time tIXKH (see Table result will that processor frequency will one-half SYSCLK while internal processor clocked SYSCLK frequency. This mode intended factory emulator tool only. Note: timing specifications given this document apply PLL-bypass mode. PLL-off mode, clocking occurs inside MPC7441 regardless SYSCLK input.
1.9.2
Power Supply Filtering
AVDD power signal provided MPC7441 provide power clock generation PLL. ensure stability internal clock, power supplied AVDD input signal should filtered noise resonant frequency range PLL. circuit similar shown Figure using surface mount capacitors with minimum effective series inductance (ESL) recommended. circuit should placed close possible AVDD minimize noise coupled from nearby circuits. often possible route directly from capacitors AVDD pin, which periphery CBGA footprint very close periphery CBGA footprint, without inductance vias.
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System Design Information
Surface Mount Capacitors AVDD
Figure Power Supply Filter Circuit
1.9.3
core voltage notes Table contain cautions about sequencing external voltages MPC7441 (when they different). These cautions necessary long-term reliability part. they violated, electrostatic discharge (ESD) protection diodesT will forward-biased excessive current flow through these diodes. system power supply design does control these requirements. 30BF10 voltage sequencing, circuit shown Figure added meet diodes (see Figure control maximum potential difference between external core power supplies power-up 1N5820 diodes regulate maximum potential difference power-down. 30BF10 30BF10 1N5820 1N5820
Figure Example Voltage Sequencing Circuit
Power Supply Voltage Sequencing
1.9.4
Decoupling Recommendations
MPC7441 dynamic power management feature, large address data buses, high operating frequencies, MPC7441 generate transient power surges high frequency noise power supply, especially while driving large capacitive loads. This noise must prevented from reaching other components MPC7441 system, MPC7441 itself requires clean, tightly regulated source power. Therefore, recommended that system designer place least decoupling capacitor each OVDD MPC7441. also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, power planes PCB, utilizing short traces minimize inductance. These capacitors should have value 0.01 Only ceramic surface mount technology (SMT) capacitors should used minimize lead inductance, preferably 0508 0603 orientations where connections made along length part. Consistent with recommendations Howard Johnson High Speed Digital Design: Handbook Black Magic (Prentice Hall, 1993) contrary previous recommendations decoupling Motorola microprocessors, multiple small capacitors equal value recommended over using multiple values capacitance. addition, recommended that there several bulk storage capacitors distributed around PCB, feeding OVDD planes, enable quick recharging smaller chip capacitors. These bulk capacitors should have equivalent series resistance (ESR) rating ensure quick response time
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System Design Information
necessary. They should also connected power ground planes through vias minimize inductance. Suggested bulk capacitors: 100-330 (AVX tantalum Sanyo OSCON).
1.9.5
Connection Recommendations
ensure reliable operation, highly recommended connect unused inputs appropriate signal level. Unused active inputs should tied OVDD. Unused active high inputs should connected GND. (no-connect) signals must remain unconnected. Power ground connections must made external VDD, OVDD, pins MPC7441.
MPC7441 processor drivers characterized over process, voltage, temperature. measure external resistor connected from chip OVDD GND. Then, value each resistor varied until voltage OVDD/2 (see Figure 16). output impedance average components,EM resistances pull-up pull-down devices. When data held low, closed (SW1 open), trimmed until voltage equals OVDD/2. then becomes resistance pull-down devices. When data held high, closed (SW2 open), trimmed until voltage equals OVDD/2. then becomes resistance pull-up devices. designed close each other value. Then, RN)/2. OVDD
1.9.6
Output Buffer Impedance
Data
OGND
Figure Driver Impedance Measurement
Table summarizes signal impedance results. impedance increases with junction temperature relatively unaffected voltage.
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System Design Information Table Impedance Characteristics
OVDD 5°-85°C
Impedance Typical Maximum
Processor 33-42 31-51
Unit
1.9.7
Pull-Up/Pull-Down Resistor Requirements
MPC7441 requires high-resistive (weak: pull-up resistors several control .pins interface maintain control signals negated state after they have been actively negated SHD1. released MPC7441 other masters. These pins are: ARTRY, SHDO,
Some pins designated being factory test must pulled OVDD down ensure proper device operation. MPC7441, BGA, pins that must pulled OVDD are: LSSD_MODE TEST[0:3]; pins that must pulled down are: L1_TSTCLK TEST[4]. addition, MPC7441 open-drain style output thatM requires pull-up resistor (weak stronger: used system. This CKSTP_OUT. pull-down resistor used configure BVSEL, resistor should less than (see Table 11).
During inactive periods bus, address transfer attributes driven master may, therefore, float high-impedance state relatively long periods time. Because MPC7441 must continually monitor these signals snooping, this float condition cause excessive power draw input receivers MPC7441 other receivers system. recommended that these signals pulled through weak (4.7 pull-up resistors system, that they otherwise driven system during inactive periods bus. snooped address transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], GBL.
extended addressing used, A[0:3] unused must pulled through weak pull-down resistors. MPC7441 mode, DTI[0:3] must pulled through weak pull-down resistors. data input receivers normally turned when read operation progress and, therefore, require pull-up resistors bus. Other data receivers system, however, require pull-ups, that those signals otherwise driven system during inactive periods system. data signals are: D[0:63] DP[0:7]. address data parity used system, respective parity checking disabled through HID0, input receivers those pins disabled, those pins require pull-up resistors should left unconnected system. parity generation disabled through HID0, then parity checking should also disabled through HID0, parity pins left unconnected system.
1.9.8
JTAG Configuration Signals
Boundary scan testing enabled through JTAG interface signals. TRST signal optional IEEE 1149.1 specification, provided processors that implement PowerPC architecture. While possible force controller reset state using only signals, more reliable power-on reset performance will obtained TRST signal asserted during power-on reset. Because JTAG interface also used accessing common on-chip processor (COP) function, simply tying TRST HRESET practical.
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System Design Information
function these processors allows remote computer system (typically, with dedicated hardware debugging software) access control internal operations processor. interface connects primarily through JTAG port processor, with some additional status monitoring signals. port requires ability independently assert HRESET TRST order fully control processor. target system independent reset sources, such voltage monitors, watchdog timers, power supply failures, push-button switches, then reset signals must merged into these signals with logic. arrangement shown Figure allows independently assert HRESET TRST, while ensuring that target drive HRESET well. optional pull-down resistor TRST populated ensure that JTAG scan chain initialized during power-on JTAG interface header will used; otherwise, this resistor should unpopulated TRST asserted when system reset signal (HRESET) asserted JTAG interface responsible driving TRST when needed.
header shown Figure adds many benefits-breakpoints,D watchpoints, register memory examination/modification, other standard debugger features possible through this interface-and inexpensive unpopulated footprint header added when needed.
interface standard header connection target system, based 0.025" square-post, 0.100" centered header assembly (oftenLcalled Berg header). connector typically removed connector key. There standardized numberFR header shown Figure consequently, many different numbers have been observed from emulator vendors. Some numbered top-to-bottom then left-to-right, while others left-to-right then top-to-bottom, while still others number pins counter clockwise from with IC). Regardless numbering, signal placement recommended Figure common known emulators. Call
shown Figure usually connected bridge chip system input QACK signal MPC7441 informing that into quiescent state. Under normal operation this occurs during low-power mode selection. order work, MPC7441 must this signal asserted (pulled down). While shown header, emulator products drive this signal. product does not, pull-down resistor populated assert this signal. Additionally, some emulator products implement open-drain type outputs only drive QACK asserted; these tools, pull-up resistor implemented ensure this signal deasserted when being driven tool. Note that pull-up pull-down resistors QACK signal mutually exclusive never necessary populate both system. preserve correct power down operation, QACK should merged logic that also driven bridge.
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System Design Information
From Target Board Sources any)
SRESET HRESET QACK HRESET SRESET
SRESET HRESET
OVDD OVDD OVDD
TRST VDD_SENSE CHKSTP_OUT
CHKSTP_IN Connector Physical QACK
OOVDD
OVDD OVDD
TRST
CHKSTP_OUT OVDD OVDD CHKSTP_IN QACK OVDD
Header
Notes:
RUN/STOP, normally found header, implemented MPC7450. Connect header OVDD with pull-up resistor. location; physically present header. .Component populated. Populate only JTAG interface unused. Component populated. Populate only debug tool does drive QACK. Populate only debug tool uses open-drain type output does actively deassert QACK.
Figure JTAG Interface Connection
1.9.9
Thermal Management Information
This section provides thermal management information ceramic ball grid array (CBGA) package air-cooled applications. Proper thermal control design primarily dependent system-level design-the heat sink, airflow, thermal interface material. reduce die-junction temperature, heat
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System Design Information
sinks attached package several methods-spring clip holes printed-circuit board package, mounting clip screw assembly (see Figure 18); however, potential large mass heat sink, attachment through printed circuit board suggested. spring clip used, spring force should exceed pounds.
Heat Sink Heat Sink Clip
CBGA Package
Thermal Interface Material
board designer choose between several types heat sinks place MPC7441. There heat sinks MPC7441 provided following vendors: several commercially available Chip Coolers Inc. 800-227-0254 (USA/Canada)
Strawberry Field Warwick, 02887-6979 Internet: www.chipcoolers.com International Electronic Research Corporation (IERC) Magnolia Blvd. Burbank, 91502 Internet: www.ctscorp.com Thermalloy 2021 Valley View Lane Dallas, 75234-8993 Internet: www.thermalloy.com Wakefield Engineering Cummings Center, Suite 157H Beverly, 01915 Internet: www.wakefield.com Aavid Engineering Apache Trail Terrell, 75160 Internet: www.aavid.com 401-739-7600
Figure Package Exploded Cross-Sectional View with Several Heat Sink Options
Printed-Circuit Board
818-842-7277
972-243-4321
781-406-3000
972-551-7330
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System Design Information
Cool Innovations Inc. Spinnaker Way, Unit Concord, Ontario Canada Internet: www.coolinnovations.com
905-760-1992
Ultimately, final selection appropriate heat sink depends many factors, such thermal performance given velocity, spatial volume, mass, attachment method, assembly, cost.
exposed-die packaging technology, shown Table intrinsic conduction thermal resistance paths follows: junction-to-case top-of-die exposed silicon) thermal resistance junction-to-ball thermal resistance Figure depicts primary heat transfer path packageIwith attached heat sink mounted printed-circuit board. Convection External Resistance Radiation Heat Sink Thermal Interface Material Die/Package Internal Resistance Junction
1.9.9.1 Internal Package Conduction Resistance
Package/Leads Printed-Circuit Board
Radiation Convection External Resistance (Note internal versus external package resistance)
Figure Package with Heat Sink Mounted Printed-Circuit Board
Heat generated active side chip conducted through silicon, then through heat sink attach material thermal interface material), finally heat sink where removed forced-air convection. Because silicon thermal resistance quite small, first-order analysis, temperature drop silicon neglected. Thus, thermal interface material heat sink conduction/convective thermal resistances dominant terms.
1.9.9.2
Thermal Interface Materials
thermal interface material recommended package lid-to-heat sink interface minimize thermal contact resistance. those applications where heat sink attached spring clip mechanism, Figure shows thermal performance three thin-sheet thermal-interface materials (silicone,
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System Design Information
graphite/oil, floroether oil), bare joint, joint with thermal grease function contact pressure. shown, performance these thermal interface materials improves with increasing contact pressure. thermal grease significantly reduces interface thermal resistance. That bare joint results thermal resistance approximately times greater than thermal grease joint. Often, heat sinks attached package means spring clip holes printed-circuit board (see Figure 18). Therefore, synthetic grease offers best thermal performance, considering interface pressure recommended high power dissipation MPC7441. course, selection thermal interface material depends many factors-thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc.
Silicone Sheet (0.006 inch) Bare Joint Floroether Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease
Specific Thermal Resistance (Kin2/W)
Contact Pressure (psi)
Figure Thermal Performance Select Thermal Interface Material
board designer choose between several types thermal interface. Heat sink adhesive materials should selected based upon high conductivity, adequate mechanical strength meet equipment shock/vibration requirements. There several commercially available thermal interfaces adhesive materials provided following vendors: Dow-Corning Corporation Dow-Corning Electronic Materials 0997 Midland, 48686-0997 Internet: www.dow.com Chomerics, Inc. Dragon Court Woburn, 01888-4014 Internet: www.chomerics.com 800-248-2481
781-935-4850
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Thermagon Inc. 3256 West 25th Street Cleveland, 44109-1668 Internet: www.thermagon.com Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, 06067-3910 Internet: www.loctite.com
888-246-9050
860-571-5100
1.9.9.3 Heat Sink Selection Example preliminary heat sink sizing, die-junction temperature expressed follows: where: die-junction temperature inlet cabinet ambient temperature temperature rise withinE computer cabinet junction-to-case thermal resistance adhesive interface material thermal resistance Ibase-to-ambient thermal resistance heat sink power dissipated device
following section provides heat sink selection example using commercially available heat sinks.
During operation, die-junction temperatures (Tj) should maintained less than value specified Table temperature cooling component greatly depends upon ambient inlet temperature temperature rise within electronic cabinet. electronic cabinet inlet-air temperature (Ta) range from 40°C. temperature rise within cabinet (Tr) range 10°C. thermal resistance thermal interface material (int) typically about 1.5°C/W. example, assuming 30°C, 5°C, CBGA package 0.1, typical power consumption (Pd) 11.5 following expression obtained: Die-junction temperature: 30°C (0.1°C/W 1.5°C/W 11.5 this example, value 4.4°C/W less required maintain junction temperature below maximum value Table Though junction-to-ambient heat sink-to-ambient thermal resistances common figure-of-merit used comparing thermal performance various microelectronic packaging technologies, should exercise caution when only using this metric determining thermal management because single parameter adequately describe three-dimensional heat flow. final die-junction operating temperature only function component-level thermal resistance, system-level design operating conditions. addition component's power consumption, number factors affect final operating die-junction temperature-airflow, board population (local heat flux adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system temperature rise, altitude, etc. complexity many variations system-level boundary conditions today's microelectronic equipment, combined effects heat transfer mechanisms (radiation, convection,
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Document Revision History
conduction) vary widely. these reasons, recommend using conjugate heat transfer models board, well system-level designs.
1.10 Document Revision History
Table provides revision history this hardware specification.
Table Document Revision History
Document Revision Initial release. Substantive Change(s)
1.11 Ordering Information
Ordering information parts fully covered this specification document provided Section 1.11.1, "Part Numbers Fully Addressed This Document."
1.11.1 Part Numbers Fully Addressed This Document
Table provides Motorola part numbering nomenclature MPC7441. Note that individual part numbers correspond maximum processor core frequency. available frequencies, contact your local Motorola sales office. addition processor frequency, part numbering scheme also includes application modifier which specify special application conditions. Each part number also contains revision level code which refers mask revision number.
Table Part Numbering Nomenclature
Product Code XPC2
7441
Part Identifier 7441
Package CBGA
Processor Frequency1
Application Modifier 105°C
Revision Level 2.3; 8000 0210
Notes: Processor core frequencies supported parts addressed this specification only. Parts addressed Part Number Specifications support other maximum core frequencies. prefix Motorola part number designates "Pilot Production Prototype" defined Motorola 3-13. These from limited production volume prototypes manufactured, tested, Q.A. inspected qualified technology simulate normal production. These parts have only preliminary reliability characterization data. Before pilot production prototypes shipped, written authorization from customer must file applicable sales office acknowledging qualification status fact that product changes still occur while shipping pilot production prototypes.
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Ordering Information
1.11.2 Part Marking
Parts marked example shown Figure
XPC7441 RX600LG MMMMMM ATWLYYWWA
7441
Notes: MMMMMM 6-digit mask number. ATWLYYWWA traceability code. CCCCC country assembly. This space left blank parts assembled United States.
Figure Part Marking Device
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REACH USA/EUROPE/LOCATIONS LISTED: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: DOCUMENT COMMENTS: (512) 933-2625, Attn: RISC Applications Engineering
implementers There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding particular purpose, does Motorola assume suitability products liability arisingA application product circuit, specifically disclaims liability, including without limitation consequential incidental ES"Typical" parameters which provided Motorola data sheets damages. and/or specifications vary different applications actual
Information this document provided solely enable system software performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
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