Module M68HC08, HCS08, HCS12 MCUs Stanislav Arendarik Application
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Document Number: AN3291 Rev. 04/2007
Module M68HC08, HCS08, HCS12 MCUs
Stanislav Arendarik Application Engineer Roznov, Czech Republic
Introduction
Contents
Introduction Summary Terminology Transfer START STOP Conditions Communication. Control Byte Address Byte Acknowledge Read/Write Format
This application note example module Freescale's MCUs. module used master slave mode, respectively. this case, master mode communicates with serial EEPROM because used mainly communication between peripheral device. communicate directly between MCUs, better this task. This application note summarizes common states definitions provides example communicate with serial EEPROMs (24C16 24C512). easily another device instead EEPROM, must change address byte that characterizes slave device.
Software Routines MCUs Initialization Write Function Read Function Example with Interrupt Used 3.4.1 Master 3.4.2 Slave Conclusion.
Freescale Semiconductor, Inc., 2007. rights reserved.
Summary
Summary
bidirectional, two-wire based wired (open drain) connection between master slave devices. proper functionality, pull-up resistors used. Each transfer originates from master device acknowledged answered slave device.
Terminology
following terminology used this application note: Transmitter Device that sends data bus. transmitter data accord (master transmitter), respond request data from another device (slave transmitter). Receiver Device that receives data from bus. Master Component that initializes transfer, generates clock signal, terminates transfer. master transmitter receiver. Slave Device addressed master. slave receiver transmitter. Multi-master Ability more than master co-exist without collision data loss. Arbitration Prearranged procedure that authorizes only master time take control bus. Synchronization Prearranged procedure that synchronizes clock signals provided more masters. Data signal line (Serial DAta). Clock signal line (Serial CLock). bidirectional lines connected positive supply voltage current source pull-up resistor. When free, both lines high. Data transfer rates kbit/s standard mode, kbit/s fast mode Mbit/s high-speed mode. number devices connected depends only capacitance; limit
Transfer
data line must stable during clock's high period. line's high state changes only when clock signal line low. Figure
Change Data Allowed
Data Line Stable Data Valid
Figure Transfer
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Summary
START STOP Conditions
Within procedure, unique situations arise, which defined START STOP conditions (see Figure While line high, high-to-low transition line START condition. While line high, low-to-high transition line STOP condition. master always generates START STOP conditions. free lines remain high level after STOP before START conditions.
START Condition STOP Condition
Figure START STOP Conditions
Communication
transfer protocol based byte transfers followed acknowledge (ACK). byte transfer starts with most significant (MSB) least significant (LSB). positive clock impulses clock each bit. impulse clocks bit. Every transfer originates from master device which sends START condition bus. next consecutive bytes' sequence depends data being transferred through bus.
Control Byte
control byte always follows START condition. control byte selects activates specific devices bus; Figure control-byte structure. first four bits represent slave device's control code. example, control byte serial EEPROM (control code `1010' binary). next three bits represent chip selects connected EEPROMs bus. EEPROM uses these three bits multiple device operations, they used higher bits internal EEPROM address memory address byte wider than bits. This address depends EEPROM capacity. example, capacity range kbits, these three bits represent highest three bits address. (read/write) bit. This determines requested operation slave device: equals this means write operation equals this means read operation. last and, this case, always generated slave.
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Summary
Control Code
Address Bits
Slave Address START Read/Write Acknowledge
Figure Control-Byte Structure
Address Byte
address byte brings address information slave device. This byte determines real address EEPROM, from data written read. address information structure depends connected EEPROM capacity. EEPROMs kbits address byte, EEPROMs with higher capacity byte addresses (address address Address sent first. structure address bytes one-byte address Figure Figure byte addresses. EEPROMs type 24C16 24C512 used communication devices.
Activity Master Control Byte Word Address Data Byte
Activity
Figure Byte Address Write Format
Activity Master Control Byte Word Address Word Address Data Byte
Activity
Figure Byte Address Write Format
Acknowledge
acknowledge (ACK) low-level impulse line during pulse line. master always generates pulses. receiver generates pulses. This means write operation slave device generates after each byte transfers. read operation, slave generates when control byte address byte sent from master; master generates when receives data from slave.
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs
Read/Write Format
There types data transfers bus: Read from slave Write slave When write operation executes, data byte follows address byte. This data byte contains actual data written address address byte; Figure Figure When read operation executes first part communication protocol: master writes actual address slave. master sends repeat START condition bus, followed control byte with equal slave device sends immediately sends actual requested data. Figure read-operation structure.
Activity Master Control Byte Word Address Control Byte Data Byte
Activity
Figure Read-Operation Structure
Figure Figure Figure read- write-byte operations. second style data transfer page-write page-read. more information these styles refer slave-device data sheet.
Software Routines MCUs
Detailed descriptions modules found data sheet. short review follows: Address register Used differently HC908 than types. HC908 core, address register's content sent automatically after START condition, data register content follows condition. This address register also serves IIC-slave address slave mode. core, address register active only slave mode comprises slave address bus. This used multi-MCU connection bus. Frequency divider register Determines clock speed. frequency acts source frequency module. Control register Controls module functionality. Status register Comprises information about actual state. Data register Serves input output point information transferred through bus.
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs
Initialization
main task right speed clock signal. These clocks based frequency. next task module functionality interrupt service routine, activate module, slave mode. Refer Example Example Example
Example Software HC908 (MC68HC908AP64 Used)
void init_I2C (void) MMCR1_MMEN MMCR1_MMCLRBB MMCR1_MMTXAK MMCR2_MMRW MMCR2_MMAST MMCR2_MMNAKIF MMCR2_MMALIF MMSR MMFDR
Enable IIC; Clear busy flag; Slave mode actually; Clear flags; Clear flags (Status register); speed 25kHz 4MHz;
Example Software 9S12 (MC9S12DP256B Used)
void IBFD IBAD IBCR Init_I2C(void) 0x4C; 0x00; 0x80; frequency divider register: 8MHz 91kHz; slave address this module; enable module interrupts;
Example Software 9S08 (MC9S08GB60 Used)
void Init_I2C (void) IIC1C_IIC1EN IIC1C_TXAK IIC1C_MST IIC1F 0x99; IIC1S_SRW
Enable I2C; generate master after transfer; Slave mode actually; speed 50kHz 18.8743MHz; 12.5k->0x39; 50k->0x99; 100k->0x59;
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs
Write Function
write slave address will discussed first. maintain this task, activate communication with slave sending START followed slave-address byte. These bits' content discussed Section 2.6, "Address Byte." When master sends byte, slave sends during impulse. slave must acknowledge each byte master sends. next byte (second byte) internal address memory array. This address bytes, depending memory size. slave must acknowledge each byte master sends. third (fourth large memory) data byte this data will write specified address. slave follows this data byte. When master receives this bit, generates STOP bit. this moment, slave internally disconnects from internally processes write operation. While slave processes requested operation (write) cannot answer next master request. Therefore, master must wait amount time defined slave-device data sheet, must periodically send requests slave test right answer (ACK from slave).
Example Write Byte HC908 (MC68HC908AP64 24C16 Used)
void I2C_write_byte (byte addr, byte wr_data) MMCR2_MMRW Write mode; MMADR own_sl_addr; combined address Slave write; MMDTR addr; address Slave read; //-start transmit bytes bus-MMCR2_MMAST Start transfer Master while (!(MMSR_MMTXBE)); wait till data transferred; while (MMSR_MMRXAK); wait from slave; //-Slave occurred-MMDTR wr_data; write data byte into EEPROM; while (!(MMSR_MMTXBE)); wait till data transferred; MMDTR 0xFF; generate impulse slave send bit; while (MMSR_MMRXAK); wait from slave; MMCR2_MMAST STOP bit;
Example Example larger type EEPROM (24C512). word address divided into parts (two bytes): byte high byte, defined Example
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs
Example Word Address Divided into Byte High Byte
typedef union word EE_Address; struct byte Address_H; byte Address_L; }Bytes; }tAddr; tAddr sADDR; #define Address sADDR.EE_Address #define Addr_L sADDR.Bytes.Address_L #define Addr_H sADDR.Bytes.Address_H
Example Write Byte 9S08 (MC9S08GB60 24C16 Used)
void IIC_write_byte(word addr, byte data) Address addr; load address; temp (Addr_H 0x07) IIC1C_TXAK RX/TX MS/SL TXAK IIC1C 0x30; generate START condition; //-start transmit first byte bus-IIC1D IIC_SLAVE temp; Address slave master transmit; while (!IIC1S_IICIF); wait until IBIF; IIC1S_IICIF=1; clear interrupt event flag; while(IIC1S_RXAK); check RXAK; //-Slave occurred-IIC1D Addr_L; Send byte word address; while (!IIC1S_IICIF); wait until IBIF; IIC1S_IICIF=1; clear interrupt event flag; while(IIC1S_RXAK); check RXAK; //-Slave occurred-IIC1D data; while (!IIC1S_IICIF); wait until IBIF; IIC1S_IICIF=1; clear interrupt event flag; while(IIC1S_RXAK); check RXAK; //-Slave occurred-IIC1S_IICIF=1; clear interrupt event flag; IIC1C_MST generate STOP condition;
Example Write Byte 9S12 (MC9S12XDT512 Used)
void IIC_write_byte(word addr, byte data) Address addr; load address; IIC0_IBCR_TXAK TXAK IIC0_IBCR 0x30; RX/TX MS/SL TXAK generate START condition; //-start transmit first byte bus-IIC0_IBDR slavewrite; Address slave master transmit;
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBDR Addr_H; Send high byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBDR Addr_L; Send byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBDR data; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBCR_MS_SL generate STOP condition;
Read Function
read function similar write function. First, write address (byte word) into slave. from slave always follows these write cycles. When address properly writes slave, master generates REPEAT START condition. Then, master again sends control byte with equal This means read-from-slave function. from slave follows this byte. master must then switch receive mode perform read data from IIC-data register (IICDR) function. This instruction generates pulses slave send data from requested address. There possible options: master does need next data byte from slave, sends NOACK (ACK STOP condition. master wants read next data byte from slave, generates (ACK slave recognizes this moves internal address pointer next address. Then, master performs read data from IICDR function generate next series pulses slave send data. This sequence perform infinitely.
Example Read Byte HC908 Family (HC908AP64 Used)
byte I2C_read_byte (byte addr)//output byte "rd_data"; MMCR2_MMRW Write mode; MMADR own_sl_addr; combined address Slave write; MMDTR addr; address; //-start transmit first byte bus-MMCR2_MMAST Start transfer Master while (!(MMSR_MMTXBE)); wait till data transferred; while (MMSR_MMRXAK); wait from slave;
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs //-Slave occurred-MMCR2_MMRW read operation; MMCR1_REPSEN enable repeat Start bit; MMCR1_MMTXAK Master will generate ACK; MMCR2_MMAST Start transfer Master //-start transmit Repeat start "A1" bus-MMDTR 0xFF; send repeated start combined address; while (!(MMSR_MMTXBE)); wait till data transferred; while (MMSR_MMRXAK); wait from slave; MMDTR 0xFF; send clocks slave send data; MMCR1_MMTXAK Disable master after read byte from Slave; while (!(MMSR_MMRXBF)); wait till data received; rd_data MMDRR; read received data; MMCR2_MMAST generate STOP transfer; return rd_data;
Example Example larger type EEPROM (24C512). word address divided into parts (two bytes): byte high byte (see Example
Example Read Byte 9S08 Family (MC9S08GB60 24C16 Used)
typedef union word EE_Address; struct byte Address_H; byte Address_L; }Bytes; }tAddr; tAddr ADDR; #define Address ADDR.EE_Address #define Addr_L ADDR.Bytes.Address_L #define Addr_H ADDR.Bytes.Address_H byte IIC_read_byte(word addr) Address addr; temp (Addr_H 0x07) IIC1C_TXAK RX/TX MS/SL TXAK IIC1C 0x30; generate START condition; IIC1D IIC_SLAVE temp; Address slave master transmit; while (!IIC1S_IICIF); wait until IBIF; IIC1S_IICIF=1; clear interrupt event flag; while(IIC1S_RXAK); check RXAK; //-Slave occurred-IIC1D Addr_L; Send byte word address; while (!IIC1S_IICIF); wait until IBIF; IIC1S_IICIF=1; clear interrupt event flag; while(IIC1S_RXAK); check RXAK; //-Slave occurred-IIC1C_RSTA repeated start; IIC1D IIC_SLAVE temp (slave_address) while (!IIC1S_IICIF); wait until IBIF; Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs IIC1S_IICIF=1; clear interrupt event flag; while (IIC1S_RXAK); check RXAK; //-Slave occurred-IIC1C_TX receive; IIC1C_TXAK acknowledge disable; RD_data IIC1D; dummy read; while (!IIC1S_IICIF); wait until IBIF; IIC1S_IICIF=1; clear interrupt event flag; IIC1C_MST generate stop signal; RD_data IIC1D; read right data; return RD_data;
Example Read Byte 9S12 Family (MC9S12DT512 24C512 Used)
typedef union word EE_Address; struct byte Address_H; byte Address_L; }Bytes; }tAddr; tAddr ADDR; #define Address ADDR.EE_Address #define Addr_L ADDR.Bytes.Address_L #define Addr_H ADDR.Bytes.Address_H void IIC_read_byte(word addr) Address addr; IIC0_IBCR_TXAK TXAK IIC0_IBCR 0x30; RX/TX MS/SL TXAK generate START condition; IIC0_IBDR slavewrite; Address slave master transmit; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBDR Addr_H; Send high byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBDR Addr_L; Send byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; //-Slave occurred-IIC0_IBCR_RSTA repeated start; IIC0_IBDR slaveread; (slave_address) while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while (IIC0_IBSR_RXAK); check RXAK; Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs //-Slave occurred-IIC0_IBCR_TX_RX receive; IIC0_IBCR_TXAK acknowledge disable; RD_data IIC0_IBDR; dummy read; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; IIC0_IBCR_MS_SL generate stop signal; RD_data IIC0_IBDR; read right data;
Example gives routine 9S12 core 24C512 EEPROM block-write block-read functions.
Example Block-Write Block-Read 9S12 Core 24C512 EEPROM (MC9s12XDT512 Used)
void IIC_write_block(word addr, byte len) byte page; Address addr; load address; page len; load length data pack written; if(page MAX_PAGE) page MAX_PAGE; limit; IIC0_IBCR_TXAK TXAK IIC0_IBCR 0x30; RX/TX MS/SL TXAK generate START condition; IIC0_IBDR slavewrite; Address slave master transmit; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; IIC0_IBDR Addr_H; Send high byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; IIC0_IBDR Addr_L; Send byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; for(i=0;i<page;i++) IIC0_IBDR WRData[i]; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; IIC0_IBCR_MS_SL generate stop signal; void IIC_read_block(word addr,word len) byte dummy; Address addr; length len; if(length MAX_LENGTH) length MAX_LENGTH; IIC0_IBCR_TXAK TXAK IIC0_IBCR 0x30; RX/TX MS/SL generate START condition; Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs IIC0_IBDR slavewrite; Address slave master transmit; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; IIC0_IBDR Addr_H; Send high byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; IIC0_IBDR Addr_L; Send byte word address; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while(IIC0_IBSR_RXAK); check RXAK; IIC0_IBCR_RSTA repeated start; IIC0_IBDR slaveread; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; while (IIC0_IBSR_RXAK); check RXAK; IIC0_IBCR_TX_RX receive; dummy IIC0_IBDR; dummy read; for(i=0;i<length-1;i++) while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; RDData[i] IIC0_IBDR; save data RAM; IIC0_IBCR_TXAK acknowledge disable; while (!IIC0_IBSR_IBIF); wait until IBIF; IIC0_IBSR_IBIF=1; clear interrupt event flag; IIC0_IBCR_MS_SL generate stop signal; RDData[i] IIC0_IBDR; save data RAM;
Example with Interrupt Used
This section shows options when interrupt service routine used: master write read from slave used slave
3.4.1
Master
This routine used when main software loop cannot poll communication sequence. first action executes only main loop; this first write into data register. IIC-interrupt-service routine then maintains whole communication. Example explains MCU.
Example IIC-Module-Initialization Routine
void Init_IIC(void) IICF IICA IICS 0x12; IICC 0xC0;
frequency divider register: 8MHz 400kHz; slave address this module; clear IBAL IICIF flags; enable module with interrupt;
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs
Example shows Read_block Write_block functions serial EEPROM 24AA256 MC9S08QG8 main loop:
Example Read_block Write_block Functions (24AA256 EEPROM MC9S08QG8 Used)
void IIC_read_block(word addr,byte len) Address addr; length len; interrupt only; IIC_Res_flg interrupt only; flag defines receive function interrupt service routine; if(length MAX_LENGTH) length MAX_LENGTH; IICC_TXAK RX/TX MS/SL TXAK IICC 0x30; generate START condition; IICD IIC_SLAVE; Address slave master transmit; void IIC_write_block(word addr, byte len) Address addr; load address; length len; load length data pack written; interrupt only; IIC_Res_flg interrupt only; flag defines transmit function interrupt service routine; if(length MAX_PAGE) length MAX_PAGE; limit; IICC_TXAK RX/TX MS/SL TXAK IICC 0x30; generate START condition; IICD IIC_SLAVE; Address slave master transmit;
flag variable byte variable used interrupt service routine recognize which byte communication protocol processed. Example shows read function from serial EEPROM (24LC16B) (S12DP256B) main loop.
Example EEPROM (24LC16B) (S12DP256B) Main Loop
void i2c_read_byte(unsigned char read_addr) flag temp read_addr; IBCR_MS_SL transmit master mode; IBCR_TX_RX generate start condition; IBDR slave_IIC_addr;
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs
temp variable common byte variable; flag variable used interrupt service routine recognize which communication-protocol byte processed. Then, interrupt-service-routine code would shown Example
Example Interrupt-Service-Routine Code MC9S08QG8 24C512 EEPROM
_interrupt void isrViic(void) IICS_IICIF clear interrupt event flag; switch(flag) case mode; IICD Addr_H; Send high byte word address; flag++; return; case mode; IICD Addr_L; Send byte word address; flag++; return; case mode; if(length) IICD WR_Data[i]; length-; i++; return; else IICC_MST generate stop signal; flag IIC_Res_flg IIC_OK; write cycle; return; case IICD Addr_H; Send high byte word address; flag++; return; case IICD Addr_L; Send byte word address; flag++; return; case IICC_RSTA repeated start; IICD IIC_SLAVE
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Software Routines MCUs flag++; return; case IICC_TX dummy IICD; flag++; return; case if(length RD_Data[i] IICD; length-; i++; return; else if(length IICC_TXAK RD_Data[i] IICD; i++; flag++; return; case IICC_MST //RD_Data[i] IICD; flag IIC_Res_flg IIC_OK; return;
receive; dummy read;
save data RAM;
acknowledge disable; save data RAM;
generate stop signal; save data RAM;
3.4.2
Slave
This routine used when presented slave device bus. needs catch bytes intended recognition valid bytes based match slave address saved IBAD register. master sends address bus, slave generates interrupt when this address matches slave address IBAD register. Then, example, slave saves bytes from buffer processes them later. Example shows slave (S12DP256B) connected master same type (two EVBS12DP256B boards connected together). variables defined are:
byte RD_data[20]; byte i2c_cnt, temp;
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Conclusion
Example Slave-Initialization Routine
void Init_IIC(void) IBFD 0x2B; IBAD My_IIC_addr; IBCR 0xC0; IBSR_IBAL
frequency divider register: 8MHz 91kHz; slave address this module; enable module interrupts, mode, Slave mode, clear IBAL flag;
Example Interrupt-Service Routine
_interrupt void I2C_ISR(void) if(IBSR_IAAS) IBCR_TX_RX IBSR_SRW; clear IAAS bit; IBSR IBSR_IBIF_MASK; temp IBDR; i2c_cnt else IBSR IBSR_IBIF_MASK; RD_data[i2c_cnt] IBDR; i2c_cnt++;
Rx/Tx mode accordance received calling address byte clear flag; dummy read initiate read data byte; clear received data counter;
clear flag; save received data data buffer;
Conclusion
This application note explains using module Freescale's HC908, 9S08, 9S12 family MCUs. user routines tested mentioned MCUs boards. serial EEPROMs often used devices serve good examples. need something other than device (for example, real-time clock [RTC]), change device address (0xD0 RTC, 0xA0 EEPROM) manage right byte sequence, described appropriate data sheet.
Module M68HC08, HCS08, HCS12 MCUs, Rev. Freescale Semiconductor
Reach
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