Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions Charl

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Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions Charl

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AN3045 Rev. 5/2006
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions
Charles Melear Infotainment, Multimedia, Telematics Division
Overview
Table Contents
Overview Changes Hardware Specification Electrical Timing Characteristics. Electrical Characteristics- Memory Interface. Pins HRESET Reset Configuration Changes Programmer's Interface Clock Enable Register -MBAR 0x0214 48-MHz Fractional Divider Configuration Register-MBAR 0x0210 SDRAM Memory Controller BestComm PCI. Registers Added Implement Enhanced AC97 Mode. LPC/GPIO 3.10 MSCAN 3.11 Codes Documentation
This document describes basic differences between MPC5200B (Mask M62C Rev. prior revisions MPC5200 microprocessors. context this document, MPC5200B always refers device built with Mask M62C Rev. MPC5200B adds enhancements device, including updated SDRAM memory controller, upgrades programmable serial controller, other functions improve operation device. Fixes known errata were also incorporated into MPC5200B, well features improved testability. MPC5200B microcontroller based e300 core using PowerPCinstruction set. MPC5200B pinout identical predecessor, MPC5200. While MPC5200B compatible with prior versions MPC5200, there significant differences electrical characteristics pins, particularly with respect drive strength slew rate capabilities SDRAM Bus.
Freescale Semiconductor, Inc., 2006. rights reserved.
Changes Hardware Specification
When upgrading existing MPC5200 design MPC5200B, imperative that circuit board layout signal line impedance matching issues checked proper performance. particular, series termination resistors, shown Figure must match board line impedance closely possible. NOTE Place termination resistors close package pins possible.
Address Control
Address Control
MPC5200B Data
Memory Data
Circuit Board Trace Impedance
Figure Proper Series Termination Resistors
Changes Hardware Specification
Electrical Timing Characteristics
target electrical timing characteristics MPC5200B MPC5200 hardware specifications.
Electrical Characteristics-Memory Interface
improved interface (DQS) results changed timing specification. Refer MPC5200B User's Guide details.
Pins
Additional Schmitt Trigger inputs have been added these pins better noise rejection: PSC1_3 PSC2_3 PSC3_2 PSC6_3 JTAG_TCK
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Hardware Specification
pins associated with ports used BITCLOCK AC97 interface CLOCK CODEC interface. JTAG_TCK clock input JTAG interface. Schmitt Triggers these inputs improve noise immunity/rejection well system performance reliability. This improvement does require system level design changes.
HRESET
MPC5200B HRESET asserted when Power Reset asserted, regardless whether SYS_XTAL clock running not. prior versions MPC5200, running system clock required configure internal circuitry driving HRESET pin. This means that period time between application power start SYS_XTAL clock, HRESET driven specified value. random chance HRESET assumed logic output value, HRESET would rise along with during power until system clock started. soon SYS_XTAL clock started, HRESET would actively driven logic (assuming that currently being driven logic Some applications used HRESET hold various peripherals, including certain FLASH memory devices, reset state. allowing HRESET float logic during time that power being applied, these peripherals would momentarily taken reset. some cases, this condition responsible memory corruption issues. Actively forcing HRESET MPC5200B logic while Power Reset asserted, even SYS_XTAL clock started, avoids these reset issues.
Reset Configuration
During reset (HRESET PORRESET), reset configuration word latched related reset configuration word register with each rising edge SYS_XTAL signal. both resets (HRESET PORRESET) inactive (high), contents this register locked.
(MPC5200)
4096 clocks SYS_XTAL PORRESET HRESET RST_CFG_WRD
sample sample sample sample sample sample sample sample
clocks
sample sample sample sample LOCK LOCK (MPC5200)
Figure Reset Configuration Word Locking
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
MPC5200B, well prior versions device, pins that configured assertion Power Reset/HRESET will maintain their reset state long HRESET asserted. That even though configuration word sampled each rising edge SYS_XTAL clock, actual microcontroller pins maintain their reset state until HRESET released. Upon release HRESET, various pins assume state controlled configuration word. versions MPC5200 prior MPC5200B, configuration word latched locked into reset configuration register second rising edge SYS_XTAL clock after release HRESET. This meant that external circuitry driving various configuration pins prior versions MPC5200 continue drive configuration pins additional SYS_XTAL clock cycles after HRESET released insure that configuration word properly latched. Also, other devices that could possibly drive configuration pins held reset these SYS_XTAL clock cycles that potential conflict issues would avoided. MPC5200B latches locks configuration word into reset configuration register first rising edge SYS_XTAL after release HRESET. This change makes external configuration word circuitry easier design significantly reduces hold time logic driving reset configuration word.
Changes Programmer's Interface
There some differences programmer's interface between MPC5200B prior versions MPC5200. Some registers were added, some reserved bits used provide extra functionality.
Clock Enable Register-MBAR 0x0214
(psc345_clk_en) separated into bits psc3_clk_en, psc4_clk_en, psc5_clk_en. function bits IR_TX IR_RX replaced psc4_clk_en psc5_clk_en, respectively. Only bits have changed between MPC5200B prior versions MPC5200. prior versions MPC5200, bits clock enable register were associated with function. function been removed from MPC5200B, along with functionality these bits. this register prior versions MPC5200 used enable clock PSC3, PSC4, PSC5. MPC5200B, bits used enable clock PSC5 PSC4 respectively. Now, only enables clock PSC3. versions MPC5200, RESET state clock enable bits clock enable register logic That clock enable bits enable. software prior versions MPC5200 have changed work MPC5200B. Specifically, user's current software wrote bits logic user wants PSC4 PSC5, these bits will have written logic user's software does write this register, then software changes will required. That PSC4 PSC5 will enabled after release reset.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.1.1
Clock Enable Register MPC5200B
mem_ clk_en pci_ clk_en lpc_ clk_en timer_ clk_en lpc_ clk_en timer_ clk_en slt_ clk_en gpio_ clk_en slt_ clk_en gpio_ clk_en
RESET: RESET:
Reserved Write bdlc_clk_
mscan_ clk_en mem_ clk_en mscan_ clk_en
scom_ clk_en
ata_ clk_en
eth_ clk_en
usb_ clk_en
spi_ clk_en
psc5_ clk_en
psc4_ clk_en
psc3_ clk_en
psc2_ clk_en
psc1_ clk_en
psc6 clk_en
Figure Clock Enable Register MPC5200B
3.1.2
Clock Enable Register Prior Versions MPC5200
pci_ clk_en i2c_ clk_en
RESET: RESET:
Reserved Write bdlc_clk_ psc345_ clk_en
scom_ clk_en
irrx_ clk_en
irtx_ clk_en
psc2_ clk_en
psc1_ clk_en
ata_ clk_en
eth_ clk_en
usb_ clk_en
spi_ clk_en
Figure Clock Enable Register Prior Versions MPC5200
Note: MPC5200B does contain module that present prior versions MPC5200. clock enable bits referred above enabled clocks this module; however, module, there CODEC mode that does implement function. This note information only.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
psc6 clk_en
i2c_ clk_en
Changes Programmer's Interface
48-MHz Fractional Divider Configuration Register-MBAR 0x0210
(ext_usb_clk_sync) added. ability synchronize external clock with internal buses added improve performance above Mbit/second. user should this when using higher speeds. default state logic which causes external 48-MHz clock synchronized with internal clock. user's software prior versions MPC5200 wrote this logic then changes software will required MPC5200B; however, user wants take advantage this feature, software will have modified. That will need logic Only this register affected.
3.2.1
48-MHz Fractional Divider Configuration Register MPC5200B
Reserved Write ext_usb_ sync_en ext_usb_ 48mhz_en ext_irda_ 48mhz_en Reserved Write fd_en
RESET:
Rsrvd Write RESET:
Rsrvd Write
Rsrvd Write
Rsrvd Write
cfgd_p3_cnt
cfgd_p2_cntt
cfgd_p1_cnt
cfgd_p0_cnt
Figure 48-MHz Fractional Divider Configuration Register MPC5200B
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.2.2
48-MHz Fractional Divider Configuration Register Prior Versions MPC5200
ext_usb_ 48mhz_en ext_irda_ 48mhz_en Reserved Write fd_en
RESET:
Reserved Write
Rsrvd Write RESET:
Rsrvd Write
Rsrvd Write
Rsrvd Write
cfgd_p3_cnt
cfgd_p2_cntt
cfgd_p1_cnt
cfgd_p0_cnt
Figure 48-MHz Fractional Divider Configuration Register Prior Versions MPC5200
3.3.1
SDRAM Memory Controller
Module Design
hardware SDRAM memory controller been redesigned; however, module complete backward software compatibility with prior versions MPC5200.
3.3.2
Multiple Open Pages
support multiple open pages internal function MPC5200B memory controller. adds functionality SDRAM interface does require change software.
3.3.3
Support 16-bit Memory Interface
SDRAM supports both 16-bit 32-bit memory structures. SDRAM control register (MBAR 0x0104) been added select between modes. convert existing MPC5200 design MPC5200B, should logic (select 32-bit port size).
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.3.4
3.3.4.1
RESET:
SDRAM Memory Controller Control Register-MBAR 0x0104
Memory Controller Control Register MPC5200B
mode Rsvd Rsvd drive addr _rule Reserved soft _ref soft _pre ref_interval[0:5]
Rsvd
RESET:
Reserved
dqs_oe
Figure Memory Controller Control Register 20065200B
3.3.4.2
Memory Controller Control Register Prior Versions MPC5200
Rsvd mode Rsvd drive addr _rule Reserved soft _ref soft _pre ref_interval[0:5]
RESET:
Rsvd
RESET:
Reserved
dqs_oe
Figure Memory Controller Control Register Prior Versions MPC5200
3.3.5
BURST TERMINATION
BURST TERMINATION SDRAM controller command. This command functional revisions MPC5200 prior MPC5200B. BURST TERMINATION command fully functional MPC5200B.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
BURST command issued automatically SDRAM memory controller terminate burst read write when only word data needs transferred. This function handled automatically SDRAM memory controller. This hardware change inside SDRAM memory controller effect system software. BURST TERMINATION command simply improves performance SDRAM bus.
3.3.6
Wakeup from Deep Sleep Mode
MPC5200B SDRAM memory controller automatically handles putting external memory devices into self-refresh mode when processor enters deep sleep mode. Likewise, when deep sleep mode MPC5200B exited, SDRAM memory controller automatically causes SDRAM exit self-refresh mode. Note that SDRAMs from various manufacturers require certain amounts delay time between exiting self-refresh mode resuming data fetches. responsibility software writer insure that this delay enforced. When entering deep sleep mode, SDRAM memory controller automatically issues series commands SDRAM memory devices them into self-refresh mode. SDRAM memory controller also controls state clock enable properly SDRAM devices into self-refresh mode. Hardware wakeup from deep sleep causes SDRAM memory controller automatically issue series commands SDRAM memory devices take them self-refresh mode. Also, state MPC5200B clock enable line properly SDRAM memory controller. change software required because this hardware change, other than enforce proper amount delay between exiting self-refresh mode SDRAM devices first memory access those devices.
3.3.7
32-bit 64-bit Gasket
gasket improved read clock recovery circuit internal improvements that affect system software. This change hardware change only improvement internal system performance.
3.3.8
Read Data Sampling Circuitry
Configuration register MBAR 0x0108 been added swt2rwp field. width single write read-write-precharge delay field been increased from bits. default state added logic prior versions MPC5200, this reserved. user software versions MPC5200 prior MPC5200B should checked that added written logic insure compatibility.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.3.9
3.3.9.1
RESET:
SDRAM Memory Controller Configuration Register MBAR 0x0108
Memory Controller Configuration Register MPC5200B
Rsvd act2rw srd2rwp swt2rwp rd_latency
pre2act
RESET:
Rsvd
ref2act
wr_latency
Reserved
Figure Memory Controller Configuration Register MPC5200B Table Memory Controller Configuration Register Field Descriptions
Name swt2rwp Description Single Write Read/Write/Precharge delay. Limiting case Write Precharge. DDR, suggested value (tWR clk) SDR, suggested value (tWR)
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.3.9.2
Memory Controller Configuration Register Prior Versions MPC5200
Rsvd swt2rwp Rsvd act2rw srd2rwp rd_latency
RESET: RESET: Rsvd
pre2act
ref2act
wr_latency
Reserved
Figure Memory Controller Configuration Register Prior Versions MPC5200 Table Memory Controller Configuration Register Field Descriptions
Name swt2rwp Reserved Single Write Read/Write/Precharge delay. Limiting case Write Precharge. DDR, suggested value (tWR clk) SDR, suggested value (tWR) Description
3.3.10 Read Clock Recovery (RCR)-Registers Added
read clock recover registers located from MBAR 0x090 MBAR 0xBC. User software MUST write these registers. User software should checked make sure that these memory locations accessed insure MPC5200B compatibility.
3.4.1
BestComm
Snoop Enable Added Arbiter
arbiter configuration register been added. This enables BestComm address snooping. This feature enabled from release reset. BestComm unit fetches data from memory places read line buffer preparation transmitting that data through peripheral elements, such Ethernet port. writes memory location just accessed BESTComm unit before data transmitted from read line buffer, snooping logic will mark data dirty read line buffer cause arbiter re-fetch fresh data from memory. User software should checked ensure that this desired setting.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.4.2
3.4.2.1
RESET:
BESTComm Arbiter Configuration Register- MBAR 0x1F40
Arbiter Configuration Register MPC5200B
PLDIS Rsvd BSDIS
Rsvd
Rsvd
RESET:
Figure Arbiter Configuration Register MPC5200B Table Arbiter Configuration Field Descriptions
Name BSDIS Description BestComm snooping disable. BestComm address snooping enabled. BestComm address snooping disabled.
3.4.2.2
RESET:
Arbiter Configuration Register Prior Versions MPC5200
PLDIS Rsvd
RESET:
Rsvd
Rsvd
Figure Arbiter Configuration Register Prior Versions MPC5200 Table Arbiter Configuration Field Descriptions
1:15 Name Reserved Description
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.4.3
External Breakpoint
SDMA debug module control register, both MPC5200B prior versions MPC5200, exactly alike; however, versions MPC5200 prior Revision "EB" bits work. MPC5200B, bits work described. these bits were logic versions MPC5200 prior Revision external breakpoints would cause BestComm unit halt. software written versions MPC5200 prior Revision "EB" bits logic this software used MPC5200B, external breakpoints will cause BestComm unit halt. compatibility, check software that "EB" bits logic when upgrading MPC5200B. This affect existing user software that uses SDMA debug module control register MBAR 0x1278.
3.4.3.1 3.4.3.2
RESET:
SDMA Debug Module Control Register-MBAR 0x1278 SDMA Debug Module Control Register MPC5200B
Block Tasks
RESET:
Comparator Type Comparator Type and/
breakpoints
Figure Debug Module Control Register MPC5200B Table SDMA Debug Module Control Field Descriptions
0:15 Name Block Tasks Description Specify each tasks 15-0, whether block that task with detection breakpoint (bit halts TASK halts TASK etc) block task Block task AutoArm-specifies whether triggered dbgStatusReg[16] will automatically reset following saving context breakpoint. This reset. Triggered will automatically reset Triggered will automatically reset Breakpoint-This specifies whether take breakpoint. This reset. Disable breakpoints Enable breakpoints Comparator type-These bits specify type data that been loaded into comparator
18:20
Comparator Type
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
Table SDMA Debug Module Control Field Descriptions (continued)
21:23 Name Comparators Type Description Comparator type-These bits specify type data that been loaded into comparator AND/OR-This specifies what type operation used with comparators. This reset. Indicates OR'ing comparators Indicates AND'ing comparators
25:28
breakpoints euBreakpoint These bits indicate that breakpoint occurred four execution units. Each execution unit dedicated these bits indicates that associated execution unit issued breakpoint. These bits sticky must overwritten continue. These bits cleared zero reset. MPC5200B integrated only EU3. Enable external breakpoint cause HALT condition. enable external breakpoint cause halt condition Allow external breakpoint cause halt condition Enable internal breakpoint enable internal breakpoint cause halt condition Allow internal breakpoint cause halt condition Master breakpoint enable (this must always allow kind breakpoint halt task) Disable external breakpoint Enable external breakpoint
3.4.3.3
SDMA Debug Module Control Register Prior Versions MPC5200
Block Tasks
RESET: RESET:
Comparator Type Comparator Type and/
breakpoints
Figure SDMA Debug Module Control Register Prior Versions MPC5200
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
Table SDMA Debug Module Control Field Descriptions
0:15 Name Block Tasks Description Specify each tasks 15-0, whether block that task with detection breakpoint (bit halts TASK halts TASK etc) block task Block task AutoArm-specifies whether triggered dbgStatusReg[16] will automatically reset following saving context breakpoint. This reset. Triggered will automatically reset Triggered will automatically reset Breakpoint-This specifies whether take breakpoint. This reset. Disable breakpoints Enable breakpoints Comparator type-These bits specify type data that been loaded into comparator Comparator type-These bits specify type data that been loaded into comparator AND/OR-This specifies what type operation used with comparators. This reset. Indicates OR'ing comparators Indicates AND'ing comparators
18:20 21:23
Comparator Type Comparators Type
25:28
breakpoints euBreakpoint These bits indicate that breakpoint occurred four execution units. Each execution unit dedicated these bits indicates that associated execution unit issued breakpoint. These bits sticky must overwritten continue. These bits cleared zero reset. MPC5200B integrated only EU3. Enable external breakpoint cause HALT condition. enable external breakpoint cause halt condition Allow external breakpoint cause halt condition Enable internal breakpoint enable internal breakpoint cause halt condition Allow external breakpoint cause halt condition Master breakpoint enable (this must always allow kind breakpoint halt task) Disable external breakpoint Enable external breakpoint
3.4.4
External BestComm Request (GPIO)
ability simple interrupt GPIO BestComm requestors been added. SDMA requestor muxcontrol register encoding values have been expanded values %10. These values allow various simple interrupt GPIO pins selected BestComm requestors. This affect user software. User code should checked make sure that reserved values were used software written MPC5200 devices prior MPC5200B insure software compatibility.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.4.5
RESET:
SDMA Requestor MuxControl-MBAR 0x125C
Req31 Req30 Req29 Req28 Req27 Req26 Req25 Req24
RESET:
Req23
Req22
Req21
Req20
Req19
Req18
Req17
Req16
Figure SDMA Request MuxControl Table SDMA Request MuxControl Field Descriptions
Name Req31 Description MPC5200B (Mask M62C Rev. Requestor (RESERVED) GPIO_PSC2_3 GPIO_IRDA_1 Always Requestor Requestor (RESERVED) GPIO_PSC2_2 GPIO_IRDA_0 Always Requestor Requestor (RESERVED) GPIO_PSC2_1 GPIO_ETH_3 Always Requestor Requestor (RESERVED) GPIO_PSC2_0 GPIO_ETH_2 Always Requestor Requestor (RESERVED) GPIO_PSC1_3 GPIO_ETH_1 Always Requestor Requestor IrDA (PSC_6) GPIO_PSC1_2 GPIO_ETH_0 Always Requestor Requestor IrDA (PSC_6) GPIO_PSC1_1 GPIO_USB_3 Always Requestor Requestor I2C1_TX GPIO_PSC1_0 GPIO_USB_2 Always Requestor Description Prior Versions MPC5200 Requestor (RESERVED) 01-10 active requestor Always Requestor Requestor (RESERVED) 01-10 active requestor Always Requestor Requestor (RESERVED) 01-10 active requestor Always Requestor Requestor (RESERVED) 01-10No active requestor Always Requestor Requestor (RESERVED) 01-10 active requestor Always Requestor Requestor IrDA (PSC_6) 01-10 active requestor Always Requestor Requestor IrDA (PSC_6) 01-10 active requestor Always Requestor Requestor I2C1_TX 01-10 active requestor Always Requestor
Req30
Req29
Req28
Req27
10:11
Req26
12:13
Req25
14:15
Req24
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
Table SDMA Request MuxControl Field Descriptions (continued)
16:17 Name Req23 Description MPC5200B (Mask M62C Rev. Requestor I2C1_RX GPIO_SINT_7 GPIO_USB_1 Always Requestor Requestor I2C2_TX GPIO_SINT_6 GPIO_USB_0 Always Requestor Requestor I2C2_RX GPIO_SINT_5 GPIO_PSC3_5 Always Requestor Requestor PSC4_TX GPIO_SINT_4 GPIO_PSC3_4 Always Requestor Requestor PSC4_RX GPIO_SINT_3 GPIO_PSC3_3 Always Requestor Requestor PSC5_TX GPIO_SINT_2 GPIO_PSC3_2 Always Requestor Requestor PSC5_RX GPIO_SINT_1 GPIO_PSC3_1 Always Requestor Requestor GPIO_SINT_0 GPIO_PSC3_0 Always Requestor Description Prior Versions MPC5200 Requestor I2C1_RX 01-10 active requestor Always Requestor Requestor I2C2_TX 01-10 active requestor Always Requestor Requestor I2C2_RX 01-10 active requestor Always Requestor Requestor PSC4_TX 01-10 active requestor Always Requestor Requestor PSC4_RX 01-10 active requestor Always Requestor Requestor PSC5_TX 01-10 active requestor Always Requestor Requestor PSC5_RX 01-10 active requestor Always Requestor Requestor 01-10 active requestor Always Requestor
18:19
Req22
20:21
Req21
22:23
Req20
24:25
Req19
26:27
Req18
28:29
Req17
30:31
Req16
3.5.1
PCI-Packet Size Increase
packet size PCITPSR(RW)-0x3800-The Packet_Size field been increased width from bits. done counts PCITDCR(R)-0x3818-The Bytes_Done field been increased from bits. Packets_Done field been moved packets done counts PCITPDCR(R) MBAR 0x3820, this field been increased from bits. packets done counts register-PCITPDCR(R) MBAR 0x3820-for changed Packets_Done increased field size from bits.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
packet size PCIRPSR(RW)-0x3880-The Packet_Size field been increased width from bits. RxDone counts PCIRDCR(R)-0x3898-The Bytes_Done field been increased from bits. Packets_Done field been moved packets done counts PCIRPDCR(R) MBAR 0x38A0, this field been increased from bits. packets done counts register-PCIRPDCR(R) MBAR 0x38A0-for changed Packets_Done increased field size from bits.
3.5.2
3.5.2.1
RESET:
Packet Size PCITPSR(RW)-MBAR 0x3800
Packet Size PCITPSR(RW) MPC5200B
Packet_Size[31:16]
RESET:
Packet_Size[15:2]
PacketSize[1:0]
Figure Packet Size PCITPSR(RW) MPC5200B Table Packet Size PCITPSR(RW) Field Descriptions
Bits 0:31 Name Packet_Size Description User writes number bytes transmit controller send over PCI.The bits hardwired low; only 32-bit data transfers FIFO allowed. Writing this register also completes Restart Sequence long Master Enable bit, PCITER[ME], high Reset Controller bit, PCITER[RC], low.
3.5.2.2
RESET:
Packet Size PCITPSR(RW) Prior Versions MPC5200
Packet_Size[16:2] Packet_Size[1:0]
RESET:
Reserved
Figure Packet Size PCITPSR(RW) Prior Versions MPC5200
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
Table Packet Size PCITPSR(RW) Field Descriptions
Bits 0:15 Name Packet_Size Description User writes number bytes transmit controller send over PCI.The bits hardwired low; only 32-bit data transfers FIFO allowed. Writing this register also completes restart sequence long master enable bit, PCITER[ME], high reset controller bit, PCITER[RC], low. Unused. Software should write zero these bits.
16:31
Reserved
3.5.3
3.5.3.1
RESET:
Bytes Done Counts PCITDCR(R)-MBAR 0x3818
Bytes Done Counts PCITDCR(R) MPC5200B
Bytes_Done
RESET:
Bytes_Done
Figure Bytes Done Counts PCITDCR(R) MPC5200B Table Bytes Done Counts PCITDCR(R) Field Descriptions
Bits 0:31 Name Bytes_Done Description This status register indicates number bytes transmitted since start packet. updated each successful data beat. normally terminated packets, Bytes_Done value Packet_Size values will equal. continuous mode active Bytes_Done value will read zero successful packet, Packets_Done field will incremented.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.3.2
RESET:
Done Counts PCITDCR(R) Prior Versions MPC5200B
Bytes_Done
RESET:
Packets_Done
Figure Done Counts PCITDCR(R) Prior Versions MPC5200B Table Done Counts PCITDCR(R) Field Descriptions
Bits 0:15 Name Bytes_Done Description This status register indicates number bytes transmitted since start packet. updated each successful data beat. normally terminated packets, Bytes_Done value Packet_Size values will equal. continuous mode active, Bytes_Done value will read zero successful packet, Packets_Done field will incremented. This status register indicates number packets transmitted active only continuous mode effect. counter reset following occurs Reset controller bit, PCITER[RC], asserted (normal restart continuous mode) Master enable bit, PCITER[ME], becomes negated Master enable reset Packets_Done status without disturbing continuous mode addressing. point time, total number bytes transmitted calculated (Packets_Done Packet_Size) Bytes_Done This assumes Packet_Size same restart sequences.
16:31
Packets_Done
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.4
3.5.4.1
RESET:
Packet Size PCIRPSR(RW)-MBAR 0x3880
Packet Size PCIRPSR(RW) MPC5200B
Packet_Size[31:16]
RESET:
Packet_Size[15:2]
Packet_Siz[1:
Figure Packet Size PCIRPSR(RW) MPC5200B Table Packet Size PCIRPSR(RW) Field Descriptions
Bits 0:31 Name Packet_Size Description user writes this register with number bytes receive controller fetch over PCI. bits hardwired low; only 32-bit data transfers FIFO allowed. Writing this register also completes restart sequence long master enable bit, PCIRER[ME], high reset controller bit, PCIRER[RC], low.
3.5.4.2
RESET
Packet Size PCIRPSR(RW) Prior Versions MPC5200
Packet_Size[16:2] Packet_Size[ 1:0!]
RESET
Reserved
Figure Packet Size PCIRPSR(RW) Prior Versions MPC5200
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
Table Packet Size PCIRPSR(RW) Field Descriptions
Bits 0:15 Name Packet_Size Description user writes this register with number bytes receive controller fetch over PCI. bits hardwired low; only 32-bit data transfers FIFO allowed. Writing this register also completes restart sequence long master enable bit, PCIRER[ME], high reset controller bit, PCIRER[RC], low. Unused bits. Software should write zero these bits. error generated
16:31
Reserved
3.5.5
3.5.5.1
RESET:
Bytes Done Counts PCIRDCR(R) -MBAR 0x3898
Bytes Done Counts PCIRDCR(R) MPC5200B
Bytes_Done
RESET:
Bytes_Done
Figure Bytes Done Counts PCIRDCR(R) MPC5200B Table Bytes Done Counts PCIRDCR(R) Field Descriptions
Bits 0:31 Name Bytes_Done Description This status register indicates number bytes received since start packet. updated each successful data beat. normally terminated packets, Bytes_Done value Packet_Size values equal. continuous mode active, Bytes_Done value reads successful packet, Packets_Done field incremented.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.5.2
RESET:
RxDone Counts PCIRDCR(R) Prior Versions MPC5200
Bytes_Done
RESET:
Packets_Done
Figure RxDone Counts PCIRDCR(R) Prior Versions MPC5200 Table xDone Counts PCIRDCR(R) Field Descriptions
Bits 0:15 Name Bytes_Done Description This status register indicates number bytes received since start packet. updated each successful data beat. normally terminated packets, Bytes_Done value Packet_Size values equal. continuous mode active, Bytes_Done value reads successful packet, Packets_Done field incremented. This status register indicates number packets received. active only continuous mode effect. following occurs, counter reset: Reset controller bit, PCIRER[RC], asserted (normal restart continuous mode) Master enable bit, PCIRER[ME], negated this way, master enable used reset Packets_Done status without disturbing continuous mode addressing. point time total number Bytes received calculated (Packets_Done Packet_Size) Bytes_Done This assumes Packet_Size same restart sequences.
16:31
Packets_Done
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.6
3.5.6.1
RESET:
Packets Done Counts PCITPDCR(R) -MBAR 0x3820
Packets Done Counts PCITPDCR(R) MPC5200B
Packets_Done
RESET:
Packets_Done
Figure Packets Done Counts PCITPDCR(R) MPC5200B Table Packets Done Counts PCITPDCR(R) Field Descriptions
Bits 0:31 Name Packets_Done Description This status register indicates number packets transmitted active only continuous mode effect. counter reset following occurs Reset controller bit, PCITER[RC], asserted (normal restart continuous mode) Master enable bit, PCITER[ME], becomes negated Master enable reset Packets_Done status without disturbing continuous mode addressing. point time, total number bytes transmitted calculated (Packets_Done Packet_Size) Bytes_Done This assumes Packet_Size same restart sequences.
packets done counts register been added MPC5200B. There corresponding register prior versions MPC5200.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.7
3.5.7.1
RESET:
Packets Done Counts PCIRPDCR(R) -MBAR 0x38A0
Packets Done Counts PCIRPDCR(R) MPC5200B
Packets_Done
RESET:
Packets_Done
Figure Packets Done Counts PCIRPDCR(R) MPC5200B Table Packets Done Counts PCIRPDCR(R) Field Descriptions
Bits 0:31 Name Packets_Done Description This status register indicates number packets received. active only continuous mode effect. following occurs, counter reset: Reset controller bit, PCIRER[RC], asserted (normal restart continuous mode) Master enable bit, PCIRER[ME], negated this way, master enable used reset Packets_Done status without disturbing continuous mode addressing. point time total number Bytes received calculated (Packets_Done Packet_Size) Bytes_Done This assumes Packet_Size same restart sequences.
packets done counts register been added MPC5200B. There corresponding register prior versions MPC5200.
3.5.8
XTPCI Write Combining Programmability
target control register PCITCR(RW)-0xD6C-has additional bits write combine feature: 23-WCD-write combine disable Bits[24:31]-WCT[7:0] write combine timer purpose this feature, added MPC5200B, allows partial packets incoming data transferred break incoming data occurs greater than specified write combine timer.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
This feature hardware function that added improve system performance does affect user software. This feature disabled PCITCR register. NOTE MPC5200B allows external burst write internal Bus. Prior versions MPC5200 allow external initiator write burst Bus.
3.5.9
3.5.9.1
Target Control Register PCITCR(RW) -MBAR 0x0D6C
Target Control Register PCITCR(RW) MPC5200B
Reserved Reserved
RESET:
RESET:
Reserved
Write Combine Timer [7:0]
Figure Target Control Register PCITCR(RW) MPC5200B Table Target Control Field Descriptions
Bits 16:22 Name Reserved Description Unused bits. Software should write zero this register.
Write Combine This control applies only when MPC5200 Target. When set, prevents Disable Controller from automatically combining write data sent burst, (WCD) possible. Instead, data transferred soon possible single-beat transactions. Better target write performance achieved when this cleared. Write Combine This register contains timer value, clocks, used when partial burst been Timer (WCT) buffered target write data path write data stops being transferred local memory from external device. Every time sequential beat write data stored buffer, counter reset with this value. partial burst data been buffered, thereby activating count-down counter, this field reprogrammed value less than current counter value, counter will jump down write combine timer value. This way, software force write buffer flush data more quickly than when counter initialized. reset value write combine timer 0x08. bits programmable.
24:31
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.9.2
Target Control Register PCITCR(RW) Prior Versions MPC5200
Reserved Reserved
RESET:
RESET:
Reserved
Figure Target Control Register PCITCR(RW) Prior Versions MPC5200 Table Target Control Field Descriptions
Bits 16:31 Name Reserved Description Unused bits. Software should write zero this register.
3.5.10 PCITTCR PCIRTCR
transaction control register PCITTCR transaction control register PCIRTCR
prior revisions MPC5200, setting Max_Retries field either PCITTCR PCIRTCR registers 0xFF 0x00 would allow INFINITE retries. MPC5200B only uses value 0x00 allow INFINITE retries. Now, value 0xFF will specify retires.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.11 Transaction Control Register PCITTCR(RW) -MBAR 0x3808
3.5.11.1 Transaction Control Register PCITTCR(RW) MPC5200B
RESET: RESET: 0111 Reserved Reserved Reserved PCI_cmnd Max_Retries
Reserved
Max_Beats
Figure Transaction Control Register PCITTCR(RW) MPC5200 Table Transaction Control Field Descriptions
Bits 8:15 Name Max_Retries Description user writes this field with maximum number retries permit perpacket. retry counter reset when packet completes normally terminated master abort, target abort, abort exceeding retry limit. slow malfunctioning target might issue infinite disconnects therefore permanently bus. finite (0x01 0xff) Max_Retries value will detect this condition generate interrupt. Setting Max_Retries 0x00 will generate interrupt.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.11.2 Transaction Control Register PCITTCR(RW) Prior Versions MPC5200
RESET: RESET: 0111 Reserved Reserved Reserved PCI_cmnd Max_Retries
Reserved
Max_Beats
Figure Transaction Control Register PCITTCR(RW) Prior Versions MPC5200 Table Transaction Control Field Descriptions
Bits 8:15 Name Max_Retries Description user writes this field with maximum number retries permit perpacket. retry counter reset when packet completes normally terminated master abort, target abort, abort exceeding retry limit. slow malfunctioning Target might issue infinite disconnects therefore permanently bus. finite (0x01 0xfe) Max_Retries value will detect this condition generate interrupt. Setting Max_Retries 0x00 0xff will generate interrupt.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.12 Transaction Control Register PCIRTCR(RW)-MBAR 0x3888
3.5.12.1 Transaction Control Register PCIRTCR(RW) MPC5200B
RESET: RESET: Reserved 1100 Reserved Reserved Reserved PCI_cmnd Max_Retries
Max_Beats
Figure Transaction Control Register PCIRTCR(RW) MPC5200B Table Transaction Control Field Descriptions
Bits 8:15 Name Max_Retries Description user writes this field with maximum number retries permit packet. retry counter reset when packet completes normally terminated master abort, target abort, abort exceeding retry limit. slow malfunctioning Target might issue infinite disconnects therefore permanently bus. finite (0x01 0xff) Max_Retries value will detect this condition generate interrupt. Setting Max_Retries 0x00 will generate interrupt.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.5.12.2 Transaction Control Register PCIRTCR(RW) Prior Versions MPC5200
RESET: RESET: Reserved 1100 Reserved Reserved Reserved PCI_cmnd Max_Retries
Max_Beats
Figure Transaction Control Register PCIRTCR(RW) Prior Versions MPC5200 Table Transaction Control Field Descriptions
Bits 8:15 Name Max_Retries Description user writes this field with maximum number retries permit packet. retry counter reset when packet completes normally terminated master abort, target abort, abort exceeding retry limit. slow malfunctioning Target might issue infinite disconnects therefore permanently bus. finite (0x01 0xfe) Max_Retries value will detect this condition generate interrupt. Setting Max_Retries 0x00 0xff will generate interrupt.
3.6.1
Serial Interface Control Register Bits SICR (MBAR PSCx 0x40)
MultiWd functionality moved renamed ESAI. More than audio sample transferred start each frame when this mode enabled. number samples transferred frame determined (frame sync frequency)., CTUR (frame sync length), Codec mode (8-,16-, 32-bit). becomes bit. When this enabled, data sample transferred every transition frame signal. (frame sync frequency) determines frame length, Codec mode (8-,16-, 32-bit) determines size data transferred. becomes ESAI bit. added enable enhanced AC97 mode. added enable/disable generation occurrence UART errors. These changes will affect user software CODEC applications.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.1.1
Serial Interface Control Register (MBAR PSCx 0x40) Modes MPC5200B
DTS1 SHDIR SIM[3:0] ACRB
RESET:
RESET: GenClk
ClkPol
SyncPol
CellSlave
Cell2xClk
ESAI
EnAC97
RESET:
MSTR
CPOL
CPHA
UseEOF
Disable_EOF
Reserved
Figure Serial Interface Control Register (MBAR PSCx 0x40) Modes MPC5200B Table Serial Interface Control Field Descriptions
Name Codec-I2S mode mode supported works mode Other modes-Reserved Codec-enhanced serial audio interface doesn't support ESAI mode. supports ESAI mode. This mode allows send receive more data word frame, frame length greater than word length. sends only complete data words. Other modes-Reserved Codec-enhanced AC97 mode-takes effect only when AC97 mode selected (SIM 0x3) effect AC97 mode selected, uses enhanced AC97 mode transmit receive data. Other modes-Reserved UART/SIR -Disable generation UART receiver generates UART error detected. more information's regarding UART errors (RB, FE,PE, CDE,). UART receiver doesn't generate UART error detected Other modes-Reserved Reserved Description
ESAI
EnAC97
Disable_
22:23
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.1.2
Serial Interface Control Register (MBAR PSCx 0x40) Modes Prior Versions MPC5200
DTS1 SHDIR SIM[3:0] ACRB
RESET:
RESET: GenClk
MultiWd
ClkPol
SyncPol
CellSlave
Cell2xClk
Reserved
RESET:
MSTR
CPOL
CPHA
UseEOF
Reserved
Figure Serial Interface Control Register (MBAR PSCx 0x40) Modes Prior Versions MPC5200 Table Serial Interface Control Field Descriptions
Name MultiWd Description Codec-Multi word mode sends receives only data word frame, even frame length greater than word length. sends receive more data word frame, frame length greater than word length. send only complete data words. This used support mode. Other modes-Reserved Reserved Reserved
14:15 21:23
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.2
Infrared Control (MBAR PSCx 0x44) IRCR1
This register controls configuration IrDA modes (SIR/MIR/FIR). 2-INV_RX added inverting incoming receive signal. This register controls configuration IrDA modes (SIR/MIR/FIR).
3.6.2.1
Infrared Control (MBAR PSCx 0x44) Mode MPC5200B
Reserved
Reserved
RESET:
INV_RX
Reserved
SPUL
Reserved
RESET:
SIPEN
Reserved
Figure Infrared Control (MBAR PSCx 0x44) MIR/FIR Modes MPC5200B Table Infrared Control Field Descriptions
Name INV_RX Description FIR-Invert line receiver doesn't invert receive line. receiver invert receive line. Other modes-Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.2.2
Infrared Control MBAR PSCx (0x44) Mode Prior Versions MPC5200
Reserved
RESET:
Reserved
SPUL
Reserved
RESET:
SIPEN
Reserved
Table Infrared Control (MBAR PSCx 0x44) MIR/FIR Modes Prior Versions MPC5200 Table Infrared Control Field Descriptions
Name Reserved Description
This been added additional functionality when using SIR/MIR/FIR modes programmable serial controller. This allows incoming data inverted. default state this logic that compatible with prior versions MPC5200.
3.6.3
Enhanced AC97 Mode
number changes were made assist software using AC97 interface PSC. addition, will hardware sample rate conversion used some AC97 codecs. creates AC97 frames hardware using registers bits when enhanced AC97 mode enabled. ISR/IMR/SR (PSC_MBAR 0x14 0x04) bits [12:15] have been added event status AC97 enhanced mode.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.4
3.6.4.1
Interrupt Status Register (MBAR PSCx 0x14)
Interrupt Status Register (MBAR PSCx 0x14) UART Mode MPC5200B
ORERR TxEMP RxRDY FFULL TxRDY Reserved Error Reserved Reserved
RESET:
Figure Interrupt Status Register (MBAR PSCx 0x14) UART Mode MPC5200B
ORERR URERR Reserved RxRDY FFULL TxRDY DEOF Error CMD_SEND DATA_OVR DATA_VALID UNEX_RX_ SLOT
Reserved
Reserved
RESET:
Figure Interrupt Status Register (MBAR PSCx 0x14) Other modes Table Interrupt Status Field Descriptions
Name Error Description Error This identical error register. clear this interrupt, reset error status command register.
CMD_SEND Enhanced AC97 mode-command send ready This identical CMD_SEND register. clear this interrupt, reset error status command register. Other modes-Reserved DATA_OVR Enhanced AC97 mode-receive data overwrite This identical DATA_OVR register. clear this interrupt, reset error status command register. Other modes-Reserved DATA_VALI Enhanced AC97 mode-received status data This identical DATA_VALID register. clear this interrupt, reset error status command register. Other modes-Reserved UNEX_RX_ Enhanced AC97 mode-unexpected slots detect SLOT This identical UNEX_RX_SLOT register. clear this interrupt, reset error status command register. Other modes-Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.4.2
Interrupt Status Register (MBAR PSCx 0x14) UART Mode Prior Versions MPC5200
ORERR URERR RxRDY FFULL TxRDY Reserved Reserved
RESET:
Figure Interrupt Status Register (MBAR PSCx 0x14) UART Mode Prior Versions MPC5200
ORERR URERR Reserved RxRDY FFULL TxRDY DEOF Reserved
Reserved
RESET:
Figure Interrupt Status Register (MBAR PSCx 0x14) Other Modes Table Interrupt Status Field Descriptions
9:15 Name Reserved Description
SICR EnAC97, enables enhanced AC97 mode. this mode enabled, interface behaves same MPC5200
3.6.4.3
Serial Interface Control Register (MBAR PSCx 0x40) Modes
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.4.4
Serial Interface Control Register (MBAR PSCx 0x40) Modes MPC5200B
DTS1 SHDIR SIM[3:0] ACRB
RESET:
RESET: GenClk
ClkPol
SyncPol
CellSlave
Cell2xClk
ESAI
EnAC97
RESET:
MSTR
CPOL
CPHA
UseEOF
Disable_EOF
Reserved
Figure Serial Interface Control Register (MBAR PSCx 0x40) Modes MPC5200B Table Serial Interface Control Field Descriptions
Name Codec-I2S mode mode supported works mode Other modes-Reserved Codec-enhanced serial audio interface doesn't support ESAI mode. supports ESAI mode. This mode allows send receive more data word frame, frame length greater than word length. sends only complete data words. Other modes-Reserved Codec -enhanced AC97 mode-takes effect only when AC97 mode selected. (SIM effect AC97 mode selected "Enhanced AC97" mode transmit receive data. Other modes-Reserved UART/SIR -disable generation UART receiver generate UART error detected. more information's regarding UART errors (RB, FE,PE, CDE). UART receiver doesn't generate UART error detected. Other modes-Reserved Reserved Description
ESAI
EnAC97
Disable_
22:23
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.6.4.5
Serial Interface Control Register (MBAR PSCx 0x40) Modes Prior Versions MPC5200
DTS1 SHDIR SIM[3:0] ACRB
RESET:
RESET: GenClk
MultiWd
ClkPol
SyncPol
CellSlave
Cell2xClk
Reserved
RESET:
MSTR
CPOL
CPHA
UseEOF
Reserved
Figure Serial Interface Control Register (MBAR PSCx 0x40) Modes Prior Versions MPC5200 Table Serial Interface Control Field Descriptions
Name MultiWd Description Codec-multi word mode sends receives only data word frame, even frame length greater than word length. sends receives more data word frame, frame length greater than word length. send only complete data words. This used support mode. Other modes-Reserved Reserved Reserved
14:15 21:23
Registers Added Implement Enhanced AC97 Mode
following registers have been added MPC5200B implement enhanced AC97 mode: AC97_SLOTS (PSC_MBAR 0x24)-defines active data slots AC97 frame AC97_CMD (PSC_MBAR 0x28)-interface AC97 mixer registers AC97_DATA (PSC_MBAR 0x2C)-interface AC97 mixer register read
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.7.1
AC97 Slots Register (0x24)-AC97Slots
This register been added MPC5200B implement enhanced AC97 mode. This write-only register defines which slots expected receive AC97 frame which slots will sent AC97 frame. received frame doesn't match expected slots, [UNEXP_RX_SLOTS] will set. This register affect only AC97 mode selected SICR register, EnAC97 active.
3.7.1.1
RESET:
AC97 Slots Register (MBAR PSCx 0x24)-AC97Slots
Reserved Reserved TX_Slots[3:12]
RESET:
Reserved Reserved RX_Slots[3:12]
Figure AC97 Slots Register (MBAR PSCx 0x24)-AC97Slots Table AC97 Slots Field Descriptions
6:15 Name TX_Slots[3:12] Reserved Enhanced AC97 mode-expected receive slots bits this register specify which data slots [3:12] will sent AC97 frame. AC97 transmitter will this information generate Slot0 read according number data words from TXFIFO. TXFIFO empty empty AC97 frame will sent until data available. Other modes-Reserved 16:21 22:3` RX_Slots[3:12]
Reserved
Description
Enhanced AC97 mode-expected receive slots bits this register specify which data slots [3:12] receive AC97 frame must contain valid data. AC97 Codec selects valid data slots setting according data valid Slot0[12:3]. received valid slots match expected slots unexpected slot received state occurs. Only received slots match expected slots, will received data written RXFIFO. receiver detects AC97 frame without data (frame empty contains only status data), unexpected slot received state will occur. Other modes-Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.7.2
AC97 Command Register (MBAR PSCx 0x28)- AC97CMD
This register been added MPC5200B implement enhanced AC97 mode. This register contains AC97 address transmit slot1 AC97 command data transmit slot write access byte this register will [CMD_SEND] one. AC97 transmitter generates frame with valid slot1 slot2 paste values this register next transmitted slot1 slot2. data sent, then [CMD_SEND] will cleared transmitter.
3.7.2.1
RESET:
AC97 Command Register (MBAR PSCx 0x28)-AC97CMD
AC97 Control Register Index AC97 Command Data[15:8]
RESET:
AC97 Command Data[7:0]
Reserved
Figure AC97 Command Register (MBAR PSCx 0x28)-AC97CMD Table AC97 Command Field Descriptions
Name AC97 Description Enhanced AC97 mode-AC97 command This indicates access Control Register read write access. will pasted Slot1 write access read access Other modes-Reserved Enhanced AC97 mode-AC97 address register This register contains target control register address. will pasted Slot1 Other modes-Reserved
AC97 Control Register Index
6:23
AC97 Command Enhanced AC97 mode-AC97 command data register Data This register used define command data value write command. will pasted Slot2 Other modes-Reserved Reserved
24:31
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.7.3
AC97 Status Data Register (MBAR PSCx 0x2C)- AC97Data
This register been added MPC5200B implement enhanced AC97 mode. This read-only register contains received response AC97 read command. this register contains data, then [DATA_VALID] will receiver. read access this register clears [DATA_VALID] bit.
3.7.3.1
AC97 Status Data Register (MBAR PSCx 0x2C)-AC97Data
Reserved AC97 Register Index Echo AC97 Control Register Read Data[15:8]
RESET:
Reserved
RESET:
AC97 Control Register Read Data[7:0] Reserved
Reserved
Figure AC97 Status Data Register (MBAR PSCx 0x2C)-AC97Data Table AC97 Status Data Field Descriptions
Name AC97 Register Index Echo Reserved Enhanced AC97 mode-AC97 register index echo This register contains received register index echo from Slot0. Other modes-Reserved 6:23 AC97 Control Register ReadData Enhanced AC97 mode-AC97 control register read data This register contains received control data from Slot2. Other modes-Reserved Reserved Description
24:31
BitClkDiv[0:7] field Codec clock register been moved from bits [8:15] bits [16:23]. bits [8:15] BitClkDiv[8:15]. CODEC mode used, software written prior versions MPC5200 will need modified.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.7.4
Codec Clock Register (MBAR PSCx 0x20)-CCR
This register defines divider Frame BitClk generation Codec mode. This register value only effect GenClk control register SICR one. UART, SIR, AC97 mode, this register reserved.
3.7.4.1
Codec Clock Register (MBAR PSCx 0x20)-CCR MPC5200B
RESET: RESET:
FrameSyncDiv[0:7]
BitClkDiv[8:15]
BitClkDiv[0:7]
Reserved
Figure Codec Clock Register (MBAR PSCx 0x20)-CCR Codec Mode MPC5200B
RESET: RESET:
Reserved
BitClkDiv[8:15]
BitClkDiv[0:7]
Reserved
Figure Codec Clock Register (MBAR PSCx 0x20)-CCR MIR/FIR Mode MPC5200B
RESET: Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface RESET:
Reserved
Figure Codec Clock Register (MBAR PSCx 0x20)-CCR Other Modes MPC5200B Table Codec Clock Field Descriptions
Name FrameSyncDiv Description Codec-frame sync divider FrameSync generated internally dividing down Clock. FrameSyncDiv defines number clock cycles between active frame edges: FrameSync Length FrameSyncDiv[0:7] Codec SPI-delay before (DSCKL) When mode (SICR[SPI] FrameSyncDiv divider used determine length time delays after goes low/active before first transition serial transfer. This feature that exists QSPI. following equation determines actual delay before SCK: Other modes-Reserved Note: value 0x00 stops this counter disables clock generator. 8:23 BitClkDiv Codec-bit clock divider clock generated internally dividing down Mclk frequency follows: Codec SPI-baud rate generated internally dividing down Mclk frequency follows: FIR-Irda clock IrdaClk generated internally dividing down Mclk frequency follows: Other modes-Reserved Note: value 0x00 stops this counter disables clock generator.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.7.4.2
Codec Clock Register (MBAR PSCx 0x20)-CCR Codec Mode Prior Versions MPC5200
RESET:
FrameSyncDiv[0:7]
BitClkDiv[0:7]
Figure Codec Clock Register (MBAR PSCx 0x20)-CCR Codec Mode Prior Versions MPC5200
RESET:
Reserved
BitClkDiv[0:7]
Figure Codec Clock Register (MBAR PSCx 0x20)- MIR/FIR Mode Prior Versions MPC5200
RESET:
Reserved
Figure Codec Clock Register (MBAR PSCx 0x20)- Other Modes Prior Versions MPC5200 Table Codec Clock Field Descriptions
Name FrameSyncDiv Description Codec-frame sync divider Frame sync generated internally dividing down Clock frequency follows: FrameSync frequency BitClk (FrameSyncDiv[0:7] Codec SPI-delay before (DSCKL) When mode (SICR[SPI] FrameSyncDiv divider used determine length time delays after goes low/active before first transition serial transfer. This feature that exists QSPI. following equation determines actual delay before SCK: Other modes-Reserved Note: value 0x00 stops this counter disables clock generator. 8:15 BitClkDiv Codec-bit clock divider clock generated internally dividing down Mclk frequency follows: Codec SPI-baud rate generated internally dividing down Mclk frequency follows: FIR-Irda clock IrdaClk generated internally dividing down Mclk frequency follows: Other modes-Reserved Note: value 0x00 stops this counter disables clock generator.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.7.5
More Clock Dividers UART Baud Rate Generation
value field (PSC_MBAR 0x04) will select divide prescaler. value field (PSC_MBAR 0x04) will disable clock generation. UART mode, fields programmed %1110 (disable clock generation) %1111 (choose divide prescaler UART receive clock generation). mode, fields programmed %1110 (disable clock generation). These codes invalid versions MPC5200 prior MPC5200B. these codes were used versions MPC5200 prior MPC5200B, existing user software should compatible with MPC5200B.
3.7.6
3.7.6.1
RESET:
Clock Select Register (MBAR PSCx 0x04)
Clock Select Register UART Mode MPC5200B0
Reserved
Figure Clock Select Register (MBAR PSCx 0x04) UART Mode MPC5200B
RESET:
Reserved
Figure Clock Select Register (MBAR PSCx 0x04) Other Modes MPC5200B Table Clock Select Field Descriptions
Name Description UART-receiver clock select register 0000 -1101 choose prescaler UART receive clock generation 1110 disable clock generation 1111 choose prescaler UART receive clock generation -clock select register 1110 disable clock generation others choose prescaler receive clock generation Other modes-Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
Table Clock Select Field Descriptions (continued)
Name Description UART-transmitter clock select register 0000 -1101 choose prescaler UART transmit clock generation 1110 disable clock generation 1111 choose prescaler UART transmit clock generation -clock select register 1110 disable clock generation others choose prescaler transmit clock generation Other modes-Reserved Reserved
8:15
3.7.6.2
Clock Select Register UART Mode Prior Versions MPC5200
RESET: Reserved
Figure Clock Select Register (MBAR PSCx 0x04) UART Mode Prior Versions MPC5200
RESET:
Reserved
Figure Clock Select Register (MBAR PSCx 0x04) Other Modes Prior Versions MPC5200 Table Clock Select Field Descriptions
Name UART -receiver clock enable 0000 -1101 enable clock generation 1110 -1111 disable clock generation Other modes-Reserved UART -transmitter clock enable 0000 -1101 enable clock generation 1110 -1111 disable clock generation Other modes-Reserved Reserved Description
8:15
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.8.1
Frequency Divider Register (MFDR) MBAR 0x3D04
Bits were added additional prescaler bits. These bits have been added increase length length prescaler. default state these bits from release RESET %00, which compatible with prior versions MPC5200. user software should checked state these bits changed. not, user code prior versions MPC5200 should compatible with MPC5200B.
3.8.2
3.8.2.1
RESET:
Frequency Divider Register (MFDR)-MBAR 0x3D04 0x3D44
Frequency Divider Register MPC5200B
FDR[7:0] Reserved
RESET:
Reserved
Figure Frequency Divider Register MPC5200B
Table Frequency Divider Field Descriptions MPC5200B
Name FDR[7:6] Description These bits prescale divider input module clock.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.8.2.2
RESET:
II2C Frequency Divider Register Prior Versions MPC5200
Reserved FDR[5:0] Reserved
RESET:
Reserved
Figure Frequency Divider Register Prior Versions MPC5200 Table Frequency Divider Field Descriptions Prior Versions MPC5200
Name Reserved Description
3.8.3
Filter Register (IFR) MBAR 0x3D24-New Register
Bits [0:7] control configuration glitch filters. These bits functionality MPC5200B programming filter reject noise pulses input. Pulses clock cycles wide rejected. default state these bits from release RESET %00000000, which compatible with prior versions MPC5200.The user software should checked state these bits changed. not, user code prior versions MPC5200 should compatible with MPC5200B.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.8.3.1
RESET:
Filter Register MPC5200BI
Resv Resv Resv Resv Reserved
RESET:
Reserved
Figure Filter Register MPC5200B Table Filter Register Field Descriptions
Name FR[7:4] Reserved Bits contain programming controls width glitch terms IPBUS clock cycles) that filter should absorb; that filter will pass glitches less than equal this width setting. FR[] 3210 0000 Filter Bypass 0001 Filter glitches width IPBUS clock cycle 0010 Filter glitches width IPBUS clock cycles 0011 Filter glitches width IPBUS clock cycles 0100 Filter glitches width IPBUS clock cycles 0101 Filter glitches width IPBUS clock cycles 0110 Filter glitches width IPBUS clock cycles 0111 Filter glitches width IPBUS clock cycles 1000 Filter glitches width IPBUS clock cycles 1001 Filter glitches width IPBUS clock cycles 1010 Filter glitches width IPBUS clock cycles 1011 Filter glitches width IPBUS clock cycles 1100 Filter glitches width IPBUS clock cycles 1101 Filter glitches width IPBUS clock cycles 1110 Filter glitches width IPBUS clock cycles 1111 Filter glitches width IPBUS clock cycles Reserved Description
8:31
3.8.4
I2S/GPIO
Additional functionality been added MPC5200B. These changes allow pins port function general purpose output.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.8.5
GPIO Output-Only Enables Register MBAR 0x0B18
These bits have been added enable individual pins port general purpose outputs. default state logic This leaves pins under control port configuration bits. user software should checked state these bits changed. not, user code prior versions MPC5200 should compatible with MPC5200B.
3.8.5.1
GPIO Output-Only Enables Register MPC5200B
ETHR
RESET:
Reserved
Reserved
RESET:
Figure GPIO Output-Only Enables Register MPC5200B Table GPIO Output-Only Enables Field Descriptions
Name ETHR Description Individual bits enable each output only GPIO pin-all reside Ethernet port. controls GPIO_ETHO_7 (ETH_7 pin) controls GPIO_ETHO_6 (ETH_6 pin) controls GPIO_ETHO_5 (ETH_5 pin) controls GPIO_ETHO_4 (ETH_4 pin) controls GPIO_ETHO_3 (ETH_3 pin) controls GPIO_ETHO_2 (ETH_2 pin) controls GPIO_ETHO_1 (ETH_1 pin) controls GPIO_ETHO_0 (ETH_0 pin) Disabled GPIO (default) Enabled GPIO 12:15 Reserved Individual bits enable each output only GPIO pin-all reside ports. controls I2C2_CLK (I2C_2 pin) controls I2C2_IO (I2C_3 pin) controls I2C1_CLK (I2C_0 pin) controls I2C1_IO (I2C_1 pin) Disabled GPIO (default) Enabled GPIO This bits used toggle clock (SCL) data (SDA) lines interface. 16:31 Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.8.6
GPIO Output-Only Data Value Register MBAR 0x0B1C
these bits enabled general purpose outputs, logic value applied respective pins read using this register.
3.8.6.1
RESET:
GPIO Output-Only Data Value Register MPC5200B
ETHR
Reserved
RESET:
Reserved
Figure GPIO Output-Only Data Value Register MPC5200B Table GPIO Output-Only Data Value Field Descriptions
Name ETHR Description Individual bits control state enabled output only GPIO pins. controls GPIO_ETHO_7 (ETH_7 pin) controls GPIO_ETHO_6 (ETH_6 pin) controls GPIO_ETHO_5 (ETH_5 pin) controls GPIO_ETHO_4 (ETH_4 pin) controls GPIO_ETHO_3 (ETH_3 pin) controls GPIO_ETHO_2 (ETH_2 pin) controls GPIO_ETHO_1 (ETH_1 pin) controls GPIO_ETHO_0 (ETH_0 pin) Drive (default) Drive 12:15 Reserved Individual bits control state enabled output only GPIO pins reside ports. controls I2C2_CLK (I2C_2 pin) controls I2C2_IO (I2C_3 pin) controls I2C1_CLK (I2C_0 pin) controls I2C1_IO (I2C_1 pin) Drive (default) Drive This bits used toggle clock (SCL) data (SDA) lines interface. 16:31 Reserved
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
LPC/GPIO
port configuration register MBAR 0x0B00 1-LPTZ added port configuration register
This added change functionality certain pins LocalPlus when operating non-muxed mode (LPC). this left logic (default condition), pins will retain their original functionality changes software will required. When this logic GPIO_WKUP_7 TEST_SEL_1 pins retain functionality prior versions MPC5200. When this set, functionality GPIO_WKUP_7 switched TSIZ1 functionality TEST_SEL_1 switched TSIZ2.
3.9.1
3.9.1.1
Port Configuration Register-MBAR 0x0B00
Port Configuration Register MPC5200B
LPTZ ALTs IR_USB_CLK IRDA Ether
RESET:
RESET:
PCI_DI
USB_S
PSC3
PSC2
PSC1
Figure Port Configuration Register MPC5200B Table Port Configuration Field Descriptions
Name LPTZ Description LocalPlus non-muxed TSIZ gpio_wkup_7 test_sel_1 TSIZ gpio_wkup_7 TSIZ test_sel_1
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.9.1.2
Port Configuration Register Prior Versions MPC5200
Rsvd ALTs IR_USB_CLK IRDA Ether
RESET:
RESET:
PCI_DI
USB_S
PSC3
PSC2
PSC1
Figure Port Configuration Register Prior Versions MPC5200 Table Port Configuration Field Descriptions
Name Reserved Description
software from prior versions MPC5200, this should checked that remains logic compatibility with MPC5200B.
3.10 MSCAN
MSCAN control register (CANCTL1)MBAR 0x0901 MSCAN control register (CANCTL1)MBAR 0x0981 1-CLKSRC CANCTL1
prior versions MPC5200, same clock source used both MSCAN modules. This requirement changed. Now, clock source each MSCAN module independently selected. user software should checked make sure that CLKSRC appropriately each MSCAN module's control register select desired MSCAN clock source.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Changes Programmer's Interface
3.10.1 MSCAN Control Register (CANCTL1)-MBAR 0x0901 0x981
3.10.1.1 MSCAN Control Register MPC5200B
CLKSRC CANE LOOPB LISTEN Rsvd WUPM SLPAK INITAK SLPAK INITAK
RESET:
Figure MSCAN Control Register MPC5200B Table MSCAN Control Field Descriptions
Name CLKSRC Description MSCAN clock source-bit defines MSCAN module clock source (only systems with system clock generation module. MSCAN clock source clock CLK) MSCAN clock source oscillator clock (SYS_XTAL_IN) Note: MSCAN modules have different selected clock sources.
3.10.1.2 MSCAN Control Register Prior Versions MPC5200B
CLKSRC CANE LOOPB LISTEN Rsvd WUPM
RESET:
Figure MSCAN Control Register Prior Versions MPC5200B Table MSCAN Control Field Descriptions
Name CLKSRC Description MSCAN clock source-bit defines MSCAN module clock source (only systems with system clock generation module. MSCAN clock source clock CLK) MSCAN clock source oscillator clock (SYS_XTAL_IN) Note: Both MSCAN modules have only same selected clock source.To select oscillator clock CLKSRC CANCTL1 register must MSCAN1 OR/AND MSCAN2.
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Documentation
3.11 Codes
MPC5200B different codes from prior versions MPC5200. codes MPC5200B presented Table
Table Codes
Code PVR_COP SVR_COP XLBArb Device JTAG IDCODE 8082 2011 8011 0012 (rev1.2) 0001 5803 1057 0001 101d MPC5200 MPC5200B 8082 2014 (G2_LE rev1.4) 8011 0020 (1st samples) 8011 0022 (prod. samples) 0001 5809 1057 1001 101d
Documentation
following documents models available. MPC5200B User Manual "MPC5200B Data Sheet" "MPC5200B Errata" MPC5200B IBIS Model MPC5200B BSDL File
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
Documentation
THIS PAGE INTENTIONALLY BLANK
Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions, Rev. Freescale Semiconductor
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AN3045 Rev. 5/2006

Comparison MPC5200B (Mask M62C) with Prior MPC5200 Versions Charl

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