Software Migration from (AMCC) 440GP MPC8540 Paul Wilson NCSD App

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Document Number: AN2661 Rev. 01/2007
Software Migration from (AMCC) 440GP MPC8540
Paul Wilson NCSD Applications Freescale Semiconductor, Inc. Austin,
embedded systems become more complex, software complexity deciding factor when system designed built. cost porting code sometimes offset benefits that come with additional features processor platform. Fortunately, software migration easy, especially when staying within processor core architecture. This document details device driver lower-level software migration from 440GP Embedded PowerPCprocessor Applied Micro Circuits Corporation (AMCC) Freescale PowerQUICCIII product family. Both processors PowerPC based, software migration caveats, leaving architects with decisions based more hardware functionality processor feature sets.
Contents Feature Comparison Software Migration Overview SDRAM Interrupt Controller General-Purpose Timers Transfers Buffer Descriptors Ethernet UART PCI-X Conclusions Document Revision History
Feature Comparison
440GP embedded PowerPC processor includes PowerPC core (based 32-bit implementation Book architecture) well following integrated peripherals: SDRAM memory controller Fast Ethernet controllers
Freescale Semiconductor, Inc., 2004, 2007. rights reserved.
Feature Comparison
32-/64-bit PCI-X UART capability Peripheral
Freescale PowerQUICC architecture based latest embedded PowerPC architecture Book definition uses high performance e500 core with 256-Kbytes Level cache. PowerQUICC also offers integrated 10/100/1000 three-speed Ethernet controllers (TSEC), SDRAM memory controller, 64-bit PCI-X/PCI controller, RapidIO interconnect. MPC8540 MPC8560 examples PowerQUICC integrated communication processors: MPC8540 integrated host processor Ethernet only options (two 10/100/1000 Mbps interfaces 10/100 Mbps interface) with dual UART interfaces provide highest level performance integration lower system cost. MPC8560 integrated communication processor. This device differs from MPC8540 that includes dedicated RISC communications controller (referred CPM) handling communication protocols. MPC8560 supports three fast serial communications channels (FCCs) Mbps ATM, 10/100 Ethernet, HDLC rates. Support full-duplex, time-division-multiplexed (TDM) channels using multi-channel controllers (MCCs) provided. addition, MPC8560 supports four serial communications controllers (SCCs), serial peripheral interface (SPI), interface. This application note discusses software migration from 440GP embedded PowerPC processor Freescale MPC8540 PowerQUICC processor. Table compares these devices, highlighting features common both processors. features 440GP subset features MPC8540, enabling easy hardware migration PowerQUICC family. Also, features common both processors similar from software point view, enabling reasonably easy migration from 440GP MPC8540 from both hardware software prospective.
Table Feature Comparison 440GP versus MPC8540
Feature Core frequency Core architecture cache (I/D) SRAM/L2 cache 440GP 32-bit Book PowerPC 32-/32-Kbytes 8-Kbytes SRAM/No MPC8540 32-bit Book PowerPC 32-/32-Kbytes 256-Kbytes 256-Kbytes SRAM 128-/128-Kbytes 32-/64-bit, Gbytes external/22 internal
controller User programmable memory controller Interrupt controller channels
32-/64-bit, Gbytes external/45 internal
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Software Migration Overview
Table Feature Comparison 440GP versus MPC8540 (continued)
Feature RapidIO PCI-X (32-/64-bit) Ethernet UART Technology Power 440GP v2.2 33/66 PCI-X 10/100 0.25 MPC8540 8-bit parallel RapidIO v2.2 33/66 PCI-X 10/100 10/100/1 Gbit 0.13
Software Migration Overview
High-level software such real-time operating system (RTOS) high-level applications running RTOS (for example, server) should affected processor selection. RTOS typically uses board support package (BSP) communicate with underlying hardware, this subject change with hardware. Changes outside scope this document because these changes only RTOS dependent, hardware dependent. During migration hardware platform, device drivers most affected software element. device driver communicates with anything external processor through mechanisms internal processor. This includes, limited interrupt handling, Ethernet physical layer devices (PHYs) through internal MAC, memory devices through DDR-SDRAM memory controller, RS-232 transceivers through UART interface, internal controller. porting code from 440GP MPC8540, differences features common both processors discussed: SDRAM controller Interrupt controller General purpose timers transfers Ethernet UART PCI-X byte ordering 440GP MPC8540 big-endian, enabling easy software migration.
SDRAM
similarities between integrated DDR-SDRAM controllers MPC8540 440GP follows:
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
SDRAM
440GP programmable SDRAM controller that supports SDRAMs provide 64-bit interface SDRAM memory with optional error checking correction (ECC). controller supports page mode operation with bank interleaving always active maintain eight open pages. controller supports four 512-Mbytes logical banks limited configurations, providing memory Gbytes. Global memory timings, address bank sizes, memory addressing modes programmable. System power reduced placing SDRAM controller sleep and/or self-refresh mode. PowerQUICC fully programmable SDRAM controller which supports JEDEC complaint DDR-I SDRAM standard memories (333-MHz data rate) with optional ECC. PowerQUICC supports page mode operation retain currently active SDRAM page pipelined burst accesses simultaneously open pages each memory bank). Fourteen multiplexed address signals logical bank signals provide support device densities Mbits Gbits. Four chip select signals provided support physical banks memory each from Mbytes Gbytes size DIMM modules. these banks provide theoretical maximum 4-Gbytes main memory, Gbytes could span entire 32-bit address space. However, since space must reserved boot ROM, configuration registers other important addressable locations, maximum memory limited Gbytes.
However, there differences DDR-SDRAM controllers MPC8540 440GP configured, explained following sections.
440GP DDR-SDRAM Controller
440GP uses indirectly accessed registers configure SDRAM controller. These registers accessed through SDRAM0_CFGADDR SDRAM0_CFGDATA registers. system reset processor, software must configure then enable SDRAM controller. registers configure 440GP SDRAM controller shown following tables. Table shows SDRAM0_CFG0 register, which enables specific features SDRAM controller.
Table 440GP SDRAM0_CFG0
Bits
Name DCEN MCHK RDEN DMWD UIOS
Description SDRAM controller enabled/disabled enabled/disabled Registered DIMM enabled/disabled Page management unit enabled/disabled SDRAM width 64-bit Unused state Page deallocation policy
Undocumented bits reserved.
Table shows SDRAM0_CFG1 register, which enables SDRAM controller power management self-refresh features.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
SDRAM
Table 440GP SDRAM0_CFG1
Bits
Name PMEN Self-refresh entry
Description
Power management enabled/disabled
Undocumented bits reserved.
Table shows SDRAM0_DEVOPT register, which allows configuration defined SDRAM device-specific options.
Table 440GP SDRAM0_DEVOPT
Bits
Name
Description SDRAM device enabled/disabled SDRAM device drive strength
Undocumented bits reserved.
440GP SRAM controller supports four logical banks. Table shows SDRAM0_BnCR registers configure enable memory each logical bank.
Table 440GP SDRAM0_BnCR
Bits 12-14 16-18
Name SDBA SDSZ SDAM SDBE Base address DDR-SDRAM size
Description
SDRAM address mode/memory organization Memory bank enabled
Undocumented bits reserved.
Table shows SDRAM0_TR0 register, which used configure DDR-SDRAM device-specific timing parameters.
Table 440GP SDRAM0_TR0
Bits 12-13 14-15 16-17 Name SDWR SDWD SDCL SDPA SDCP SDLD Description SDRAM write recovery SDRAM write-to-write delay SDRAM latency SDRAM precharge command next activate command minimum SDRAM read/write precharge command command SDRAM command leadoff
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
SDRAM
Table 440GP SDRAM0_TR0 (continued)
Bits 27-29 30-31
Name SDRA SDRD
Description SDRAM refresh command next activate SDRAM delay
Undocumented bits reserved.
SDRAM0_TR1 register used control various aspects SDRAM read data path.
MPC8540 DDR-SDRAM Controller
MPC8540 DDR-SDRAM controller registers directly accessed shown following tables. Table shows chip select memory bound registers (CSn_BNDS), which define address range memory banks controlled that chip select.
Table MPC8540 CSn_BNDS
Bits 16-23
Name
Description Starting address chip select (bank) address chip select (bank)
Undocumented bits reserved.
Table shows chip select configuration registers (CSn_CONFIG), which define memory organization (number row/columns).
Table MPC8540 CSn_CONFIG
Bits 21-23 29-31
Name CS_n_EN AP_n_EN Chip select enable
Description
Chip select auto precharge enable bits SDRAM chip select column bits SDRAM chip select
Undocumented bits reserved.
Table shows SDRAM timing configuration register (TIMING_CFG1), which defines timing intervals between various SDRAM control commands.
Table MPC8540 TIMING_CFG1
Bits 9-11 13-15 Name PRETOACT ACTTOPRE ACTTORW CASLAT Description Precharge activate interval (trp) Activate precharge interval (tras) Activate read/write interval SDRAM (trcd) latency from read command
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
SDRAM
Table MPC8540 TIMING_CFG1 (continued)
Bits 16-19 22-23 25-27 30-31
Name REFREC WRREC ACTTOACT WRTORD
Description Refresh recovery time (trfc) Last data precharge interval (twr) Activate activate interval (trrd) Last write data pair read command issue internal (twtr)
Undocumented bits reserved.
Table shows SDRAM configuration register (DDR_SDRAM_CFG), which enables/disables features memory controller including: self-refresh, ECC, dynamic power management.
Table MPC8540 DDR_SDRAM_CFG
Bits
Name MEM_EN SREN ECC_EN RDEN
Description SDRAM controller enabled/disabled Self-refresh enable enable Registered DIMM enabled/disabled
SDRAM_TYPE Type SDRAM device used DYN_PWR Dynamic power management enabled/disabled
Undocumented bits reserved.
Table shows SDRAM mode configuration (DDR_SDRAM_Mode), which defines mode registers SDRAM device.
Table MPC8540 DDR_SDRAM_MODE
Bits 0-15 16-31 Name ESDMODE SDMODE Extended SDRAM mode SDRAM mode Description
Table shows SDRAM interval configuration (DDR_SDRAM_INTERVAL), which configures precharge refresh intervals.
Table MPC8540 DDR_SDRAM_INTERVAL
Bits 18-31
Name REFINT BSTOPRE Refresh interval Precharge interval
Description
Undocumented bits reserved.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Interrupt Controller
Porting SDRAM MPC8540
There similarities between SDRAM controller 440GP MPC8540, although exact register formats different. MPC8540 DDR-SDRAM controller registers directly accessed CPU, 440GP SDRAM controller registers indirectly accessed CPU. features SDRAM controller registers from 440GP MPC8540 shown Table
Table Register Mapping 440GP MPC8540
Feature Refresh enable/timer 440GP Register SDRAM0_CFG1[SRE] MPC8540 Register DDR_SDRAM_CFG[SREN] DDR_SDRAM_INTERVAL[REFINT] TIMING_CFG_1[CASLAT] TIMING_CFG_1[PRETOACT] TIMING_CFG_1[ACTTOPRE] TIMING_CFG_1[REFREC] TIMING_CFG_1[ACTTORW] TIMING_CFG_1[WRREC] DDR_SDRAM_CFG[DYN_PWR] LCRR[DBYP] CSn_BNDs[SAn] CSn_BNDs[SAn] [EAn] CSn_CONFIG[ROW_BIT_CS_n] CSn_CONFIG[COL_BIT_CS_n] CSn_CONFIG[CS_n_EN]
latency (taa) Precharge activate timing (trp) Activate precharge (tras) Refresh recovery timing (trfc) Activate read/write timing (trcd) Write recovery (twr) Power management enable SDRAM disabled SDRAM base address SDRAM size Memory organization
SDRAM0_TR0[SDCL] SDRAM0_TR0[SDPA] SDRAM0_TR0[SDCP] SDRAM0_TR0[SDRA] SDRAM0_TR0[SDCP] SDRAM0_TR0[SDWR] SDRAM0_CFG1[PMEN] SDRAM0_DEVOPT[DLL] SDRAM0_BnCR[SDBA] SDRAM0_BnCR[SDSZ] SDRAM0_BnCR[SDBA]
Memory bank enabled
SDRAM0_BnCR[SDBE]
440GP uses predefined modes (SDRAM0_BnCR[SDRAM]) each logical bank, which defines supported DDR-SDRAM configuration. combination with size (SDRAM0_BnCR[SDSZ]) memory, this mode initializes DDR-SDRAM memory controller address muliplexing (precharge pin) settings. MPC8540 uses CSn_CONFIG registers each logical bank define DDR-SDRAM configuration terms number columns. These settings combined with size (CSn_BNDs) memory initialize DDR-SDRAM memory controller address muliplexing (precharge pin) settings.
Interrupt Controller
Although there many similarities between interrupt controllers 440GP MPC8540, they configured somewhat differently, explained this section.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Interrupt Controller
440GP Interrupt Controller
440GP contains universal interrupt controllers (UIC0 UIC1) that provide necessary control, status, communication between internal interrupts, external interrupts, processor core. UICs cascaded shown Figure
Interrupt Sources
Non-Critical Interrupt Processor Core Critical Interrupt
Non-Critical Interrupt Interrupt Sources UIC1 Critical Interrupt
UIC0
Figure 440GP Overview
UIC0 collects interrupts from internal external sources, including critical non-critical interrupt outputs secondary interrupt controller, UIC1. Table shows registers used configure 440GP universal interrupt controller.
Table 440GP Interrupt Controller Registers
Offset 0x0C0 0x0D0 0x0C2 0x0D2 0x0C3 0x0D3 0x0C4 0x0D4 0x0C5 0x0D5 0x0C6 0x0D6 0x0C7 0x0D7 0x0C8 0x0D8 Name UIC0_SR UIC1_SR UIC0_ER UIC1_ER UIC0_CR UIC1_CR UIC0_PR UIC1_PR UIC0_TR UIC1_TR UIC0_MSR UIC1_MSR UIC0_VCR UIC1_VCR UIC0_VR UIC1_VR Description status register status register enable register enable register critical register critical register polarity register polarity register trigger register trigger register masked status register masked status register vector configuration register vector configuration register vector register vector register
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Interrupt Controller
status registers (UIC0_SR UIC1_SR) capture hold internal external interrupts until software resets them writing interrupt (bit) location these registers. fields enable registers (UIC0_E UIC1_ER) match status registers enable disable interrupt reporting status registers. Similarly, fields critical registers (UIC0_CR UIC1_CR) determine whether interrupt captured status registers generates non-critical critical interrupt. fields priority registers (UIC0_PR UIC1_PR) determine whether interrupt captured status registers positive negative priority. fields trigger registers (UIC0_TR UIC1_TR) determine whether interrupt captured status registers edge-sensitive level-sensitive. masked status registers (UIC0_MSR UIC1_MSR) read-only registers which contain result masking status registers (UIC0_SR UIC1_SR) enable registers (UIC0_E UIC1_ER). This allows software check which enabled interrupts active. vector configuration registers (UIC0_VCR UIC1_VCR) write-only registers which enable software control interrupt vector generation critical interrupts only. These registers contain address, used interrupt vector base address (VBA), field specifying interrupt ordering priority (PRO). field contains either base address interrupt handler vector table base address interrupt handler associated with each interrupt. actual interrupt vector (the address interrupt handler that services interrupt) generated vector registers (UIC0_VR UIC1_VR) using VBA. field controls whether interrupt associated with UICn_SR[0] UICn_SR[31] highest priority. UICn_VCR[PRO] interrupt associated with UICn_SR[31] highest priority; UICn_VCR[PRO] interrupt associated with UICn_SR[0] highest priority. closest highest priority field that programmed UICn_CR interrupt second highest priority. Priority decreases across UICn_SR opposite highest priority field.
MPC8540 Interrupt Controller
MPC8540 programmable interrupt controller (PIC) compliant with OpenPIC architecture supports external internal interrupt sources, inter-processor interrupts, global timers, message registers. reset through global configuration register (GCR). addition, this register used program operate modes: Pass through mode. external active high interrupt request IRQ0 directly passed e500 core. other external requests ignored internal interrupts passed IRQ_OUT signal. Mixed mode. External internal interrupts delivered according programmed options (IRQ_OUT e500 interrupt destination registers). Each interrupt source (except inter-processor interrupts) interrupt destination register, which determines destination that interrupt: external sources-EIDR0-EIDR11 internal sources-IIDR0-IIDR31 messaging sources-MIDR0-MIDR3
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Interrupt Controller
timer sources-GTDR0-GTDR3
There three interrupt destinations interrupt basis: Core_int (e500 interrupt) Core_cint (e500 critical interrupt) IRQ_OUT (external pin) Each interrupt source interrupt vector/priority register configure priority (there programmable interrupt priority levels interrupt), vector, masking, polarity/sensing (for external interrupt sources only). external sources-EIVPR0-EIVPR11 internal sources-IIVPR0-IIVPR31 messaging sources-MIVPR0-MIVPR3 timer sources-GTVPR0-GTVPR3 inter-processor sources-IPIVR0-IPIVR3 There critical interrupt summary registers (CISR0 CISR1), which determine active interrupt directed processor critical interrupt signal, Core_cint. Software uses processor current task priority register (CTPR) current task priority executed core. current priority interrupt should higher than value CTPR serviced. response interrupt, software should read processor interrupts acknowledge register (IACK) obtain vector interrupt being serviced. Reading IACK also following side effects: Associated field interrupt pending register cleared edge-sensitive interrupts. In-service register (ISR) updated. Interrupt signal (int cint) processor negated. Writing interrupt (EOI) register signals processing highest-priority interrupt currently service processor. write updates retiring highest-priority interrupt. nested interrupts, processor servicing interrupt, only interrupted receives interrupt request from source with higher priority than being serviced. This true even software, part interrupt service routine, writes lower value into CTPR. Thus, although several interrupts in-service simultaneously, code currently executing always handles highest-priority interrupts that service. When processor performs cycle, this highest-priority interrupt taken out-of-service. next cycle takes next-highest priority interrupt out-of-service, interrupt with lower priority than those currently in-service started until higher priority interrupts complete even priority greater than CTPR value. addition, MPC8560 device, there separate interrupt controller manage, prioritize, route interrupts from serial peripheral parallel ports PIC.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Interrupt Controller
Porting Interrupts MPC8540
There similarities between interrupt controller 440GP MPC8540, although exact register formats different. Table lists features interrupt controller registers from 440GP MPC8540.
Table Mapping Features 440GP Interrupt Controller PowerQUICC
Feature Enabling/masking interrupts 440GP Register UIC0_ER-UIC1_ER UIC0_MSR-UIC1_MSR MPC8540 Register Mask field following registers: EIVPR0-EIVPR11 IIVPR0-IIVPR31 IVPR0-MIVPR3 GTVPR0-GTVPR3 IPIVR0-IPIVR3 Activity field following registers: EIVPR0-EIVPR11 IIVPR0-IIVPR31 IVPR0-MIVPR3 GTVPR0-GTVPR3 IPIVR0-IPIVR3 CISR0 CISR1 Polarity field following registers: EIVPR0-EIVPR11 IIVPR0-IIVPR31 IVPR0-MIVPR3 GTVPR0-GTVPR3 IPIVR0-IPIVR3 Sense field following registers external interrupt sources only: EIVPR0-EIVPR11 Priority vector fields following registers: EIVPR0-EIVPR11 IIVPR0-IIVPR31 IVPR0-MIVPR3 GTVPR0-GTVPR3 IPIVR0-IPIVR3
Interrupt status
UIC0_SR-UIC1_SR
Critical interrupts Interrupt polarity
UIC0_CR-UIC1_CR UIC0_PR-UIC1_PR
Edge level sensitive
UIC0_TR-UIC1_TR
Vector/prioritization
UIC0_VR-UIC1_VR UIC0_VCR-UIC1_VCR
440GP defines separate registers different features interrupt controller. MPC8540 defines registers each interrupt source, which determines polarity, vector/prioritization, sensing, interrupt status, interrupt source enabled. 440GP, critical interrupts, only fixed priority levels defined priority field vector configuration registers. MPC8540 more flexible interrupt controller that defines interrupt vector/priority register each interrupt source. This controller used configure levels priority.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
General-Purpose Timers
General-Purpose Timers
Timer facilities (including time base, decrementer, fixed internal timer (FIT), watchdog) between 440GP MPC8540 Book implementation identical discussed this section. However, configuration general-purpose timers differs.
440GP General Purpose Timers
440GP supports general-purpose timer (GPT) with five maskable compare registers 32-bit time base counter. Each compare register corresponding interrupt universal interrupt controller (UIC). interrupts generated specific count match between contents compare register time base counter. interrupts also generated specific interval masking individual bits compare register.
MPC8540 General Purpose Timers
MPC8540 supports four global general purpose timers that programmed programmable interrupt controller. There appropriate clock prescalers synchronizers provide time base four internal timers unit. timers individually programmed generate processor interrupt when they count down zero used generate regular periodic interrupts. Each timer four configuration control registers: Global timer current count register (GTCCRn) Global timer base count register (GTBCRn) Global timer vector-priority register (GTVPRn) Global timer destination register (GTDRn) timer frequency four timers determined timer frequency reporting register (TFRR), timer interrupts edge-triggered interrupts. timer period expires while previous interrupt from same source pending in-service, subsequent interrupt lost. Using timer control register (TCR), create timers larger than 31-bit global timers. 16-bit timers internally cascaded form 32-bit counter. Timer internally cascaded timer timer internally cascaded timer timer global configuration registers (TGCRs) used timers into cascaded mode. change timer frequency setting appropriate fields TCR.
Porting General-Purpose Timers MPC8540
There similarities general-purpose timers 440GP MPC8540, although exact register formats different. Table illustrates general-purpose timer registers from 440GP MPC8540.
Table Mapping Features 440GP MPC8540
Feature Number timers Time base counter 440GP Register GP0_TBC MPC8540 Register GTBCR0-3
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Transfers
Table Mapping Features 440GP MPC8540 (continued)
Feature Compare timers Interrupt enable/status information Polarity (for external trigger) Status information 440GP Register GP0_COMP0-4 GP0_MASK0-4 GPT0_ISS, GPT0_ISC, GPT0_IE DMA0_POL DMA0_SR MPC8540 Register GTCCR0-3 GTVPR0-3 programmable. DGSR
Transfers
440GP Controller
This section discusses controller transfers data 440GP MPC8540.
440GP controller provides four channels, each with control, count control, source address, destination address, scatter/gather address registers (see Table 17).
Table 440GP Controller Registers
Offset 0x100 Mnemonic DMA0_CR0 Register channel control register Description DMA0_CR0-DMA0_CR3 configure enable their respective channels. Configuration settings include transfer modes, width, channel priority. Before channel transfer data, channel control, count control, source address, destination address registers must programmed. DMA0_CT0-DMA0_CT3 contain number transfers remaining transaction their respective channels when EOTn[TCn] programmed terminal count output, along with additional channel control information. addition, these registers contain fields used enable interrupts terminal count, transfer, error conditions. Other fields enable parity checking during peripheral portion peripheral type.
0x101
DMA0_CTC0
count control register
0x102 0x103
DMA0_SAH0 DMA0_SAL0
source address high register DMA0_SAHn DMA0_SALn contain source address memory-to-memory source address register memory-to-peripheral transfers. destination address registers (DMA0_DAH0-DMA0_DAH3 DMA0_DAL0-DMA0_DAL3) contain destination address memory-to-memory peripheral-to-memory transfers. description address high register description address register
0x104 0x105
DMA0_DAH0 DMA0_DAL0
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Transfers
Table 440GP Controller Registers
Offset 0x106 0x107 Mnemonic DMA0_SGH0 DMA0_SGL0 Register scatter/gather address high register scatter/gather address register Description Contain memory address next scatter/gather descriptor table. Prior starting scatter/gather transfer, software must write address channel's descriptor table DMA0_SGHn DMA0_SGLn. Once scatter/gather transfer starts, DMA0_SGHn DMA0_SGLn automatically updated from descriptor table.
0x108-0x11F 0x120
DMA0_SR
above channels status register Provides status information each channels. sleep mode register (DMA0_SLP) enables controller enter sleep (low-power) mode after programmed number idle cycles. Sets channel scatter/gather transfers (DMA0_SGC[SSGn] Determines whether start scatter/gather transfers enabled channels
0x123
DMA0_SGC
scatter/gather command register
0x125 0x125
DMA0_SLP DMA0_POL
sleep mode register polarity configuration register Sets polarity (active state) external DMAI/O signals: DMAReqn, DMAAckn, EOTn[TCn].
When program these registers, controller performs requested data transfer between memory peripherals memory-to-memory without need host intervention. external peripheral transfers, three external signals supported each channel, follows: DMAReqn-DMA request used request data transfer DMAAckn-DMA acknowledge used instruct peripheral start transfer EOTn[TCn]-End transfer terminal count signal used stop channel. With normal transfer, necessary program channel's control, count control, source, destination registers each transfer. scatter/gather capability controller provides more efficient solution applications that require multiple transactions single channel. Instead individually programming channel's registers, software creates (linked list) descriptor tables system memory. configure channel scatter/gather transfer, scatter/gather descriptor address registers (DMA0_SGHn DMA0_SGLn) channel address first descriptor table, which must quadword (16-byte) aligned. format these descriptor tables shown Figure
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Transfers
Byte Word Word Word Word Word Word Word Word
BYTE
Byte
Byte
Channel Control Word (DMA_CRn) Configuration Bits Count (DMA_CTCn) Source Address High (DMA_SAHn) Source Address (DMA_SALn) Destination Address High (DMA_DAHn) Destination Address (DMA_DALn) Linked Next Scatter/Gather Descriptor Address High (DMA_SGHn) Linked Next Scatter/Gather Descriptor Address (DMA_SGLn)
word link (LK).
Figure Descriptor Table Format
begin scatter/gather transfer, software writes DMA0_SGC register follows: Enable mask-DMA0_SGC[EMn] Start scatter/gather DMA0_SGC[SSGn] Finally, indicate location descriptor tables DMA0_SGC[SGLn] controller then reads descriptor table address (DMA0_SGHn DMA0_SGLn) updates controller registers. receiving data from scatter/gather descriptor table, channel's terminal count status (DMA0_SR[TCn]) transfer status (DMA0_SR[EOTn]) automatically cleared. After channel registers loaded from descriptor table, transfer functions normal non-scatter/gather operation. (link) set, scatter/gather process stops when current transfer completes. Otherwise, controller reads descriptor table address (DMA0_SGHn DMA0_SGLn) process repeats.
MPC8540 Controller
MPC8540 supports four high-speed channels transferring blocks data between RapidIO controller, PCI, local address space, independent e500 core external hosts. Data transfers triggered controlled software triggered controlled external device using handshake signals DMA_DREQ, DMA_DACK, DMA_DDONE. addition, misaligned transfers sub-block transfers bytes supported channel basis, minimize number discrete memory transactions maximize performance over interfaces, such RapidIO. summary controller registers shown Table
Table MPC8540 Register Summary
Name CLNDARn SATRn SARn
Description mode register Status register current link descriptor address register source attributes register source address register
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Transfers
Table MPC8540 Register Summary (continued)
Name
Description destination attributes register destination address register byte count register next link descriptor address register current list alternate base descriptor address register next list alternate base descriptor address register source stride register destination stride register general status register
DATRn DARn BCRn NLNDARn CLSDARn NLSDARn SSRn DSRn DGSR
four channels.
There main modes operation, direct mode chaining mode. direct mode, software initializes parameters transfer appropriate register follows: Mode register (MRn), including MRn[CTM] stride mode desired, MRn[XFE] external starts transfer, MRn[EMS_EN] software (single-register write) starts transfer, MRn[SRW] Program other options Program stride registers (SSRn DSRn), enabled. Stride capability allows channel transfer data from selected memory regions memory segment skippng over certain regions that segment. Program number bytes transfer byte count register (BCRn), Mbytes. Program source attributes 32-bit source attributes register (SATRn). Program source address 32-bit source address register (SARn). Program destination attributes 32-bit destination attributes register (DATRn). Program destination address 32-bit destination address register (DARn). chaining mode, software does program source/destination parameters registers. Instead, software provides parameters transfer link descriptor tables memory (one chain). Program mode register (MRn) Current link descriptor address register (CLNDARn) used point first descriptor. When started, reads parameters transfer including next descriptor address loaded next link descriptor address register (NLNDARn). When current segment transferred, NLNDARn[EOLND] set, complete. set, next link descriptor address from NLNDARn read current link descriptor address register (CLNDARn) process repeated. link descriptor format basic chaining mode shown Figure
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Transfers
extended chaining mode allows user setup series buffer descriptors referenced from linked list. Through this linked list, controller then walk through multiple allowing complex transactions performed.
Memory CLNDARn Descriptor Link Descriptor Source Attributes Source Address Destination Attributes NLNDARn Descriptor Destination Address Reserved Next Link Descriptor Address Byte Count Descriptor Reserved
Last Descriptor
Figure MPC8540 Basic Chaining Mode-Link Descriptor Format
Porting Transfers MPC8540
Similarities exist between controller 440GP MPC8540, although exact register formats different. features controllers registers from 440GP MPC8540 shown Table
Table Mapping Features 440GP Controller MPC8540
Feature Enabling channels mode operation Transfer size Source address/attributes Destination address/attributes chaining 440GP Register DMA0_CRn DMA0_CRn[PW] DMA0_CTn[TC] DMA0_SAHn DMA0_SALn DMA0_DAHn DMA0_DALn MPC8540 Register BCRn SARn SATRn DARn DATRn
DMA0_SCHn, DMA0_SGLn, DMA_SCRn, MRn[CTM] link descriptor tables external CLNDARn, NLNDARn, link descriptor memory tables external memory DMA0_SLP DMA0_POL DMA0_SR Supported globally specific programmable DGSR
Sleep mode Polarity (for external trigger) Status information
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Buffer Descriptors
MPC8540 features identical those 440GP transfers. addition, controller MPC8540 more flexible offers support extended chaining mode stride transfers.
Buffer Descriptors
Buffer descriptors (BDs) primary data structures used 440GP MPC8540 passing data between higher level software on-chip serial communication peripherals. Organization differs between 440GP MPC8540, basic structure similar, easing migration MPC8540. example, differences Ethernet operation 440GP MPC8540 will examined.
440GP Buffer Descriptors
440GP, hardware block referred memory access layer (MAL) manages data transfers between Ethernet controllers (EMACs). communicate with software device drivers, utilizes buffer descriptor ring structure external memory. software device driver uses buffer descriptor structure inform about buffer locations packet buffer status. descriptors pointers actual buffers organized circular queues. Each EMAC associated with tables (transmit receive) buffer descriptors table. format buffer descriptor (BD) shown Figure same both transmit receive.
Offset Offset Status/Control Data Buffer Pointer MSbs) Data Buffer Pointer LSbs) Data Length
Figure 440GP Buffer Descriptor Format
most significant half word each buffer descriptor contains status/control bits. second half word determines MSbs data buffer pointer data length bytes) referenced this buffer descriptor. second word buffer descriptor contains LSbs data buffer pointer that points actual data buffer memory. example data buffer structure external memory shown Figure
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Buffer Descriptors
Table Pointer Register
Tables (Memory) Memory Descriptor Descriptor
Channel Table Pointer
Buffer Pointer Data Buffer
NOTE: means wrap this descriptor.
Buffer Pointer
Figure 440GP Data Buffers External Memory
Table shows format status/control bits transmit buffer descriptors. Bits 6-15 used EMAC specific control information during write access status information during read access.
Table 440GP Status/Control Bits TxBDs
Name Description Ready-indicates buffer ready transmission Wrap-last buffer circular table Continuous mode-indicates continuous transmission buffer regardless Indicates last buffer frame Reserved Specifies Interrupt generated processing Generate (control) Indicates (status) BPACK LOCS Generate padding (control) Indicates packet (status) Insert source address (control) Loss carrier sense (status) Replace source address (control) Excessive deferral (status)
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Buffer Descriptors
Table 440GP Status/Control Bits TxBDs (continued)
Name IVTg RVTg Insert VLAN (control) Excessive collisions (status) Replace VLAN (control) Late collisions (status) Multiple collisions (status) Single collision (status) Underrun (status) Signal quality error (status) Description
Table shows format status/control bits receive buffer descriptors. Bits 6-15 used EMAC-specific status information.
Table 440GP Status/Control Bits RxBDs
Name Description Empty-indicates receive data buffer ready receive data Wrap-last buffer circular table Continuous mode-indicates continuous reception data regardless Indicates last buffer frame Indicates first buffer frame Specifies interrupt generated processing Indicates overrun error indication Pause packet indication packet-indicates early termination caused packet error Runt packet error indication Short event error indication Alignment error indication error indication Packet long error indication range error indication range error indication
MPC8540 Buffer Descriptors
three-speed ethernet controllers (TSECs) MPC8540 also buffer descriptors data buffers transmission reception Ethernet frames.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Buffer Descriptors
format buffer descriptor (BD) shown Figure same both transmit receive:
Offset 0x00 Offset 0x02 Offset 0x04 Offset 0x06
Status/Control Bits Data Length Tx/Rx Buffer Pointer
Figure MPC8540 Buffer Descriptor Format
first word contains status/control bits buffer data length bytes) transmitted received. second word buffer descriptor contains data buffer pointer that points actual data buffer memory. example data buffer structure external memory shown Figure
Memory System Memory Buffer Descriptors
Status Control TxBD Table Pointer (TBASE) RxBD Table Pointer (RBASE) TxBD Table Data Length Buffer Pointer
Buffer
Buffer Descriptors
RxBD Table
Status Control Data Length Buffer Pointer
Buffer
Figure Example MPC8540 TSEC Memory Structures
Table shows format status/control bits MPC8540 TSEC transmit buffer descriptors.
Table MPC8540 TSEC Status/Control Bits
Name Description Ready-indicates buffer ready transmission Padding short <64-byte Ethernet frames Wrap-last buffer circular table Specifies interrupt generated processing Indicates last buffer frame Transmit
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Buffer Descriptors
Table MPC8540 TSEC Status/Control Bits (continued)
Name 10-13 Defer Reserved Hugh frame enable (control) Late collision indication Retry limit reached indication Retry count indicates number retries Underrun indication Reserved Description
Table shows format status/control fields MPC8540 TSEC receive buffer descriptors.
Table MPC8540 TSEC Status/Control Fields RxBDs
Name Description Empty-indicates receive data buffer ready receive data Reserved Wrap-last buffer circular table Specifies interrupt generated processing Indicates last buffer frame Indicates first buffer frame Reserved Miss-frame accepted because promiscuous match address Broadcast-frame broadcast address Multicast-frame multicast address Large-indicates frame bigger than maximum frame length received Non-octet-frame divisible received Short-indicates short frame received enabled CRC-frame error Overrun indication Truncation-indicates frame truncated
Porting Buffer Descriptors MPC8540
Since both MPC8540 440GP rely circular queues buffer descriptors, porting software applications from 440GP MPC8540 should relatively straightforward. Buffer descriptors themselves have similar format, although exact contents differ.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Ethernet
Ethernet
Table compares Ethernet features 440GP MPC8540. Many similarities exist between Ethernet access controllers (EMACs) 440GP three-speed ethernet controllers (TSECs) MPC8540. following sections discuss only Ethernet features common both processors configuration differences.
Table Ethernet Comparison 440GP versus MPC8540
Ethernet Feature Standards Speeds Interfaces Half-duplex support Full-duplex support Automatic retransmission packets collision (CRC) checking generation Programmable inter-packet Flow control (including pause packet checking generation) Address recognition Jumbo frame support Automatic source address insertion replacement VLAN support Wake (WOL) handling 440GP IEEE 802.3, 802.3u, 802.3x, 10/100 Mbps MII, RMII, SMII 10/100 Mbps 10/100 Mbps Unicast, multicast, broadcast, promiscuous mode Programmable option VLAN insertion/replacement transmit packets MPC8540 IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ab 10/100/1000 Mbps GMII, RGMII, MII, RMII, TBI, RTBI 10/100 Mbps 10/100/1000 Mbps Unicast, multicast, broadcast, promiscuous mode Programmable option None
440GP Ethernet Controllers
440GP supports Ethernet access controllers (EMACs) half-/full-duplex operation 10/100 Mbps. Each EMAC uses media independent interface (MII) controlled ZMII bridge connect standard Ethernet physical devices (PHYs). ZMII bridge supports interface, RMII/SMII interfaces selected enabling bits 28-29 power-on configuration register (CPC0_STRP0). addition, there three registers which control maintain status information ZMII bridge. register summary each EMAC shown Table
Table 440GP Ethernet Register Summary
Mnemonic EMACn_MR01 EMACn_MR1 Register Mode register Mode register Description Define operating mode including: Tx/Rx enable, full-duplex operation, flow control, 10/100 Mbps operation, FIFO size, loopback mode, VLAN enable.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Ethernet
Table 440GP Ethernet Register Summary
Mnemonic EMACn_TR0 EMACn_TR1 EMACn_RMR Register Transmit mode register Transmit mode register Receive mode register Defines EMAC mode during receive operation including: address recognition modes, strip padding/FCS enable/disable, propagate pause packets, reception oversized packets. EMAC generates interrupt events using contents interrupt status register (EMACn_ISR) corresponding mask bits interrupt status enable register (EMACn_ISER). EMACn_IAHR contains high-order half word station unique individual address. During packet reception, EMAC programmed individual address match mode (EMACn_RMR[IAE] contents EMACn_IAHR concatenated with contents individual address register (EMACn_IALR) form composite address that compared with destination address received packet. individual address hash tables (EMACn_IAHT1-EMACn_IAHT4) used hash table function multiple individual addressing mode. group address hash tables (EMACn_GAHT1-EMACn_GAHT4) used hash table function multiple group addressing mode. Description
EMACn_ISR EMACn_ISER
Interrupt status register Interrupt status enable register
EMACn_IAHR EMACn_IALR
Individual address high Individual address
EMACn_VTPID EMACn_VTCI EMACn_PTR
VLAN TPID (tag protocol identifier) register VLAN (tag control information) register Pause timer register Defines time period which pause function enabled. inter-packet value register (EMACn_IPGVR) defines value one-third inter-packet next packet transmitted.
EMACn_IAHT1-4 EMACn_GAHT1-4 EMACn_LSAH EMACn_LSAL EMACn_IPGVR EMACn_STACR EMACn_TRTR EMACn_RWMR EMACn_OCTX EMACn_OCRX Note:
Individual address hash tables Group address hash tables Last source address high Last source address Inter-packet value register control register Transmit request threshold register Receive low/high water mark register Defines conditions that cause EMAC activate urgent priority request, that manage flow control Transmitted octets Received octets Read-only registers which contain number octets transmitted received. These registers used software RMON statistics.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Ethernet
MPC8540 Ethernet Controllers
MPC8540 supports three-speed Ethernet controllers (TSECs). Each TSEC supports 10/100/1000 Mbps Ethernet/802.3 networks using standard MAC-PHY interfaces follows connect external Ethernet transceiver: interface running 10/100 Mbps GMII interface running Gbps interface that connected SerDes device fibre channel applications Reduced signal count versions GMII (RGMII) ten-bit (RTBI) interfaces TSEC interface (GMII TBI) width (reduced standard) initialized sampling certain signals during power-on reset sequence. value these signals sampled into PORDEVSR (POR device status register) while HRESET asserted. addition, Ethernet control register (ECNTRL) determines interface type width, enabled RMON statistics. block diagram TSEC controller shown Figure
Tx/Rx Descriptors Tx/Rx Data Tx/Rx Status
Block Interface
FIFO Kbytes Address/Data Filtering Pack Words
FIFO Control
FIFO Kbytes Unpack Words System Data Path
Layer
GMII
Counters
Clocks
Reduced Signal Interface
Reduced Signal Interface
GMII
RGMI
RTBI
Management
Figure MPC8540 TSEC Block Diagram
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Ethernet
TSEC device programmed combination control/status registers buffer descriptors. CSRs used mode control, interrupts, access status information. descriptors pass data buffers related buffer status frame information between hardware software. TSEC control/status registers 32-bits wide divided into following sections depending functions they support: General control/status registers-The interrupt event (IEVENT) generates operational interrupts, transceiver/network error interrupts, corresponding interrupt enable register (IMASK) also set. Ethernet control register (ECNTR0) used reset, configure, initialize TSEC including: enabling/resetting counters statistics, enabling mode, reduced standard interfaces, interface speed. pause timer value register (PTV) written user store pause duration used when TSEC initiates pause. FIFO control/status registers-Allow user change some default settings FIFO that used optimize operation performance safety. Transmit specific control/status registers-The transmit control register (TCTRL) used half-duplex flow control operation pause frame transmission requests. Additional registers used maintain TxBD parameters (including length, base address, pointers). Receive specific control/status registers-The receive control register (RCTRL) enables broadcast reject, promiscuous mode, receive short frame modes. Additional registers used maintain RxBD parameters (including length, base address, pointers). control/status registers-The configuration register (MACCFG1) used configure functionality including: transmit/receive enable, flow control transmit/receive enable, loopback operation. configuration register (MACCFG2) configures functionality, including: preamble length, interface modes, padding/CRC enable, Hugh frame enable, full- half-duplex operation. inter-packet gap/inter-frame register (IPGIFG) used program inter-frame frame, non-back-to-back back-to-back inter-packet gaps. half-duplex register (HAFDUP) used program features TSEC half-duplex operation 10/100 Mbps. maximum frame length register (MAXFRM) sets maximum frame size both transmit receive directions. Additional registers used management interface. statistic registers-The separate statistics counter registers, which simply count accumulate statistical events that occur packets transmitted received. Hash function registers-The individual address registers (IADDRn) represent entries individual (unicast) address hash table used address recognition process. While field receive frame processed through 32-bit generator, bits remainder mapped entries. user enable hash entry setting appropriate bit. hash table occurs result points enabled hash entry. group address registers (GADDRn) represent entries group (multicast) address hash table used address recognition process. While field receive frame processed through 32-bit generator, bits remainder mapped entries. user enable hash entry setting appropriate bit. hash table occurs result points enabled hash entry.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
UART
Finally, attribute register (ATTR) defines attributes transaction types access buffer descriptors, write receive data, read transmit data buffers including: snooping cache data extraction. Finally, registers define operation ten-bit interface (TBI).
Porting Ethernet MPC8540
There similarities between 440GP Ethernet controllers three-speed Ethernet controllers MPC8540, although exact register formats different. features Ethernet controllers registers from 440GP MPC8540 shown Table
Table Mapping Features 440GP Ethernet Controller MPC8540
Feature Enable interrupts Interface modes/speed Pause packet time Address recognition (individual) Inter-packet (frame) Enabled MAC/flow control functionality Loopback operation RMON statistics 440GP Register EMACn_ISR EMACn_ISER ZMII0_FER ZMII0_SSR EMACn_PTR EMACn_IAHR, EMACn_IAHR EMACn_IAHT1-4, EMACn_GAHT1-4 EMACn_IPGVR EMACn_MR0 EMACn_MR1 EMACn_MR1 Limited support with octet counts EMACn_OCTRX EMACn_OCTTX registers MPC8540 Register IEVENT IMASK ECNTR0 MACCFG2 IADDR0-7, GADDR0-8 IPGFG MACCFG1 MACCFG1 separate statistics counter registers
addition, MPC8540 TSEC FIFO control status registers enable features including: FIFO thresholds Underrun trigger Flow control Interrupt coalescing This allows user optimized Ethernet system performance minimize underrun overrun events.
UART
440GP UART
This section compares 440GP UART MPC8540 UART.
440GP there UART interfaces complete sets UART registers (one UART0 UART1) almost identical MPC8540. There registers shown Table each UART interface used configuration, control, status.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
UART
Table 440GP UART Register Summary
Name
Description UART receive buffer register UART transmitter holding register UART interrupt enable register UART interrupt identification register UART FIFO control register UART line control register UART modem control register UART line status register UART modem status register UART scratch register UART divisor latch (LSB) UART divisor latch (MSB)
UARTn_RBR UARTn_THR UARTn_IER UARTn_IIR UARTn_FCR UARTn_LCR UARTn_MCR UARTn_LSR UARTn_MSR UARTn_SCR UARTn_DLL UARTn_DLM
MPC8540 PowerQUICC
MPC8540 (dual) universal asynchronous receiver/transmitters (UARTs). There complete sets DUART registers (one UART0 UART1). There registers shown Table each UART interface used configuration, control, status.
Table MPC8540 DUART Register Summary
Name
Description UART receive buffer register UART transmitter holding register UART divisor least significant byte register UART interrupt enable register UART divisor most significant byte register UART interrupt identification register UART FIFO control register UART alternate function register UART line control register UART modem control register UART line status register UART modem status register UART scratch register UART status register
URBRn UTHRn UDLBn UIER UDMBn UIIRn UFCRn UAFRn ULCRn UMCRn ULSRs UMSRn USCRn UDSRn
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Porting UART MPC8540
UART programming mode between 440GP MPC8540 almost identical. registers byte wide. Reads writes these registers must byte-wide operations. However, there additional registers MPC8540 DUART programming model, follows: UART alternate function registers (UAFRs), which enable software write both UART0 UART1 registers simultaneously with same write operation. UAFRs also provide means device performance monitor track baud clock. UART status registers (UDSRs), which read-only registers that return transmitter receiver FIFO status.
inter-IC (I2C) two-wire, bidirectional serial that provides simple, efficient method data exchange between devices. synchronous, multi-master allows 440GP MPC8540 exchange data with other devices such microcontrollers, EEPROMs, real-time clock devices, converters. Table compares features 440GP MPC8540.
Table Comparison 440GP versus MPC8540
Ethernet Feature Clocking Addressing Data transfers Support master/slave operation Multi-master operation On-chip filtering 440GP 10-bit 8-bit MPC8540 Software programmable clock frequency 7-bit only 8-bit
Many similarities exist between controllers 440GP PowerQUICC III.
10.1
440GP Controller
440GP supports interfaces. Table shows registers configuring interfaces 440GP. There 1-byte wide registers each interface.
Table 440GP Register Summary
Mnemonic I2Cn_MDBUF I2Cn_SDBUF I2Cn_LMADR I2Cn_HMADR Register master data buffer slave data buffer master address high master address Description I2Cn_MDBUF I2Cn_SDBUF 1-byte 4-byte FIFO buffer. I2Cn_LMADR I2Cn_LSADR form addresses that interface transmits bus. master slave high address (I2Cn_HMADR I2Cn_HSADR) registers provide upper address bits 10-bit addressing mode.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Table 440GP Register Summary (continued)
Mnemonic I2Cn_CNTL I2Cn_MDCNTL control mode control Register Description Starts stops interface master transfers bus. When transfer begins, interface uses values I2Cn_CNTL determine type size transfer. I2Cn mode control register (I2Cn_MDCNTL) sets major modes operation bus. addition, I2Cx_MDCNTL force data buffers into empty state. Contains state interface status previously requested master transfers. Reports additional status. During after transfers, software read I2Cn_STS I2Cn_EXTSTS registers determine state interface bus. I2Cn_LMADR I2Cn_LSADR form addresses that interface transmits bus. master slave high address (I2Cn_HMADR I2Cn_HSADR) registers provide upper address bits 10-bit addressing mode. Contains clock divider ratio determine base clock from (on-chip peripheral bus) clock. Specifies which conditions generate interrupt when interrupt enabled. Reports number bytes transferred during master slave operation. Provides additional control interface functions reports status slave operations. Controls monitors serial clock (I2CSCL) serial data (I2CSDA) signal, used error recovery when malfunction detected interface.
I2Cn_STS I2Cn_EXTSTS
status extended status
I2Cn_LSADR I2Cn_HSADR
slave address high slave address clock divide interrupt mask transfer count extended control slave status direct control
I2Cn_CLKDIV I2Cn_INTRMSK I2Cn_XFRCNT I2C_XTCNTLSS I2Cn_DIRECTCNTL
10.2
MPC8540 Controller
MPC8540 supports interface. Table shows registers 1-byte wide) configuration, control, status information interface MPC8540.
Table MPC8540 Register Summary
Name I2CADR I2CFDR I2CCR I2CSR I2CDR I2CDFSRR Description address register frequency divider register control register status register data register digital filter sampling rate register
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
PCI-X
address register defines address which interface responds when addressed slave. This address sent during address-calling cycle when module master mode. frequency divider register contains frequency divider ratio determine serial clock frequency from clock. control register determines controller mode operation. status register read-only software determine status information controller. data register initiates transmission reception data byte time. digital filter sampling rate register assists filtering signal noise.
10.3
Porting MPC8540
programming mode between 440GP MPC8540 almost identical. However, 440GP controller supports 10-bit addressing, programming model differs that separate address/data registers supported master slave operation. Therefore, programming model MPC8540 operation much simpler. Table illustrates registers from 440GP MPC8540 operation.
Table Mapping Features 440GP Controller MPC8540
Feature 7-bit addressing 10-bit addressing Master/slave data buffers Clock divide Status information Control 440GP Register I2C_LMADR I2C_LMSDR I2C_HMADR I2C_HSADR I2C_MBUF I2C_SBUF I2C_CLKDIV I2C_STS I2C_CNTL, I2C_MDCNTL I2C_XTCNTLSS MPC8540 Register I2CADR I2CDR I2CFDR I2CCSR I2CCCR
PCI-X
interface 440GP MPC8540 version compliant support transaction speeds MHz. addition support, both devices support PCI-X standard (version 1.0A) MHz. Designers systems incorporating PCI/PICE-X devices should refer respective specification thorough description PCI/PCI-X buses.
11.1
440GP PCI-X Bridge
PCI-X bridge 440GP provides interface between processor local (PLB). enables initiators access slaves masters access targets. initiators targets conventional PCI-X mode. PCI-X bridge includes optional arbiter typically used only host-bridge mode. This internal arbiter used with external masters (six pairs) disabled. When disabled, PCI-X bridge REQ/GNT pair that attach external arbiter. PCI-X bridge register memory consists internal registers used controlling PCI-X bridge. These registers accessed from both enabled). Most accessed
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
PCI-X
from type configuration cycles when IDSEL input PCI-X bridge active. PCI-X bridge hardware implements registers little-endian byte ordering. Thus, software that runs big-endian mode must take this into account when accessing registers. PCI-X bridge registers 440GP must must accessed with single-beat, 4-byte transfers. These divided into following sections depending functions they support: PCI-X standard header registers-Located offsets 0x00-0x3f part defined standard header, include configuration address data registers used generate external configuration cycles. Bridge options registers-Determine miscellaneous control operation PCI-X bridge including frequency operation, interrupts sources, PCI-X enabled, etc. Error handling registers- 32-bit read/write registers enable detection reporting errors bus. outbound/inbound registers-The outbound (POM) registers used address space memory space vice versa inbound (PIM) registers. capability block definition registers-Generate interrupts (outbound interrupts) receive interrupts from (inbound interrupts). These interrupts either standard interrupt signals message signaled interrupts (MSI). Power management register block definition registers-Include capabilities power management status control registers determine functions related power management defined Power Management Interface Specification, Version 1.1. PCI-X capability block definition registers-Support additional standard registers defined standard PCI-X addendum Local Specification. Simple message passing inbound registers-For simple message passing mechanism inbound MSI. masters generate configuration cycles accessing CONFIG_ADDRESS CONFIG_DATA registers that located space. CONFIG_ADDRESS CONFIG_DATA must accessed with single-beat transfers that don't cross 32-bit boundary. general mechanism accessing configuration space write value into CONFIG_ADDRESS that specifies number, device number that bus, configuration register that device being accessed. Then, read write CONFIG_DATA causes bridge generate configuration cycle, with address type translated from CONFIG_ADDRESS value. format CONFIG_ADDRESS register shown Figure CONFIG_ADDRESS register controls what type cycle generated when CONFIG_DATA accessed.
Number Function Device Number Number Register Number Type
Figure Format 440GP CONFIG_ADDRESS Register
PCI-X bridge controller supports detection reporting several types errors. errors reported status information saved configuration register set, that error type determination done.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
PCI-X
PCI-X bridge register several ranges address space several ranges address space that claim. These ranges allow master access internal register set, cause PCI-X bridge generate memory, I/O, configuration, special cycles bus. destination memory space, there three address ranges that PCI-X bridge claim. number ranges their location address space programmable determined outbound `POM' registers. Figure shows registers address space address space.
Local Address Size/Attribute BAR-PCI Base Address
Size
Memory Region
Memory Region
Size
Starting Address
Starting Address
Figure Registers Used Outbound Address Translation
destination space, there memory address ranges address range that PCI-X bridge claim. number ranges their locations address space programmable determined inbound (PIM) registers. Figure shows registers address space memory space.
#/BAR Local Address Size/Attribute BAR-PCI Base Address
Size
Memory Region
Memory Region
Size
Starting Address
Starting Address
Figure Registers Used Inbound Address Translation
simple message passing mechanism enables messages exchanged between master device (the host) master device (the local CPU). interface consists 32-bit message register 32-bit message register. 64-bit messages, message high message high registers used.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
PCI-X
11.2
MPC8540 PCI-X Controller
architecture hierarchical, multi-master arbritration scheme that uses either 64-bit addressing post transactions onto bus. Transactions either accepted, retried, deferred. later cases, master repeats transaction that needs retried deferred transactions accepted started target while master retries transaction. MPC8540 five different pairs request/grant pairs, hence five external masters supported. performance interface enhanced level round-robin arbitration algorithm used arbiter through ability mirror pre-fetched read accesses. While interface supports both inbound outbound data streaming, amount data that actually streamed limited both depth pre-fetching target disconnect limit specification. MPC8540, this disconnect will occur after cache lines (that after bytes). This helps devices hogging prevents system bottlenecks/interface starvation, when operating high speed interfaces such RapidIO Gigabit Ethernet. MPC8540 PCI-X controller supports following register types: Memory-mapped registers-these registers control address translation (inbound/outbound), error management, configuration register access MPC8540. PCI-X configuration registers contained within PCI-X configuration header-these registers specified specification every device. PCI-X memory-mapped registers accessed reading writing address comprised base address (specified CCSRBAR local side PCSRBAR PCI-X side) plus offset specific register accessed. Note that memory-mapped registers (except PCI-X configuration data register, CFG_DATA) must only accessed 32-bit words. outbound address translation mapping unit controls mapping transactions from internal 32-bit address space MPC8540 external address space. outbound ATMU consists four translation windows plus default translation transactions that four windows. Each window contains base address that points beginning window local address map, translation address that specifies high-order bits transaction external address space, attributes including window size external transaction type. inbound address translation mapping unit controls mapping transactions from external address space local address space MPC8540. inbound ATMU comprised four windows-a configuration window (highest priority) three general translation windows. Each window contains base address, which points beginning window external address map, translation address that specifies upper order bits transaction local address space, attributes including window size internal transaction attributes. When PCI-X error detected, appropriate error PCI-X error detect register. Subsequent errors appropriate error bits error detection registers, relevant information (attributes, address, data) captured only first error. Local Specification defines configuration registers contained within PCI-X configuration header from 0x00 through 0x3F. PCI-X Addendum Local Specification defines additional registers beyond 0x3F. common PCI-X configuration header implemented
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
PCI-X
MPC8540 shown Figure accessed indirect method using pair 32-bit memory-mapped access registers, CFG_ADDR CFG_DATA.
Reserved Device Vendor Address Offset (Hex)
Status Command Programming Interface Base Class Code Subclass Code Revision BIST Control Header Type Latency Timer Cache Line Size Configuration Status Register Base Address Register (PCSRBAR) 32-Bit Memory Base Address Register 64-Bit Memory Base Address Register 64-Bit High Memory Base Address Register 64-Bit Memory Base Address Register 64-Bit High Memory Base Address Register Subsystem Subsystem Vendor
Capability Pointer
MAX_LAT
MIN_GNT
Interrupt
Interrupt Line
Arbiter Configuration
Function
Figure MPC8540 Common PCI-X Configuration Header
access configuration space, 32-bit value must written CFG_ADDR register specifying target bus, target device that bus, configuration register accessed within that device. read write CFG_DATA register causes host bridge translate access into configuration cycle (provided enable CONFIG_ADDR device number 0b1_1111). translated information will according type number device number type number equal
11.3
Porting MPC8540
interface 440GP MPC8540 both version compliant support PCI-X standard (version 1.0A). Therefore, many programming similarities between programming mode 440GP MPC8540 exist, although exact register formats differ. Table illustrates registers from 440GP MPC8540 general operation.
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
PCI-X
Table Mapping Features 440GP PCI-X Controller MPC8540
Feature configuration header 440GP Register standard header registers (offsets 0x00-0x3F) MPC8540 Register Accessed indirectly using device number CONFIG_ADDR register. PCI-X standard header registers (offsets 0x00-0x44) type transaction determined from translated information CONFIG_ADDR register. Type number device number Type number equal Note CONFIG_ADDR register, enabled reserved. Inbound transactions- window size attributes PICX0_PIM0SA PICX0_PIM1SA PICX0_PIM2SA PICX0_PIM0LAL PICX0_PIM0LAH PICX0_BAR0L PICX0_BAR0H PICX0_PIM1LAL PICX0_PIM1LAH PICX0_BAR1 PICX0_PIM2LAL PICX0_PIM2LAH PICX0_BAR2L PICX0_BAR2H Outbound transactions- window size attributes PICX0_POM0SA PICX0_POM1SA PICX0_POM2SA PICX0_P0M0LAL PICX0_P0M0LAH PICX0_POM0PCIAL PICX0_POM0PCIAH PICX0_P0M1LAL PICX0_P0M1LAH PICX0_POM1PCIAL PICX0_POM1PCIAH fixed hardware coded address fixed Error handling-enable errors PCIX0_ERREN status/detection PCIX0_ERRSTS Error handling-attributes PCIX0_PLBBESR (error attributes) ERR_EN ERR_DR ERR_ATTRIB POWAR PIWAR
type transaction
CONFIG_ADDR register 31-Reserved 0-Determines transaction type
Inbound transactions- address mapping
PITAR PIWBAR PIWBEAR
Outbound transactions- address mapping
POTAR POTEAR POWBAR
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Conclusions
Table Mapping Features 440GP PCI-X Controller MPC8540 (continued)
Feature Error handling-address capture Error handling-data capture 440GP Register PCIX0_PLBEARL PCIX0_PLBEARH MPC8540 Register ERR_ADDR ERR_EXT_ADDR ERR_DL ERR_DH
Conclusions
Migrating hardware platform inherent software implications typically becomes challenge many software engineers unwilling face. Fortunately, both 440GP MPC8540 based 32-bit implementation Book PowerPC architecture, enabling high-level software port with minimal trouble. low-level feature 440GP subset features available MPC8540, with many similarities between implementation architectures. shown this document, porting low-level code relatively straightforward process. Software migration longer deciding factor processor selection. Performance, flexibility, features become deciding factors, PowerQUICC family provides high level performance integration cost today's embedded systems.
Document Revision History
Table provides revision history this document.
Table Document Revision History
Rev. Date 5/26/2004 1/2007 Initial release. Non-substantive formatting. Substantive Change(s)
Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
Document Revision History
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Software Migration from (AMCC) 440GP MPC8540, Rev. Freescale Semiconductor
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Freescale Semiconductor, Inc., 2007. rights reserved.
Document Number: AN2661 Rev. 01/2007

Software Migration from (AMCC) 440GP MPC8540 Paul Wilson NCSD App

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