Software Migration from NPe405H/L PowerQUICCII Paul Genua NCSG Fr
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Document Number: AN2587 Rev. 01/2007
Software Migration from NPe405H/L PowerQUICCII
Paul Genua NCSG Freescale Semiconductor, Inc.
embedded systems become more complex, software complexity ultimately rules become deciding factor when architecting system. cost porting code sometimes offset benefits that come with additional features processor platform. Fortunately, software migration easy, especially when staying within processor core architecture. This document details device driver lower-level software migration from PowerNP(NPe405H, NPe405L) Freescale's PowerQUICCII product family. both PowerPCprocessors (built Power Architecturetechnology), software migration caveats, leaving architects with decisions based more hardware functionality processor feature sets.
Contents Feature Comparison Software Migration Overview SDRAM Controller Buffer Descriptors Time-Slot Assignment Conclusions Revision History
Freescale Semiconductor, Inc., 2004, 2007. rights reserved.
Feature Comparison
Feature Comparison
PowerNP processor family builds IBM's experience with 405GP 405CR families processors. includes PowerPC core well integrated peripherals such following: Multiple fast Ethernet controllers SDRAM controller HDLC controller with time-slot assigner (TSA) UART capability Peripheral PowerQUICC (PQII) successor highly popular PowerQUICC (8xx) family processors from Freescale. Over years since initial product launch, PQII grown into whole family devices, ranging from fully featured MPC8280 ultra-low-cost MPC8270VR. latest devices this family were built using 0.13- technology, enabling very power (~1.5 high frequencies (~450 MHz). heart PQII communications processor module (CPM), RISC protocol engine capable processing Ethernet, ATM, HDLC, without intervention from core PowerPC processor. PQII ability updated with new, custom, and/or enhanced, protocols through microcode updates CPM. example, Freescale offers microcode signaling, well microcode packages adding features such (without PowerPC core intervention) addition standard protocols shipped with silicon. This flexibility eases processing burden PowerPC increase time-in-market, with microcode updates protocols they become needed marketplace. Typical features available PQII include following: Multiple fast Ethernet controllers ASARRing SDRAM controller 256-channel HDLC controller Time-slot assigner Multiple UARTS
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Software Migration Overview
Table side-by-side comparison features commonly available both processors.
Table Feature Comparison PowerNP PowerQUICC
Feature Peripheral SDRAM controller User programmable memory controller External channels Cache UARTs interfaces ASAR engine functionality Technology Frequency Power 32-bit channels 0.25 PowerNP 64-bit 60x-compliant channels 0.13 MHz, PowerQUICC
features NPe405 shown subset features found PQII, enabling easy hardware migration PQII. Upon further investigation, features common processors somewhat similar from software point view well, enabling reasonably easy migration from NPe405 PQII from both hardware software prospective.
Software Migration Overview
High-level software such RTOS (real-time operating system) high-level applications riding RTOS (for example, server) should affected processor selection. RTOS typically utilizes board support package (BSP) order communicate with underlying hardware, this subject change with hardware. Changes outside scope this document, since these changes only RTOS dependent, hardware dependent well. Device drivers most affected software element migrating hardware platform. term "device driver" concerned with communication with anything external processor through mechanisms internal processor. This includes limited Ethernet physical layer devices (PHYs) through internal MAC, memory devices through memory controller, framers through time-slot interchanger (TSA), devices through internal controller. porting code from NPe405 PQII, differences following explored: SDRAM controller Buffer descriptors
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
SDRAM Controller
time-slot assigner transfers
SDRAM Controller
Many similarities exist between integrated SDRAM controllers PQII NPe405. However, PQII SDRAM controller allows some enhanced flexibility SDRAM configuration pertaining memory sizing row/column multiplexing; thus, configuration SDRAM controllers differs somewhat.
NPe405
PowerNP utilizes sixteen indirectly accessed registers status control SDRAM controller. They accessed through PowerNP's SDRAM0_CFGADDR SDRAM0_CFGDATA registers. Upon system reset processor, software must configure then enable SDRAM controller. PowerNP registers that involved with SDRAM controller outlined below Table through Table
Table NPe405 SDRAM0_CFG
Bits Mnemonic MEMCHK REGEN BRPF ECCDD EMDULR Description SDRAM controller enable/disable Self refresh enable/disable Power management enable/disable enable/disable Registered memory enable/disable SDRAM width (must bits) Burst read prefetch driver enable/disable Condition when inactive
Table NPe405 SDRAM0_TR
Bits 9-11 12-13 14-15 16-17 18-26 Mnemonic CASL Reserved latency Reserved Precharge activate minimum Command precharge minimum SDRAM command leadoff Reserved Description
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
SDRAM Controller
Table NPe405 SDRAM0_TR (continued)
27-29 30-31 RFTA before refresh activate delay
Table NPe405 SDRAM0_B0CR
Bits 10-11 12-14 16-18 19-30 Mnemonic Base address Reserved Size Reserved Addressing mode Reserved Memory bank enable Description
PowerQUICC
Similarities exist between SDRAM controller NPe405 PQII, although exact register format differs between two. Registers within PQII directly accessed CPU, instead indirectly accessed with NPe405. PQII registers that involved with SDRAM controller outlined below Table through Table
Table PowerQUICC
Bits 0-16 17-18 19-20 21-22 24-26 28-29 Mnemonic DECC EMEMC ATOM Base address Reserved Size enable/disable Write protect Machine select External memory controller enable Atomic operation enable Data pipelining enable/disable Valid Description
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
SDRAM Controller
Table PowerQUICC
Bits 0-11 12-16 17-18 19-21 23-25 28-31 Mnemonic SDAM LSDAM ROWST NUMR PMSEL IBID Address mask Lower address mask Banks device start address Reserved Number address lines Page mode select Internal bank interleaving Reserved Description
Table PowerQUICC PSDMR
Bits 8-10 11-13 14-16 17-19 20-22 24-25 26-27 30-31 Mnemonic RFEN SDAM BSMA SDA10 RFRC PRETOACT ACTTORW LDOTOPRE EAMUX BUFCMD Description Paged based interleaving Refresh enable SDRAM operation Address multiplex size Bank select multiplexed address control Refresh recovery Precharge activate interval Activate read/write Burst length Last data precharge Write recovery time External address External buffer timing latency
Porting PowerQUICC
Many SDRAM controller registers effortlessly from PowerNP PQII. Consider following SDRAM organization: 32-bit port size Mbit) Each device rows, columns, banks.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
SDRAM Controller
bank-based interleaving, address should partitioned Table
Table Address Partitioning SDRAM
A[0-6] address A[7-8] Bank select A[9-20] A[21-29] Column A[30-31]
Table indicates that during activate command, addresses A[7-20] multiplexed over A[16-29].
Table SDRAM During Activate
A[0-15] A[16-17] Bank select A[7-8] A[18-29] A[9-20] A[30-31]
Table indicates that during read/write command alternates with A[8] lines.
Table SDRAM During Read/Write Command
A[0-5] A[16-17] Bank select A[6-7] A[19] A[20] A[21-29] Column A[30-31]
Using data above assuming timing information, such latency, initialization this SDRAM would shown Table
Table SDRAM Register Mappings NPe405 PQII
NPe405 Register SDRAM0_CFG[SRE] SDRAM0_TR[CASL] SDRAM0_CFG[DRW] SDRAM0_TR[PTA] SDRAM0_TR[CTP] SDRAM0_TR[RFTA] SDRAM0_TR[RCD] SDRAM0_B0CR[BA] SDRAM0_B0CR[BE] PQII Register PSDMR[RFEN] PSDMR[CL] BRx[PS] PSDMR[PRETOACT] PSDMR[LDOTOPRE] PSDMR[RFRC] PSDMR[ACCTORW] BRx[BA] BRx[V] Comments Refresh enabled latency SDRAM width (must bits NPE405) Precharge activate timing command precharge timing Refresh recovery timing Activate read/write timing Base address Memory valid
Unfortunately, memory size column multiplexing readily ported from NPe405 PQII. NPe405 uses pre-defined "modes" (SDRAM0_B0CR[AM]), each which defines supported configuration SDRAM. above example row, column, banks) NPe405 would mode mode, combined with size (SDRAM0TR[SZ]) memory, this case Mbytes, initializes memory controller's multiplexing setting.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Buffer Descriptors
PQII instead provides increased flexibility predefining memory configurations. above configuration, would necessary following: ORx[BPR] banks device ORx[ROWST] 0b0110 define RowStart ORx[NUMR] 0b011 define rows PSDMR[SDAM] 0b001 address multiplexing PSDMR[SDA10] 0b100 output Additionally, PQII accommodates future memory expansion with dedicated bank select signals, instead using address lines select banks. This allows migration SDRAM devices with differing numbers rows columns without hardware change. order dedicated bank select pins, PSDMR[BSMA] must corresponding addresses that output.
Buffer Descriptors
Buffer descriptors (BDs) primary data structures used both NPe405 PQII passing data between higher level software on-chip serial communication peripherals. Organization differs between NPe405 PQII, basic structure similar, easing migration PQII. example, differences serial communication controllers (SCCs) both NPe405 PQII will examined.
NPe405 Buffer Descriptors
NPe405 locates buffers buffer descriptors external memory. descriptors pointers actual buffers organized circular queues. Each on-chip peripheral associated with tables (transmit receive) buffer descriptors table.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Buffer Descriptors
Figure shows example buffer descriptors data buffer organization.
Figure Example Buffer Descriptors Data Buffer Organization
Table shows NPe405 buffer descriptor format.
Table NPe405 Buffer Descriptor Format
Offset Bits 0-15 4-15 0-15 0-15 Field Status control Data length High buffer pointer buffer pointer Description status control information Number bytes sent/received Define 32-bit address where starts
Table shows NPe405 transmit control field.
Table NPe405 Transmit Status Control Field
Bits Mnemonic Description Ready. Indicates buffer ready transmission. Wrap. Last buffer circular table. Continuous mode. Indicates continuous transmission regardless bit. Last buffer frame Reserved Specifies interrupt generated upon processing Allows multiple transmission packet. Reports abort errors during transmission.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Buffer Descriptors
Table NPe405 Transmit Status Control Field (continued)
11-15 Reports FIFO buffer underrun errors specify that frame unnumbered frame. Notifies software corresponding frame been transmitted because link disconnected. Reserved
Table shows NPe405 receive control field.
Table NPe405 Receive Status Control Field
Bits 14-15 Mnemonic Description Empty. Indicates that receive data buffer ready receive data. Wrap. Last buffer circular table. Continuous mode. Indicates continuous transmission regardless bit. Indicates last buffer frame Indicates first buffer frame Specifies interrupt generated upon processing Reports non-byte-aligned frame errors during reception Reports detection too-short frame error Reports detection too-large error Reports detection frame check sequence (FCS) error Reports detection abort error Reports detection FIFO overrun Reports detection protocol error during reception Reports detection frame-sequence error Reserved
PowerQUICC
PQII also uses buffer descriptors (BDs) form circular queues buffers order communicate with on-chip peripherals. purposes this document PQII's will used example organized within PQII. communications controller within PQII that capable protocols such UART, HDLC, AppleTalk, 10bT Ethernet. parameter RAM, located within PQII's internal dual-port RAM, used locate tables memory. SCC, tables located either within internal dual-port external memory. Other peripherals, such fast communications controllers (FCCs) multi-channel controllers (MCCs), require placement external memory. Buffers then pointed tables should also located external memory.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Buffer Descriptors
Figure shows PQII buffer descriptor organization.
Figure PQII Buffer Descriptor Organization
Table shows PQII buffer descriptor format.
Table PQII Buffer Descriptor Format
Offset Bits 0-15 0-15 0-15 0-15 Field Status control Data length High buffer pointer buffer pointer Description status control information Number bytes sent/received Defines 32-bit address where starts
Table shows PQII HDLC TxBD status control field.
Table PQII HDLC TxBD Status Control Field
Bits Mnemonic Description Ready. Used indicate that transmit data buffer ready transmission. Reserved Wrap. Last buffer circular table. Specifies interrupt generated upon processing buffer
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Buffer Descriptors
Table PQII HDLC TxBD Status Control Field (continued)
7-13 Indicates last buffer frame CRC. Specifies should appended frame. Continuous mode. Allows continuous transmission regardless status. Reserved Underrun. after sends buffer transmitter underrun occurs. lost. Indicates lost errors during transmission.
Table shows PQII HDLC RxBD status control field.
Table PQII HDLC RxBD Status Control Field
Bits Mnemonic Description Empty. Indicates corresponding buffer full empty. Reserved Wrap. Last buffer circular table. Specifies interrupt generated upon processing buffer Indicates last buffer frame First frame. Indicates that buffer first frame. Continuous mode. Allows continuous reception data, regardless bit. Reserved DPLL error. DPLL error occurs when buffer being received. Reserved Reports frame length violation Reports nonoctet aligned frames Reports abort sequence Reports error Reports receiver overrun during frame reception Reports loss carrier detect
Porting PowerQUICC
Since both PQII NPe405 rely circular queues buffer descriptors, porting software applications from NPe405 PQII should relatively straightforward. Buffer descriptors
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Time-Slot Assignment
themselves seem have very similar format. However there some application-specific differences. example, PQII utilizes serial communications channels, including UARTs I2C. NPe405 does either above mentioned peripherals.
Time-Slot Assignment
mechanisms handling time-slot assignment differ from NPe405 PQII both actual on-chip peripherals registers used initialize time slots.
NPe405 Time-Slot Assignment
NPe405 provides separate time-slot assigners (TSA1 TSA2). Each time-slot assigner consists RAMs (transmit receive) entries each used assign time slots within NPe405. Each channel programmed independently with 1-bit resolution 4.096 Mbps 8.192 Mbps port
NOTE
rates 4.096 Mbps only port enabled, port must disabled. Table shows NPe405 time-slot assignment.
Table NPe405
Bits 0-23 25-26 27-31 Mnemonic Reserved Indicates that assigned unassigned corresponding channel Default value that places line disabled channel Specifies channel number (from Description
Table shows NPe405 time-slot assignment.
Table NPe405
Bits 0-25 27-31 Mnemonic Reserved Indicates that assigned unassigned corresponding channel Specifies channel number (from Description
PowerQUICC
PQII provides separate time-slot assigners (TSA1 TSA2) capable connecting four independent channels rate each. TDMa also ability used interface clear channel. External signals allow option independent transmit receive frame syncs clocks. Figure shows PQII organization.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Time-Slot Assignment
Figure PowerQUICC Organization
Each serial interface (SI) RAMs associated with transmit receive. Each composed four banks 16-bit entries (256 entries total) that enable control channel routing serial devices within PQII. Each entry table defines routing bits bytes time. evident Figure PQII ability work concert with multi-channel controllers (MCCs). MCCs each have ability perform HDLC formatting/de-formatting transparent channel serial full-duplex data channels. There option table route channel not; routing changes format entry. Without enabled, software ability route directly from serial interface serial communications channel (that FCC, SCC, SMC). Table shows PQII table with enabled.
Table PQII Table
Bits Mnemonic Description Indicates used
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Time-Slot Assignment
Table PQII Table (continued)
SWTR Allows special circumstances where desired receive data transmit data Selects internal strobe pins Reserved Channel select. Selects routing data specific SCC, FCC, SMC. Indicates number bits/bytes this time slot Byte resolution. Defines number field either bits bytes. Indicates last entry table
7-10 11-13
Slacks CSEL
Table shows PQII table with enabled.
Table PQII Table
Bits 3-10 11-13 Mnemonic LOOP/ECHO SUPER MCSEL Description Indicates used not. enable MCC. Channel loopback echo mode. Current timeslot part superchannel Indicates channel this timeslot routed Indicates number bits/bytes this time slot Byte resolution. Defines number field either bits bytes. Indicates last entry RAM.
Porting PowerQUICC
time-slot assignment/configurations supported NPe405 PQII very similar, porting between should straightforward. PQII allows superchannels combining multiple time slots into single channel, which provides added functionality software user chooses take advantage addition, PQII gives user flexibility route directly from serial communications device, HDLC transparent processing. Unfortunately there NPe405, routing within would mean additional programming work. configured using buffer descriptors that very similar PQII buffer descriptors Section "Buffer Descriptors," this application note.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Time-Slot Assignment
Table shows PQII transmit status control field.
Table PQII Transmit Status Control Field
Bits Mnemonic Ready Reserved Wrap. Indicates that this ends circular table. Specifies that interrupt should generated upon processing this Indicates this last frame Specifies that append data transmitted Continuous mode. Allows continuous retransmission data buffer without examining bit. Reserved User defined does touch Reserved Specifies number idle symbols sent after frame closing flag Description
9-11 12-15
Table shows PQII receive status control field.
Table PQII Receive Status Control Field
Bits Mnemonic Description Indicates that empty ready receive data. Reserved Wrap. Indicates that this ends circular table. Specifies that interrupt should generated upon processing this Indicates this last frame First. Indicates this points buffer frame Continuous mode. Allows continuous retransmission data buffer without examining bit. Reserved User defined does touch Reserved
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Table PQII Receive Status Control Field (continued)
14-15 Reports too-large frame error Reports aborted frame errors Reports errors Reserved
major differences between NPe405 PQII lies configuration dynamic time-slot assignment. NPe405 allows software dynamically change routing through process consisting following: Disabling channel through TECR register Waiting TESR report that channel inactive Configuring entry Assigning entry (through bit) Setting "Go" TECR activate channel PQII utilizes sets tables perform dynamic time-slot assignment. active, while shadows active table updated with routes software. Once updates made shadow RAM, software simply swaps active with shadow table, time-slot assignment takes effect.
NPe405
Both NPe405 PowerQUICC support function.
NPe405 includes four channel (unidirectional) controller on-chip. Each channel programmable through configuration registers. controller read write address accessible NPe405. each transfer necessary program channel's control, source, destination, count registers each transfer. NPe405 additionally provides "scatter/gather" functionality. Scatter/gather functionality allows software descriptor table accommodate multiple transfers place individually programming each channel every transfer. implements internal 32-byte buffer, enabled per-channel basis, minimize number discrete memory transactions. Each channel configurable either peripheral memory-to-memory transfers.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
PowerQUICC
PQII provides physical serial (SDMA) engines transactions to/from serial controllers (FCC, MCC, SCC, SMC, I2C). Four additional virtual SDMA channels provided used general-purpose independent (IDMA) channels. Dual address IDMA channels transfer data from source destination using intermediate transfer buffer, located internal PQII dual-port RAM). Transfers memory-to-memory, memory-to-peripheral, peripheral-to-memory. requests made internally configured operate external request mode using external ~DREQ pins. Figure shows PQII dual-address transfer.
Figure PQII Dual-Address Transfer
dual-address transfer, IDMA first reads from source fills internal transfer buffer with data transferred. then empties data from buffer destination initiating separate transfer destination device. Since accesses memory initiated separate transfers case Figure read from SDRAM, write SRAM) addresses would bus, hence name "dual-address transfer". internal transfer buffer described Section 19-5, "IDMA Transfers," MPC8260 PowerQUICC Family Reference Manual. size buffer determined DMA_WRAP must multiple bytes. STS/DTS transfer sizes source destination memory. Valid sizes 1,2,4, bytes, size data transferred memory/peripheral accepts bursts. SS_MAX defined steady-state maximum transfer size IDMA transfer. transfer buffer either filled emptied with SS_MAX bytes. example, initialized SS_MAX, buffer will filled with burst access from source written destination multiple transfers.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Figure PQII Dual-Address Timing Diagram
Figure example dual-address memory-to-peripheral transfer. this case memory Chip Select1, Peripheral CS2. Upon DREQ assertion peripheral, SS_MAX bytes read from memory. purposes this example imagine that SS_MAX port size memory bits wide. Thus four bytes transferred from memory into internal buffer. peripheral port size byte purpose this discussion, following write peripheral only empties byte from internal buffer. will require three more DREQ assertions peripheral order transfer full four bytes. When internal transfer buffer fewer than bytes left this case, one) next DREQ assertion triggers read SS_MAX bytes from memory automatically followed write peripheral. Note that this case example bursting, corresponding memory assignment must programmed accept bursts (that PQII programming).
NOTE
DREQ active high signal. This errata original 8260 user's manual.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Single-address mode bypasses internal transfer buffer 82xx instead transfers data directly between peripheral memory.
Figure PowerQUICC Single Access
example Figure steps would follows:
FPGA requests through ~DREQ signal. PQII preforms write access memory, with address write signal, while asserting ~DACK acknowledge request. Data driven data sourced FPGA input SRAM.
internal intermediate transfer buffer used this mode, thus parameters (SS_MAX, DPR_BUF, DMA_WRAP) related dual-port used.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Figure Fly-By Peripheral Memory Timing
Figure example fly-by timing peripheral memory transfer. above example regular data tenure prior transfer. During fly-by transfer, address memory provided memory from 82xx while data directly from peripheral. this case each DREQ assertion peripheral triggers transfer full port size between peripheral memory. When program transfer length reached ~DONE asserted peripheral, buffer descriptor closed.
Porting PowerQUICC
PQII NPe405 provide equivalent functionality user. NPe405's engine similar PQII's dual-address mode transfers, with some basic differences: NPe405 internal 32-byte buffer, while PQII programmable internal buffer NPe405 ability implement scatter/gather through linked lists. PQII implements similar functionality through circular buffers. addition PQII allows faster transfers peripherals through single-address mode. Since this feature currently available NPe405, porting features should dual-address mode functionality PQII. Single-address DMAs could conceivably implemented later date increase performance certain transfers.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Conclusions
Conclusions
Migrating hardware platform inherent software implications typically becomes challenge engineers unwilling face. Fortunately, both NPe405 PQII based PowerPC architecture, enabling high-level software port with minimal trouble. low-level feature NPe405 subset features available PQII, with many similarities between implementation architectures. shown this document, porting low-level code relatively straightforward process. With software migration longer deciding factor processor selection, embedded processors once again decided upon system architects. Performance, flexibility, features become deciding factors, PowerQUICC family provides compelling story processor choice many today's embedded systems.
Revision History
Table Document Revision History
Revision Number Document template update. Added TOC, history table, minor nontechnical corrections, changed document title from `Software Implications Migrating from NPe495H/L PowerQUICC `Software Migration from NPe495H/L PowerQUICC II'. Initial release. Substantive Change(s)
Table provides revision history this application note.
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
Software Migration from NPe405H/L PowerQUICCII, Rev. Freescale Semiconductor
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Document Number: AN2587 Rev. 01/2007
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