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AN-HK-33

Order this document by AN-HK-33 / H Rev. 1
Freescale Semiconductor
AN-HK-33
In-Circuit Programming of FLASH Memory in the MC68HC908JL3
Freescale Semiconductor, Inc..
Roger Fan Applications Engineering Microcontroller Division Hong Kong This application note describes In-Circuit Programming (ICP) of the FLASH memory in the Freescale MC68HC908JL3 (JL3) microcontroller and its variants: MC68HRC908JL3, MC68HC908JK3, MC68HRC908JK3, MC68HC908JK1, and MC68HRC908JK1. The text is divided into two parts: · · PART 1 - covers a general overview of ICP and techniques that can be applied to the JL3 PART 2 - covers a low-cost ICP implementation for the JL3
For detailed specification on MC68HC908JL3, please refer to the datasheet: Freescale order number MC68HC908JL3 / H.
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Monitor Mode
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Initial FLASH Programming
In-Circuit Programming in User Mode
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In-Circuit Programming in Monitor Mode
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Other ICP Considerations
Signal Conditioning
Normal system activities will usually be halted during an ICP operation, to allow an uninterrupted programming process. Therefore, at the start of the ICP process, the MCU should be configured such that no pin contention or runaway signal will occur during the ICP process. Also note that when the system is first switched-on with a MCU having a blank FLASH memory, the port pins default to their reset states. If the MCU pins used for connecting to the external host are shared with the target system, make sure they are isolated to the proper logic level when the ICP connection is made.
Pin Isolation
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Mass Erasing the FLASH Memory in User Mode
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In the erase routine, the delay timing is based on a bus frequency of 2.4576MHz, and the mass erase operation is repeated until the user vectors and the security bytes are erased. The time required for the mass erase operation is less than two seconds.
VDD JL3 MCU
PTB0 Pins for target system use
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Figure 1. Mass Erase Port Pin Configuration The flowchart in figure 2 shows the sequence of events for the mass erase operation.
Power-On Reset
Perform mass erase routine
Continue with user main program
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Procedure for mass erase Using the sample program, this step-by-step procedure erases the JL3 FLASH in user mode: 1. Switch off the power to the target system. 2. Isolate port pins PTB0 and PTD3 from target system logic. 3. Set PTB0 to high via a pull-up resistor to VDD. 4. Set PTD3 to ground directly to VSS. 5. Switch on the power to the target system. 6. Wait 2 seconds.
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7. Switch off power to the target system. 8. FLASH memory is now erased. The next section describes the procedure for programming the JL3 FLASH memory using blank vector entry to monitor mode.
Programming the FLASH Memory in Monitor Mode
The latter method for entering monitor mode for programming the FLASH memory will be described here. With this method, the MCU enters monitor mode after a power-on reset when it detects that the reset
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SPGMR08 Adapter board connector Pin 1 GND
(9.8304MHz)
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Pins for target system use
PTB3 PTB1 PTB2 RST
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Freescale Semiconductor, Inc. Further Information
The above ICP method has two limitations. They are: 1. The erase and program operations are for the entire 4k-bytes of FLASH memory - An erase operation erases all FLASH locations a program operation programs all FLASH locations. 2. There must be no power outage during erase or program operations otherwise, a high voltage must be applied to the IRQ1 pin so that the MCU can enter Monitor mode. The alternative is to extract the MCU off the target system and reprogrammed using an external programmer.
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Further cost-savings can be achieved by using the circuit in figure 4 to replace the SPGMR08 serial programmer.
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7.5 to 8.5V
0.1 µF 10 µF 10 k 10 k 1k 1N914 2N3906 VDD
2N3906
(for high voltage entry to monitor mode)
Serial programming Schematic
74HC125
1 k 2N3904
74HC125 74HC125 74HC125
9.8304 MHz OSCILLATOR
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The CLK signal is optional.
9.8304 MHz
CLK (optional)
The VTST signal is only required for high voltage entry to Monitor Mode.
Freescale Semiconductor, Inc. Program Listing
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