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GS8321Z18 / 32 / 36E-xxxV

36Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8321Z18 / 32 / 36E-xxxV
165-Bump FP-BGA Commercial Temp Industrial Temp Features
· User-configurable Pipeline and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization · Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBL and ZBT SRAMs · IEEE 1149.1 JTAG-compatible Boundary Scan · 1.8 V or 2.5 V core power supply · 1.8 V or 2.5 V I / O supply · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ pin for automatic power-down · JEDEC-standard 165-bump FP-BGA package · RoHS-compliant 165-bump BGA package available
36Mb Pipelined and Flow Through Synchronous NBT SRAM
250 MHz-133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I / O
Functional Description
Parameter Synopsis
tKQ tCycle Curr (x18) Curr (x32 / x36) tKQ Flow tCycle Through Curr (x18) 2-1-1-1 Curr (x32 / x36) Pipeline 3-1-1-1 -250 -225 -200 -166 -150 -133 Unit 3.0 3.0 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.6 7.5 ns 285 350 6.5 6.5 205 235 265 320 7.0 7.0 195 225 245 295 7.5 7.5 185 210 220 210 185 mA 260 240 215 mA 8.0 8.5 8.5 ns 8.0 8.5 8.5 ns 175 165 155 mA 200 190 175 mA
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
165 Bump BGA-x18 Commom I / O-Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQB NC LBO 2 A A NC DQB DQB DQB DQB MCH NC NC NC NC NC NC A 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC DQA DQA DQA DQA DQA ZZ NC NC NC NC NC NC A A B C D E F G H J K L M N P R
11 x 15 Bump BGA-15 mm x 17 mm Body-1.0 mm Bump Pitch
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
165 Bump BGA-x32 Common I / O-Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC DQC DQC DQC DQC FT DQD DQD DQD DQD NC NC LBO 2 A A NC DQC DQC DQC DQC MCH DQD DQD DQD DQD NC NC A 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC NC DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC NC A A B C D E F G H J K L M N P R
11 x 15 Bump BGA-15 mm x 17 mm Body-1.0 mm Bump Pitch
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
165 Bump BGA-x36 Common I / O-Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC DQC DQC DQC DQC DQC FT DQD DQD DQD DQD DQD NC LBO 2 A A NC DQC DQC DQC DQC MCH DQD DQD DQD DQD NC NC A 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA NC A A B C D E F G H J K L M N P R
11 x 15 Bump BGA-15 mm x 17 mm Body-1.0 mm Bump Pitch
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
GS8321Z18 / 32 / 36E-xxxV 165-Bump BGA Pin Description Symbol
A 0, A 1 An DQA DQB DQC DQD BA , BB , BC , BD NC CK CKE W E1 E3 E2 FT G ADV ZZ LBO TMS TDI TDO TCK MCH VDD VSS VDDQ
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I / Os active low No Connect Clock Input Signal active high Clock Enable active low Write Enable active low Chip Enable active low Chip Enable active low Chip Enable active high Flow Through / Pipeline Mode Control Output Enable active low Burst address counter advance enable active high Sleep mode control active high Linear Burst Order mode active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High Core power supply I / O and Core Ground Output driver power supply
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
GS8321Z18 / 32 / 36E-xxxV NBT SRAM Functional Block Diagram
DQa-DQn
Write Data
Register 1
Write Data
Write Address
Burst Counter
Register 2
Read, Write and
Data Coherency
Control Logic
SA1 SA0
Write Address
Register 1
Match
A0-An
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Write Drivers
Memory Array
Register 2
Sense Amps
GS8321Z18 / 32 / 36E-xxxV
Functional Details
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Synchronous Truth Table Operation
Read Cycle, Begin Burst Read Cycle, Continue Burst NOP / Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ
Q Q High-Z High-Z D D
Notes
High-Z 1, 2, 3, 10 High-Z High-Z High-Z High-Z High-Z High-Z 4 1 1
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Pipelined and Flow Through Read Write Control State Diagram
Deselect
New Read
New Write
Burst Read
Burst Write
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n) Next State (n+1)
2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. n+2 n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read / Write Control State Diagram
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Pipeline Mode Data I / O State Diagram
Intermediate
B W High Z (Data In) D
Intermediate W Intermediate Intermediate
R B Data Out (Q Valid) D
Intermediate
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n)
Transition Next State (n+2)
Intermediate State (N+1)
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate State
Next State
Current State and Next State Definition for Pipeline Mode Data I / O State Diagram
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Flow Through Mode Data I / O State Diagram
B W High Z (Data In) D
R B Data Out (Q Valid) D
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n) Next State (n+1)
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
Function
Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence A1:0 A1:0 A1:0 A1:0
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A1:0 A1:0 A1:0 A1:0
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Sleep Mode Timing Diagram
tKH tKC CK tZZR tZZS ZZ tZZH tKL
Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VI / O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage on VDDQ Pins Voltage on I / O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I / O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to VDD -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) + / -20 + / -20 1.5 -55 to 125 -55 to 125
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Power Supply Voltage Ranges (1.8 V / 2.5 V Version) Parameter
1.8 V Supply Voltage 2.5 V Supply Voltage 1.8 V VDDQ I / O Supply Voltage 2.5 V VDDQ I / O Supply Voltage
Symbol
VDD1 VDD2 VDDQ1 VDDQ2
2.0 2.7 VDD VDD
Notes
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
VDDQ2 & VDDQ1 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage
Symbol
VIH VIL
0.6VDD -0.3
VDD + 0.3 0.3VDD
Notes
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Notes
Undershoot Measurement and Timing
Overshoot Measurement and Timing
Capacitance
Parameter
Input Capacitance Input / Output Capacitance Note: These parameters are sample tested.
Symbol
Test conditions
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
Distributed Test Jig Capacitance
Figure 1
Output Load 1 DQ 50 30pF
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) FT, ZZ Input Current Output Leakage Current
Symbol
IIL IIN IOL
Test Conditions
-1 uA -100 uA -1 uA
DC Output Characteristics (1.8 V / 2.5 V Version) Parameter
1.8 V Output High Voltage 2.5 V Output High Voltage 1.8 V Output Low Voltage 2.5 V Output Low Voltage
Symbol
VOH1 VOH2 VOL1 VOL2
Test Conditions
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-250 Mode Symbol 0 to 70°C -40 to 85°C 320 50 220 25 280 25 200 15 80 80 115 100 85 100 95 110 90 80 60 80 60 80 105 95 60 80 60 80 60 60 85 80 180 15 190 15 170 15 180 15 160 15 170 15 80 80 100 95 240 25 260 25 225 20 245 20 200 20 220 20 190 20 150 15 60 60 85 75 210 20 160 15 80 80 100 90 200 25 210 25 190 20 200 20 180 20 190 20 170 20 180 20 160 15 170 15 140 15 60 60 80 70 275 45 295 45 255 40 275 40 225 35 245 35 210 30 230 30 190 25 210 25 170 15 190 15 150 15 80 80 95 85
-225 0 to 70°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C Unit
Rev: 1.05a 12 / 2007 Pipeline (x32 / x36) Flow Through Pipeline (x18) Flow Through IDDQ ISB 60 60 100 85 ISB IDD IDD Pipeline - Flow Through Pipeline - Flow Through IDD 190 15 IDDQ IDD 260 25 IDD IDDQ 210 25 IDD IDDQ 300 50
Parameter
Test Conditions
Operating Current
Device Selected All other inputs VIH or VIL Output open
Standby Current
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Deselect Current
Device Deselected All other inputs VIH or VIL
Notes: 1. IDD and IDDQ apply to any combination of VDD1, VDD2, VDDQ1, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
GS8321Z18 / 32 / 36E-xxxV
AC Electrical Characteristics
Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Pipeline Mode Timing (NBT)
Write A Read B Suspend tKH tKL Read C tKC Write D writeno-op Read E Deselect
tH tS tLZ tKQ Q(B) Q(C) D(D) Q(E) tHZ tKQX
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Flow Through Mode Timing (NBT)
Write A Write B Write B+1 tKL tKH
Read C tKC
Read D
Write E
Read F
Write G
tKQ tH tS
DQ D(A) D(B)
tKQ tLZ
D(B+1) Q(C)
tKQX tHZ
D(E) Q(F)
tOLZ tOE tOHZ
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
Test Data In
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
JTAG TAP Block Diagram
Boundary Scan Register
Bypass Register
Instruction Register TDI ID Code Register
Control Signals TMS TCK Test Access Port (TAP) Controller
For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com. Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
GSI Technology JEDEC Vendor ID Code Presence Register 0 1
Not Used
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Tap Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990 the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I / O pads, and can be used to load address, data or control signals into the RAM or to preload the I / O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
Run Test Idle
Select DR
Select IR
Capture DR
Capture IR
Shift DR
Shift IR
Exit1 DR
Exit1 IR
Pause DR
Pause IR
Exit2 DR
Exit2 IR
Update DR
Update IR
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE / PRELOAD GSI RFU
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I / O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I / O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Notes
BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8 / 2.5 V Version) Parameter
1.8 V Test Port Input Low Voltage 2.5 V Test Port Input Low Voltage 1.8 V Test Port Input High Voltage 2.5 V Test Port Input High Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VILJ1 VILJ2 VIHJ1 VIHJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
-0.3 -0.3 0.6 VDD1 0.6 VDD2 -300 -1 -1 1.7 - VDDQ - 100 mV -
0.3 VDD1 0.3 VDD2 VDD1 +0.3 VDD2 +0.3 1 100 1 - 0.4 - 100 mV
Unit Notes
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
JTAG Port AC Test Load
Distributed Test Jig Capacitance
Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 - 20 20 10 10 Max - 20 - - - - Unit ns ns ns ns ns ns
Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com.
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Package Dimensions-165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
A1 CORNER
Rev: 1.05a 12 / 2007
0.36~0.46 1.50 MAX.
SEATING PLANE
0.20 C
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Ordering Information for GSI Synchronous Burst RAMs Org
Part Number1
GS8321Z18E-250V GS8321Z18E-225V GS8321Z18E-200V GS8321Z18E-166V GS8321Z18E-150V GS8321Z18E-133V GS8321Z32E-250V GS8321Z32E-225V GS8321Z32E-200V GS8321Z32E-166V GS8321Z32E-150V GS8321Z32E-133V GS8321Z36E-250V GS8321Z36E-225V GS8321Z36E-200V GS8321Z36E-166V GS8321Z36E-150V GS8321Z36E-133V GS8321Z18E-250IV GS8321Z18E-225IV GS8321Z18E-200IV GS8321Z18E-166IV GS8321Z18E-150IV GS8321Z18E-133IV GS8321Z32E-250IV GS8321Z32E-225IV GS8321Z32E-200IV GS8321Z32E-166IV
NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT
Voltage Option
Package
165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA
Speed2 (MHz / ns)
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Ordering Information for GSI Synchronous Burst RAMs Org
Part Number1
GS8321Z32E-133IV GS8321Z36E-250IV GS8321Z36E-225IV GS8321Z36E-200IV GS8321Z36E-166IV GS8321Z36E-150IV GS8321Z36E-133IV GS8321Z18GE-250V GS8321Z18GE-225V GS8321Z18GE-200V GS8321Z18GE-166V GS8321Z18GE-150V GS8321Z18GE-133V GS8321Z32GE-250V GS8321Z32GE-225V GS8321Z32GE-200V GS8321Z32GE-166V GS8321Z32GE-150V GS8321Z32GE-133V GS8321Z36GE-250V GS8321Z36GE-225V GS8321Z36GE-200V GS8321Z36GE-166V GS8321Z36GE-150V GS8321Z36GE-133V GS8321Z18GE-250IV GS8321Z18GE-225IV GS8321Z18GE-200IV GS8321Z18GE-166IV GS8321Z18GE-150IV
NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT
Voltage Option
Package
165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA
Speed2 (MHz / ns)
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
Ordering Information for GSI Synchronous Burst RAMs Org
Part Number1
GS8321Z32GE-250IV GS8321Z32GE-225IV GS8321Z32GE-200IV GS8321Z32GE-166IV GS8321Z32GE-150IV GS8321Z32GE-133IV GS8321Z36GE-250IV GS8321Z36GE-225IV GS8321Z36GE-200IV GS8321Z36GE-166IV GS8321Z36GE-150IV
NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT NBT
Voltage Option
Package
RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA RoHS-compliant 165 BGA
Speed2 (MHz / ns)
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18 / 32 / 36E-xxxV
36Mb Sync SRAM Data Sheet Revision History
Content Content / Format Content Content
Rev: 1.05a 12 / 2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.