user-configurable flow through pipeline operation Dual Cycle Deselect

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user-configurable flow through pipeline operation Dual Cycle Deselect

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GS8321E18/32/36E-xxxV
user-configurable flow through pipeline operation Dual Cycle Deselect (DCD) operation IEEE 1149.1 JTAG-compatible Boundary Scan core power supply supply Linear Interleaved Burst mode Internal input resistors mode pins allow floating mode pins Default Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down portable applications JEDEC-standard 165-bump FP-BGA package RoHS-compliant 165-bump package available
36Mb Sync Burst SRAMs
MHz-133
Linear Burst Order (LBO) input. Burst function need used. addresses loaded every cycle with degradation chip performance.
Flow Through/Pipeline Reads function Data Output register controlled user mode (Pin 14). Holding mode places Flow Through mode, causing output data bypass Data Output Register. Holding high places Pipeline mode, activating rising-edge-triggered Data Output Register. Pipelined Reads GS8321E18/32/36E-xxxV (Dual Cycle Deselect) pipelined synchronous SRAM. (Single Cycle Deselect) versions also available. SRAMs pipeline disable commands same degree read commands. RAMs hold deselect command full cycle then begin turning their outputs just after second rising edge clock. Byte Write Global Write Byte write operation performed using Byte Write enable (BW) input combined with more individual byte write signals (Bx). addition, Global Write (GW) available writing bytes time, regardless Byte Write control inputs. Sleep Mode power (Sleep mode) attained through assertion (High) signal, stopping clock (CK). Memory data retained during Sleep mode. Core Interface Voltages GS8321E18/32/36E-xxxV operates power supply. inputs compatible. Separate output power (VDDQ) pins used decouple output noise from internal circuits Vcompatible.
Functional Description
Applications GS8321E18/32/36E-xxxV 37,748,736-bit high performance synchronous SRAM with 2-bit burst address counter. Although type originally developed Level Cache applications supporting high performance CPUs, device finds application synchronous SRAM applications, ranging from main store networking chip support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) write control inputs (Bx, synchronous controlled positive-edgetriggered clock input (CK3). Output enable power down control (ZZ) asynchronous inputs. Burst cycles initiated with either ADSP ADSC inputs. Burst mode, subsequent burst addresses generated internally controlled ADV. burst address counter configured count either linear interleave order with
Parameter Synopsis
tCycle Curr (x18) Curr (x32/x36) Flow tCycle Through Curr (x18) 2-1-1-1 Curr (x32/x36) Pipeline 3-1-1-1 Rev: 1.05a 12/2007 -250 -225 -200 -166 -150 -133 Unit 1/31 2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
Bump BGA-x18 Commom I/O-Top View (Package
DQPB VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ADSC ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPA
Bump BGA-15 Body-1.0 Bump Pitch
Rev: 1.05a 12/2007
2/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
Bump BGA-x32 Common I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ADSC ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-15 Body-1.0 Bump Pitch
Rev: 1.05a 12/2007
3/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
Bump BGA-x36 Common I/O-Top View (Package
DQPC DQPD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ADSC ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPB DQPA
Bump BGA-15 Body-1.0 Bump Pitch
Rev: 1.05a 12/2007
4/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
GS8321E18/32/36E-xxxV 165-Bump Description Symbol
ADSC, ADSP VDDQ
Type
Description
Address field LSBs Address Counter Preset Inputs Address Inputs Data Input Output pins Byte Write Enable DQA, DQB, DQC, I/Os; active Connect Clock Input Signal; active high Byte Write-Writes enabled bytes; active Global Write Enable-Writes bytes; active Chip Enable; active Chip Enable; active Chip Enable; active high Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep mode control; active high Flow Through Pipeline mode; active Linear Burst Order mode; active Scan Test Mode Select Scan Test Data Scan Test Data Scan Test Clock Must Connect Core power supply Core Ground Output driver power supply
Rev: 1.05a 12/2007
5/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
GS8321E18/32/36E-xxxV Block Diagram
Register
A0-An
Counter Load
ADSC ADSP
Register
Memory Array
Register
Register
Register
Register
Register
Register
Register
Parity Encode Parity Compare
Register
Power Down Control
DQx1-DQx9
Note: Only version shown simplicity.
Rev: 1.05a 12/2007
6/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Register
GS8321E18/32/36E-xxxV
Mode Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Name
State
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby,
Note: There pull-down device pin, this input unconnected chip will operate default states specified above table. There pull-up device pull-down device pin, this input unconnected chip will operate default states specified above table.
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Note: burst counter wraps initial state clock.
Note: burst counter wraps initial state clock.
1999.05.18
Rev: 1.05a 12/2007
7/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
Byte Write Truth Table Function
Read Write Bytes Write byte Write byte Write byte Write byte Write bytes Write bytes
Notes
Notes: byte outputs active read cycles regardless state Byte Write Enable inputs, and/or Byte Write Enable inputs and/or used combination with write single multiple bytes. byte I/Os remain High-Z during write operations regardless state Byte Write Enable inputs. Bytes only available versions.
Rev: 1.05a 12/2007
8/31
2003, Technology
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GS8321E18/32/36E-xxxV
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
State Address Diagram Used
None None None None None External External External Next Next Next Next Current Current Current Current
ADSP ADSC
High-Z High-Z High-Z High-Z High-Z
Notes: Don't Care, High, (True) (False) (True) (False) defined Byte Write Truth Table preceding. asynchronous input. driven high time disable active output drivers. only enable active drivers (shown Truth Table above). input combinations shown above tested supported. Input combinations shown gray boxes need used accomplish basic synchronous synchronous burst operations avoided simplicity. Tying ADSP high ADSC allows simple non-burst synchronous operations. BOLD items above. Tying ADSP high while using ADSC load addresses allows simple burst operations. ITALIC items above.
Rev: 1.05a 12/2007
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GS8321E18/32/36E-xxxV
Simplified State Diagram
Deselect Simple Synchronous Operation
First Write
First Read
Simple Burst Synchronous Operation
Burst Write
Burst Read
Notes: diagram shows only supported (tested) synchronous state transitions. diagram presumes tied low. upper portion diagram assumes active only Enable (E1) Write (BA, control inputs, that ADSP tied high ADSC tied low. upper lower portions diagram together assume active only Enable, Write, ADSC control inputs, assumes ADSP tied high tied low.
Rev: 1.05a 12/2007
10/31
2003, Technology
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GS8321E18/32/36E-xxxV
Simplified State Diagram with
Deselect
First Write
First Read
Burst Write
Burst Read
Notes: diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon "Dummy Reads" (Read Cycles with High) used make transition from read cycles write cycles without passing through Deselect cycle. Dummy Read cycles increment address counter just like normal read cycles. Transitions shown gray tone assume been pulsed high long enough turn RAM's drivers incoming data meet Data Input Time.
Rev: 1.05a 12/2007
11/31
2003, Technology
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GS8321E18/32/36E-xxxV
Absolute Maximum Ratings
(All voltages reference VSS)
Symbol
VDDQ VI/O IOUT TSTG TBIAS
Description
Voltage Pins Voltage VDDQ Pins Voltage Pins Voltage Other Input Pins Input Current Output Current Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 -0.5 -0.5 VDDQ +0.5 max.) -0.5 +0.5 max.) +/-20 +/-20
Unit
Note: Permanent damage device occur Absolute Maximum Ratings exceeded. Operation should restricted Recommended Operating Conditions. Exposure conditions exceeding Absolute Maximum Ratings, extended period time, affect reliability this component.
Power Supply Voltage Ranges (1.8 V/2.5 Version) Parameter
Supply Voltage Supply Voltage VDDQ Supply Voltage VDDQ Supply Voltage
Symbol
VDD1 VDD2 VDDQ1 VDDQ2
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Rev: 1.05a 12/2007
12/31
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GS8321E18/32/36E-xxxV
VDDQ2 VDDQ1 Range Logic Levels Parameter
Input High Voltage Input Voltage
Symbol
Min.
0.6*VDD -0.3
Typ.
Max.
0.3*VDD
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Undershoot Measurement Timing
Overshoot Measurement Timing
Capacitance
25oC, MHZ,
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters sample tested.
Symbol
CI/O
Test conditions
VOUT
Typ.
Max.
Unit
Rev: 1.05a 12/2007
13/31
2003, Technology
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GS8321E18/32/36E-xxxV
Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level Output load
Conditions
V/ns VDD/2 VDDQ/2 Fig. VDDQ/2
Distributed Test Capacitance
Figure
Output Load 30pF*
Notes: Include scope capacitance. Test conditions specified with output loading shown Fig. unless otherwise noted. Device deselected defined Truth Table.
Electrical Characteristics Parameter
Input Leakage Current (except mode pins) Input Current Output Leakage Current
Symbol
Test Conditions
Output Disable, VOUT
-100
Output Characteristics (1.8 V/2.5 Version) Parameter
Output High Voltage Output High Voltage Output Voltage Output Voltage
Symbol
VOH1 VOH2 VOL1 VOL2
Test Conditions
VDDQ VDDQ 2.375
VDDQ
Rev: 1.05a 12/2007
14/31
2003, Technology
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Operating Currents
-250 Mode Symbol 70°C 85°C Unit
-225 70°C 85°C 85°C 85°C 85°C 85°C 70°C 70°C 70°C 70°C
-200
-166
-150
-133
Rev: 1.05a 12/2007 Pipeline (x32/ x36) Flow Through IDDQ IDDQ IDDQ Pipeline (x18) Flow Through Pipeline Flow Through Pipeline Flow Through IDDQ
Parameter
Test Conditions
Operating Current
Device Selected; other inputs Output open
15/31
Standby Current
Deselect Current
Device Deselected; other inputs
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Notes: IDDQ apply combination VDD1, VDD2, VDDQ1, VDDQ2 operation. parameters listed worst case scenario.
GS8321E18/32/36E-xxxV
2003, Technology
GS8321E18/32/36E-xxxV
Electrical Characteristics
Parameter Clock Cycle Time Clock Output Valid Pipeline Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock Cycle Time Clock Output Valid Flow Through Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock HIGH Time Clock Time Clock Output High-Z Output Valid output Low-Z output High-Z setup time hold time recovery Symbol tKQX tLZ1 tKQX tLZ1 tHZ1 tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR -250 -225 -200 -166 -150 -133 Unit
Notes: These parameters sampled 100% tested. asynchronous signal. However, order recognized given clock cycle, must meet specified setup hold times specified above.
Rev: 1.05a 12/2007
16/31
2003, Technology
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GS8321E18/32/36E-xxxV
Pipeline Mode Timing (DCD)
Begin
Read
Cont
Deselect Deselect Write
Read
Read Read Read Cont
Deselect Deselect
ADSP ADSC Ao-An
ADSC initiated read
Ba-Bd DQa-DQd
Hi-Z only sampled with ADSC Deselected with
Q(C) Q(C+1) Q(C+2) Q(C+3)
tKQX
tOHZ
Q(A) D(B)
Rev: 1.05a 12/2007
17/31
2003, Technology
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GS8321E18/32/36E-xxxV
Flow Through Mode Timing (DCD)
Begin
Read
Cont
Deselect Write
Read
Read Read Read Read
Deselect
ADSP ADSC Ao-An
Fixed High
ADSC initiated read
Ba-Bd DQa-DQd
Q(A) masks ADSP Deselected with
only sampled with ADSP ADSC
masks ADSP
tOHZ
D(B)
Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tKQX
Rev: 1.05a 12/2007
18/31
2003, Technology
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GS8321E18/32/36E-xxxV
Sleep Mode
During normal operation, must pulled low, either user internal pull down resistor. When pulled high, SRAM will enter Power Sleep mode after cycles. this time, internal state SRAM preserved. When returns low, SRAM operates normally after recovery time. Sleep mode current, power-down mode which device deselected current reduced ISB2. duration Sleep mode dictated length time High state. After entering Sleep mode, inputs except become disabled outputs High-Z asynchronous, active high input that causes device enter Sleep mode. When driven high, ISB2 guaranteed after time tZZI met. Because asynchronous input, pending operations operations progress properly completed asserted. Therefore, Sleep mode must initiated until valid pending operations completed. Similarly, when exiting Sleep mode during tZZR, only Deselect Read commands applied while SRAM recovering from Sleep mode.
Sleep Mode Timing Diagram
Setup Hold ADSP ADSC tZZR tZZS tZZH
Application Tips
Single Dual Cycle Deselect devices force "dummy read cycles" (read cycles that launched normally that ended with output drivers inactive) fully synchronous environment. Dummy read cycles waste performance their usually assures there will contention transitions from reads writes between banks RAMs. SRAMs (like this one) waste bandwidth dummy cycles logically simpler manage multiple bank application (wait states need inserted bank address boundary crossings) greater care must exercised avoid excessive contention.
JTAG Port Operation
Overview JTAG Port this operates manner that compliant with IEEE Standard 1149.1-1990, serial boundary scan interface standard (commonly referred JTAG). JTAG Port input interface levels scale with VDD. JTAG output drivers powered VDDQ. Disabling JTAG Port possible this device without utilizing JTAG port. port reset power-up will remain inactive unless clocked. TCK, TDI, designed with internal pull-up circuits.To assure normal operation with JTAG Port unused, TCK, TDI, left floating tied either VSS. should left unconnected.
Rev: 1.05a 12/2007
19/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
JTAG Descriptions
Name
Test Clock Test Mode Select
Description
Clocks events. inputs captured rising edge outputs propagate from falling edge TCK. input sampled rising edge TCK. This command input controller state machine. undriven input will produce same result logic input level. input sampled rising edge TCK. This input side serial registers placed between TDO. register placed between determined state Controller state machine instruction that currently loaded Instruction Register (refer Controller State Diagram). undriven will produce same result logic input level.
Test Data
Test Data
Output that active depending state state machine. Output changes response falling edge TCK. This output side serial registers placed between TDO.
Note: This device does have TRST (TAP Reset) pin. TRST optional IEEE 1149.1. Test-Logic-Reset state entered while held high five rising edges TCK. Controller also reset automaticly power-up.
JTAG Port Registers
Overview various JTAG registers, refered Test Access Port orTAP Registers, selected (one time) sequences applied strobed. Each Registers serial shift register that captures serial input data rising edge pushes serial data next falling edge TCK. When register selected, placed between pins. Instruction Register Instruction Register holds instructions that executed controller when moved into Run, Test/Idle, various data register states. Instructions bits long. Instruction Register loaded when placed between pins. Instruction Register automatically preloaded with IDCODE instruction power-up whenever controller placed Test-Logic-Reset state. Bypass Register Bypass Register single register that placed between TDO. allows serial test data passed through RAM's JTAG Port another device scan chain with little delay possible. Boundary Scan Register Boundary Scan Register collection flip flops that preset logic level found RAM's input pins. flip flops then daisy chained together levels found shifted serially JTAG Port's pin. Boundary Scan Register also includes number place holder flip flops (always logic relationship between device pins bits Boundary Scan Register described Scan Order Table following. Boundary Scan Register, under control Controller, loaded with contents RAMs ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD EXTEST instructions used activate Boundary Scan Register.
Rev: 1.05a 12/2007
20/31
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GS8321E18/32/36E-xxxV
JTAG Block Diagram
Boundary Scan Register
Bypass Register
Instruction Register Code Register
Control Signals Test Access Port (TAP) Controller
value BSDL file, which available contacting apps@gsitechnology.com. Identification (ID) Register Register 32-bit register that loaded with device vendor specific 32-bit code when controller Capture-DR state with IDCODE command loaded Instruction Register. code loaded from 32-bit on-chip ROM. describes various attributes indicated below. register then placed between pins when controller moved into Shift-DR state. register first reach when shifting begins.
Register Contents
Technology JEDEC Vendor Code Presence Register
Used
Rev: 1.05a 12/2007
21/31
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GS8321E18/32/36E-xxxV
Controller Instruction
Overview There classes instructions defined Standard 1149.1-1990; standard (Public) instructions, device specific (Private) instructions. Some Public instructions mandatory 1149.1 compliance. Optional Public instructions must implemented prescribed ways. this device used monitor input pads, used load address, data control signals into preload buffers. When controller placed Capture-IR state least significant bits instruction register loaded with When controller moved Shift-IR state Instruction Register placed between TDO. this state desired instruction serially loaded through input (while previous contents shifted TDO). instructions, executes newly loaded instructions only when controller moved Update-IR state. instruction this device listed following table.
JTAG Controller State Diagram
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Exit2
Update
Update
Instruction Descriptions BYPASS When BYPASS instruction loaded Instruction Register Bypass Register placed between TDO. This occurs when controller moved Shift-DR state. This allows board level scan path shortened facilitate testing other devices scan path.
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GS8321E18/32/36E-xxxV
SAMPLE/PRELOAD SAMPLE/PRELOAD Standard 1149.1 mandatory public instruction. When SAMPLE PRELOAD instruction loaded Instruction Register, moving controller into Capture-DR state loads data RAMs input buffers into Boundary Scan Register. Boundary Scan Register locations associated with input pin, loaded with default state identified Boundary Scan Chain table this section datasheet. Because clock independent from Clock (TCK) possible attempt capture ring contents while input buffers transition (i.e. metastable state). Although allowing sample metastable inputs will harm device, repeatable results cannot expected. input signals must stabilized long enough meet TAPs input data capture set-up plus hold time (tTS plus tTH). RAMs clock inputs need paused other operation except capturing ring contents into Boundary Scan Register. Moving controller Shift-DR state then places boundary scan register between pins. EXTEST EXTEST IEEE 1149.1 mandatory public instruction. executed whenever instruction register loaded with logic EXTEST command does block override RAM's input pins; therefore, RAM's internal state still determined input pins. Typically, Boundary Scan Register loaded with desired pattern data with SAMPLE/PRELOAD command. Then EXTEST command used output Boundary Scan Register's contents, parallel, RAM's data output drivers falling edge when controller Update-IR state. Alternately, Boundary Scan Register loaded parallel using EXTEST command. When EXTEST instruction selected, sate RAM's input pins, well default values Scan Register locations associated with pin, transferred parallel into Boundary Scan Register rising edge Capture-DR state, RAM's output pins drive value Boundary Scan Register location with which each output associated. IDCODE IDCODE instruction causes loaded into register when controller Capture-DR mode places register between pins Shift-DR mode. IDCODE instruction default instruction loaded power time controller placed Test-Logic-Reset state. SAMPLE-Z SAMPLE-Z instruction loaded instruction register, outputs forced inactive drive state (highZ) Boundary Scan Register connected between when controller moved Shift-DR state. These instructions Reserved Future Use. this device they replicate BYPASS instruction.
Rev: 1.05a 12/2007
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GS8321E18/32/36E-xxxV
JTAG Instruction Summary Instruction
EXTEST IDCODE SAMPLE-Z SAMPLE/ PRELOAD
Code
Description
Places Boundary Scan Register between TDO. Preloads Register places between TDO. Captures ring contents. Places Boundary Scan Register between TDO. Forces output drivers High-Z. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO. Captures ring contents. Places Boundary Scan Register between TDO. private instruction. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO.
Notes
BYPASS Places Bypass Register between TDO. Notes: Instruction codes expressed binary, left, right. Default instruction automatically loaded power-up test-logic-reset state.
Rev: 1.05a 12/2007
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GS8321E18/32/36E-xxxV
JTAG Port Recommended Operating Conditions Characteristics (1.8/2.5 Version) Parameter
Test Port Input Voltage Test Port Input Voltage Test Port Input High Voltage Test Port Input High Voltage TMS, Input Leakage Current TMS, Input Leakage Current Output Leakage Current Test Port Output High Voltage Test Port Output Voltage Test Port Output CMOS High Test Port Output CMOS
Symbol
VILJ1 VILJ2 VIHJ1 VIHJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
-0.3 -0.3 VDD1 VDD2 -300 VDDQ
Max.
VDD1 VDD2 VDD1 +0.3 VDD2 +0.3
Unit Notes
Notes: Input Under/overshoot voltage must VDDn exceed maximum, with pulse width exceed tTKC. VILJ VDDn VILJn Output Disable, VOUT VDDn output driver served VDDQ supply. IOHJ IOLJ IOHJC -100 IOLJC +100
JTAG Port Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level
Conditions
V/ns VDDQ/2 VDDQ/2
JTAG Port Test Load
VDDQ/2
Distributed Test Capacitance
30pF*
Notes: Include scope capacitance. Test conditions shown unless otherwise noted.
Rev: 1.05a 12/2007
25/31
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Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
JTAG Port Timing Diagram
tTKC tTKQ Parallel SRAM input tTKH tTKL
JTAG Port Electrical Characteristics
Parameter Cycle Time Valid High Pulse Width Pulse Width Time Hold Time Symbol tTKC tTKQ tTKH tTKL Unit
Boundary Scan (BSDL Files) information regarding Boundary Scan Chain, obtain BSDL files this part, please contact Applications Engineering Department apps@gsitechnology.com.
Rev: 1.05a 12/2007
26/31
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GS8321E18/32/36E-xxxV
Package Dimensions-165-Bump FPBGA (Package
CORNER
VIEW
BOTTOM VIEW (165x)
CORNER
10.0 0.20(4x) 15±0.05
17±0.05
14.0
Rev: 1.05a 12/2007
0.36~0.46 1.50 MAX.
SEATING PLANE
0.20
27/31
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GS8321E18/32/36E-xxxV
Ordering Information Synchronous Burst RAMs
Part Number1
GS8321E18E-250V GS8321E18E-225V GS8321E18E-200V GS8321E18E-166V GS8321E18E-150V GS8321E18E-133V GS8321E32E-250V GS8321E32E-225V GS8321E32E-200V GS8321E32E-166V GS8321E32E-150V GS8321E32E-133V GS8321E36E-250V GS8321E36E-225V GS8321E36E-200V GS8321E36E-166V GS8321E36E-150V GS8321E36E-133V GS8321E18E-250IV GS8321E18E-225IV GS8321E18E-200IV GS8321E18E-166IV GS8321E18E-150IV GS8321E18E-133IV GS8321E32E-250IV GS8321E32E-225IV GS8321E32E-200IV GS8321E32E-166IV
Type
Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst
Voltage Option
Package
Speed2 (MHz/ns)
250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8
GS8321E32E-150IV Synchronous Burst 150/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8321E18E-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.05a 12/2007
28/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
Ordering Information Synchronous Burst RAMs
Part Number1
GS8321E32E-133IV GS8321E36E-250IV GS8321E36E-225IV GS8321E36E-200IV GS8321E36E-166IV GS8321E36E-150IV GS8321E36E-133IV GS8321E18GE-250V GS8321E18GE-225V GS8321E18GE-200V GS8321E18GE-166V GS8321E18GE-150V GS8321E18GE-133V GS8321E32GE-250V GS8321E32GE-225V GS8321E32GE-200V GS8321E32GE-166V GS8321E32GE-150V GS8321E32GE-133V GS8321E36GE-250V GS8321E36GE-225V GS8321E36GE-200V GS8321E36GE-166V GS8321E36GE-150V GS8321E36GE-133V GS8321E18GE-250IV GS8321E18GE-225IV GS8321E18GE-200IV GS8321E18GE-166IV GS8321E18GE-150IV
Type
Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst
Voltage Option
Package
RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant
Speed2 (MHz/ns)
133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5
GS8321E18GE-133IV Synchronous Burst RoHS-compliant 133/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8321E18E-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.05a 12/2007
29/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
Ordering Information Synchronous Burst RAMs
Part Number1
GS8321E32GE-250IV GS8321E32GE-225IV GS8321E32GE-200IV GS8321E32GE-166IV GS8321E32GE-150IV GS8321E32GE-133IV GS8321E36GE-250IV GS8321E36GE-225IV GS8321E36GE-200IV GS8321E36GE-166IV GS8321E36GE-150IV
Type
Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst Synchronous Burst
Voltage Option
Package
RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant
Speed2 (MHz/ns)
250/6.5 225/7 200/7.5 166/8 150/8.5 133/8.5 250/6.5 225/7 200/7.5 166/8 150/8.5
GS8321E36GE-133IV Synchronous Burst RoHS-compliant 133/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8321E18E-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.05a 12/2007
30/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8321E18/32/36E-xxxV
36Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
8321EVxx_r1 8321EVxx_r1; 8321EVxx_r1_01 8321EVxx_r1_01; 8321EVxx_r1_02 8321EVxx_r1_02; 8321EVxx_r1_03 8321EVxx_r1_03; 8321EVxx_r1_04 8321EVxx_r1_04; 8321EVxx_r1_05 Content Content/Format Format Format Content
Types Changes Format Content
Page;Revisions;Reason
Creation datasheet Added parity designators pinouts Removed address numbers (except Corrected package thickness Updated format Added variation information package mechanical Pb-free information added Updated entire document reflect change part nomenclature Updated Truth Tables (pg. (Rev 1.05a: Removed Preliminary banner production status)
Rev: 1.05a 12/2007
31/31
2003, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.

user-configurable flow through pipeline operation Dual Cycle Deselect

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