119- 165-Bump Commercial Temp Industrial Temp Features Turn Aroun

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119- 165-Bump Commercial Temp Industrial Temp Features Turn Aroun

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GS8162Z18/36B(B/D)
119- 165-Bump Commercial Temp Industrial Temp Features
Turn Around) functionality allows zero wait Read-Write-Read utilization; fully pin-compatible with both pipelined flow through NtRAMTM, NoBLand ZBTSRAMs +10%/-10% core power supply supply User-configurable Pipeline Flow Through mode mode user-selectable high/low output drive IEEE 1149.1 JTAG-compatible Boundary Scan On-chip write parity checking; even selectable On-chip parity encoding error detection Linear Interleave Burst mode Pin-compatible with devices Byte write operation (9-bit Bytes) chip enable signals easy depth expansion automatic power-down JEDEC-standard 119-bump 165-bump packages RoHS-compliant 119-bump 165-bump packages available
18Mb Pipelined Flow Through Synchronous SRAM
MHz-150
Because synchronous device, address, data inputs, read/write control inputs captured rising edge input clock. Burst order control (LBO) must tied power rail proper operation. Asynchronous inputs include Sleep mode enable (ZZ) Output Enable. Output Enable used override synchronous control output drivers turn RAM's output drivers time. Write cycles internally self-timed initiated rising edge clock input. This feature eliminates complex offchip write pulse generation required asynchronous SRAMs simplifies input signal timing. GS8162Z18/36B(B/D) configured user operate Pipeline Flow Through mode. Operating pipelined synchronous device, addition rising-edgetriggered registers that capture input signals, device incorporates rising edge triggered output register. read cycles, pipelined SRAM output data temporarily stored edge-triggered output register during access cycle then released output drivers next rising edge clock. GS8162Z18/36B(B/D) implemented with GSI's high performance CMOS technology available JEDECstandard 119-bump 165-bump package.
Functional Description
GS8162Z18/36B(B/D) 18Mbit Synchronous Static SRAM. GSI's SRAMs, like ZBT, NtRAM, NoBL other pipelined read/double late write flow through read/ single late write SRAMs, allow utilization available bandwidth eliminating need insert deselect cycles when device switched from read write cycles.
Parameter Synopsis
-250
Pipeline 3-1-1-1 tCycle Curr (x18) Curr (x36) tCycle Curr (x18) Curr (x36)
-200
-150
Unit
Flow Through 2-1-1-1
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GS8162Z18/36B(B/D)
Bump BGA-x18 Commom I/O-Top View (Package
DQPB VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPA
Bump BGA-13 Body-1.0 Bump Pitch
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GS8162Z18/36B(B/D)
Bump BGA-x36 Common I/O-Top View (Package
DQPC DQPD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPB DQPA
Bump BGA-13 Body-1.0 Bump Pitch
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GS8162Z18/36B(B/D)
GS8162Z36B Out-119-Bump BGA-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ DQPC DQPD DQPB DQPA VDDQ VDDQ VDDQ VDDQ VDDQ
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GS8162Z18/36B(B/D)
GS8162Z18B Out-119-Bump BGA-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ DQPB DQPA VDDQ VDDQ VDDQ VDDQ VDDQ
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GS8162Z18/36B(B/D)
GS8162Z18/36 119-Bump 165-Bump Description Symbol
VDDQ
Type
Description
Address field LSBs Address Counter Preset Inputs Address Inputs Data Input Output pins Byte Write Enable DQA, DQB, DQC, I/Os; active Connect Clock Input Signal; active high Clock Enable; active Write Enable; active Chip Enable; active Chip Enable; active Chip Enable; active high Output Enable; active Burst address counter advance enable; active high Sleep mode control; active high Flow Through Pipeline mode; active Linear Burst Order mode; active FLXDrive Output Impedance Control (Low Impedance [High Drive], High High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data Scan Test Data Scan Test Clock Core power supply Core Ground Output driver power supply Must Connect High (165 only)
BPR1999.05.18
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GS8162Z18/36B(B/D)
Functional Details
Clocking Deassertion Clock Enable (CKE) input blocks Clock input from reaching RAM's internal circuits. used suspend operations. Failure observe Clock Enable set-up hold requirements will result erratic operation. Pipeline Mode Read Write Operations inputs (with exception Output Enable, Linear Burst Order Sleep) synchronized rising clock edges. Single cycle read write operations must initiated with Advance/Load (ADV) held low, order load address. Device activation accomplished asserting three Chip Enable inputs (E1, E3). Deassertion Enable inputs will deactivate device. Function Read Write Byte Write Byte Write Byte Write Byte Write Bytes Write Abort/NOP
Read operation initiated when following conditions satisfied rising edge clock: asserted low, three chip enables (E1, active, write enable input signals deasserted high, asserted low. address presented address inputs latched into address register presented memory core control logic. control logic determines that read access progress allows requested data propagate input output register. next rising edge clock read data allowed propagate through output register onto output pins. Write operation occurs when selected, asserted low, Write input sampled rising edge clock. Byte Write Enable inputs (BA, determine which bytes will written. none activated. write cycle with Byte Write inputs active no-op cycle. pipelined SRAM provides double late write functionality, matching write command versus data pipeline length cycles) read command versus data pipeline length cycles). first rising edge clock, Enable, Write, Byte Write(s), Address registered. Data associated with that address required third rising edge clock. Flow Through Mode Read Write Operations Operation Flow Through mode very similar operations Pipeline mode. Activation Read Cycle Burst Address Counter identical. Flow Through mode device begin driving data immediately after address clocked into RAM, rather than holding data until following (second) clock edge. Therefore, Flow Through mode read pipeline cycle shorter than Pipeline mode. Write operations initiated same way, differ that write pipeline cycle shorter well, preserving ability turn from reads writes without inserting dead cycles. While pipelined RAMs implement double late write protocol Flow Through mode single late write protocol mode observed. Therefore, Flow Through mode, address control registered first rising edge clock data required data input pins second rising edge clock.
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GS8162Z18/36B(B/D)
Synchronous Truth Table Operation
Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall
Type Address
External Next External Next External Next Next None None None None None None Current
High-Z High-Z
Notes
1,10 1,2,10 1,3,10
High-Z 1,2,3,10 High-Z High-Z High-Z High-Z High-Z High-Z
Notes: Continue Burst cycles, whether read write, same control inputs. Deselect continue cycle only entered into Deselect cycle executed first. Dummy Read Write abort considered NOPs because SRAM performs operation. Write abort occurs when sampled Byte Write pins active write operation performed. wired minimize number control signals provided SRAM. Output drivers will automatically turn during write cycles. High occurs during pipelined read cycle, will remain active (Low High occurs during write cycle, will remain High Don't Care; Logic High; Logic Low; High Byte Write signals high; more Byte/Write signals inputs, except must meet setup hold times rising clock edge. Wait states inserted setting high. This device contains circuitry that ensures outputs High during power-up. 2-bit burst counter incorporated. address counter incriminated Burst continue cycles.
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GS8162Z18/36B(B/D)
Pipelined Flow Through Read Write Control State Diagram
Deselect
Read
Write
Burst Read
Burst Write
Input Command Code
Notes
Hold command (CKE Low) shown because prevents state change.
Transition
Current State Next State (n+1)
represent input command codes indicated Synchronous Truth Table.
Clock (CK)
Command
Current State
Next State
Current State Next State Definition Pipelined Flow through Read/Write Control State Diagram
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GS8162Z18/36B(B/D)
Pipeline Mode Data State Diagram
Intermediate
High (Data
Intermediate Intermediate Intermediate
Data Valid)
Intermediate
High
Intermediate
Input Command Code
Notes
Hold command (CKE Low) shown because prevents state change.
Transition
Current State
Transition Next State (n+2)
Intermediate State (N+1)
represent input command codes indicated Truth Tables.
Clock (CK)
Command
Current State
Intermediate State
Next State
Current State Next State Definition Pipeline Mode Data State Diagram
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GS8162Z18/36B(B/D)
Flow Through Mode Data State Diagram
High (Data
Data Valid)
High
Input Command Code
Notes
Hold command (CKE Low) shown because prevents state change.
Transition
Current State Next State (n+1)
represent input command codes indicated Truth Tables.
Clock (CK)
Command
Current State
Next State
Current State Next State Definition for: Pipeline Flow Through Read Write Control State Diagram
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GS8162Z18/36B(B/D)
Burst Cycles Although RAMs designed sustain 100% bandwidth eliminating turnaround cycle when there transition from read write, multiple back-to-back reads writes also performed. SRAMs provide on-chip burst address generator that utilized, desired, further simplify burst read write implementations. control pin, when driven high, commands SRAM advance internal address counter counter generated address read write SRAM. starting address first cycle burst cycle series loaded into SRAM driving low, into Load mode. Burst Order burst address counter wraps around initial state after four addresses (the loaded address three more) have been accessed. burst sequence determined state Linear Burst Order (LBO). When this Low, linear burst sequence selected. When installed with tied high, Interleaved burst sequence selected. tables below details. FLXDriveThe allows selection between nominal drive strength low) multi-drop applications drive strength floating high) point-to-point applications. Output Driver Characteristics chart details.
Mode Functions Mode Name
Burst Order Control Output Register Control Power Down Control FLXDrive Output Impedance Control
Name
State
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, High Drive (Low Impedance) Drive (High Impedance)
Note: There pull-up devices pins pull-down device pin, those input pins unconnected chip will operate default states specified above tables.
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GS8162Z18/36B(B/D)
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Note: burst counter wraps initial state clock.
Note: burst counter wraps initial state clock.
1999.05.18
Sleep Mode During normal operation, must pulled low, either user internal pull down resistor. When pulled high, SRAM will enter Power Sleep mode after cycles. this time, internal state SRAM preserved. When returns low, SRAM operates normally after recovery time. Sleep mode current, power-down mode which device deselected current reduced ISB2. duration Sleep mode dictated length time High state. After entering Sleep mode, inputs except become disabled outputs High-Z asynchronous, active high input that causes device enter Sleep mode. When driven high, ISB2 guaranteed after time tZZI met. Because asynchronous input, pending operations operations progress properly completed asserted. Therefore, Sleep mode must initiated until valid pending operations completed. Similarly, when exiting Sleep mode during tZZR, only Deselect Read commands applied while SRAM recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR tZZS tZZH
Designing Compatibility SRAMs offer users configurable selection between Flow Through mode Pipeline mode signal found Bump vendors offer this option, however most mark Bump VDDQ pipelined parts flow through parts. SRAMs fully compatible with these sockets.
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GS8162Z18/36B(B/D)
Absolute Maximum Ratings
(All voltages reference VSS)
Symbol
VDDQ VI/O IOUT TSTG TBIAS
Description
Voltage Pins Voltage VDDQ Pins Voltage Pins Voltage Other Input Pins Input Current Output Current Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 -0.5 -0.5 VDDQ +0.5 max.) -0.5 +0.5 max.) +/-20 +/-20
Unit
Note: Permanent damage device occur Absolute Maximum Ratings exceeded. Operation should restricted Recommended Operating Conditions. Exposure conditions exceeding Absolute Maximum Ratings, extended period time, affect reliability this component.
Power Supply Voltage Ranges Parameter
Supply Voltage Supply Voltage VDDQ Supply Voltage VDDQ Supply Voltage
Symbol
VDD3 VDD2 VDDQ3 VDDQ2
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
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GS8162Z18/36B(B/D)
VDDQ3 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
-0.3 -0.3
Typ.
Max.
VDDQ
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
VDDQ2 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
Max.
0.3*VDD VDDQ 0.3*VDD
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
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GS8162Z18/36B(B/D)
Undershoot Measurement Timing
Overshoot Measurement Timing
Capacitance
25oC, MHZ,
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters sample tested.
Symbol
CI/O
Test conditions
VOUT
Typ.
Max.
Unit
Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level Output load
Conditions
V/ns VDD/2 VDDQ/2 Fig.
Notes: Include scope capacitance. Test conditions specified with output loading shown Fig. unless otherwise noted. Device deselected defined Truth Table.
Output Load VDDQ/2
Distributed Test Capacitance
30pF*
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GS8162Z18/36B(B/D)
Electrical Characteristics Parameter
Input Leakage Current (except mode pins) Input Current Input Current Output Leakage Current Output High Voltage Output High Voltage Output Voltage
Symbol
IIN1 IIN2 VOH2 VOH3
Test Conditions
Output Disable, VOUT VDDQ 2.375 VDDQ 3.135
-100
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GS8162Z18/36B(B/D)
Operating Currents
-250 Parameter Test Conditions Mode Symbol 70°C
-200 85°C
-150 85°C
70°C
70°C
85°C
Unit
Pipeline (x36) Operating Current Device Selected; other inputs Output open (x18) Flow Through Standby Current Deselect Current Device Deselected; other inputs Pipeline Flow Through Pipeline Flow Through Flow Through Pipeline
IDDQ IDDQ IDDQ IDDQ
Notes: IDDQ apply combination VDD3, VDD2, VDDQ3, VDDQ2 operation. parameters listed worst case scenario.
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GS8162Z18/36B(B/D)
Electrical Characteristics
Parameter
Clock Cycle Time Clock Output Valid Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock Cycle Time Clock Output Valid Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock HIGH Time Clock Time Clock Output High-Z Output Valid output Low-Z output High-Z setup time hold time recovery
Symbol
tKQX tLZ1 tKQX tHZ1 tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR
-250
-200
-150
Unit
Pipeline
Flow Through
Notes: These parameters sampled 100% tested. asynchronous signal. However, order recognized given clock cycle, must meet specified setup hold times specified above.
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GS8162Z18/36B(B/D)
Pipeline Mode Timing (NBT)
Write Read Suspend Read Write writeno-op Read Deselect
Q(B) Q(C) D(D) Q(E) tKQX
D(A)
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GS8162Z18/36B(B/D)
Flow Through Mode Timing (NBT)
Write Write Write
Read
Cont
Read
Write
Read
Write
A0-An
D(A) D(B)
D(B+1) Q(C)
tKQX
Q(D)
D(E) Q(F)
tKQX
D(G)
tOLZ tOHZ
*Note: High(False)
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GS8162Z18/36B(B/D)
JTAG Port Operation
Overview JTAG Port this operates manner that compliant with IEEE Standard 1149.1-1990, serial boundary scan interface standard (commonly referred JTAG). JTAG Port input interface levels scale with VDD. JTAG output drivers powered VDDQ. Disabling JTAG Port possible this device without utilizing JTAG port. port reset power-up will remain inactive unless clocked. TCK, TDI, designed with internal pull-up circuits.To assure normal operation with JTAG Port unused, TCK, TDI, left floating tied either VSS. should left unconnected.
JTAG Port Registers JTAG Descriptions
Name
Test Clock Test Mode Select
Description
Clocks events. inputs captured rising edge outputs propagate from falling edge TCK. input sampled rising edge TCK. This command input controller state machine. undriven input will produce same result logic input level. input sampled rising edge TCK. This input side serial registers placed between TDO. register placed between determined state Controller state machine instruction that currently loaded Instruction Register (refer Controller State Diagram). undriven will produce same result logic input level.
Test Data
Test Data
Output that active depending state state machine. Output changes response falling edge TCK. This output side serial registers placed between TDO.
Note: This device does have TRST (TAP Reset) pin. TRST optional IEEE 1149.1. Test-Logic-Reset state entered while held high five rising edges TCK. Controller also reset automaticly power-up. Overview various JTAG registers, refered Test Access Port orTAP Registers, selected (one time) sequences applied strobed. Each Registers serial shift register that captures serial input data rising edge pushes serial data next falling edge TCK. When register selected, placed between pins. Instruction Register Instruction Register holds instructions that executed controller when moved into Run, Test/Idle, various data register states. Instructions bits long. Instruction Register loaded when placed between pins. Instruction Register automatically preloaded with IDCODE instruction power-up whenever controller placed Test-Logic-Reset state. Bypass Register Bypass Register single register that placed between TDO. allows serial test data passed through RAM's JTAG Port another device scan chain with little delay possible. Boundary Scan Register Boundary Scan Register collection flip flops that preset logic level found RAM's input pins. flip flops then daisy chained together levels found shifted serially JTAG Port's pin. Boundary Scan Register also includes number place holder flip flops (always logic relationship between Rev: 1.05 7/2007 22/34 2004, Technology
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GS8162Z18/36B(B/D)
device pins bits Boundary Scan Register described Scan Order Table following. Boundary Scan Register, under control Controller, loaded with contents RAMs ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD EXTEST instructions used activate Boundary Scan Register.
JTAG Block Diagram
Boundary Scan Register
Bypass Register
Instruction Register Code Register
Control Signals Test Access Port (TAP) Controller
Identification (ID) Register Register 32-bit register that loaded with device vendor specific 32-bit code when controller Capture-DR state with IDCODE command loaded Instruction Register. code loaded from 32-bit on-chip ROM. describes various attributes indicated below. register then placed between pins when controller moved into Shift-DR state. register first reach when shifting begins.
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GS8162Z18/36B(B/D)
Controller Instruction Register Contents
Revision Code Technology JEDEC Vendor Code Presence Register
Used
Configuration
Overview There classes instructions defined Standard 1149.1-1990; standard (Public) instructions, device specific (Private) instructions. Some Public instructions mandatory 1149.1 compliance. Optional Public instructions must implemented prescribed ways. this device used monitor input pads, used load address, data control signals into preload buffers. When controller placed Capture-IR state least significant bits instruction register loaded with When controller moved Shift-IR state Instruction Register placed between TDO. this state desired instruction serially loaded through input (while previous contents shifted TDO). instructions, executes newly loaded instructions only when controller moved Update-IR state. instruction this device listed following table.
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GS8162Z18/36B(B/D)
JTAG Controller State Diagram
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Exit2
Update
Update
Instruction Descriptions BYPASS When BYPASS instruction loaded Instruction Register Bypass Register placed between TDO. This occurs when controller moved Shift-DR state. This allows board level scan path shortened facilitate testing other devices scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD Standard 1149.1 mandatory public instruction. When SAMPLE PRELOAD instruction loaded Instruction Register, moving controller into Capture-DR state loads data RAMs input buffers into Boundary Scan Register. Boundary Scan Register locations associated with input pin, loaded with default state identified Boundary Scan Chain table this section datasheet. Because clock independent from Clock (TCK) possible attempt capture ring contents while input buffers transition (i.e. metastable state). Although allowing sample metastable inputs will harm device, repeatable results cannot expected. input signals must stabilized long enough meet TAPs input data capture set-up plus hold time (tTS plus tTH). RAMs clock inputs need paused other operation except capturing ring contents into Boundary Scan Register. Moving controller Shift-DR state then places boundary scan register between pins. EXTEST EXTEST IEEE 1149.1 mandatory public instruction. executed whenever instruction register loaded with logic EXTEST command does block override RAM's input pins; therefore, RAM's internal state still determined input pins.
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GS8162Z18/36B(B/D)
Typically, Boundary Scan Register loaded with desired pattern data with SAMPLE/PRELOAD command. Then EXTEST command used output Boundary Scan Register's contents, parallel, RAM's data output drivers falling edge when controller Update-IR state. Alternately, Boundary Scan Register loaded parallel using EXTEST command. When EXTEST instruction selected, sate RAM's input pins, well default values Scan Register locations associated with pin, transferred parallel into Boundary Scan Register rising edge Capture-DR state, RAM's output pins drive value Boundary Scan Register location with which each output associated. IDCODE IDCODE instruction causes loaded into register when controller Capture-DR mode places register between pins Shift-DR mode. IDCODE instruction default instruction loaded power time controller placed Test-Logic-Reset state. SAMPLE-Z SAMPLE-Z instruction loaded instruction register, outputs forced inactive drive state (highZ) Boundary Scan Register connected between when controller moved Shift-DR state. These instructions Reserved Future Use. this device they replicate BYPASS instruction.
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GS8162Z18/36B(B/D)
JTAG Port Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level
Conditions
V/ns VDDQ/2 VDDQ/2
JTAG Port Test Load
VDDQ/2
Distributed Test Capacitance
30pF*
Notes: Include scope capacitance. Test conditions shown unless otherwise noted.
JTAG Instruction Summary Instruction
EXTEST IDCODE SAMPLE-Z SAMPLE/ PRELOAD
Code
Description
Places Boundary Scan Register between TDO. Preloads Register places between TDO. Captures ring contents. Places Boundary Scan Register between TDO. Forces output drivers High-Z. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO. Captures ring contents. Places Boundary Scan Register between TDO. private instruction. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO.
Notes
BYPASS Places Bypass Register between TDO. Notes: Instruction codes expressed binary, left, right. Default instruction automatically loaded power-up test-logic-reset state.
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GS8162Z18/36B(B/D)
JTAG Port Recommended Operating Conditions Characteristics Parameter
Test Port Input High Voltage Test Port Input Voltage Test Port Input High Voltage Test Port Input Voltage TMS, Input Leakage Current TMS, Input Leakage Current Output Leakage Current Test Port Output High Voltage Test Port Output Voltage Test Port Output CMOS High Test Port Output CMOS
Symbol
VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
-0.3 VDD2 -0.3 -300 VDDQ
Max.
VDD3 +0.3 VDD2 +0.3 VDD2
Unit Notes
Notes: Input Under/overshoot voltage must VDDn +1.5 maximum, with pulse width exceed tTKC. VILJ VDDn VILJn Output Disable, VOUT VDDn output driver served VDDQ supply. IOHJ IOLJ IOHJC -100 IOHJC +100
JTAG Port Timing Diagram
tTKC tTKQ Parallel SRAM input tTKH tTKL
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GS8162Z18/36B(B/D)
JTAG Port Electrical Characteristics
Parameter Cycle Time Valid High Pulse Width Pulse Width Time Hold Time Symbol tTKC tTKQ tTKH tTKL Unit
Boundary Scan (BSDL Files) information regarding Boundary Scan Chain, obtain BSDL files this part, please contact Applications Engineering Department apps@gsitechnology.com.
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GS8162Z18/36B(B/D)
Package Dimensions-165-Bump FPBGA (Package
CORNER
VIEW
BOTTOM VIEW (165x)
CORNER
10.0 0.20(4x) 13±0.05
15±0.05
14.0
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0.36~0.46 1.40 MAX.
SEATING PLANE
0.20
30/34
2004, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8162Z18/36B(B/D)
Package Dimensions-119-Bump FPBGA (Package Variation
VIEW
BOTTOM VIEW (119x)
22±0.10
1.27 7.62 0.15 0.20(4x) 14±0.10
Rev: 1.05 7/2007
0.50~0.70 1.86.±0.13
SEATING PLANE
31/34
20.32
1.27
2004, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8162Z18/36B(B/D)
Ordering Information Synchronous Burst RAMs
512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K
Part Number1
GS8162Z18BB-250 GS8162Z18BB-200 GS8162Z18BB-150 GS8162Z36BB-250 GS8162Z36BB-200 GS8162Z36BB-150 GS8162Z18BB-250I GS8162Z18BB-200I GS8162Z18BB-150I GS8162Z36BB-250I GS8162Z36BB-200I GS8162Z36BB-150I GS8162Z18BGB-250 GS8162Z18BGB-200 GS8162Z18BGB-150 GS8162Z36BGB-250 GS8162Z36BGB-200 GS8162Z36BGB-150 GS8162Z18BGB-250I GS8162Z18BGB-200I GS8162Z18BGB-150I GS8162Z36BGB-250I GS8162Z36BGB-200I GS8162Z36BGB-150I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
(Var. (Var. (Var. (Var. (Var. (Var. (Var. (Var. (Var. (Var. (Var. (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var. RoHS-compliant (Var.
Speed2 (MHz/ns)
250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5
Status
Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8162Z36BB-200IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. Mass Production. Pre-Qualification. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings
Rev: 1.05 7/2007
32/34
2004, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8162Z18/36B(B/D)
Ordering Information Synchronous Burst RAMs (Cont.)
512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K
Part Number1
GS8162Z18BD-250 GS8162Z18BD-200 GS8162Z18BD-150 GS8162Z36BD-250 GS8162Z36BD-200 GS8162Z36BD-150 GS8162Z18BD-250I GS8162Z18BD-200I GS8162Z18BD-150I GS8162Z36BD-250I GS8162Z36BD-200I GS8162Z36BD-150I GS8162Z18BGD-250 GS8162Z18BGD-200 GS8162Z18BGD-150 GS8162Z36BGD-250 GS8162Z36BGD-200 GS8162Z36BGD-150 GS8162Z18BGD-250I GS8162Z18BGD-200I GS8162Z18BGD-150I GS8162Z36BGD-250I GS8162Z36BGD-200I GS8162Z36BGD-150I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant RoHS-compliant
Speed2 (MHz/ns)
250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5
Status
Notes: Customers requiring delivery Tape Reel should character part number. Example: GS8162Z36BB-200IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. Mass Production. Pre-Qualification. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings
Rev: 1.05 7/2007
33/34
2004, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS8162Z18/36B(B/D)
18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
GSxxB_r1 GSxxB_r1; GS8162ZxxB_r1_01 GSxxB_r1_01; GS8162ZxxB_r1_02 GSxxB_r1_02; GS8162ZxxB_r1_03 GSxxB_r1_03; GS8162ZxxB_r1_04 GS8162ZxxB_r1_05 Content Content Content
Types Changes Page;Revisions;Reason Format Content
Creation datasheet Updated overshoot/undershoot information Added information Added Pb-free information Added speed Corrected extra pins pinout (changed DQD) Removed speed Changed Pb-Free RoHS-compliant Added Status column Ordering Information table (rev. 1.04a) Added missing section Added (Must Connect High) description
Content Content
Rev: 1.05 7/2007
34/34
2004, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.

119- 165-Bump Commercial Temp Industrial Temp Features Turn Aroun

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