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8-bit Microcontroller with 2K Bytes Flash ATtiny26 ATtiny26L Summary

1477J­AVR­06 / 07

Features
· High-performance, Low-power AVR® 8-bit Microcontroller · RISC Architecture
8-bit Microcontroller with 2K Bytes Flash ATtiny26 ATtiny26L Summary
Not recommended for new design
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Pin Configuration
PDIP / SOIC
(MOSI / DI / SDA / OC1A) PB0 (MISO / DO / OC1A) PB1 (SCK / SCL / OC1B) PB2 (OC1B) PB3 VCC GND (ADC7 / XTAL1) PB4 (ADC8 / XTAL2) PB5 (ADC9 / INT0 / T0) PB6 (ADC10 / RESET) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC PA4 (ADC3) PA5 (ADC4) PA6 (ADC5 / AIN0) PA7 (ADC6 / AIN1)
MLF Top View
PB2 (SCK / SCL / OC1B) PB1 (MISO / DO / OC1A) PB0 (MOSI / DI / SDA / OC1A) NC NC NC PA0 (ADC0) PA1 (ADC1) 32 31 30 29 28 27 26 25
NC (OC1B) PB3 NC VCC GND NC (ADC7 / XTAL1) PB4 (ADC8 / XTAL2) PB5
NC PA2 (ADC2) PA3 (AREF) GND NC NC AVCC PA4 (ADC3)
Note:
The bottom pad under the QFN / MLF package should be soldered to ground.
ATtiny26(L)
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NC (ADC9 / INT0 / T0) PB6 (ADC10 / RESET) PB7 NC (ADC6 / AIN1) PA7 (ADC5 / AIN0) PA6 (ADC4) PA5 NC
ATtiny26(L)
Description
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Block Diagram
Figure 1. The ATtiny26(L) Block Diagram
VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND
PROGRAM COUNTER STACK POINTER
INTERNAL CALIBRATED OSCILLATOR
WATCHDOG TIMER MCU CONTROL REGISTER
TIMING AND CONTROL
PROGRAM FLASH
INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS
MCU STATUS REGISTER TIMER / COUNTER0 TIMER / COUNTER1
INSTRUCTION DECODER
CONTROL LINES
UNIVERSAL SERIAL INTERFACE
STATUS REGISTER
INTERRUPT UNIT
PROGRAMMING LOGIC
ISP INTERFACE
EEPROM
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORT A
DATA DIR. REG.PORT A
DATA REGISTER PORT B
DATA DIR. REG.PORT B
PORT A DRIVERS
PORT B DRIVERS
PA0-PA7
PB0-PB7
ATtiny26(L)
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ATtiny26(L)
Pin Descriptions
VCC GND AVCC Digital supply voltage pin. Digital ground pin. AVCC is the supply voltage pin for Port A and the A / D Converter (ADC). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. See page 96 for details on operating of the ADC. Port A is an 8-bit general purpose I / O port. PA7.PA0 are all I / O pins that can provide internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs for the ADC and analog comparator and pin change interrupt as described in "Alternate Port Functions" on page 48. Port B is an 8-bit general purpose I / O port. PB6.0 are all I / O pins that can provide internal pull-ups (selected for each bit). PB7 is an I / O pin if not used as the reset. To use pin PB7 as an I / O pin, instead of RESET pin, program ("0") RSTDISBL Fuse. Port B has alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and pin change interrupt as described in "Alternate Port Functions" on page 48. An External Reset is generated by a low level on the PB7 / RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 XTAL2 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier.
Port A (PA7.PA0)
Port B (PB7.PB0)
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Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com / avr.
ATtiny26(L)
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ATtiny26(L)
About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
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Register Summary
Address
SREG Reserved SP Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 OSCCAL TCCR1A TCCR1B TCNT1 OCR1A OCR1B OCR1C Reserved PLLCSR Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB Reserved Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved Reserved Reserved Reserved ACSR ADMUX ADCSR ADCH ADCL Reserved Reserved
T SP6 INT0 INTF0 OCIE1A OCF1A
H SP5 PCIE1 PCIF OCIE1B OCF1B
S SP4 PCIE0 -
N SP2 TOIE1 TOV1
Z SP1 TOIE0 TOV0
SM0 WDRF PSR0
BORF CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
Timer / Counter0 (8-Bit) Oscillator Calibration Register COM1A1 CTC1 COM1A0 PSR1 COM1B1 COM1B0 FOC1A CS13 FOC1B CS12 PWM1A CS11 PWM1B CS10
Timer / Counter1 (8-Bit) Timer / Counter1 Output Compare Register A (8-Bit) Timer / Counter1 Output Compare Register B (8-Bit) Timer / Counter1 Output Compare Register C (8-Bit) PCKE PLLE PLOCK
PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7
EEAR6 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6
EEAR5 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5
EEAR4 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4
EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3
EEAR2 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2
EEAR1 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1
EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0
EEPROM Data Register (8-Bit)
Universal Serial Interface Data Register (8-Bit) USISIF USISIE USIOIF USIOIE USIPF USIWM1 USIDC USIWM0 USICNT3 USICS1 USICNT2 USICS0 USICNT1 USICLK USICNT0 USITC
ACD REFS1 ADEN
ACBG REFS0 ADSC
ACO ADLAR ADFR
ACI MUX4 ADIF
ACIE MUX3 ADIE
ACME MUX2 ADPS2
ACIS1 MUX1 ADPS1
ACIS0 MUX0 ADPS0
ADC Data Register High Byte ADC Data Register Low Byte
ATtiny26(L)
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ATtiny26(L)
Instruction Set Summary
Mnemonic
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID MOV LDI LD LD LD Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, K Rd, X Rd, X+ Rd, -X k
Operands
Rd, Rr Rd, Rr Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k
Description
Operation
Flags
Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, C, N, V Z, C, N, V, H Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V None None None None None None I None Z, N, V, C, H Z, N, V, C, H Z, N, V, C, H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
# Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
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Instruction Set Summary (Continued)
Mnemonic
LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, Z Rd, P P, Rr Rr Rd P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Operands
Rd, Y Rd, Y+ Rd, -Y Rd, Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr
Description
Operation
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z, C, N, V Z, C, N, V Z, C, N, V Z, C, N, V Z, C, N, V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None
# Clocks
BIT AND BIT-TEST INSTRUCTIONS
ATtiny26(L)
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ATtiny26(L)
Ordering Information
Speed (MHz) Power Supply Ordering Code ATtiny26L-8PC ATtiny26L-8SC ATtiny26L-8MC 8 2.7 - 5.5V ATtiny26L-8PI ATtiny26L-8SI ATtiny26L-8MI ATtiny26L-8PU(2) ATtiny26L-8SU(2) ATtiny26L-8MU(2) ATtiny26-16PC ATtiny26-16SC ATtiny26-16MC 16 4.5 - 5.5V ATtiny26-16PI ATtiny26-16SI ATtiny26-16MI ATtiny26-16PU(2) ATtiny26-16SU(2) ATtiny26-16MU(2)
Package(1)
Operational Range Commercial (0°C to 70°C)
20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A 20P3 20S 32M1-A
Industrial (-40°C to 85°C)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 20P3 20S 32M1-A 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead / Micro Lead Frame Package (QFN / MLF)
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Packaging Information
SEATING PLANE
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
2.540 TYP
1 / 12 / 04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300" / 7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C
ATtiny26(L)
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ATtiny26(L)
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32M1-A
SIDE VIEW
TOP VIEW
0.08 C
SYMBOL A
Pin #1 Notch (0.20 R)
BOTTOM VIEW
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K
5 / 25 / 06 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. E
ATtiny26(L)
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ATtiny26(L)
Errata
ATtiny26 Rev. B / C / D
The revision letter refers to the revision of the device. · First Analog Comparator conversion may be delayed 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix / Workaround When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion.
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Datasheet Revision History
Rev. 1477J-06 / 07 Rev. 1477I-10 / 06 Rev. 1477H-04 / 06
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 1. "Not recommended for new design" 1. Updated "Errata" on page 15 1. Updated typos. 2. Added "Resources" on page 6. 3. Updated features in "System Control and Reset" on page 33. 4. Updated "Prescaling and Conversion Timing" on page 98. 5. Updated algorithm for "Enter Programming Mode" on page 114.
Rev. 1477G-03 / 05
1. MLF-package alternative changed to "Quad Flat No-Lead / Micro Lead Frame Package QFN / MLF". 2. Updated "Electrical Characteristics" on page 128 3. Updated "Ordering Information" on page 11
Rev. 1477F-12 / 04
1. Updated Table 16 on page 34, Table 9 on page 29, and Table 29 on page 59. 2. Added Table 20 on page 41. 3. Added "Changing Channel or Reference Selection" on page 100. 4. Updated "Offset Compensation Schemes" on page 107. 5. Updated "Electrical Characteristics" on page 128. 6. Updated package information for "20P3" on page 12. 7. Rearranged some sections in the datasheet.
Rev. 1477E-10 / 03
1. Removed Preliminary references. 2. Updated "Features" on page 1. 3. Removed SSOP package reference from "Pin Configuration" on page 2. 4. Updated VRST and tRST in Table 16 on page 34. 5. Updated "Calibrated Internal RC Oscillator" on page 30. 6. Updated DC Characteristics for VOL, IIL, IIH, ICC Power Down and VACIO in "Electrical Characteristics" on page 128.
ATtiny26(L)
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ATtiny26(L)
7. Updated VINT, INL and Gain Error in "ADC Characteristics" on page 131 and page 132. Fixed typo in "Absolute Accuracy" on page 132. 8. Added Figure 106 in "Pin Driver Strength" on page 148, Figure 120, Figure 121 and Figure 122 in "BOD Thresholds and Analog Comparator Offset" on page 157. Updated Figure 117 and Figure 118. 9. Removed LPM Rd, Z+ from "Instruction Set Summary" on page 9. This instruction is not supported in ATtiny26.
Rev. 1477D-05 / 03
Rev. 1477C-09 / 02 Rev. 1477B-04 / 02
1. Changed the Endurance on the Flash to 10, 000 Write / Erase Cycles. 1. Removed all references to Power Save sleep mode in the section "System Clock and Clock Options" on page 24. 2. Updated the section "Analog to Digital Converter" on page 96 with more details on how to read the conversion result for both differential and singleended conversion. 3. Updated "Ordering Information" on page 11 and added QFN / MLF package information.
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Rev. 1477A-03 / 02
1. Initial version.
ATtiny26(L)
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