8-bit Microcontroller with Bytes Flash ATtiny26 ATtiny26L Summary

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8-bit Microcontroller with Bytes Flash ATtiny26 ATtiny26L Summary

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8-bit Microcontroller with Bytes Flash ATtiny26 ATtiny26L Summary
recommended design
1477J-AVR-06/07
Configuration
PDIP/SOIC
(MOSI/DI/SDA/OC1A) (MISO/DO/OC1A) (SCK/SCL/OC1B) (OC1B) (ADC7/XTAL1) (ADC8/XTAL2) (ADC9/INT0/T0) (ADC10/RESET) (ADC0) (ADC1) (ADC2) (AREF) AVCC (ADC3) (ADC4) (ADC5/AIN0) (ADC6/AIN1)
View
(SCK/SCL/OC1B) (MISO/DO/OC1A) (MOSI/DI/SDA/OC1A) (ADC0) (ADC1)
(OC1B) (ADC7/XTAL1) (ADC8/XTAL2)
(ADC2) (AREF) AVCC (ADC3)
Note:
bottom under QFN/MLF package should soldered ground.
ATtiny26(L)
1477J-AVR-06/07
(ADC9/INT0/T0) (ADC10/RESET) (ADC6/AIN1) (ADC5/AIN0) (ADC4)
ATtiny26(L)
Description
ATtiny26(L) low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATtiny26(L) achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed. core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATtiny26(L) high precision with single ended channels differential channels. Seven differential channels have optional gain 20x. Four seven differential channels, which have optional gain, used same time. ATtiny26(L) also high frequency 8-bit module with independent outputs. outputs have inverted non-overlapping output pins ideal synchronous rectification. Universal Serial Interface ATtiny26(L) allows efficient software implementation (Two-wire Serial Interface) SM-bus interface. These features allow highly integrated battery charger lighting ballast applications, low-end thermostats, firedetectors, among other applications. ATtiny26(L) provides bytes Flash, bytes EEPROM, bytes SRAM, general purpose lines, general purpose working registers, 8-bit Timer/Counters, with outputs, internal external Oscillators, internal external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog Digital Converter with differential voltage input gain stages, four software selectable power saving modes. Idle mode stops while allowing Timer/Counters interrupt system continue functioning. ATtiny26(L) also dedicated Noise Reduction mode reducing noise conversion. this sleep mode, only functioning. Power-down mode saves register contents freezes oscillators, disabling other chip functions until next interrupt hardware reset. Standby mode same Power-down mode, external oscillators enabled. wakeup interrupt change features enable ATtiny26(L) highly responsive external events, still featuring lowest power consumption while Power-down mode. device manufactured using Atmel's high density non-volatile memory technology. combining enhanced RISC 8-bit with Flash monolithic chip, ATtiny26(L) powerful microcontroller that provides highly flexible cost effective solution many embedded control applications. ATtiny26(L) supported with full suite program system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, evaluation kits.
1477J-AVR-06/07
Block Diagram
Figure ATtiny26(L) Block Diagram
8-BIT DATA INTERNAL OSCILLATOR
PROGRAM COUNTER STACK POINTER
INTERNAL CALIBRATED OSCILLATOR
WATCHDOG TIMER CONTROL REGISTER
TIMING CONTROL
PROGRAM FLASH
SRAM
AVCC
INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS
STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1
INSTRUCTION DECODER
CONTROL LINES
UNIVERSAL SERIAL INTERFACE
STATUS REGISTER
INTERRUPT UNIT
PROGRAMMING LOGIC
INTERFACE
EEPROM
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORT
DATA DIR. REG.PORT
DATA REGISTER PORT
DATA DIR. REG.PORT
PORT DRIVERS
PORT DRIVERS
PA0-PA7
PB0-PB7
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Descriptions
AVCC Digital supply voltage pin. Digital ground pin. AVCC supply voltage Port Converter (ADC). should externally connected VCC, even used. used, should connected through low-pass filter. page details operating ADC. Port 8-bit general purpose port. PA7.PA0 pins that provide internal pull-ups (selected each bit). Port alternate functions analog inputs analog comparator change interrupt described "Alternate Port Functions" page Port 8-bit general purpose port. PB6.0 pins that provide internal pull-ups (selected each bit). used reset. pin, instead RESET pin, program ("0") RSTDISBL Fuse. Port alternate functions ADC, clocking, timer counters, USI, programming, change interrupt described "Alternate Port Functions" page External Reset generated level PB7/RESET pin. Reset pulses longer than will generate reset, even clock running. Shorter pulses guaranteed generate reset. XTAL1 XTAL2 Input inverting oscillator amplifier input internal clock operating circuit. Output from inverting oscillator amplifier.
Port (PA7.PA0)
Port (PB7.PB0)
1477J-AVR-06/07
Resources
comprehensive development tools, application notes datasheets available download http://www.atmel.com/avr.
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
About Code Examples
This datasheet contains simple code examples that briefly show various parts device. These code examples assume that part specific header file included before compilation. aware that compiler vendors include definitions header files interrupt handling compiler dependent. Please confirm with compiler documentation more details.
1477J-AVR-06/07
Register Summary
Address
($5F) ($5E) ($5D) ($5C) ($5B) ($5A) ($59) ($58) ($57) ($56) ($55) ($54) ($53) ($52) ($51) ($50) ($4F) ($4E) ($4D) ($4C) ($4B) ($4A) ($49) ($48) ($47) ($46) ($45) ($44) ($43) ($42) ($41) ($40) ($3F) ($3E) ($3D) ($3C) ($3B) ($3A) ($39) ($38) ($37) ($36) ($35) ($34) ($33) ($32) ($31) ($30) ($2F) ($2E) ($2D) ($2C) ($2)B ($2A) ($29) ($28) ($27) ($26) ($25) ($24) ($20)
Name
SREG Reserved Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 OSCCAL TCCR1A TCCR1B TCNT1 OCR1A OCR1B OCR1C Reserved PLLCSR Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB Reserved Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved Reserved Reserved Reserved ACSR ADMUX ADCSR ADCH ADCL Reserved Reserved
INT0 INTF0 OCIE1A OCF1A
PCIE1 PCIF OCIE1B OCF1B
PCIE0
TOIE1 TOV1
TOIE0 TOV0
Page
WDRF PSR0
BORF CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
Timer/Counter0 (8-Bit) Oscillator Calibration Register COM1A1 CTC1 COM1A0 PSR1 COM1B1 COM1B0 FOC1A CS13 FOC1B CS12 PWM1A CS11 PWM1B CS10
Timer/Counter1 (8-Bit) Timer/Counter1 Output Compare Register (8-Bit) Timer/Counter1 Output Compare Register (8-Bit) Timer/Counter1 Output Compare Register (8-Bit) PCKE PLLE PLOCK
WDCE
WDP2
WDP1
WDP0
PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7
EEAR6 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6
EEAR5 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5
EEAR4 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4
EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3
EEAR2 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2
EEAR1 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1
EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0
EEPROM Data Register (8-Bit)
Universal Serial Interface Data Register (8-Bit) USISIF USISIE USIOIF USIOIE USIPF USIWM1 USIDC USIWM0 USICNT3 USICS1 USICNT2 USICS0 USICNT1 USICLK USICNT0 USITC
REFS1 ADEN
ACBG REFS0 ADSC
ADLAR ADFR
MUX4 ADIF
ACIE MUX3 ADIE
ACME MUX2 ADPS2
ACIS1 MUX1 ADPS1
ACIS0 MUX0 ADPS0
Data Register High Byte Data Register Byte
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Instruction Summary
Mnemonic
ADIW SUBI SBCI SBIW ANDI RJMP IJMP RCALL ICALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID
Operands
Rdl, Rdl,
Description
Registers with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Relative Jump Indirect Jump Relative Subroutine Call Indirect Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less than Zero, Signed Branch Half-carry Flag Branch Half-carry Flag Cleared Branch T-flag Branch T-flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared Branch Interrupt Enabled Branch Interrupt Disabled Move between Registers Load Immediate Load Indirect Load Indirect Post-inc. Load Indirect Pre-dec.
Operation
Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl ($FF STACK STACK (Rr(b) (Rr(b) (P(b) (P(b) (SREG(s) then (SREG(s) then then then then then then then then then then then then then then then then then then then (X),
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
Clocks
1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
ARITHMETIC LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
1477J-AVR-06/07
Instruction Summary (Continued)
Mnemonic
PUSH SWAP BSET BCLR SLEEP
Operands
Rd,Y+q Y+q, Z+q,
Description
Load Indirect Load Indirect Post-inc. Load Indirect Pre-dec. Load Indirect with Displacement Load Indirect Load Indirect Post-inc. Load Indirect Pre-dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-inc. Store Indirect Pre-dec. Store Indirect Store Indirect Post-inc. Store Indirect Pre-dec. Store Indirect with Displacement Store Indirect Store Indirect Post-inc. Store Indirect Pre-dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Load Program Memory Port Port Push Register Stack Register from Stack Register Clear Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register Load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Two's Complement Overflow Clear Two's Complement Overflow SREG Clear SREG Half-carry Flag SREG Clear Half-carry Flag SREG Operation Sleep Watchdog Reset
Operation
(Y), (Z), STACK STACK I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7) Rd(0) Rd(n+1) Rd(n), Rd(7) Rd(7) Rd(n) Rd(n+1), Rd(0) Rd(n) Rd(n+1), Rd(3.0) Rd(7.4), Rd(7.4) Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b) (see specific descr. Sleep function) (see specific descr. WDR/timer)
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None None None None
Clocks
BIT-TEST INSTRUCTIONS
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Ordering Information
Speed (MHz) Power Supply Ordering Code ATtiny26L-8PC ATtiny26L-8SC ATtiny26L-8MC 5.5V ATtiny26L-8PI ATtiny26L-8SI ATtiny26L-8MI ATtiny26L-8PU(2) ATtiny26L-8SU(2) ATtiny26L-8MU(2) ATtiny26-16PC ATtiny26-16SC ATtiny26-16MC 5.5V ATtiny26-16PI ATtiny26-16SI ATtiny26-16MI ATtiny26-16PU(2) ATtiny26-16SU(2) ATtiny26-16MU(2)
Package(1)
Operational Range Commercial (0°C 70°C)
20P3 32M1-A 20P3 32M1-A 20P3 32M1-A 20P3 32M1-A 20P3 32M1-A 20P3 32M1-A
Industrial (-40°C 85°C)
Commercial (0°C 70°C)
Industrial (-40°C 85°C)
Notes:
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. Pb-free packaging alternative, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 20P3 32M1-A 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 32-pad, body, Lead Pitch 0.50 Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
1477J-AVR-06/07
Packaging Information
20P3
SEATING PLANE
SYMBOL Notes: This package conforms JEDEC reference MS-001, Variation Dimensions include mold Flash Protrusion. Mold Flash Protrusion shall exceed 0.25 (0.010").
COMMON DIMENSIONS (Unit Measure 0.381 25.493 7.620 6.096 0.356 1.270 2.921 0.203 0.000 5.334 25.984 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note Note NOTE
2.540
1/12/04 2325 Orchard Parkway Jose, 95131 TITLE 20P3, 20-lead (0.300"/7.62 Wide) Plastic Dual Inline Package (PDIP) DRAWING 20P3 REV.
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
1477J-AVR-06/07
32M1-A
SIDE VIEW
VIEW
0.08
COMMON DIMENSIONS (Unit Measure 0.80 0.90 0.02 0.65 0.20 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 0.30 0.20 0.40 0.50 0.60 0.30 5.10 4.80 3.25 5.10 4.80 3.25 1.00 0.05 1.00 NOTE
SYMBOL
Notch (0.20
BOTTOM VIEW
Note: JEDEC Standard MO-220, Fig. (Anvil Singulation), VHHD-2.
5/25/06 2325 Orchard Parkway Jose, 95131 TITLE 32M1-A, 32-pad, Body, Lead Pitch 0.50 3.10 Exposed Pad, Micro Lead Frame Package (MLF) DRAWING 32M1-A REV.
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Errata
ATtiny26 Rev. B/C/D
revision letter refers revision device. First Analog Comparator conversion delayed First Analog Comparator conversion delayed device powered slow rising VCC, first Analog Comparator conversion will take longer than expected some devices. Problem Fix/Workaround When device been powered reset, disable then enable Analog Comparator before first conversion.
1477J-AVR-06/07
Datasheet Revision History
Rev. 1477J-06/07 Rev. 1477I-10/06 Rev. 1477H-04/06
Please note that referring page numbers this section referred this document. referring revision this section referring document revision. "Not recommended design" Updated "Errata" page Updated typos. Added "Resources" page Updated features "System Control Reset" page Updated "Prescaling Conversion Timing" page Updated algorithm "Enter Programming Mode" page 114.
Rev. 1477G-03/05
MLF-package alternative changed "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". Updated "Electrical Characteristics" page Updated "Ordering Information" page
Rev. 1477F-12/04
Updated Table page Table page Table page Added Table page Added "Changing Channel Reference Selection" page 100. Updated "Offset Compensation Schemes" page 107. Updated "Electrical Characteristics" page 128. Updated package information "20P3" page Rearranged some sections datasheet.
Rev. 1477E-10/03
Removed Preliminary references. Updated "Features" page Removed SSOP package reference from "Pin Configuration" page Updated VRST tRST Table page Updated "Calibrated Internal Oscillator" page Updated Characteristics VOL, IIL, IIH, Power Down VACIO "Electrical Characteristics" page 128.
ATtiny26(L)
1477J-AVR-06/07
ATtiny26(L)
Updated VINT, Gain Error "ADC Characteristics" page page 132. Fixed typo "Absolute Accuracy" page 132. Added Figure "Pin Driver Strength" page 148, Figure 120, Figure Figure "BOD Thresholds Analog Comparator Offset" page 157. Updated Figure Figure 118. Removed from "Instruction Summary" page This instruction supported ATtiny26.
Rev. 1477D-05/03
Updated "Packaging Information" page Removed ADHSM from "ADC Characteristics" page 131. Added section "EEPROM Write During Power-down Sleep Mode" page Added section "Default Clock Source" page Corrected Lock value "Bit PLOCK: Lock Detector" page Added information about conversion time when selecting differential channels page Corrected {DDxn, PORTxn} value page Added section "Unconnected Pins" page Added note RSTDISBL Fuse Table page 110. Corrected DATA value Figure page 118. Added WD_FUSE period Table page 125. Updated "ADC Characteristics" page added Table "ADC Characteristics, Differential Channels, -40°C 85°C," page 132. Updated "ATtiny26 Typical Characteristics" page 133. Added "Instruction Summary" page
Rev. 1477C-09/02 Rev. 1477B-04/02
Changed Endurance Flash 10,000 Write/Erase Cycles. Removed references Power Save sleep mode section "System Clock Clock Options" page Updated section "Analog Digital Converter" page with more details read conversion result both differential singleended conversion. Updated "Ordering Information" page added QFN/MLF package information.
1477J-AVR-06/07
Rev. 1477A-03/02
Initial version.
ATtiny26(L)
1477J-AVR-06/07
Headquarters
Atmel Corporation 2325 Orchard Parkway Jose, 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
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1477J-AVR-06/07

8-bit Microcontroller with Bytes Flash ATtiny26 ATtiny26L Summary

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