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Digital Audio Processor With Codec Digital Audio Products SL


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TAS3004
Digital Audio Processor With Codec
Digital Audio Products
SLAS325
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such products services might used. TI's publication information regarding third party's products services does constitute TI's approval, license, warranty endorsement thereof. Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations notices. Representation reproduction this information with alteration voids warranties provided associated product service, unfair deceptive business practice, responsible liable such use. Resale TI's products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service, unfair deceptive business practice, responsible liable such use. Also see: Standard Terms Conditions Sale Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
Contents
Section Title Page Introduction Description Features Functional Block Diagram Terminal Assignments Terminal Functions Audio Data Formats Serial Interface Formats Digital Output Modes 2.2.1 First, Right-Justified Serial Interface Format-Normal Mode 2.2.2 Serial Interface Format-Normal Mode 2.2.3 Left-Justified Serial Interface Format-Normal Mode Digital Output Mode-Monaural 2.3.1 First, Right-Justified Serial Interface Format-Monaural Mode, Left Input Selected 2.3.2 Serial Interface Format-Monaural Mode, Left Input Selected 2.3.3 Left-Justified Serial Interface Format-Monaural Mode, Left Input Selected 2.3.4 First, Right-Justified Serial Interface Format-Monaural Mode, Right Input Selected 2.3.5 Serial Interface Format-Monaural Mode, Right Input Selected 2.3.6 Left-Justified Serial Interface Format-Monaural Mode, Right Input Selected 2-10 Switching Characteristics 2-11 Analog Input/Output Analog Input Analog Output 3.2.1 Analog Output 3.2.2 Analog Output With Gain 3.2.3 Reference Voltage Filter Audio Control/Enhancement Functions Soft Volume Update Software Soft Mute Input Mixer Control Mono Mixer Control Treble Control
Bass Control De-Emphasis (DM) Analog Control Register Operation Dynamic Loudness Contour 4.9.1 Loudness Biquads 4.9.2 Loudness Gain 4.9.3 Loudness Contour Operation 4.10 Dynamic Range Compression/Expansion 4.11 AllPass Function 4.12 Main Control Register (43h) Filter Processor Biquad Block 5.1.1 Filter Coefficients 5.1.2 Biquad Structure Serial Control Interface Introduction Protocol Operation 6.3.1 Write Cycle Example 6.3.2 TAS3004 Readback Example 6.3.3 Wait States SMBus Operation 6.4.1 Block Write Protocol 6.4.2 Write Byte Protocol 6.4.3 Wait States 6.4.4 TAS3004 SMBus Readback Microcontroller Operation General Description Power-Up/Power-Down Reset 7.2.1 Power-Up Sequence 7.2.2 Reset 7.2.3 Reset Circuit 7.2.4 Fast Load Mode 7.2.5 Codec Reset Power-Down Mode 7.3.1 Power-Down Timing Sequence Test Mode Internal Interface Terminal Programming 7.6.1 Switch Interface 7.6.2 Architecture External EPROM Memory Maps Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges
Recommended Operating Conditions Static Digital Specifications Digital Filter Analog-to-Digital Converter Input Multiplexer Interpolation Filter Digital-to-Analog Converter Output Performance Data 8.10 Serial Port Timing Characteristics System Diagrams Mechanical Information Software Interface Main Control Register A.1.1 Main Control Register A.1.2 Main Control Register A.1.3 Analog Control Register Volume Gain Command Treble Control Register Command Bass Control Register Command Register Command Programming Instruction Loudness Contour Examples DRCE A.7.1 DRCE On/Off A.7.2 Above Threshold Ratios A.7.3 Below Threshold Ratios A.7.4 Threshold A.7.5 Time Constants A.7.6 DRCE Example With Threshold
10-1 A-10 A-11 A-12 A-12 A-13
List Illustrations
Figure 2-10 Title Page TAS3004 Block Diagram TAS3004 Terminal Assignments First, Right-Justified Serial Interface Format-Normal Mode Serial Interface Format-Normal Mode Left-Justified Serial Interface Format-Normal Mode First, Right-Justified Serial Interface Format-Monaural Mode, Left Input Selected Serial Interface Format-Monaural Mode, Left Input Selected Left-Justified Serial Interface Format-Monaural Mode, Left Input Selected First, Right-Justified Serial Interface Format-Monaural Mode, Right Input Selected Serial Interface Format-Monaural Mode, Right Input Selected Left-Justified Serial Interface Format-Monaural Mode, Right Input Selected 2-10 Right-/Left-Justified, I2S, Left-/Left-Justified Serial Protocols 2-11 Analog Input TAS3004 Device VCOM Decoupling Network Analog Output With External Amplifier TAS3004 Reference Voltage Filter TAS3004 Function De-Emphasis Mode Frequency Response Block Diagram TAS3004 Digital Signal Processing Block Diagram Biquad Cascade Configuration Typical Data Transfer Sequence TAS3004 Reset Circuit Power-Down Timing Sequence Internal Interface Block Diagram Digital Filter Characteristics Digital Filter Stopband Characteristics Digital Filter Passband Characteristics High Pass Filter Characteristics Filter Overall Frequency Characteristics
Digital Filter Passband Ripple Characteristics Timing Stereo Application TAS3004 Device, Channels TAS3004 DRCE Characteristics Domain A-10 DRCE Example With Threshold A-13
List Tables
Table A-10 A-11 A-12 A-13 A-14 A-15 A-16 Title TAS3004 Terminal Functions Serial Interface Options Analog Control Register Description Main Control Register Description Protocol Definitions Address Byte Table Wait States Terminal Programming 512-Byte EEPROM Memory Channels 512-Byte EEPROM Memory Channels (with TAS3001) 2048-Byte EEPROM Memory Map-2.0 Speakers With Multiple Equalizations 2048-Byte EEPROM Memory Map-2.1 Speakers With Multiple Equalizations Register Main Control Register Description Main Control Register Description Analog Control Register Description Volume Versus Gain Values Treble Control Register Bass Control Register Mixer1 Mixer2 Gain Values Example DRCE Instruction With DRCE Example DRCE Instruction With DRCE Above Threshold Ratios Compression Above Threshold Ratios Expansion Below Threshold Ratios Expansion Below Threshold Ratios Compression Threshold Values Time Constants Page A-10 A-11 A-11 A-11 A-12 A-13
viii
Introduction
Description
TAS3004 device system-on-a-chip that replaces conventional analog equalization perform digital parametric equalization, dynamic range compression, loudness contour. Additionally, this device provides high-quality, soft digital volume, bass, treble control. control parameters uploaded through port from outside through slave port from external EPROM through master port. TAS3004 device also integrated 24-bit stereo codec with I2C-selectable, single-ended inputs channel. digital parametric equalization consists seven cascaded, independent biquad filters channel. Each biquad filter five 24-bit coefficients that configured into many different filter functions (such bandpass, high pass, pass). internal loudness contour algorithm controlled programmed with command. Dynamic range compression/expansion (DRCE) programmable through port. system designer threshold, energy estimation time constant, compression ratio, attack decay time constants. TAS3004 device supports serial interface formats (I2S, left justified, right justified) with data word lengths bits. sampling frequency (fS) kHz, 44.1 kHz, kHz. TAS3004 device uses system clock generated internal phase-locked loop (PLL). reference clock provided external master clock (MCLK) 256fS 512fS, 256fS crystal. TAS3004 device internally configurable general-purpose input (GPI) terminals that control volume, bass, treble, equalization. Each terminal debounce algorithm that programmed into TAS3004 internal microcontroller.
Features
Programmable seven-band parametric equalization Programmable digital volume control Programmable digital bass treble control Programmable dynamic range compression/expansion (DRCE) Programmable loudness contour/dynamic bass control Configurable serial port audio data input data channels that mixed with digital data from analog-to-digital converter (ADC) codec (analog input). These channels controlled commands. Three output data channels: Left right data through equalization; bass, treble, DRCE, volume SDOUT1; SDOUT2 mixes left right data. SDOUT2 operates center channel subwoofer channel. output available additional processing. Capability configure output monaural data streams stereo data stream Capability digitally left right input channels monaural output facilitate subwoofer operation Serial master/slave port that allows: Downloading control data device externally from EPROM master
Controlling other devices
I2C-selectable, single-ended analog input stereo channels Equalization bypass mode Single 3.3-V power supply Powerdown without reloading coefficients Sampling rates: kHz, 44.1 kHz, Master clock frequency, 256fS 512fS have crystal input replace MCLK. Crystal input frequency 256fS. terminals volume, bass, treble up/down control, mute, selection equalization filters
AVSS(REF) VREFM
Functional Block Diagram
VREFP VRFILT
AVDD
DVDD Analog Control Register Output Format Control Logic
AINRP AINRM RINA RINB Voltage Reference Analog Supplies Digital Supplies
AINRP
AINRM AINLP AINLM LINA LINB AINLP 24-Bit Stereo SDOUT0
AINLM ALLPASS INPA Controller GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 Control SDOUT2 32-Bit Audio Signal Processor SDOUT1 32-Bit Audio Signal Processor VCOM AOUTL AOUTR 24-Bit Stereo
Control
PWR_DN RESET TEST
SDATA Control
OSC/CLK Select
LRCLK/O
SCLK/O
XTALI/ MCLK XTALO
SDIN1 SDIN2
IFM/S
Figure 1-1. TAS3004 Block Diagram
CAP_PLL
CLKSEL
MCLKO
DVSS
AVSS
Terminal Assignments
PACKAGE (TOP VIEW)
LINB AINLP AINLM REFM REFP AINRM AINRP RINB RINA AOUTL VCOM AOUTR
LINA VRFILT AVSS(REF) AVSS INPA RESET PWR_DN TEST CAP_PLL CLKSEL MCLKO
AVDD GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 ALLPASS SDOUT1 SDOUT0
Figure 1-2. TAS3004 Terminal Assignments
Terminal Functions
Table 1-1. TAS3004 Terminal Functions
TERMINAL NAME AINLM AINLP AINRM AINRP ALLPASS AOUTL AOUTR AVDD AVSS AVSS(REF) CAP_PLL CLKSEL DESCRIPTION left channel analog input (anti-alias capacitor) left channel analog input (anti-alias capacitor) right channel analog input (anti-alias capacitor) right channel analog input (anti-alias capacitor) Logic high bypasses equalization filters Left channel analog output Right channel analog output Analog power supply (3.3 Analog voltage ground Analog ground voltage reference Loop filter internal phase-locked loop (PLL) Logic selects 256fS; logic high selects 512fS MCLK address 68h, high
XTALI/MCLK XTALO DVDD DVSS LRCLK/O SCLK/O IFM/S SDIN1 SDIN2 SDOUT2
Table 1-1. TAS3004 Terminal Functions (Continued)
TERMINAL NAME DVDD DVSS GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 IFM/S INPA LINA LINB LRCLK/O MCLKO PWR_DN RESET RINA RINB SCLK/O SDIN1 SDIN2 SDOUT1 SDOUT2 SDOUT0 TEST VCOM VREFM VREFP VRFILT XTALI/MCLK XTALO Digital power supply (3.3 Digital ground Switch input terminals DESCRIPTION
Digital audio control (low input; high output) when analog input selected (will sink Left channel analog input Left channel analog input Left/right clock input/output (output when IFM/S high) MCLK output slave devices connection; used printed circuit board routing channel connection; used printed circuit board routing channel Logic high places TAS3004 device power-down mode Logic resets TAS3004 device initial state Right channel analog input Right channel analog input clock connection Shift (bit) clock input (output when IFM/S high) data connection Serial data input Serial data input Serial data output (from internal audio processing) Serial data output monaural left right, before processing) Serial data output from Reserved manufacturing test terminal; connect DVSS Digital-to-analog converter mid-rail supply (decouple with parallel combination 10-µF 0.1-µF capacitors) minus voltage reference plus voltage reference Voltage reference pass filter Crystal external MCLK input Crystal input (crystal connected between terminals
Audio Data Formats
Serial Interface Formats
TAS3004 device works master slave mode. master mode, terminal (IFM/S) tied high. This activates master clock (MCLK) circuitry. crystal connected across terminals (XTALI/MCLK) (XTALO), external, TTL-compatible MCLK connected XTALI/MCLK. that case, MCLK outputs from terminal (MCLKO) with terminals (LRCLK/O) (SCLK/O) becoming outputs drive slave devices. slave mode, IFM/S tied low. LRCLK/O SCLK/O inputs interface operates slave device requiring externally supplied MCLK, LRCLK (left/right clock), SCLK (shift clock) inputs. There options selecting clock rates. 512fS MCLK rate selected, terminal (CLKSEL) tied high MCLK rate 512fS must supplied. 256fS MCLK selected, CLKSEL tied MCLK 256fS must supplied. both cases, LRCLK 64SCLK must supplied. MCLK SCLK must synchronous their edges must least apart. LRCLK phase changes more than 10MCLK, codec automatically resets.
TAS3004 device compatible with different serial interfaces. Available interface options I2S, right justified, left justified. Table indicates options selected using main control register (MCR, address x01h). serial interface options either bits operate with SCLK 64fS. Additionally, 16-bit mode operates 32fS. Table 2-1. Serial Interface Options
MODE (5-4) (1-0) SERIAL INTERFACE SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT0 16-bit, left justified, 32fS 16-bit, left justified, 64fS 16-bit, right justified, 64fS 16-bit, I2S, 64fS 18-bit, left justified, 64fS 18-bit, right justified, 64fS 18-bit, I2S, 64fS 20-bit, left justified, 64fS 20-bit, right justified, 64fS 20-bit, I2S, 64fS 24-bit, left justified, 64fS 24-bit, right justified, 64fS 24-bit, I2S, 64fS
Figure through Figure illustrate relationship between SCLK, LRCLK, serial data different interface protocols.
Digital Output Modes
digital output mode (SDOUT0) operational modes, normal monaural. normal mode, output conforms output modes described Sections 2.2.1 through 2.2.3. enter normal output mode, (ADM) analog control register must cleared monaural output mode, digital output conforms output modes described Sections 2.3.1 through 2.3.6. enter monaural mode, (ADM) analog control register must
2.2.1
First, Right-Justified Serial Interface Format-Normal Mode
normal output mode first, right-justified serial interface format bits with (ADM) analog control register cleared Figure shows following characteristics this protocol: Left channel transmitted when LRCLK high. SDIN(s) (recorded) data justified trailing edge LRCLK. SDOUT(s) (playback) data transmitted same time LRCLK edge captured next rising edge SCLK. LRCLK phase changes more than 10MCLK, codec automatically resets.
SCLK
LRCLK
SDIN
SDOUT
Left Channel
Right Channel
Figure 2-1. First, Right-Justified Serial Interface Format-Normal Mode
2.2.2
Serial Interface Format-Normal Mode
normal output mode serial interface format bits with (ADM) analog control register cleared Figure shows following characteristics this protocol: Left channel transmitted when LRCLK low. SDIN sampled with rising edge SCLK. SDOUT transmitted falling edge SCLK. LRCLK phase changes more than 10MCLK, codec automatically resets.
SCLK
LRCLK
SDIN
SDOUT
Left Channel
Right Channel
Figure 2-2. Serial Interface Format-Normal Mode
2.2.3
Left-Justified Serial Interface Format-Normal Mode
normal output mode left-justified serial interface format bits with (ADM) analog control register cleared Figure shows following characteristics this protocol: Left channel transmitted when LRCLK high. SDIN data justified leading edge LRCLK. MSBs transmitted same time LRCLK edge captured next rising edge SCLK.
SCLK
LRCLK
SDIN
SDOUT
Left Channel
Right Channel
Figure 2-3. Left-Justified Serial Interface Format-Normal Mode
Digital Output Mode-Monaural
monaural digital output mode, (ADM) (LRB) (INP) analog control register (see Section 4.8, Analog Control Register Operation) control operation monaural output mode. interface formats bits.
2.3.1 First, Right-Justified Serial Interface Format-Monaural Mode, Left Input Selected
monaural output mode first, right-justified serial interface format bits with following bits analog control register shown: (ADM) (LRB) cleared (INP)
Figure shows following characteristics this protocol: Left channel transmitted when LRCLK either high low. SDIN(s) (recorded) data justified trailing edge LRCLK. SDOUT(s) (playback) data transmitted same time LRCLK edge captured next rising edge SCLK. LRCLK phase changes more than 10MCLK, codec automatically resets.
SCLK
LRCLK
SDIN
SDOUT0
Left Channel
Left Channel
Figure 2-4. First, Right-Justified Serial Interface Format-Monaural Mode, Left Input Selected
2.3.2
Serial Interface Format-Monaural Mode, Left Input Selected
monaural output mode serial interface format bits with following bits analog control register shown: (ADM) (LRB) cleared (INP)
Figure shows following characteristics this protocol: Left channel transmitted when LRCLK either high low. SDIN sampled with rising edge SCLK. SDOUT transmitted falling edge SCLK. LRCLK phase changes more than 10MCLK, codec automatically resets.
SCLK
LRCLK
SDIN
SDOUT0
Left Channel
Left Channel
Figure 2-5. Serial Interface Format-Monaural Mode, Left Input Selected
2.3.3
Left-Justified Serial Interface Format-Monaural Mode, Left Input Selected
monaural output mode left-justified serial interface format bits with following bits analog control register shown: (ADM) (LRB) cleared (INP)
Figure shows following characteristics this protocol: Left channel transmitted when LRCLK either high low. SDIN data justified leading edge LRCLK. MSBs transmitted same time LRCLK edge captured next rising edge SCLK.
SCLK
LRCLK
SDIN
SDOUT0
Left Channel
Left Channel
Figure 2-6. Left-Justified Serial Interface Format-Monaural Mode, Left Input Selected
2.3.4 First, Right-Justified Serial Interface Format-Monaural Mode, Right Input Selected
monaural output mode first, right-justified serial interface format bits with following bits analog control register shown: (ADM) (LRB) (INP)
Figure shows following characteristics this protocol: Right channel transmitted when LRCLK either high low. SDIN(s) (recorded) data justified trailing edge LRCLK. SDOUT(s) (playback) data transmitted same time LRCLK edge captured next rising edge SCLK. LRCLK phase changes more than 10MCLK, codec automatically resets.
SCLK
LRCLK
SDIN
SDOUT0
Right Channel
Right Channel
Figure 2-7. First, Right-Justified Serial Interface Format-Monaural Mode, Right Input Selected
2.3.5
Serial Interface Format-Monaural Mode, Right Input Selected
monaural output mode serial interface format bits with following bits analog control register shown: (ADM) (LRB) (INP)
Figure shows following characteristics this protocol: Right channel transmitted when LRCLK either high low. SDIN sampled with rising edge SCLK. SDOUT transmitted falling edge SCLK. LRCLK phase changes more than 10MCLK, codec automatically resets.
SCLK
LRCLK
SDIN
SDOUT0
Right Channel
Right Channel
Figure 2-8. Serial Interface Format-Monaural Mode, Right Input Selected
2.3.6
Left-Justified Serial Interface Format-Monaural Mode, Right Input Selected
monaural output mode left-justified serial interface format bits with following bits analog control register shown: (ADM) (LRB) (INP)
Figure shows following characteristics this protocol: Right channel transmitted when LRCLK either high low. SDIN data justified leading edge LRCLK. MSBs transmitted same time LRCLK edge captured next rising edge SCLK.
SCLK
LRCLK
SDIN
SDOUT0
Right Channel
Right Channel
Figure 2-9. Left-Justified Serial Interface Format-Monaural Mode, Right Input Selected
2-10
Switching Characteristics
PARAMETER tc(SCLK) td(SLR) td(SDOUT) tsu(SDIN) th(SDIN) LRCLK SCLK frequency SCLK rising LRCLK edge SDOUT valid from SCLK falling (see Note SDIN setup before SCLK rising edge SDIN hold after SCLK rising edge Duty cycle NOTE Maximum 50-pF external load SDOUT. tc(SCLK) tr(SCLK) 44.1 (1/256fS) 3.072 UNIT
SCLK
td(SLR)
tf(SCLK)
LRCLK
td(SDOUT) SDOUT1 SDOUT2 SDOUT0 tsu(SDIN)
td(SLR)
th(SDIN) SDIN1 SDIN2
Figure 2-10. Right-/Left-Justified, I2S, Left-/Left-Justified Serial Protocols
2-11
2-12
Analog Input/Output
TAS3004 device contains stereo 24-bit with single-ended inputs channel. Selection analog input accomplished setting analog control register (ACR) command. Additionally, TAS3004 device stereo 24-bit digital-to-analog converter (DAC).
Analog Input
Figure shows technique components required analog input TAS3004 device. maximum input signal must exceed Vrms. Selection above component values gives frequency response from sampling frequency without alias frequency problems.
1200 0.47 0.47 AINRP AINRP AINRM RINA RINB Voltage Reference
1200 0.47 0.47 AINLP AINLM LINA LINB
AINRM 24-Bit Stereo AINLP
AINLM
Analog Inputs 0.47 20-Hz Cutoff Anti-Alias Capacitors unused analog inputs analog ground through 0.1-µF capacitors.
Input Select Command From Internal Controller
Figure 3-1. Analog Input TAS3004 Device
Analog Output
3.2.1 Analog Output
full scale analog output from TAS3004 device Vrms. referenced VCOM which approximately Vdc. VCOM must decoupled with network shown Figure 3-2.
Analog Output (Adjust Capacitors Desired Frequency Response) AOUTR
24-Bit
VCOM AOUTL
AGND
Figure 3-2. VCOM Decoupling Network
3.2.2
Analog Output With Gain
Since analog output from TAS3004 device Vrms, output level increased using external amplifier. circuit shown Figure boosts output level Vrms (when gain 1.414) provides improved signal-to-noise ratio (SNR). Since this circuit lowers noise floor, improved also.
Analog Output (Adjust Capacitors Desired Frequency Response) 24-Bit VCOM AOUTL Amp/2 AGND TLV2362 Equilvalent
AOUTR
TLV2362 Equilvalent
Amp/2
Figure 3-3. Analog Output With External Amplifier
3.2.3
Reference Voltage Filter
Figure shows TAS3004 reference voltage filter.
AVSS
AVSS(REF)
VRFILT
VREFM VREFP
TAS3004
Figure 3-4. TAS3004 Reference Voltage Filter
Audio Control/Enhancement Functions
Soft Volume Update
TAS3004 device implements proprietary soft volume update. This feature allows smooth pleasant-sounding change from volume level another over entire range volume control mute). volume adjustable downloading 4.16 gain coefficient through interface. Table lists 4.16 coefficients converted into range with 0.5-dB step resolution. Right left channel volumes unganged different values. This feature implements balance control. Volume changed writing desired value into volume control registers. This done asserting terminals volume-up volume-down limited range volume control. Alternately, volume control settings sent TAS3004 device over bus.
Software Soft Mute
Mute implemented loading zeros volume control register. This causes volume ramp down over duration 2048fS samples final output infinity dB). Soft mute enabled either asserting mute terminal sending mute command over bus.
Input Mixer Control
TAS3004 device capable mixing multiplexing three channels serial audio data. mixing controlled through three mixer control registers. This accomplished loading values into corresponding bytes mixer left gain (07h) mixer right gain (08h) control registers. values loaded into these registers 4.20 format-4 bits integer bits fractional part. Table lists 4.20 numbers converted into range although positive 4.20 number used. mute channels, loaded into respective mixer control register. Mixer controls updated instantly cause audible artifacts large changes setting when updated dynamically outside fast load mode; therefore, desirable fast load conjunction with soft-volume mode. SDIN1, SDIN2, output mixed with user-selectable gain each channel. gain control registers represented 4.20 format.
Left Channel Coefficients Register Address
SDIN1 SDIN2 24-Bit Left Coefficient
SDIN1_L
SDIN2_L
L_SUM
Biquad Filters
Tone
Soft Volume DRCE
ADC_L SDOUT1 SDIN1_R
SDIN2_R
Biquad Filters
Tone
Soft Volume DRCE
ADC_R R_SUM R_SUM Right Channel Coefficients Register Address SDOUT2
SDIN1 SDIN2 24-Bit Right Coefficient
Figure 4-1. TAS3004 Function
Mono Mixer Control
TAS3004 device contains second mixer that performs function mixing left right channel digital audio data from input mixer order derive monaural channel. This mixer fixed gain that full scale inputs L_sum R_sum produce clipping resulting L+R_sum. output this mixer present terminal (SDOUT2) generally used digitally-mixed subwoofer center channel application.
Treble Control
treble gain level adjusted within range with 0.5-dB step resolution. level changes accomplished downloading treble codes (shown Appendix into treble gain register. Alternately, limited range treble control available asserting terminals. treble control corner frequency 48-kHz sample rate. gain values treble control found Section A.3.
Bass Control
bass gain level adjusted within range with 0.5-dB step resolution. level changes accomplished downloading bass codes (shown Appendix into bass frequency control register. Alternately, limited range bass control available asserting terminals. Bass control shelf filter with corner frequency 48-kHz sample rate. gain values bass control found Section A.4.
De-Emphasis (DM)
De-emphasis implemented software controlled. De-emphasis valid 44.1 kHz. enable de-emphasis, values written into analog control register command. Section analog control register operation. Figure illustrates frequency response de-emphasis mode.
De-Emphasis
Response (dB)
3.18 Frequency (kHz)
10.6
Figure 4-2. De-Emphasis Mode Frequency Response
Analog Control Register Operation
analog control register (ACR) allows control de-emphasis, selection analog input channel ADC, analog power down. master required write appropriate command into ACR. subaddress 0x40.
Type Default
Table 4-1. Analog Control Register Description
FIELD NAME TYPE output mode. Normal operation inputs normal; inputs monaural. Selects left right input monaural output. left input selected monaural output when (ADM) right input selected monaural output when (ADM) RSVD DM(1-0) Reserved. Bits return when read. De-emphasis control. De-emphasis (initial condition after reset) sample rate de-emphasis selected 44.1 sample rate de-emphasis selected Reserved Analog input select. LINA RINA selected (initial condition after reset) LINB RINB selected Analog powerdown. Normal operation (initial condition after reset) Powerdown DESCRIPTION
Dynamic Loudness Contour
necessity applying loudness compensation playback systems compensate fact that perceives bass treble less audibly levels than high ones been established with first data published Fletcher Munson 1933. There many equal-loudness contours publication, like Steven's contours, Robinson Dadson contours even reached acceptance level recommendation. TAS3004 device simplified loudness contour algorithm that diminishes effect weak bass listening levels. Since contour volume level dependency, user must define relation between gain contour circuit volume level. Figure block diagram this circuit.
Volume
Biquad
Gain
Figure 4-3. Block Diagram loudness contour activated sending activation command from external device. Optionally, contour gain command sent external device provide tracking with system's volume control.
4.9.1
Loudness Biquads
Loudness biquad filters left right channels independently programmable I2C. Their subaddresses 0x21 0x22, respectively. digital filters written five 24-bit (4.20) coefficients each channel.
4.9.2
Loudness Gain
Loudness gain values left right channels independently programmable I2C. Their subaddresses 0x23 0x24, respectively. gain values written 4.20 coefficient each channel.
4.9.3
Loudness Contour Operation
When frequency loudness contour determined, digital filter must developed. Then, gain filter determined. These values placed storage area system controller (microcontroller) sent TAS3004 device when desired activate loudness contour. necessary change frequency gain contour, gain filter coefficients sent system controller. This function performed normally when volume control changed (that more volume, less contour). gain loudness contour filter then tracks volume control. loudness contour biquad filters provided addition seven equalization biquad filters. Section programming instructions.
4.10 Dynamic Range Compression/Expansion
TAS3004 device provides user with ability manage dynamic range audio system. DRCE receives data, affects scaling after volume/loudness block. shown Figure 4-4, DRCE applied after volume/loudness control block DRCE scale factor. DRCE must adjusted such that signal does reach hard limit value. However, signal does reach maximum digital value, saturation logic serves hard limiter that does allow signal extend beyond available range.
Loudness (Left Channel Mixer) SDIN1_L LEFT_SUM SDIN2_L (Parametric Equalization) Order Filters (Tone) Bass/ Treble Soft Volume/
(DRCE Scaling) Saturation Logic LEFT_OUT
ANALOGIN_L
(Analog From ADC)
Dynamic Range Control
ANALOGIN_R
SDIN1_R SDIN2_R
RIGHT_SUM
Order Filters (Parametric Equalization)
Bass/ Treble (Tone)
Soft Volume/ (DRCE Scaling) Loudness
Saturation Logic
RIGHT_OUT
(Right Channel Mixer)
Figure 4-4. TAS3004 Digital Signal Processing Block Diagram DRCE instruction consists eight bytes that must sent each time order shown example code Table A-9. Each instruction downloaded must eight bytes. only byte changed, eight bytes must transmitted. first bytes remain same every instruction, however last bytes programmed using hexadecimal values from corresponding tables referred Section A.7. With high compression ratios fast attack times available, this function suited commercial killer television application.
4.11 AllPass Function
This function enabled setting terminal (ALLPASS) TAS3004 device When asserted, internal equalization filters into AllPass (flat) mode. When this terminal reset equalization filters returned equalization that before terminal asserted. AllPass mode, bass treble controls still functional. This function frequently used headphones. When headphone plug inserted into jack, switched contact jack enables AllPass function. AllPass function also activated writing analog control register.
4.12 Main Control Register (43h)
TAS3004 device contains main control registers: main control register (MCR1) main control register (MCR2). MCR2 contains bits associated with AllPass function download bass treble control information, accessed with address 43h. MCR2 (43h)
Type Default
Table 4-2. Main Control Register Description
b6-b5 b4-b2 TYPE DESCRIPTION Normal operation (initial condition after reset) Download bass treble Reserved. Bits return when read. Undefined. Normal operation (initial condition after reset) AllPass mode (bass treble still functional) Reserved. returns when read.
Filter Processor
Biquad Block
biquad block consists seven digital biquad filters channel organized cascade structure, shown Figure 5-1. Each these biquad filters five downloadable 24-bit (4.20) coefficients. Each stereo channel independent coefficients.
Biquad Biquad Biquad
Figure 5-1. Biquad Cascade Configuration
5.1.1
Filter Coefficients
filter coefficients TAS3004 device downloaded through port loaded into biquad memory space. Each biquad filter memory space independent address. Digital audio data coming into device processed biquad block then converted into analog waveforms DAC. Alternately, filters loaded asserting terminals port.
5.1.2
Biquad Structure
biquad structure that used parametric equalization filters follows: H(z) NOTE: fixed value downloadable. coefficients these filters represented 4.20 format-4 bits integer part bits fractional part. order transmit them over I2C, necessary separate each coefficient into three bytes. upper bits byte integer part, second nibble byte byte byte fractional parts. filters designed using automatic loudspeaker equalization program (ALE) script running under MatLab named Filtermaker. Both these tools available from Texas Instruments.
Serial Control Interface
Introduction
Control parameters TAS3004 device loaded from serial EPROM using TAS3004 master interface mode. EPROM found, TAS3004 device becomes slave device loads from another master interface. Information loaded into TAS3004 registers defined Appendix uses terminals (SDA data) (SCL clock) communicate between integrated circuits system. These devices addressed sending unique 7-bit slave address plus byte). compatible devices share same terminals bidirectional using wired-AND connection. external pullup resistor must used high level bus. TAS3004 device operates standard mode kbps with many devices desired capacitance load limit Furthermore, TAS3004 device supports subset SMBus protocol. When attached SMBUS, then byte, word, block transfers supported. SMBus function supported care must taken with sequence instructions sent TAS3004 device. Additionally, TAS3004 device operates either master slave mode; therefore, least device connected must operate master mode.
Protocol
standard uses transitions while clock high indicate start stop conditions. high-to-low transition indicates start low-to-high transition indicates stop. Normal data transitions must occur within time clock period. Figure shows these conditions. These start stop conditions required standard protocol generated master. master must also generate 7-bit slave address read/write (R/W) open communication with another device then wait acknowledge condition. slave holds during acknowledge clock period indicate acknowledgment. When this occurs, master transmits next byte sequence. After each 8-bit word, acknowledgment must transmitted receiving device. There limit number bytes that transmitted between start stop conditions. When last word transfers, master generates stop condition release bus. Figure shows generic data transfer sequence.
7-Bit Slave Address 8-Bit Register Data Address 8-Bit Register Data Address 8-Bit Register Data Address (N+1)
Start Stop
Figure 6-1. Typical Data Transfer Sequence
Table lists definitions used protocol. Table 6-1. Protocol Definitions
DEFINITION Transmitter Receiver Master Slave Multimaster Arbitration Synchronization device that sends data device that receives data device that initiates transfer, generates clock signals, terminates transfer device addressed master More than master attempt control same time without corrupting message. Procedure ensure message corrupted when masters attempt control bus. Procedure synchronize clock signals more devices DESCRIPTION
Operation
7-bit address TAS3004 device 011010X where programmable address bit, terminal (CS1). Combining bit, TAS3004 device respond four different addresses (two read write). These addresses licensed addresses that conflict with other licensed audio devices. addition 7-bit device address, subaddresses direct communication proper memory location within device. complete table subaddresses control registers provided Appendix example, change bass 10-dB gain, Section 6.3.1 shows data that written port: Table 6-2. Address Byte Table
ADDRESS BYTE 0x68 0x69 0x6A 0x6B A6-A1 011010 011010 011010 011010 (A0)
6.3.1
Start
Write Cycle Example
Slave Address FUNCTION Start Slave address Subaddress Data Stop Subaddress Data Stop
DESCRIPTION Start condition defined 0110100 (CS1 (write) Acknowledgement defined (slave) 00000110 (see Appendix 00011100 (see Appendix Stop condition defined
NOTE: Table serial data (SDA); serial clock (SCL) shown conditions apply well.
Whenever writing subaddress, correct number data bytes must follow order complete write cycle. example, volume control register with subaddress (hex) written bytes data must follow; otherwise, cycle incomplete errors occur.
6.3.2
TAS3004 Readback Example
TAS3004 will save Stack First-In First-Out (FIFO) buffer last bytes that were sent When read command sent device (LSB=high), answers popping first byte stack. TAS3004 will then expect either SendAck command Stop command from host. SendAck command sent from host then TAS3004 will another byte stack. Stop sent then TAS3004 will this transaction. proper sequence reading described follows:
Start
Send address byte with read (LSB equal receive Byte Send receive Byte Send receive Byte Send receive Byte Send receive Byte Send receive Byte Send receive Byte send after Byte will lock TAS3004) Stop
Where: Start valid Start Command Receive Byte valid Command which reads byte from TAS3004. SendAck avalid Command that informs TAS3004 that byte been read. Stop valid Stop Command
NOTES: TAS3004 will appear locked SendACK issued after last byte read. required send Stop Condition after last byte SendACK. I2Cstart I2Cstop commands same both read write.
6.3.3
Wait States
TAS3004 device performs interpolation algorithms volume tone controls. volume tone change sent part I2C, command sent after volume tone (bass treble) change causes wait state occur. This wait state lasts from depending system clock rate, command sent, and, case bass treble, amount change. Secondly, long series commands sent TAS3004 device, occasionally create short wait state order while loads processes commands. When sample rate used, longer wait states occur, occasionally preferred take care wait states controller that recognizes wait states. During wait state period, stops sending data over I2C. this function available system controller, fixed delays implemented system software ensure that controller trying send more data while TAS3004 device busy. Sending data while TAS3004 device busy causes errors locks device, which must then reset.
Table gives typical values wait states that expected with various functions part: Table 6-3. Wait States
SYSTEM SAMPLING FREQUENCY Volume Bass Treble Mixer Loudness Equalization None None 44.1 None None None None occur with each filter Comment dependent size change 0.055 0.055
SMBus Operation
TAS3004 device supports subset SMBus protocol. With proper programming techniques, possible SMBus TAS3004 device.
6.4.1
Block Write Protocol
TAS3004 device supports block write protocol that allows bytes sent block. send command using this format, most significant (MSB) TAS3004 subaddress must high subaddress (also with high) must programmed into SMBus command byte. This operation signals TAS3004 device realize that next byte SMBus byte count byte. next byte after byte count then entered into device first byte data.
SMBus Command Byte TAS3004 Address Subaddress subaddress) Byte Count (Don't Care) Data Data Data
6.4.2
Write Byte Protocol
TAS3004 device also supports SMBus write byte protocol. Writing main control register (MCR), bass, treble registers require using byte write protocol. send command using this format, most significant (MSB) TAS3004 subaddress must high subaddress (also with high) must programmed into SMBus command byte. next byte after command byte then entered into device first byte data.
SMBus Command Byte TAS3004 Address Subaddress subaddress) Data
6.4.3
Wait States
separate I2C/SMBus commands sent frequently, TAS3004 device generate wait state. This happens when device busy while performing smoothing operations changing volume, bass, treble. wait occurs after acknowledge first data byte exceed maximum allowable time allowed according SMBus specification (worst case ms). following possible wait state scenario:
CODE Start Wait Stop
ACTUAL Start Stop master does recognize waiting master times long wait, master must send consecutive I2C/SMBus commands without time interval between transactions.
6.4.4
TAS3004 SMBus Readback
TAS3004 device supports subset SMBus readback. When SMBus read command sent device (LSB high), answers with subaddress last bytes written.
SMBus Command Byte SENT RECEIVED Start Start Byte Count Byte Count Stop Stop
Where: Command byte, don't care because response contains only subaddress last bytes data written TAS3004 device last subaddress accessed device Data bytes from TAS3004 device
NOTE: read sequence defined 6.3.2
Microcontroller Operation
TAS3004 device contains internal microcontroller programmed Texas Instruments perform housekeeping interface functions. Additionally, handles communication general purpose input functions.
General Description
microcontroller uses 256fS system clock access bytes memory. interfaces with digital audio interface master/slave downloading data coefficients. also interfaces with internal DSPs transferring coefficients other information. TAS3004 coefficients loaded through master slave mode. Standard audio processing functions (volume, bass, treble) controlled/activated through external switches connected terminals. Upon reset, internal microcontroller sets coefficients audio parameters default values. Section 7.2.2 default values. TAS3004 address (ADDR_SEL=0), becomes master device attempts load parameters coefficients from external EPROM. EPROM present, TAS3004 device remains default condition. addresses other than 68h/69h set, TAS3004 device only operates slave device. microcontroller determines TAS3004 device address 68h/69h EPROM present, microcontroller downloads coefficients from EPROM. Once download complete, enables serial audio mode defined write transfer data into device. Before reading EPROM, serial audio port defaults mode. TAS3004 device allows user update volume, bass, treble dynamically slave command simple switch input. select volume down, bass/treble down, digital equalizations. five different equalizations (that flat, jazz, rock, voice, etc.) stored external EPROM. Also, DRCE, MCR1, MCR2, loudness contour enabled disabled I2C. When TAS3004 device operates master mode, echoes changes functions other addresses that defined external EPROM. addresses defined, does echo.
Power-Up/Power-Down Reset
7.2.1 Power-Up Sequence
active terminal (RESET) while MCLK running, resets internal microcontroller DSP(s). RESET synchronizes internally asserted asynchronously with simple circuit Figure 7-1. reset, high-impedance state. address 68h, approximately after RESET returns device sends one-byte query look EPROM. EPROM found, becomes master; otherwise, becomes slave. When using address slave mode, external master must wait until after EPROM query else contention improper operation occurs. address x6Ah does query EPROM. address EPROM xA0h.
7.2.2
Reset
TAS3004 device asynchronous reset terminal (RESET). This reset synchronized with various clocks used this device generate synchronous internal reset. Upon reset, TAS3004 device goes through following process: Clears memory content
Clears registers circuits Purges codec Selects analog input (RINA LINA) sets input active indicator (INPA) low. Initializes equalization parameters AllPass filters Sets digital audio interface I2S-18-bit mode Sets bass/treble Sets mixer gain SDIN1 mutes both SDIN2 analog-in Sets volume Turns enhancement features (DRCE, etc.). Reads address. address 68h, device reads EPROM. possible load user-defined bass/treble data break points (optional). there data, device loads default bass/treble delta break points from ROM. address 6Ah, device puts interface slave mode waits input.
7.2.3
Reset Circuit
Since TAS3004 device internal power-on reset (POR), many cases, additional components needed reset device. resets internally approximately VDD. case where system's power supplies slow reaching their final voltage where there difference time system power supplies take become stable, TAS3004 reset delayed simple circuit.
DVDD
DVSS RESET
TAS3004
Figure 7-1. TAS3004 Reset Circuit values above circuit calculated simple equation: 0.8RC Where: delay before TAS3004 device comes reset Value capacitance from RESET (pin DVSS Value resistance from RESET (pin DVDD circuit described Figure delays start-up TAS3004 device approximately When necessary control reset TAS3004 device with external device, such microcontroller, RESET (pin treated logic signal. then brings device reset when voltage RESET reaches VDD/2.
7.2.4
Fast Load Mode
While fast load mode, possible update parametric equalization without audio processing delay. audio processor pauses while updated this mode. Bass treble cannot download this mode. Mixer1 Mixer2 registers download this mode normal mode
Once download complete, fast load must cleared writing into main control register (MCR). This puts TAS3004 device into normal mode.
7.2.5
Codec Reset
During initialization, output CODEC disabled. Throughout reset initialization, output muted prevent extraneous noise being sent system output. Data from other internal processing purged that when reset/initialization complete, only valid inputs sent system output.
Power-Down Mode
TAS3004 device asynchronous power-down mode. power-down mode, internal control registers equalization programming device stored device. enter power-down mode: Assert power-down control signal serial audio input clocks
TAS3004 device goes into power-down mode. exit power-down mode: Assert RESET (logic Restart serial audio clocks Wait delay allow lock) Negate power-down control signal (logic Negate RESET (logic
device then returns state before power down (resumes normal operation).
7.3.1
Power-Down Timing Sequence
PWR_DN
RESET
MCLK
SCLK
LRCLK
SDATA Power-Down Mode Normal Operation
Figure 7-2. Power-Down Timing Sequence power-down mode, TAS3004 device consumes typically less than
Test Mode
Terminal (TEST) tied normal operation. This function reserved factory test must asserted.
Internal Interface
Figure shows block diagram interface between microcontroller peripheral blocks.
Terminal Programming
During initialization, microcontroller fetches control byte from EPROM receives command from I2C.
7.6.1
Switch Interface
terminals programmed operate following manner: Table 7-1. Terminal Programming
GPI5 VOL_UP, VOL_DN, BASS_UP, BASS_DN, TREB_UP, TREB_DN, Shift Mute Shift NOTE: Logic GPI4 GPI3 GPI2 GPI1 GPI0
Initially (after reset), TAS3004 control volume, bass, treble. Simultaneously setting bits second changes function terminals control mute equalization. return volume, bass, treble control, simultaneously terminals second. When switch activated, TAS3004 device echoes function over TAS3001 device mapped address x6Ah. Therefore, system with audio equalization chips implemented without need microcontroller.
7.6.2
Architecture
provides simple flexible input port activate input parameters. Each terminal input active logic low.
Start
Power
Restore Volume
Initialize Default
EPROM
Initialize TAS3004 TAS3001
Slave Write
Load Parameters Coefficients
Volume/Bass/Treble Up/Down Echo TAS3001 Switch
Power Down
Save Volume, Mute Save PWR_DN Stop
Stop DRC_OFF
Figure 7-3. Internal Interface Block Diagram
External EPROM Memory Maps
Table through Table show 512-byte 2048-byte EPROM memory maps. Table 7-2. 512-Byte EPROM Memory Channels
ADDRESS 000h 001h 002h 003h-00Bh 00Ch-014h 015h-01Ah 01Bh 01Ch 01Dh-022h 031h-03Fh 040h-04Eh 04Fh-05Dh 05Eh-06Ch 06Dh-07Bh 07Ch-08Ah 08Bh-099h 09Ah 09Bh 09Ch-0A1h 0A2h-0A7h 0A8h-110h 111h-179h 17Ah-17Fh 180h-185h 186h-194h 195h-1A3h 1A4h-1B2h 1B3h-1C1h 1C2h-1D0h 1D1h-1DFh 1E0h-1EEh BYTE NUMBER Signature (2Ah) byte 0000 0000 Mixer left gain Mixer right gain (ratio, threshold, energy, attack, decay) Bass Treble Volume Biquad Biquad Biquad Biquad Biquad Biquad Biquad dB/bass dB/treble Bass break Treble break Bass delta Treble delta Bass point Treble point Biquad Biquad Biquad Biquad Biquad Biquad Biquad Right channel Left channel FUNCTION
NOTE: Bytes same order they appear register map. EPROM address xA0h.
Table 7-3. 512-Byte EPROM Memory Channels (with TAS3001)
ADDRESS 000h 001h TAS3004 002h 003h-00Bh 00Ch-014h 015h-01Ah 01Bh 01Ch 01Dh-022h 031h-03Fh 040h-04Eh 04Fh-05Dh 05Eh-06Ch 06Dh-07Bh 07Ch-08Ah 08Bh-099h 09Ah 09Bh 09Ch-0A1h 0A2h-0A7h 0A8h-110h 111h-179h 17Ah-17Fh 180h-185h 186h-194h 195h-1A3h 1A4h-1B2h 1B3h-1C1h 1C2h-1D0h 1D1h-1DFh 1E0h-1EEh Biquad Biquad Biquad Biquad Biquad Biquad Biquad TAS3001 right left channel BYTE NUMBER AD81 Mixer left gain Mixer right gain (ratio, threshold, energy, attack, decay) Bass Treble Volume Biquad Biquad Biquad Biquad Biquad Biquad Biquad dB/bass dB/treble Bass break Treble break Bass delta Treble delta Bass point Treble point TAS3004 right left channel TAS3004 FUNCTION Signature (2Ah) byte 0000 0011 TAS3001 1EFh 1F0h-1F2h 1F3h-1F5h 1F6h-1F7h 1F8h 1F9h 1FAh-1FFh
NOTE: this mode, TAS3004 TAS3001 devices both same equalization coefficients their right left channels. Bytes same order they appear register map. EPROM address xA0h.
Table 7-4. 2048-Byte EPROM Memory Map-2.0 Speakers With Multiple Equalizations
TAS3004 ADDRESS LEFT BIQUAD 000h 001h 002h 003h-00Bh 00Ch-014h 015h-019h 01Ah 01Bh 01Ch-021h 031h-03Fh 040h-04Eh 04Fh-05Dh 05Eh-06Ch 06Dh-07Bh 07Ch-08Ah 08Bh-099h 09Ah-185h 200h-20Eh 20Fh-21Dh 21Eh-22Ch 22Dh-23Bh 23Ch-24Ah 24Bh-259h 25Ah-268h 269h-277h 278h-286h 287h-295h 296h-2A4h 2A5h-2B3h 2B4h-2C2h 2C3h-2D1h 2D2h-2E0h 2E1h-2EFh 2F0h-2FEh 2FFh-30Dh 30Eh-31Ch 31Dh-32Bh 32Ch-33Ah 33Bh-349h 34Ah-358h 359h-367h 368h-376h 377h-385h 386h-394h 395h-3A3h NUMBER BYTES Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Bass treble table 40Dh-41Bh 41Ch-42Ah 42Bh-439h 43Ah-448h 449h-457h 458h-466h 467h-475h 476h-484h 485h-493h 494h-4A2h 4A3h-4B1h 4B2h-4C0h 4C1h-4CFh 4D0h-4DEh 4DFh-4EDh 4EEh-4FCh 4FDh-50Bh 50Ch-51Ah 51Bh-529h 52Ah-538h 539h-547h 548h-556h 557h-565h 566h-574h 575h-583h 584h-592h 593h-5A1h 5A2h-5B0h 5B1h-5BFh 5C0h-5CEh 5CFh-5DDh 5DEh-5ECh 5EDh-5FBh 5FCh-60Ah 60Bh-619h 61Ah-628h 629h-637h 638h-646h 647h-655h 656h-664h 665h-673h 674h-682h 683h-691h 692h-6A0h 6A1h-6AFh 6B0h-6BEh 6BFh-6CDh 6CEh-6DCh 6DDh-6EBh 6ECh-6FAh 6FBh-709h 70Ah-718h 719h-727h 728h-736h 737h-745h 746h-754h Mixer left gain Mixer right gain (ratio, threshold, energy, attack, decay) Bass Treble Volume 3A4h-3B2h 3B3h-3C1h 3C2h-3D0h 3D1h-3DFh 3E0h-3EEh 3EFh-3FDh 3FEh-40Ch FUNCTION CATEGORY TAS3004 ADDRESS RIGHT BIQUAD TAS3001
Signature (2Ah) 1EFh 1F0h-1F2h 1F3h-1F5h 1F6h-1F7h 1F8h 1F9h 1FAh-1FFh 186h-194h 195h-1A3h 1A4h-1B2h 1B3h-1C1h 1C2h-1D0h 1D1h-1DFh 1E0h-1EEh
NOTE: Bytes same order they appear register map. EPROM address xA0h.
Table 7-5. 2048-Byte EPROM Memory Map-2.1 Speakers With Multiple Equalizations
TAS3004 ADDRESS 000h 001h 002h 003h-00Bh 00Ch-014h 015h-019h 01Ah 01Bh 01Ch-021h 031h-03Fh 040h-04Eh 04Fh-05Dh 05Eh-06Ch 06Dh-07Bh 07Ch-08Ah 08Bh-099h 09Ah-185h 200h-20Eh 20Fh-21Dh 21Eh-22Ch 22Dh-23Bh 23Ch-24Ah 24Bh-259h 25Ah-268h 269h-277h 278h-286h 287h-295h 296h-2A4h 2A5h-2B3h 2B4h-2C2h 2C3h-2D1h 2D2h-2E0h 2E1h-2EFh 2F0h-2FEh 2FFh-30Dh 30Eh-31Ch 31Dh-32Bh 32Ch-33Ah 33Bh-349h 34Ah-358h 359h-367h 368h-376h 377h-385h 386h-394h 395h-3A3h NUMBER BYTES Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Bass treble table 5B1h-5BFh 5C0h-5CEh 5CFh-5DDh 5DEh-5ECh 5EDh-5FBh 5FCh-60Ah 60Bh-619h 61Ah-628h 629h-637h 638h-646h 647h-655h 656h-664h 665h-673h 674h-682h 683h-691h 692h-6A0h 6A1h-6AFh 6B0h-6BEh 6BFh-6CDh 6CEh-6DCh 6DDh-6EBh 6ECh-6FAh 6FBh-709h 70Ah-718h 719h-727h 728h-736h 737h-745h 746h-754h 40Dh-41Bh 41Ch-42Ah 42Bh-439h 43Ah-448h 449h-457h 458h-466h 467h-475h 476h-484h 485h-493h 494h-4A2h 4A3h-4B1h 4B2h-4C0h 4C1h-4CFh 4D0h-4DEh 4DFh-4EDh 4EEh-4FCh 4FDh-50Bh 50Ch-51Ah 51Bh-529h 52Ah-538h 539h-547h 548h-556h 557h-565h 566h-574h 575h-583h 584h-592h 593h-5A1h 5A2h-5B0h Mixer left gain Mixer right gain (ratio, threshold, energy, attack, decay) Bass Treble Volume 186h-194h 195h-1A3h 1A4h-1B2h 1B3h-1C1h 1C2h-1D0h 1D1h-1DFh 1E0h-1EEh FUNCTION CATEGORY TAS3001 ADDRESS LEFT CHANNEL TAS3001 ADDRESS RIGHT CHANNEL
Signature (2Ah) 1EFh 1F0h-1F2h 1F3h-1F5h 1F6h-1F7h 1F8h 1F9h 1FAh-1FFh 3A4h-3B2h 3B3h-3C1h 3C2h-3D0h 3D1h-3DFh 3E0h-3EEh 3EFh-3FDh 3FEh-40Ch
NOTE: Bytes same order they appear register map. EPROM address xA0h.
7-10
Electrical Characteristics
Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range: AVDD_PLL -0.3 DVDD -0.3 Digital input voltage range: -0.3 Operating free-air temperature, 70°C Storage temperature range, Tstg -65°C 150°C Case temperature seconds +122°C Lead temperature from case seconds +97.8°C Electrostatic discharge (see Note 2000
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE Human body model Method 3015.2 MIL-STD-833B.
Recommended Operating Conditions
25°C, AVDD DVDD Voltages analog inputs outputs AVDD with respect ground.
Supply voltage, AVDD Supply voltage, DVDD Operating Supply current, analog current Power down (see Note Operating Supply current digital current, Power down (see Note Operating Power dissipation NOTE clocks turned off. Power down (see Note 0.35 UNIT
Static Digital Specifications
25°C, AVDD DVDD
PARAMETER High-level input voltage Low-level output voltage High-level output voltage Low-level output voltage Input leakage current Output load capacitance TEST CONDITIONS -0.3 UNIT
Digital Filter
25°C, AVDD DVDD kHz, 20-bit mode terms characterized frequency scaled with chosen sampling frequency, Figure through Figure performance curves digital filter.
PARAMETER decimation filter (LPF) Pass band Pass band ripple Stop band Stop band attenuation Group delay high-pass filter (HPF) Pass band Deviation from linear phase Amplitude -100 -150 -200 Frequency 0.87 1.23 degrees ±0.01 24.1 20.0 TEST CONDITIONS UNIT
Figure 8-1. Digital Filter Characteristics
Amplitude -100 Frequency
Figure 8-2. Digital Filter Stopband Characteristics
0.008 0.006 Amplitude 0.004 0.002 -0.002 Frequency
Figure 8-3. Digital Filter Passband Characteristics
Amplitude -0.2 -0.4 -0.6 -0.8 Frequency
Figure 8-4. High Pass Filter Characteristics
Analog-to-Digital Converter
25°C, AVDD DVDD kHz, 20-bit mode terms characterized frequency scaled with chosen sampling frequency,
PARAMETER (EIAJ) Dynamic range Signal (noise distortion) ratio Power supply rejection ratio Idle channel tone rejection Intermodulation distortion crosstalk Overall frequency response Gain error Gain matching NOTE Measured with 50-mV peak sine curve. ±0.02 TEST CONDITIONS weighted kHz, (see Note +110 ±0.1 UNIT
Input Multiplexer
25°C, AVDD DVDD kHz, 20-bit mode terms characterized frequency scaled with chosen sampling frequency,
PARAMETER Input impedance Crosstalk Full scale input voltage range TEST CONDITIONS UNIT
Interpolation Filter
25°C, AVDD DVDD kHz, 20-bit mode terms characterized frequency scaled with normal mode sampling frequency, Figure Figure performance curves digital filter.
PARAMETER Pass band Pass band ripple Stop band Stop band attenuation Group delay Amplitude -100 fs/2 Frequency 28.8 TEST CONDITIONS ±0.005 24.1 20.0 UNIT
Figure 8-5. Filter Overall Frequency Characteristics
Amplitude
0.05
-0.05
-0.1 Frequency
Figure 8-6. Digital Filter Passband Ripple Characteristics
Digital-to-Analog Converter
25°C, AVDD DVDD kHz, input dB-fS sine wave terms characterized frequency scaled with chosen sampling frequency,
PARAMETER (EIAJ) Dynamic range Signal (noise distortion) ratio Power supply rejection ratio Idle channel tone rejection Intermodulation distortion Frequency response Deviation from linear phase crosstalk Jitter tolerance Full scale, single-ended, output voltage range offset -7.0 -0.5 TEST CONDITIONS weighted kHz, +118 +0.5 ±1.4 UNIT degree
Output Performance Data
25°C, AVDD DVDD output load resistance connected through blocking capacitor.
PARAMETER Output load resistance Output load capacitance VCOM internal resistance (see Note VCOM output CLOAD VRFILT internal resistance (see Note NOTES: VCOM vary during power down. VRFILT must never used voltage reference. TEST CONDITIONS UNIT
8.10 Serial Port Timing Characteristics
fscl tbuf tlow thigh thdsta tsusta thddat tsudat tsusto clock frequency free time between start stop period clock High period clock Hold time repeated start Setup time repeated start Data hold time (See Note Data setup time Rise time Fall time Setup time stop condition Capacitive load each line 1000 UNIT
NOTE device must internally provide hold time least signal bridge undefined region falling edge SCL.
tBUF
Valid tHD(DAT) tsu(DAT) Change Data Allowed tsu(STO) tsu(STA)
Data Line Stable
tHD(STA) NOTE: tlow measured from beginning thigh measured from beginning
tHD(STA)
Figure 8-7. Timing
System Diagrams
Figure Figure show TAS3004 stereo 2.1-channel applications, respectively.
+3.3
RESET Clock Select Logic Analog
Analog
SPDIF
TAS3004
EPROM
Master
B-T-V-EQ Switches NOTE: Items such network power supplies omitted clarity.
Figure 9-1. Stereo Application
+3.3
RESET Clock Select Logic Analog Satellite Amplifiers)
Analog
SPDIF
TAS3004
EPROM
Master
SDOUT2
I2S_OUT
Echos Switches GPIO
B-T-V-EQ-Sub
Slave PCM1744 Analog
TAS3001
Address NOTE: Items such network power supplies omitted clarity.
Figure 9-2. TAS3004 Device, Channels
Mechanical Information
TAS3004 device packaged 48-terminal package. following illustration shows mechanical dimensions package. (S-PQFP-G48) PLASTIC QUAD FLATPACK
0,50
0,27 0,17
0,08
0,13 5,50 7,20 6,80 9,20 8,80 0,05 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0°-7°
1,20
0,08 4073176/B 10/96
NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
10-1
10-2
Appendix Software Interface
Table A-1. Register
REGISTER Reserved Main control Reserved Volume Treble Bass Mixer left gain ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 VL(23-16), VL(15-8), VL(7-0) VR(23-16), VR(15-8), VR(7-0) T(7-0) B(7-0) S1L(23-16), S1L(15-8), S1L(7-0) S2L(23-16), S2L(15-8), S2L(7-0) AIL(23-16), AIL(15-8), AIL(7-0) S1R(23-16), S1R(15-8), S1R(7-0) S2R(23-16), S2R(15-8), S2R(7-0) AIR(23-16), AIR(15-8), AIR(7-0) C(7-0) Ratio(7-0), Threshold(7-0), Energy(7-0), Attack(7-0), Decay(7-0) NUMBER BYTES BYTE DESCRIPTION
Mixer right gain
0x08
Reserved Left biquad
0x09 0x0A B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Left biquad
0x0B
Left biquad
0x0C
Left biquad
0x0D
Left biquad
0x0E
Left biquad
0x0F
Table A-1. Register (Continued)
NUMBER BYTES
REGISTER Left biquad
ADDRESS 0x10
BYTE DESCRIPTION B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Reserved Reserved Right biquad
0x11 0x12 0x13 B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Right biquad
0x14
Right biquad
0x15
Right biquad
0x16
Right biquad
0x17
Right biquad
0x18
Right biquad
0x19
Reserved Left loudness biquad
0x20 0x21 B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0) B1(23-16), B1(15-8), B1(7-0) B2(23-16), B2(15-8), B2(7-0) A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0)
Right loudness biquad
0x22
Table A-1. Register (Continued)
REGISTER Left loudness biquad gain Right loudness biquad gain ADDRESS 0x23 0x24 NUMBER BYTES BYTE DESCRIPTION LBG(23-16), LBG(15-8), LBG(7-0) RBG(23-16), RBG(15-8), RBG(7-0)
Test Reserved Analog control Test Test Main control
0x29 0x30 0xFF 0x40 0x41 0x42 0x43
Reserved Anal_ctrl(7-0)
MCR2(7-0)
Main Control Register
A.1.1 Main Control Register
C(6) C(5) C(4) C(3) C(2) C(1) C(0)
0X01 C(7)
Table A-2. Main Control Register Description
REGISTER C(7) C(6) C(5-4) DESCRIPTOR E(1-0) FUNCTION Fast load SCLK frequency Serial port mode VALUE C(3) C(2) C(1-0) W(1-0) Serial port word length Normal operation mode Fast load mode SCLK 32fS SCLK 64fS Left justified Right justified Reserved Reserved Download 16-bit 18-bit 20-bit 24-bit DESCRIPTION
A.1.2
Main Control Register
C2(6) C2(5) C2(4) C2(3) C2(2) C2(1) C2(0)
MCR2 0X43 C2(7)
Table A-3. Main Control Register Description
REGISTER C2(7) C2(6) C2(5) C2(4) C2(3) C2(2) C2(1) C2(0) DESCRIPTOR FUNCTION Bass treble load Reserved Reserved Reserved Reserved Reserved Allpass mode Reserved VALUE Normal operation Sets equalization filters pass Normal operation mode Downloaded values DESCRIPTION
A.1.3
Analog Control Register
A(6) A(5) A(4) A(3) A(2) A(1) A(0)
0X40 A(7)
Table A-4. Analog Control Register Description
REGISTER A(7) A(6) DESCRIPTOR FUNCTION output mode Selects left right input monaural output VALUE A(4) A(3-2) DM(1-0) Reserved De-emphasis control A(1) A(0) Analog input select Analog power down De-emphasis off, normal operation De-emphasis De-emphasis 44.1 Reserved inputs selected inputs selected Powers down analog section Normal operation Normal operation inputs monaural left input selected monaural output when (ADM) right input selected monaural output when (ADM) DESCRIPTION
A(5)
Reserved
Volume Gain Command
gain error less than 0.12 (exclusive mute).
Device Subaddress VL(23-16) VL(15-8) VL(7-0) VR(23-16) VR(15-8) VR(7-0)
example, left volume right volume then command
Table A-5. Volume Versus Gain Values
GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0) GAIN (dB) VOLUME V(23-16), V(15-8), V(7-0)
18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5
-12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5
-27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5
-42.0 -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5 -54.0 -54.5 -55.0 -55.5 -56.0 -56.5
Table A-5. Volume Versus Gain Values (Continued)
VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0) VOLUME V(23-16), V(15-8), V(7-0)
GAIN (dB)
GAIN (dB)
GAIN (dB)
GAIN (dB)
GAIN (dB)
-57.0 -57.5 -58.0 -58.5 -59.0 -59.5
-60.0 -60.5 -61.0 -61.5 -62.0 -62.5
-63.0 -63.5 -64.0 -64.5 -65.0 -65.5
-66.0 -66.5 -67.0 -67.5 -68.0 -68.5
-69.0 -69.5 -70.0 mute
Treble Control Register Command
Both left right channel given same treble gain setting.
Device Subaddress T(7-0)
example, treble gain then command
Table A-6. Treble Control Register
GAIN (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 T(7-0) (hex) 0x01 0x01 0x04 0x08 0x13 0x1A 0x20 0x26 0x2C 0x31 0x36 0x3B 0x3F 0x43 0x47 GAIN (dB) 10.5 10.0 T(7-0) (hex) 0x4A 0x4D 0x51 0x53 0x56 0x59 0x5B 0x5D 0x60 0x62 0x63 0x65 0x67 0x68 0x69 GAIN (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 T(7-0) (hex) 0x6B 0x6C 0x6D 0x3F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A GAIN (dB) -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 T(7-0) (hex) 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 GAIN (dB) -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 T(7-0) (hex) 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96
Bass Control Register Command
Both left right channel given same bass gain setting.
Device Subaddress B(7-0)
example, bass gain then command
Table A-7. Bass Control Register
GAIN (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 B(7-0) (hex) 0x01 0x0A 0x11 0x18 0x1E 0x24 0x29 0x2E 0x33 0x37 0x3B 0x3F 0x43 0x46 0x49 GAIN (dB) 10.5 10.0 B(7-0) (hex) 0x4C 0x4F 0x52 0x55 0x58 0x5B 0x5D 0x5F 0x61 0x62 0x63 0x65 0x66 0x67 0x69 GAIN (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 B(7-0) (hex) 0x6A 0x6B 0x6D 0x6E 0x6F 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A GAIN (dB) -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 B(7-0) (hex) 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 GAIN (dB) -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 B(7-0) (hex) 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96
Mixer Register Command
gain error less than 0.12 excluding mute.
Device Subaddress Mixer1 Mixer2 Mixer
example, Sdin1 +6dB, Sdin2 0dB, Mute, then command Left
Right
Even only mixers needs changed, whole command must sent.
Table A-8. Mixer1 Mixer2 Gain Values
GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) GAIN (dB) GAIN S(23-16), S(15-8), S(7-0) GAIN (dB) GAIN S(23-16), S(15-8), S(7-0)
18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5
-18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5
-36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5
-54.0 -54.5 -55.0 -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 -63.5 -64.0 -64.5 -65.0 -65.5 -66.0 -66.5 -67.0 -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute
Programming Instruction Loudness Contour
gain error less than 0.12 excluding mute.
Device Subaddress B0(23-0) B1(23-0) B2(23-0) A1(23-0) A2(23-0)
example: Left Loudness Biquad
001A82 000000 FFE57E E03550 0FCABB
Right Loudness Biquad
001A82 000000 FFE57E E03550 0FCABB
Left Loudness Biquad Gain
G(23-0)
04C6D0
Right Loudness Biquad Gain
04C6D0
Examples DRCE
gain error less than 0.12 (excluding mute). Table A-9. Example DRCE Instruction With DRCE
BYTE NUMBER INSTRUCTION (HEX) INSTRUCTION DEFINITION TAS3004 device identification subaddress Above-threshold ratio 5.33:1 with DRCE Below-threshold ratio 1.33:1 Threshold Integration interval energy level detection Attack time constant Decay time constant Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 TABLE
A.7.1
DRCE On/Off
DRCE default mode TAS3004 device off. DRCE turns eight bytes Table transmitted above threshold ratio byte DRCE turns eight bytes Table A-10 transmitted above threshold ratio byte Table A-10 identical Table except this third byte. Table A-10. Example DRCE Instruction With DRCE
BYTE NUMBER INSTRUCTION (HEX) INSTRUCTION DEFINITION TAS3004 device identification subaddress Above threshold ratio 5.33:1 with DRCE Below threshold ratio 1.33:1 Threshold Integration interval energy level detection Attack time constant Decay time constant Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 TABLE
A.7.2
Above Threshold Ratios
above threshold ratios applied when energy level incoming signal detected anywhere between threshold (from Table A-15) Figure A-1.
Output (dB)
Expansion
Ratio
Compression
-89.625 -89.625
Input (dB) Threshold Above Threshold
Below Threshold
Figure A-1. TAS3004 DRCE Characteristics Domain Table A-11. Above Threshold Ratios Compression
HEXADECIMAL VALUE RATIO (IN:OUT) 1.00 1.07 1.14 1.23 1.33 1.45 1.60 1.78 2.00 2.29 2.67 3.20 4.00 5.33 8.00 16.0
A-10
Table A-12. Above Threshold Ratios Expansion
HEXADECIMAL VALUE RATIO (IN:OUT) 1.00 1.06 1.13 1.19 1.25 1.31 1.38 1.44 1.50
A.7.3
Below Threshold Ratios
below threshold ratios applied when energy level incoming signal detected being anywhere between threshold (from Table A-15) -89.625 Figure A-1. Table A-13. Below Threshold Ratios Expansion
HEXADECIMAL VALUE RATIO (IN:OUT) 1.00 1.06 1.13 1.19 1.25 1.31 1.38 1.44 1.50 1.56 1.63 1.69 1.75 1.81 1.88 1.94 2.00
Table A-14. Below Threshold Ratios Compression
HEXADECIMAL VALUE RATIO (IN:OUT) 1.00 1.07 1.14 1.23 1.33 1.45 1.60 1.78 2.00
A-11
A.7.4
Threshold
Table A-15 lists range threshold values from -89.625 0.75-dB decrements. NOTE: TAS3004 device capable 0.375-dB increments. associated hexidecimal value determined interpolating between existing hexidecimal values Table A-15. Table A-15. Threshold Values
VALUE -0.75 -1.50 -2.25 -3.00 -3.75 -4.50 -5.25 -6.00 -6.75 -7.50 -8.25 -9.00 -9.75 -10.50 -11.25 -12.00 -12.75 -13.50 -14.25 -15.00 -15.75 -16.50 -17.25 -18.00 VALUE -18.75 -19.50 -20.25 -21.00 -21.75 -22.50 -23.25 -24.00 -24.75 -25.50 -26.25 -27.00 -27.75 -28.50 -29.25 -30.00 -30.75 -31.50 -32.25 -33.00 -33.75 -34.50 -35.25 -36.00 -36.75 VALUE -37.50 -38.25 -39.00 -39.75 -40.50 -41.25 -42.00 -42.75 -43.50 -44.25 -45.00 -45.75 -46.50 -47.25 -48.00 -48.75 -49.50 -50.25 -51.00 -51.75 -52.50 -53.25 -54.00 -54.75 -55.50 VALUE -56.25 -57.00 -57.75 -58.50 -59.25 -60.00 -60.75 -61.50 -62.25 -63.00 -63.75 -64.50 -65.25 -66.00 -66.75 -67.50 -68.25 -69.00 -69.75 -70.50 -71.25 -72.00 -72.75 -73.50 -74.25 VALUE -75.00 -75.75 -76.50 -77.25 -78.00 -78.75 -79.50 -80.25 -80.00 -81.75 -82.50 -83.25 -84.00 -84.75 -85.50 -86.25 -87.00 -87.75 -88.50 -89.25 -89.625
A.7.5
Time Constants
Table A-16 program attack time, decay time, integration interval energy level detection. Level detection performed using alpha filter input DRCE, which functions energy-level detection block DRCE. time constant level detection thought integration interval. time constant from Table A-16 integration interval energy level detection. Table A-16 lists time constants used integration interval energy level detection, attack time constant, decay time constant. values represent time required reach maximum value from zero.
A-12
Table A-16. Time Constants
HEXADECIMAL VALUE TIME DELAY
A.7.6
DRCE Example With Threshold
From DRCE example shown Figure A-2, threshold input energy value Output (dB) [T(dB) E(dB) T(dB) (1/CR)] [-12 (-12)) (1/3)] Where: Compression Ratio Threshold (dB) Energy estimate current input Note: Energy sine wave approximately lower than peak.
Output (dB)
Final Output Threshold Above Threshold Ratio Compression
Below Threshold Ratio Compression
Input (dB) Threshold
Figure A-2. DRCE Example With Threshold
A-13
A-14
PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2005
PACKAGING INFORMATION
Orderable Device TAS3004PFB TAS3004PFBR
Status ACTIVE ACTIVE
Package Type TQFP TQFP
Package Drawing
Pins Package Plan 1000 None None
Lead/Ball Finish NIPDAU NIPDAU
Peak Temp Level-2-220C-1 YEAR Level-2-220C-1 YEAR
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page

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