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High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-In
Top Searches for this datasheetCD54HC257, CD74HC257, CD54HCT257, CD74HCT257 High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs other input conditions. Moving data from groups registers four common output buses common 257. state Select input determines particular register from which data comes. also used function generator. Features Buffered Inputs /Title (CD74 HC257 CD74 HCT25 /Subject (High Speed CMOS Logic Quad 2-Input Multiplexer Typical Propagation Delay Output 12ns 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL, Ordering Information PART NUMBER CD54HC257F3A CD54HCT257F3A CD74HC257E CD74HC257M CD74HC257MT CD74HC257M96 CD74HCT257E CD74HCT257M CD74HCT257MT TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC Description 'HC257 'HCT257 quad 2-input multiplexers which select four bits data from sources under control common Select Input (S). Output Enable input (OE) active LOW. When HIGH, outputs (1Y-4Y) high impedance state regardless CD74HCT257M96 NOTE: When ordering, entire part number. suffix denotes tape reel. suffix denotes small-quantity reel 250. Pinout CD54HC257, CD54HCT257 (CERDIP) CD74HC257, CD74HCT257 (PDIP, SOIC) VIEW CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright 2003, Texas Instruments Incorporated CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Functional Diagram CIRCUITS IDENTICAL CIRCUIT ABOVE DASHED ENCLOSURE TRUTH TABLE OUTPUT ENABLE SELECT INPUT DATA INPUTS OUTPUT High Voltage Level Voltage Level Don't Care High Impedance, State CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Absolute Maximum Ratings Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±35mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±70mA Thermal Information Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only) Operating Conditions Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max) CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied. NOTE: package thermal impedance calculated accordance with JESD 51-7. Electrical Specifications TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads -0.02 -0.02 -0.02 High Level Output Voltage Loads Level Output Voltage CMOS Loads -7.8 0.02 0.02 0.02 Level Output Voltage Loads Input Leakage Current 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three-State Leakage Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load Three-State Leakage Current NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC ±0.5 -40oC 85oC -55oC 125oC UNITS 3.98 3.84 0.02 0.26 0.33 ±0.1 ±0.5 Input Loading Table INPUT Data UNIT LOADS 0.95 NOTE: Unit Load limit specified Electrical Specifications table, e.g., 360µA 25oC. CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Switching Specifications Input TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS PARAMETER TYPES Propagation Delay SYMBOL tPLH, tPHL 50pF 15pF 50pF Propagation Delay tPLH, tPHL 50pF 15pF 50pF Propagation Delay tPLZ, tPHZ, tPZL, tPZH 50pF 50pF 15pF 50pF Output Transition Times tTLH, tTHL 50pF Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay Propagation Delay Propagation Delay Output Transition Times Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes NOTES: tPLH, tPHL 50pF 15pF tPZL, tPZH 50pF 15pF tPLZ, tPHZ 50pF 15pF tTLH, tTHL 50pF used determine dynamic power consumption, multiplexer. VCC2 (CPD where Input Frequency, Output Load Capacitance, Supply Voltage. CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Test Circuits Waveforms INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V tTHL INVERTING OUTPUT FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC OUTPUT DISABLE tPZL tPHZ OUTPUT HIGH OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED tPZH FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC OUTPUT DISABLE tPLZ OUTPUT tPHZ OUTPUT HIGH OUTPUTS ENABLED tPZL tPLZ OUTPUT tPZH 1.3V 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OUTPUT DISABLE WITH THREESTATE OUTPUT OUTPUT 50pF tPLZ tPZL tPHZ tPZH NOTE: Open drain waveforms tPLZ tPZL same those three-state shown left. test circuit Output VCC, 50pF. FIGURE THREE-STATE PROPAGATION DELAY TEST CIRCUIT PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device 5962-8970501EA CD54HC257F3A CD54HCT257F3A CD74HC257E CD74HC257M CD74HC257M96 CD74HC257MT CD74HCT257E CD74HCT257M CD74HCT257M96 CD74HCT257MT Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP CDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC Package Drawing Pins Package Plan 2500 2500 None None None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Lead/Ball Finish Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device. Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight. MSL, Peak Temp. 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