Wide Operating Voltage Range High-Current 3-State Outputs Drive LSTTL

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Wide Operating Voltage Range High-Current 3-State Outputs Drive LSTTL

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SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
Wide Operating Voltage Range High-Current 3-State Outputs Drive LSTTL Loads Power Consumption, 80-µA Typical ±6-mA Output Drive
SN54HC652 PACKAGE SN74HC652 PACKAGE (TOP VIEW)
Input Current Independent Registers Enables Buses Multiplexed Real-Time Stored Data True Data Paths
SN54HC652 PACKAGE (TOP VIEW)
internal connection
description/ordering information
'HC652 devices consist bus-transceiver circuits, D-type flip-flops, control circuitry arranged multiplexed transmission data directly from data from internal storage registers. Output-enable (OEAB OEBA) inputs provided control transceiver functions. Select-control (SAB SBA) inputs provided select real-time stored-data transfer. input level selects real-time data, high input level selects stored data. Figure illustrates four fundamental bus-management functions that performed with these devices. ORDERING INFORMATION
PACKAGE PDIP -40°C 85°C SOIC CDIP -55°C 125°C LCCC Tube Tube Tape reel Tube Tube Tube ORDERABLE PART NUMBER SN74HC652NT SN74HC652DW SN74HC652DWR SNJ54HC652JT SNJ54HC652W SNJ54HC652FK TOP-SIDE MARKING SN74HC652NT HC652 SNJ54HC652JT SNJ54HC652W SNJ54HC652FK
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
DALLAS, TEXAS 75265
CLKAB OEAB
CLKBA OEBA
OEAB CLKAB CLKBA
OEBA
SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
description/ordering information (continued)
Data data bus, both, stored internal D-type flip-flops low-to-high transitions appropriate clock (CLKAB CLKBA) terminals, regardless select- output-control terminals. When real-time transfer mode, possible store data without using internal D-type flip-flops simultaneously enabling OEAB OEBA. this configuration, each output reinforces input. When other data sources sets lines high impedance, each lines remains last state. ensure high-impedance state during power power down, OEBA should tied through pullup resistor, OEAB should tied through pulldown resistor; minimum value resistor determined capability driver.
FUNCTION TABLE INPUTS OEAB OEBA CLKAB CLKBA A1-A8 Input Input Input Input Unspecified Output Output Output Input Input Output DATA B1-B8 Input Input Unspecified Output Input Input Input Input Output Output Output OPERATION FUNCTION Isolation Store data Store hold Store both registers Hold store Store both registers Real-time data Stored data Real-time data Stored data Stored data stored data
data-output functions enabled disabled variety level combinations OEAB OEBA. Data-input functions always enabled; i.e., data terminals stored every low-to-high transition clock inputs. Select control clocks occur simultaneously. Select control clocks must staggered load both registers.
POST OFFICE 655303
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SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
OEAB OEBA
CLKAB CLKBA
OEAB OEBA
CLKAB
CLKBA
REAL-TIME TRANSFER CLKAB CLKBA TRANSFER STORED DATA AND/OR
REAL-TIME TRANSFER
OEAB
OEBA
OEAB
CLKAB CLKBA
OEBA
STORAGE FROM numbers shown packages.
Figure Bus-Management Functions
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
logic diagram (positive logic)
OEBA
OEAB CLKBA CLKAB
Eight Channels
Seven Other Channels numbers shown packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 46°C/W (see Note package 67°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7. package thermal impedance calculated accordance with JESD 51-3.
POST OFFICE 655303
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SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54HC652 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise fall) time 3.15 1.35 1000 SN74HC652 3.15 1.35 1000 UNIT
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS -7.8 Control inputs Control inputs 3.98 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.15 ±0.1 ±0.01 0.26 0.26 ±100 ±0.5 SN54HC652 ±1000 SN74HC652 3.84 5.34 0.33 0.33 ±1000 UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
fclock Clock frequency Pulse duration, CLKBA CLKAB high Setup time, before CLKAB before CLKBA Hold time, after CLKAB after CLKBA 25°C SN54HC652 SN74HC652 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) fmax CLKBA CLKAB OEBA OEAB tdis OEBA OEAB 25°C SN54HC652 SN74HC652 UNIT
These parameters measured with internal output state storage register opposite that input.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) CLKBA CLKAB OEBA OEAB 25°C SN54HC652 SN74HC652 UNIT
These parameters measured with internal output state storage register opposite that input.
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
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SN54HC652, SN74HC652 OCTAL TRANSCEIVERS REGISTERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
PARAMETER tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open Closed Open Closed Open Open
From Output Under Test (see Note
Test Point
tdis
LOAD CIRCUIT
High-Level Pulse
VOLTAGE WAVEFORMS PULSE DURATIONS
Reference Input Data Input
Low-Level Pulse
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES
Input tPLH In-Phase Output tPHL Out-ofPhase Output tPLH tPHL
Output Control (Low-Level Enabling) tPZL Output Waveform (See Note tPZH Output Waveform (See Note
tPLZ tPHZ
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES 3-STATE OUTPUTS
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured when input duty cycle 50%. outputs measured time with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device SN74HC652DW SN74HC652DWR SN74HC652NT SN74HC652NT3
Status ACTIVE ACTIVE ACTIVE OBSOLETE
Package Type SOIC SOIC PDIP PDIP
Package Drawing
Pins Package Plan 2000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None
Lead/Ball Finish NIPDAU NIPDAU NIPDAU Call
Peak Temp Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MPDI004 OCTOBER 1994
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
1.260 (32,04) 1.230 (31,24) 0.310 (7,87) 0.290 (7,37)
1.425 (36,20) 1.385 (35,18) 0.315 (8,00) 0.295 (7,49)
0.280 (7,11) 0.250 (6,35)
0.070 (1,78)
0.020 (0,51)
0.200 (5,08) Seating Plane 0.125 (3,18)
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25)
4040050 04/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
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Wide Operating Voltage Range High-Current 3-State Outputs Drive LSTTL

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